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Sometimes you need defined outputs even if there is no clock. In such cases, pulling the prog line low may not cut it. In such cases, an asynchronously asserted, and syncrhonously deasserted, asynchronous reset is the safest option. But, like Ray said, you often don't need reset everywhere. As to the initial values after configuration, remember that the end of configuration is likely to be asynchronous to your clock, so for example, a down counter initialized to a zero may not be a good idea! In general, down counters should be initialized to odd values, and up counters should be initialised to even values, to avoid having an uncertainty in more than one bit (the LSB) on the first clock at/after reset/config. For synchronous deassertion of asynchronous resets, another option is to disable the clock until several periods after reset is deasserted, giving it time to propagate to all targets. AndyArticle: 94001
Monica, the DCM is obviously not well suited to cope with drastic changes in its input frequency. I would just forget the DCM (in this application) and use three good old flip-flops to build a (synchronous) divide-by-eight circuit. All your problems are gone... :-) Peter Alfke, Xilinx ApplicationsArticle: 94002
No this is not a typo, and yes, it does not make sense, and so this variant has been removed from v2.0 of the Xilinx floating-point operator core. (Note that the logic multiplier uses an optimized multiplier and so is pretty good in its utilization of resources). The release of v2.0 is imminent, and the 4x DSP single precision multiplier will be much faster and use less slices that v1.0. Thanks, Richard Walke Robin Bruce wrote: > http://www.xilinx.com/bvdocs/ipcenter/data_sheet/floating_point.pdf > > With regard to the speed-optimised single-precision floating-point > core, look at: > > Table 6: Latency of Speed Optimized Core (Page 10) > Table 10: Characterization of Speed-Optimized Single-Precision Core > (Page 18) > > These are the characteristics of the speed-optimised floating-point > cores from Xilinx. For virtex-4 there's a multiplier version that > uses a single DSP48 block, as opposed to the standard 4x DSP48 version. > My question is: What's the point of it? There's a pure logic one > there that uses less slices, has a lower latency and operates > as-near-as-damn-it at the same frequency. More to the point you're not > throwing away a DSP48... > > I've spoken to colleagues about this, and the best guess we can come to > is that there's a typo, most likely on the slice count for the single > DSP48 + slices version. Anyone know better? > > Cheers, > > Robin BruceArticle: 94003
If you have no multcycle path or false path constraints, then yes, STA plus RTL simulation are all you need. But... If you have any multicylce or false path constraints, you either need a tool that will verify their validity, or you must run sim with full timing to verify them. Otherwise, what you thought was a multicycle or false path may not really be so (or more commonly: not properly specified), but the RTL sim and STA would indicate all was well. Note that the full timing sim can be reduced to cover only sections that have such constraints. AndyArticle: 94004
Is there anything that would stop the same version of ISE Evaluation being reloaded onto the same PC or another PC once the 60 days evaluation period had lapsed to begin a new 60 days? GeraldArticle: 94005
Peter, Yes, I agree! If all we are doing is dividing by 8, then a DCM is definitely not required. Thanks for observing the obvious. "When you are a hammer, every problem looks like a nail." Austin (ex DCM IC design team member) Peter Alfke wrote: > Monica, the DCM is obviously not well suited to cope with drastic > changes in its input frequency. > I would just forget the DCM (in this application) and use three good > old flip-flops to build a (synchronous) divide-by-eight circuit. All > your problems are gone... :-) > Peter Alfke, Xilinx Applications >Article: 94006
Dirk Bruere at Neopax wrote: > Robert Baer wrote: > > > Eric Smith wrote: > > > >> wtxwtx@gmail.com writes: > >> > >>> Why 'a plurality of N' or 'the plurality of N' must be used fo 'N' in > >>> patent claims? > >> > >> > >> > >> Because patents are written to be legal documents, not engineering > >> documents. Legal documents are written using traditions that have > >> evolved over hundreds of years. Since patent examiners, lawyers, and > >> judges all expect patents to be written in a certain way, if you > >> submit an application that isn't written that way, you're just wasting > >> money. > > > > Again, that is what i call "patent-ese". > > Instead of "many" or "multiple" one sees "a plurality of". > > Like i said, follow the terminology and useage that you find in other > > patents that are closely related to your particular idea. > > Legalese is a very precise language, quite comparable to computer languages. > If you ever see "...time is of the essence..." in a contract, prepare to run. Legalese is designed to keep lawyers employed. It is not, by itself, "precise". Contracts and other legal documents written in "plain English" are just as enforceable as the legalese version. Maybe even more so, because a jury (non-lawyers) can understand them. MOOYMMV. Tom SeimArticle: 94007
Hi All, I am new to VHDL and am attempting to create an object similar to a parallel load register. Each FF loads its input from the same signal and all are clocked by the same signal. In my "entity" definition I desire only the two inputs as I don't want to use any more IOB's. In the architecture block I declare a signal that is an N-bit vector (say N=8). However Xilinx ISE 7.1 seems to optimize out the F/F's becuase they are logically not required. Here is the question; how does one declare a set of F/F's to be instantiated in "slices" not "IOB's" whose outputs are not used (to be manually routed later)? Thanks, BrendanArticle: 94008
Peter Alfke wrote: Hallo, > Monica, the DCM is obviously not well suited to cope with drastic > changes in its input frequency. > I would just forget the DCM (in this application) and use three good > old flip-flops to build a (synchronous) divide-by-eight circuit. All > your problems are gone... :-) > Peter Alfke, Xilinx Applications Do you mean to use a 3bit counter and connect the Most significant bit to output clock? But I fear there will be some delays between the master clock and derived clock. Wont we have problems when tranferring data from the derived clock domain to master clock domain? I am using DCM because it gives zero delay 1/8th Clock. Kindly let me if I understood your suggestion correctly. Thanking you, MonicaArticle: 94009
Brendan Illingworth wrote: > Hi All, > > I am new to VHDL and am attempting to create an object similar to a parallel > load register. Each FF loads its input from the same signal and all are > clocked by the same signal. In my "entity" definition I desire only the two > inputs as I don't want to use any more IOB's. In the architecture block I > declare a signal that is an N-bit vector (say N=8). However Xilinx ISE 7.1 > seems to optimize out the F/F's becuase they are logically not required. > Here is the question; how does one declare a set of F/F's to be instantiated > in "slices" not "IOB's" whose outputs are not used (to be manually routed > later)? > > Thanks, > > Brendan Hallo, Didnt understand clearly what you are trying to do.Can you post your entity and architecture to throw some light on it? Cheers, Monica, GermanyArticle: 94010
Monica, you can avoid the delay by clocking everything with the fast clock, and using a 1-of-8 Clock Enable for the slow circuitry. That keeps everything in the same clock domain. The only drawback is the higher power consumption due to the wide distribution of the fast clock. If almost everything runs at the slower clock, then it might make sense to analyze carefully whether you can tolerate the skew between the fast and the slow clock. Yes, you would use the third bit of a synchronous counter as the slower clock. Do not even think about a ripple-counter :-( Since your "high" clock frequency is only 40 MHz, you can also camouflage the clock skew by using the "other" edge of the 40 MHz clock... Frohes Neues Jahr! Peter AlfkeArticle: 94011
Hallo gerald, This is not recommended.You may use ISE webpack freely as long as you want.You may download it from http://www.xilinx.com/ise/logic_design_prod/webpack.htm Cheers, MonicaArticle: 94012
Hallo Peter, Danke sch=F6n,Ich wunshe Ihnen guten rutz ins neue Jahr. Thank you very much, MonicaArticle: 94013
<soar2morrow@yahoo.com> wrote in message news:1136396771.716617.244960@f14g2000cwb.googlegroups.com... > > Legalese is designed to keep lawyers employed. It is not, by itself, > "precise". Contracts and other legal documents written in "plain > English" are just as enforceable as the legalese version. Maybe even > more so, because a jury (non-lawyers) can understand them. > Hi Tom, So, on this one I disagree with you. Legalese exists because it has terms that have been defined to have a strict meaning in case law. It's not much different to the jargon used by electronics engineers which has a precise meaning. Contracts written in (say) "plain English" are enforceable, but with a lot more effort as there will be no precedent. IMO ;-) Cheers, Syms.Article: 94014
Could somebody also show a little example how to use this DCM-goodie in practice, on Spartan-3 (the Starter Kit, that I use...)? That is, I'd like to know what exactly I need to write into the Verilog-source and/or UCF-file to get the CLK divided or multiplied by two, for example. That is, how to do it purely "textually", as I have only ISE 7 WebPack, without anything fancy like FPGA Editor. I guess I have just to instantiate the "DCM module" in the main module, and then pass the divided or multiplied clock signal to other clock-using modules as their default clock, without needing to do any changes to them, right? I'm sure this is explained somewhere at Xilinx application notes, but they are not really organized for the easiest perusal, IMHO. Any help appreciated, Veli IgorArticle: 94015
In my design I use the block sync and the 64B/66B descrambler and bypasses the 64B/66B decoder in the Rx direction of the MGT. In the Tx direction I bypass the 64B/66B encoding and applies the sync header in the fabric i/f. I use the gearbox and the scrambler. I want to use the Rx buffer clock correction function and I have defined a 66-bits pattern used for this purpose as follows: 0x01_5555000000000000 My problem is to get a correct match of the pattern. In my simulation the pattern is matched independent of the sync header, i.e. both 01 and 10 matches. I have configured the MGT as follows: CLK_COR_SEQ_1_1 = "11001010101" CLK_COR_SEQ_1_2 = "10001010101" CLK_COR_SEQ_1_3 = "10000000000" CLK_COR_SEQ_1_4 = "10000000000" CLK_COR_SEQ_1_MASK = "0000" CLK_COR_SEQ_2_1 = "10000000000" CLK_COR_SEQ_2_2 = "10000000000" CLK_COR_SEQ_2_3 = "10000000000" CLK_COR_SEQ_2_4 = "10000000000" CLK_COR_SEQ_2_MASK = "0000" CLK_CORRECT_USE = true CLK_COR_MAX_LAT = 48 -- According to UG035 v1.5 table 1-5 CLK_COR_MIN_LAT = 32 -- According to UG035 v1.5 table 1-5 CLK_COR_SEQ_2_USE = false I have also tried to use the opposite syncheader value for my sequence (10) but it still fails. Is it possible to say which serial bits that are matched with which bits of the generics/attributes debending of the diffrent configurations? It should be some kind of mux that connects the bits to the comparator logic. Looking forward for Your answers. Best Regards Patrik Eriksson ------ Patrik ErikssonArticle: 94016
Now, is it this: http://www.avnet.com/img_shared/evk/df2df2usa/Spartan-3E-Starter-Kit.gif what we have been waiting for like a moon rising? This I found with a little "URL hacking" from avnet's site at: http://www.em.avnet.com/evk/home/0,1719,RID%253D0%2526CID%253D27812%2526CCD%253DUSA%2526SID%253D4742%2526DID%253DDF2%2526SRT%253D1%2526LID%253D18806%2526PVW%253D%2526BID%253DDF2%2526CTP%253DEVK,00.html (If above URL falls in pieces, the same page can be found from the list http://www.fpga-faq.org/FPGA_Boards.shtml by searching for SPAR3E) But I wonder, is this really exactly the same board as what Xilinx will sell: http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-SPAR3E-DK (the page is now saying that Spartan-3E Starter Kit available February, 2006 !) Note that in the advertisement photo at Xilinx site, they still use the photo of the old Spartan-3 (DO-SPAR3-DK) Starter Kit. (So I had presumed all the time, that the new Spartan-3E Starter Kit would also be manufactured by Digilent, but apparently it's not so...) Yours, Veli IgorArticle: 94017
Greetings. I'm looking at doing some basic CPLD designs via Schematic Entry. Who has easier to learn/use schematic entry software, Xilinx or Altera? Both companies have CPLD's that meet my criteria, and design portability isn't an issue. Thank you.Article: 94018
<veligor@gmail.com> schrieb im Newsbeitrag news:1136401988.584558.129590@g49g2000cwa.googlegroups.com... > Now, is it this: > http://www.avnet.com/img_shared/evk/df2df2usa/Spartan-3E-Starter-Kit.gif > what we have been waiting for like a moon rising? > yes this is it I think its first time that Avnet is selling Digilent boards and not their own ! (they have S3e-100 boards of their own making) this is the digilent board aka Spartan 3E starterkit, notice that Avnet says lead time 5 weeks what is february also AnttiArticle: 94019
Mike Oxlarge wrote: > module top(clk, reset, enable, cnt); > always @ (posedge clk) begin > if (reset) begin > curval <= 5; ^^^^^^^^^^^^^^^^^^^^^^ curval is synchronously set here. > end > else begin > case (acnt) > 0: cnt <= curval; > 1: cnt <= ov1; > 2: cnt <= 2; > 3: cnt <= 3; > endcase > > if (!enable) > acnt <= acnt + 1; > end > end > > // Update the values > always @ (negedge clk) begin > if (enable) begin > ov1 <= curval; > curval <= curval + 1; ^^^^^^^^^^^^^^^^ curval is clocked here. The simple rule to remember is that you can't assign to a signal in more than one always block. Put the synchronous reset curval <= 5; in the negedge-clocked block. -aArticle: 94020
> I'm looking at doing some basic CPLD designs via Schematic Entry. Who > has easier to learn/use schematic entry software, Xilinx or Altera? Altera Regards, ThomasArticle: 94021
Xilinx does not discriminate against Europe. It was the other way around: I used a friend who flew home to Germany for Xmas, to hand-carry a kit, and mail it locally to Antti. So Antti got the first kit outside the US. We cannot do that for everybody in Europe. Maybe it was "the squeaky wheel gets the grease..." In the meantime, we are mailing Antti another board, since we don't want him to be a complaining repairman... Peter Alfke Ralph wrote: > Unfortunately we in europe are not able to play with the kit... > > I assume guys at Xilinx think there are not enough potential customers there :-((Article: 94022
On Wed, 04 Jan 2006 11:36:30 -0800, Andy Peters wrote: > Mike Oxlarge wrote: >> module top(clk, reset, enable, cnt); >> always @ (posedge clk) begin >> if (reset) begin >> curval <= 5; > > ^^^^^^^^^^^^^^^^^^^^^^ curval is synchronously set here. > >> end >> else begin >> case (acnt) >> 0: cnt <= curval; >> 1: cnt <= ov1; >> 2: cnt <= 2; >> 3: cnt <= 3; >> endcase >> >> if (!enable) >> acnt <= acnt + 1; >> end >> end >> >> // Update the values >> always @ (negedge clk) begin >> if (enable) begin >> ov1 <= curval; >> curval <= curval + 1; > > ^^^^^^^^^^^^^^^^ curval is clocked here. > > The simple rule to remember is that you can't assign to a signal in > more than one always block. Put the synchronous reset curval <= 5; in > the negedge-clocked block. > > -a I get what you're saying, and have tried your (and the other's) suggestion of putting the reset in the negedge-clocked block, and it synthesizes just fine. However, I'm now trying to implement what mk suggested: <quote mk> ... You don't need a two phase implementation which necessiates mixed clock edges. You can do everything you need with a single edge. Imagine a cloud of logic which takes your enable and the cnt value and calculates the next value of cnt to be presented. When the clock edge happens this value gets to the flop output and the cycle starts again. ... </quote mk> Any ideas on how I can implement what he suggested? I'm working on it, but not making much progress. I'm sure there's probably a simple and elegant solution to this that I'm missing.Article: 94023
Andy wrote:
> If you have no multcycle path or false path constraints, then yes, STA
> plus RTL simulation are all you need.
Yes. I pipeline multicycles and cover
synchronization without false path constraints.
> But... If you have any multicylce or false path constraints, you
> either need a tool that will verify their validity, or you must run sim
> with full timing to verify them. Otherwise, what you thought was a
> multicycle or false path may not really be so (or more commonly: not
> properly specified), but the RTL sim and STA would indicate all was
> well. Note that the full timing sim can be reduced to cover only
> sections that have such constraints.
A full timing sim is a good release check-off item,
but I keep it out of the detailed design loop.
-- Mike Treseler
Article: 94024
Parkov wrote:
> I'm looking at doing some basic CPLD designs via Schematic Entry. Who
> has easier to learn/use schematic entry software, Xilinx or Altera?
Altera Quartus.
-- Mike Treseler
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