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Hi I am having extreme trouble with ChipScope and Spartan3e (using the Spartan3E Sample Pack PCB from digilent). ISE 7.1 sample top, CS coregen, ICON+VIO wired up build, then: 1 First I tried CS 7.1SP2, no cores found... 2 tested with CS analyzer 7.1SP4, no cores found... 3 then regenerated the ICON+VIO with 7.1SP4, cores found, I am happy. 4 then ISE clean, rebuild, no cores found... 5 regenereting the ICON+VIO with CS 8.1 no cores found... 6 updating the project to ISE 8.1, cores found, I am happy 7 ISE clean, rebuild, no cores found.. 8 what should I do next? I am running my 3rd Day of struggle, and all I wanted todo was to programm the Intel Flash on the board, the board can be seen there http://www.nuhorizons.com/products/xilinx/spartan3e/samplepack.html any ideas? AnttiArticle: 93501
"ajcrm125" <ajcrm125@gmail.com> schrieb im Newsbeitrag news:1135279466.216912.316820@o13g2000cwo.googlegroups.com... > Hey guys, does anyone know where I can get VHDL/Verilog source for the > Z8001/Z8002 processor? > Thanks for any info! > > -Adam > ajcrm125@gmail.com > yes, sure! www.zilog.com I think some other entities have it also but not available. the Z8 project at opencores is dead and unuseable, and there is little hope that free z8000 core would exist AnttiArticle: 93502
"Antti Lukats" <antti@openchip.org> wrote in message news:dogh9h$s4e$00$1@news.t-online.com... > "Alex Gibson" <news@alxx.org> schrieb im Newsbeitrag > news:411umcF1cgt5hU1@individual.net... >> >> "bjzhangwn" <bjzhangwn@163.com> wrote in message >> news:1135317395.120472.211170@o13g2000cwo.googlegroups.com... >>>I want to learn more about this! >>> >> >> look at uclinux >> >> uclinux on microblaze >> http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux >> >> uclinux for nios2 >> http://www.enseirb.fr/~kadionik/embedded/uclinux/nios-uclinux.html >> http://www.enseirb.fr/~kadionik/embedded/uclinux/HOWTO_compile_uClinux_for_NIOS.html >> >> http://linuxdevices.com/news/NS9386138954.html >> >> Note I don't know if that is the correct link for Nios as have only used >> uclinux on microblaze. >> >> Can also run full linux on v2pro and v4FX with ppc hard cores. >> >> Alex >> > Alex, you as many others are saying that 'can run full linux' on V2P/V4, > but well I belive that > and I do know it works, but there seems to be only one way to the goal, > namly montavista > > trying the full linux on virtex by using EDK and opensource linux kernel > seems to be a real > pain, and yes I have studied all the info about this on the web, all > references go back to > montavista, or V2PDK. > > So maybe you know where to get HOWTO > > EDK+opensource ppc-linux, all done in one day? > > I know that Denx did a lot of work for V2Pro ppc linux, but as Xilinx did > not talk the them then they got really pissed off and stopped their > efforts for the Virtex PPC linux support. And montavista is something very > strange type of entity, can not understand what they are selling or > offering or what it costs :( > > Antti I haven't tried denix myself but believe it can be made to run. Download their eldk. Could try asking on the uclinux microblaze list. A lot of the guys there know a lot lot more than me on this. Have not been doing much with fpgas / edk lately working on TI DM642 based video systems. And preparing to work on cradle mdsp based systems. Alex From the microblaze uclinux list microblaze-uclinux mailing list microblaze-uclinux@itee.uq.edu.au Project Home Page : http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux Mailing List Archive : http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/ (email addresses deleted) In thread titled "New Digilentinc board" back in April this year. OP was myself. Paul Hartke wrote: Or http://www.crhc.uiuc.edu/IMPACT/gsrc/hardwarelab/docs/kernel-HOWTO.html I've already used these helpful references to get a Linux kernel running on the PowerPC405 on the Digilent XUP-V2Pro board. I'm new to ucLinux but it doesn't appear to be much more complicated than the ucLinux steps. Paul Quoting Schunke Jan-Hendrik : Hi Aurash, hi John, We are working with the PPC on virtex2p. You do not need Monta Vista Linux. All you need is denx eldk: http://www.denx.de/twiki/bin/view/DULG/ELDK And the penguin ppc linux distribution: http://www.penguinppc.org/kernel/#developers (we are using the 2.4 Kernel) To get started: http://www.klingauf.de/v2p/index.phtml might be helpful. On the other hand we are also using uClinux on spartan3. It is really a question of what hardware you have and what you want to do ;-) Have Fun JanArticle: 93503
Hi, As a student I'm working on a project which requires us to read a file from a Compact Flash card using the Xilinx SystemACE controller on the XUP V2P developement boards. Because of a bug in our program it ended up in an endless loop, so it never got to the fclose() statement. Now it seamed that the whole CompactFlash filesystem had gone corrupted by this. Now I have tryed many different methods of formatting the Compact Flash card (even used mkdos fs, with its needed arguments) and the card works on any compact flash card reader for pc but for some reason the xup board doesn't want to read from the compact flash card anymore. Has anyone of you encountered that same problem, or maybe knows a solution to this problem? thanks in advance for your help Arne DemmersArticle: 93504
How much was the S3E board? LeonArticle: 93505
"Leon" <leon_heller@hotmail.com> schrieb im Newsbeitrag news:1135334486.716451.7320@f14g2000cwb.googlegroups.com... > How much was the S3E board? > > Leon > Hi Leon, please contact your local Xilinx FAE ASAP, there might be a surprise for you :) Antti PS I contacted nuhorizon regarding the S3e Sample Pack (as they are the only entity who has published any info about the board at the moment) but they did not even care to respond to the email at all, so I guess contacting nu makes no sense, but maybe I am on their blacklist as I have never ever purchased anything from them or even considered that. So others may be more lucky with nu. Anyway I would suggest contacting the Xilinx FAE and not any disti regarding the board.Article: 93506
"Arne Demmers" <arne.demmers@scarlet.be> schrieb im Newsbeitrag news:lcidnUVGeqf8TjbeRVnyrw@scarlet.biz... > Hi, > > As a student I'm working on a project which requires us to read a file > from a Compact Flash card using the Xilinx SystemACE controller on the XUP > V2P developement boards. Because of a bug in our program it ended up in an > endless loop, so it never got to the fclose() statement. Now it seamed > that the whole CompactFlash filesystem had gone corrupted by this. Now I > have tryed many different methods of formatting the Compact Flash card > (even used mkdos fs, with its needed arguments) and the card works on any > compact flash card reader for pc but for some reason the xup board doesn't > want to read from the compact flash card anymore. > Has anyone of you encountered that same problem, or maybe knows a solution > to this problem? > > thanks in advance for your help > > Arne Demmers > checkl first that the systemACE works buy a new CF card format with FAT16 copy a good known .ACE into the root dir insert card check if the FPGA gets configured, then proceed with next steps.. AnttiArticle: 93507
"Antti Lukats" <antti@openchip.org> wrote in message news:dogklm$f2b$02$1@news.t-online.com... > "Leon" <leon_heller@hotmail.com> schrieb im Newsbeitrag > news:1135334486.716451.7320@f14g2000cwb.googlegroups.com... >> How much was the S3E board? >> >> Leon >> > Hi Leon, > > please contact your local Xilinx FAE ASAP, there might be a surprise for > you :) > > Antti > > PS I contacted nuhorizon regarding the S3e Sample Pack (as they are the > only entity who has published any info about the board at the moment) but > they did not even care to respond to the email at all, so I guess > contacting nu makes no sense, but maybe I am on their blacklist as I have > never ever purchased anything from them or even considered that. So others > may be more lucky with nu. Anyway I would suggest contacting the Xilinx > FAE and not any disti regarding the board. Unlucky for those of us not in Europe , US or Japan then. Same as with <http://www.em.avnet.com/spc/home/0,1727,RID%253D0%2526CID%253D27914%2526CCD%253DUSA%2526SID%253D4745%2526DID%253DDF2%2526LID%253D0%2526BID%253DDF2%2526CTP%253DSPC,00.html> See bottom of that page. ADDS-BFFPGA-EZEXT is a nice addon to the Analog Blackfin Ezkits (S31000 not S3e) if you were lucky enough to pick up the Ezkit at US$99 when they first came out a year or so back(now US$450) <http://www.analog.com/en/epHSProd/0,,BF-EXTENDERFPG,00.html> <http://www.analog.com/processors/epManualsDisplay/0,2795,,00.html?SectionWeblawId=207&ContentID=87691&Language=English> Blackfin stamps are currently cheapest dsp boards around (digikey) http://www.analog.com/en/epHSProd/0,,BF533-STAMP,00.html http://www.analog.com/en/prod/0,2877,BF537%252DSTAMP,00.html http://blackfin.uclinux.org/ Similar but lot priceier (for TI DM642 EVM dsp board) uses a SX4 <http://www.spectrumdigital.com/product_info.php?cPath=33&products_id=174&osCsid=7ebc2584cab24a47e0e2fac9f1c689a3> AlexArticle: 93508
"Leon" <leon_heller@hotmail.com> schrieb im Newsbeitrag news:1135334486.716451.7320@f14g2000cwb.googlegroups.com... > How much was the S3E board? > > Leon > things are moving on, I wasnt sure if it was ok to say that the board is FREE, but as Avnet has said that in public so its public info now. The boards are ready for customers, just need to contact whoever is responsible for you as FAE/Disti. Antti http://xilant.com/content/category/4/81/55/ reviews of 2 different Spartan3e based boards (the sample pack review will be heavily updated over this weekend) http://xilant.com/content/view/28/51/ standalone programming and test utility for the s3e sample pack internal beta test at the moment, will be available shortlyArticle: 93509
On 2005-12-23, Antti Lukats <antti@openchip.org> wrote:
>> Hey guys, does anyone know where I can get VHDL/Verilog source for the
>> Z8001/Z8002 processor?
>
> yes, sure!
> www.zilog.com
So you're stating that Zilog has VHDL/Verilog for the Z8000
processor and it's available to the public?
--
Grant Edwards grante Yow! All of life is a blur
at of Republicans and meat!
visi.com
Article: 93510"Grant Edwards" <grante@visi.com> schrieb im Newsbeitrag news:11qo23re0afujbc@corp.supernews.com... > On 2005-12-23, Antti Lukats <antti@openchip.org> wrote: > >>> Hey guys, does anyone know where I can get VHDL/Verilog source for the >>> Z8001/Z8002 processor? >> >> yes, sure! >> www.zilog.com > > So you're stating that Zilog has VHDL/Verilog for the Z8000 > processor and it's available to the public? > I suppose, if you buy 51% of Zilog stock then its public for you :) I stated where to get - not the amount of $$$ that is needed. AnttiArticle: 93511
"Jan Panteltje" <pNaonStpealmtje@yahoo.com> ha scritto nel messaggio news:do4ia4$mc4$1@news.datemas.de... > On a sunny day (Sun, 18 Dec 2005 21:22:17 +0100) it happened Markus Knauss > <markus.knauss@gmx.net> wrote in <do4gc9$7rc$1@online.de>: > >>Karl wrote: >>> This should fit your needs.... >>> >>> http://altera.com/education/univ/materials/boards/unv-de2-board.html >> >>Hi Karl, >> >>thanks for the hint, I didn't find this board on the altera website yet. >> >>Unfortunately, it has no composite video output, but vga output. >>For composite video output, you usually need a video encoder chip. >> >>I think that this can't be used as a composite color video (FBAS) output. >> >>But if I don't find a board with video out, I will take this one >>and add a video encoder on a separate board. >> >>Thanks! >> >>Markus > What makes you think that you could not use one of the RGB 10bit DA > channels > for FBAS out (composite?) composite is only 1 Vpp (in Europe). > On opencores.org IIRC there is even a PAL modulator. > Not sure if it will fit with that clock. Take a look at the website of http://www.altera.com/corporate/cust_successes/customer_showcase/csh-seventech_lp.html http://www.seventech.it/english/merlinoboard/3/2.php and the demo code this board http://www.seventech.it/english/merlinosdk/3/2.phpArticle: 93512
> >>> Hey guys, does anyone know where I can get VHDL/Verilog source for the > >>> Z8001/Z8002 processor? > >> > >> yes, sure! > >> www.zilog.com > > > > So you're stating that Zilog has VHDL/Verilog for the Z8000 > > processor and it's available to the public? > > > I suppose, if you buy 51% of Zilog stock then its public for you :) > > I stated where to get - not the amount of $$$ that is needed. > > Antti > > The Z8000 was designed before Verilog existed. I doubt that they still even have the schematics. The Z8002 is available in Verilog from www.systemyde.com , but it's not free. (But it's significantly cheaper than buying half of Zilog.) MonteArticle: 93513
Hallo, I'm planning to buy a development board based on Virtex-4FX. I have read about V-4FX that ethernet mac is inside the FPGA. I should buy also the license to use it when I make a project into EDK for plb interface? Many Thanks MarcoArticle: 93514
Hello, I am starting to work on Spartran FPGA. and most of my work will be related to image processing. I never worked with xilinx chips and webpack before. So, would any one advice me that does xilinx offers any image processing libraries ( for VHDL ) like for example MATLab does and any sample code or example to use those libraries in VHDL coding. Please advice! Thanks Regards JohnArticle: 93515
"Antti Lukats" <antti@openchip.org> schreef in bericht news:dogku2$ia2$01$1@news.t-online.com... > "Arne Demmers" <arne.demmers@scarlet.be> schrieb im Newsbeitrag > news:lcidnUVGeqf8TjbeRVnyrw@scarlet.biz... >> Hi, >> >> As a student I'm working on a project which requires us to read a file >> from a Compact Flash card using the Xilinx SystemACE controller on the >> XUP V2P developement boards. Because of a bug in our program it ended up >> in an endless loop, so it never got to the fclose() statement. Now it >> seamed that the whole CompactFlash filesystem had gone corrupted by this. >> Now I have tryed many different methods of formatting the Compact Flash >> card (even used mkdos fs, with its needed arguments) and the card works >> on any compact flash card reader for pc but for some reason the xup board >> doesn't want to read from the compact flash card anymore. >> Has anyone of you encountered that same problem, or maybe knows a >> solution to this problem? >> >> thanks in advance for your help >> >> Arne Demmers >> > checkl first that the systemACE works > buy a new CF card > format with FAT16 > copy a good known .ACE into the root dir > insert card > check if the FPGA gets configured, > > then proceed with next steps.. > > Antti > Thanks for your fast anwer, but have tried an other CF card and then it worked again, untill we came up with a similar loop problem in our code, and the file system was corrupted again. Btw, at this moment We're not using the CF card to configure our device, just as a medium were we can read some data (.jpg in our case) Greets, ArneArticle: 93516
"john" <conphiloso@hotmail.com> schreef in bericht news:1135354501.554630.199210@f14g2000cwb.googlegroups.com... > Hello, > > I am starting to work on Spartran FPGA. and most of my work will be > related to image processing. I never worked with xilinx chips and > webpack before. So, would any one advice me that does xilinx offers any > image processing libraries ( for VHDL ) like for example MATLab does > and any sample code or example to use those libraries in VHDL coding. > > Please advice! > > Thanks > Regards > John > As far as I know, xilinx doesn't offer image processing tools, however I recently I found this link to a VHDL jpeg encoding library http://www.opencores.org/projects.cgi/web/jpeg/overview Have fun with it Greets ArneArticle: 93517
"Arne Demmers" <arne.demmers@scarlet.be> schrieb im Newsbeitrag news:m-Kdnbmdj-ravjHeRVny1w@scarlet.biz... > > "Antti Lukats" <antti@openchip.org> schreef in bericht > news:dogku2$ia2$01$1@news.t-online.com... >> "Arne Demmers" <arne.demmers@scarlet.be> schrieb im Newsbeitrag >> news:lcidnUVGeqf8TjbeRVnyrw@scarlet.biz... >>> Hi, >>> >>> As a student I'm working on a project which requires us to read a file >>> from a Compact Flash card using the Xilinx SystemACE controller on the >>> XUP V2P developement boards. Because of a bug in our program it ended up >>> in an endless loop, so it never got to the fclose() statement. Now it >>> seamed that the whole CompactFlash filesystem had gone corrupted by >>> this. Now I have tryed many different methods of formatting the Compact >>> Flash card (even used mkdos fs, with its needed arguments) and the card >>> works on any compact flash card reader for pc but for some reason the >>> xup board doesn't want to read from the compact flash card anymore. >>> Has anyone of you encountered that same problem, or maybe knows a >>> solution to this problem? >>> >>> thanks in advance for your help >>> >>> Arne Demmers >>> >> checkl first that the systemACE works >> buy a new CF card >> format with FAT16 >> copy a good known .ACE into the root dir >> insert card >> check if the FPGA gets configured, >> >> then proceed with next steps.. >> >> Antti >> > > Thanks for your fast anwer, but have tried an other CF card and then it > worked again, untill we came up with a similar loop problem in our code, > and the file system was corrupted again. > > Btw, at this moment We're not using the CF card to configure our device, > just as a medium were we can read some data (.jpg in our case) > > Greets, > Arne > get winhex program and check the card afer it gets unreadable maybe it gives a clue whats up AnttiArticle: 93518
Hi, Put a pull-down on CKE pin that would make CKE low when power is up and DONE pin of FPGA is low. That will make sure that there are no unstable conditions for the DDR chip. WengArticle: 93519
Hi,
Your problem is here:
if clk_50mhz'event and clk_50mhz = '1' then -- main clock
if input_clk_prev = '0' and input_clk = '1' then
-- input clock detected. sample the data
end if;
input_clk_prev <= input_clk;
end if;
They should change to the following code:
if clk_50mhz'event and clk_50mhz = '1' then -- main clock
if input_clk_prev_R = '0' and input_clk_R = '1' then
-- input clock detected. sample the data
end if;
input_clk_R <= input_clk;
input_clk_prev_R <= input_clk_R;
end if;
Never use any asynchronous input signal in your design directly.
All asynchronous input signals must be registered and their registered
data can be used in your design.
Weng
You must use 50MHz clock to latch them, then their latched registered
values should replace the above two data.
...
elsif(
Article: 93520Antti Lukats wrote: > Hi > > I am having extreme trouble with ChipScope and Spartan3e (using the > Spartan3E Sample Pack PCB from digilent). > > ISE 7.1 sample top, CS coregen, ICON+VIO wired up build, then: > 1 First I tried CS 7.1SP2, no cores found... > 2 tested with CS analyzer 7.1SP4, no cores found... > 3 then regenerated the ICON+VIO with 7.1SP4, cores found, I am happy. > 4 then ISE clean, rebuild, no cores found... > 5 regenereting the ICON+VIO with CS 8.1 no cores found... > 6 updating the project to ISE 8.1, cores found, I am happy > 7 ISE clean, rebuild, no cores found.. > 8 what should I do next? I never instantiate ChipScope in the design. I always use the ChipScope Core Inserter. Making changes to what you wish to probe is a lot easier this way. I've noticed that, at least with Spartan 2E, you can't configure the chip from within ChipScope. It always fails. I use Impact to program the configuration EEPROM, then power-cycle the board, then reconnect ChipScope. When ChipScope works, it's the shit. When it doesn't, lots of cursing ensues ... -aArticle: 93521
The Z8000 was designed at the transistor level by Shima, who also had designed the 4004, 8008, 8080, and Z80. No logic diagram existed when I got involved in the transfer to second-source AMD. Those were the days..(1979/80). Hi, Monte! Peter AlfkeArticle: 93522
>I found the RTL schematic viewer - though I sitll am not sure what RTL >stands for. google works pretty well for that sort of problem. If you can't find something interesting right away, add acronym to the search list. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 93523
"Peter Alfke" <alfke@sbcglobal.net> wrote in message news:1135359654.384929.210170@g49g2000cwa.googlegroups.com... > The Z8000 was designed at the transistor level by Shima, who also had > designed the 4004, 8008, 8080, and Z80. No logic diagram existed when I > got involved in the transfer to second-source AMD. > Those were the days..(1979/80). Hi, Monte! > Peter Alfke > Hello Peter, long time no see! Yes, Shima's schematics were a nightmare to try to understand, given that he only drew transistors, and there were only signal names for signals that left a sheet. But if you laid the schematic sheets out so that the signals matched up, you had a complete floorplan of the device. And the transistors on the sheets were good guides for the layout designers when they were doing the layout, because the "density" of schematic transistors was relatively proportional to the layout density. Not like today, when I can describe a few thousand transistors in a couple of pages of Verilog code... I doubt that those schematics survive though, as they predated the era of document control at Zilog. MonteArticle: 93524
"Andy Peters" <Bassman59a@yahoo.com> schrieb im Newsbeitrag news:1135359469.557185.162020@g44g2000cwa.googlegroups.com... > Antti Lukats wrote: >> Hi >> >> I am having extreme trouble with ChipScope and Spartan3e (using the >> Spartan3E Sample Pack PCB from digilent). >> >> ISE 7.1 sample top, CS coregen, ICON+VIO wired up build, then: >> 1 First I tried CS 7.1SP2, no cores found... >> 2 tested with CS analyzer 7.1SP4, no cores found... >> 3 then regenerated the ICON+VIO with 7.1SP4, cores found, I am happy. >> 4 then ISE clean, rebuild, no cores found... >> 5 regenereting the ICON+VIO with CS 8.1 no cores found... >> 6 updating the project to ISE 8.1, cores found, I am happy >> 7 ISE clean, rebuild, no cores found.. >> 8 what should I do next? > > I never instantiate ChipScope in the design. I always use the > ChipScope Core Inserter. Making changes to what you wish to probe is a > lot easier this way. > > I've noticed that, at least with Spartan 2E, you can't configure the > chip from within ChipScope. It always fails. I use Impact to program > the configuration EEPROM, then power-cycle the board, then reconnect > ChipScope. > > When ChipScope works, it's the shit. When it doesn't, lots of cursing > ensues ... > > -a > shit when works and cursing when not? That was a typo I guess :) well you can not use core inserter for the VIO, so thats no option. I dont know why you can not configure with chipscope, the way you do it is very troublesome. be aware that chipscope does not auto fix the startup clock so if the clock wasnt set to JTAG in the bitgen option then chipscope want of course configure. Antti
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