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Peter Alfke wrote: > Let me clarify: > Intel developed and designed the 4004, then 8008, which evolved into > the 8080. Then there ws the race to 16 bits: Intel 8086, Motorola > 68000, and Zilog Z8000. > Intel also made an economy-version of the 8086, called 8088 (8-bit bus > insted of 16-bit), and IBM picked this intel 8088 for their PC. IBM was > not in the commodity microprocessor business in those days, and IBM > never manufactured 8086-like chips. They did! There were several 386 and 486 level chips designed and manufactured by IBM based on the agreement with Intel. IBM 386SLC, 486SLC and 486BL series are the examples. The chips carried Intel's and IBM's copyrights and incorporated a reasonable amount of cache. I still have some PS/2 computers with IBM 486SLC2 and SLC3 CPUs inside. Then IBM served several x86 companies as chip foundry. They did it at least for NexGen, Cyrix and AMD.Article: 93551
I have used other VHDL simulators, but I am now trying to run the Xilinx ISE simulator in Foundation 7.1 for the first time. As you can see below, I'm not having much success. I get the following message: Compiling vhdl file "<expunged path>Match8.vhd" in Library work. Entity <match8> compiled. Entity <match8> (Architecture <behavior>) compiled. Parsing "match8_lau.prj": 0.73 ERROR:Simulator:222 - Generated C++ compilation was unsuccessful Codegen UNISIM/VPKG: 0.13 Codegen UNISIM/VPKG: 0.09 Codegen UNISIM/VPKG: 0.09 Codegen UNISIM/VPKG: 0.11 Codegen UNISIM/VPKG: 0.11 Codegen unisim/VPKG: 0.11 Codegen unisim/VPKG: 0.09 ERROR:Simulator:222 - Generated C++ compilation was unsuccessful Codegen UNISIM/VCOMPONENTS: 0.03 Codegen UNISIM/VCOMPONENTS: 0.00 Codegen unisim/SRLC16E: 0.00 Codegen unisim/SRLC16E: 0.02 Codegen unisim/SRLC16E: 0.00 Codegen unisim/MUXCY: 0.00 Codegen unisim/MUXCY: 0.01 Codegen work/MATCH8: 0.00 ERROR:Simulator:222 - Generated C++ compilation was unsuccessful Codegen unisim/SRLC16E/SRLC16E_V: 0.02 Codegen unisim/SRLC16E/SRLC16E_V: 0.00 ERROR:Simulator:222 - Generated C++ compilation was unsuccessful Codegen unisim/MUXCY/MUXCY_V: 0.00 Codegen unisim/MUXCY/MUXCY_V: 0.00 ERROR:Simulator:222 - Generated C++ compilation was unsuccessful Codegen work/MATCH8/BEHAVIOR: 0.01 ERROR: Fuse failed When trying to simulate a simple 8 bit identity comparator that is known to work fine. Basically no matter what code I try to simulate, I get the ERROR: Simulator:222 error. It looks that something very basic is wrong, like some environment setting, but I have found no information on this error anywhere. The code compiles into a bitstream without any problems, and the VHDL syntax checker works fine, it just doesn't want to simulate. Any suggestions would be greatly appreciated. Thanks Chris JohnsonArticle: 93552
<mail@deeptrace.com> schrieb im Newsbeitrag news:1135419786.208624.11930@f14g2000cwb.googlegroups.com... >I have used other VHDL simulators, but I am now trying to run the > Xilinx ISE simulator in Foundation 7.1 for the first time. As you can > see below, I'm not having much success. the ISIM is useable for some applications and there is nothing special required to have it working. if you send me the code that fails I can check with 8.1 to see if it still fail. I assume the 8.1 simulator is better than the 7.1 one AnttiArticle: 93553
ajcrm125 schrieb:
> How would I be violating anything if I made a Z8000 equivalent design
> in Verilog/VHDL? I mean, if they had source for it, and I tweaked it
> slightly and called it my own, I can see where that crosses the line.
> But reverse engineering a design from its databook and creating a clone
> isn't copyright infringement from what I understand.
> What do you think?
ISAs are not protected under copyright law. (The ISA documents and the
CPU design are, but not the ISA)
The real pitfall are patents. As Peter noted all original pantents
should be invalid by now, but
- there might be some patents that Zilog filed that were only granted
many years later. These might be still alive. Check USPTO in that case.
Sometimes companies threaten people with patents that were granted, but
for which they stop paying patent fees years ago.
- even when building an old school uC you will likely use modern
concepts some of which might be patented by zilog or others.
Companies like to invoke trademarks and trade secrets in the context.
For the former just make sure that you do not use z8000 as the name of
your processor but use it only in a descriptive way. ("Executes z8000 ISA")
For the latter make sure, that you do not know any trade secrets from
zilog. E.g. that you have never signed an NDA for an z8000 errata sheet
or anything like that.
I would not worry too muc, but h I agree with Peter that it might be a
good idea to try to get zilog on board. They might like what you do and
provide you with advice, contacts, etc.
Kolja Sulimma
Sidenote:
There is a story about a guy who built an Apple-I clone recently and got
sued by apple. When Steve Wozniak realized that he informed the guy that
he never signed off exclusive rights to apple.
Moral: Never believe a company that threatens you. Allways demand proof.
Article: 93554I got one of the Blackfin EZ-kits when they were on special offer, and one of the Stamp kits. Haven't used them much, though. LeonArticle: 93555
On Fri, 23 Dec 2005 18:20:15 GMT, "Monte Dalrymple" <monted@systemyde.com> wrote: [snipped] >I doubt that those schematics survive though, as they predated >the era of document control at Zilog. > I often wonder how many products never got developed further because of lost documents at companies. Also how many companies can truly recover if somwhow they had to start from scratch with only their documentation in config control. Regards Anton ErasmusArticle: 93556
"Leon" <leon_heller@hotmail.com> wrote in message news:1135429069.663788.187480@g44g2000cwa.googlegroups.com... >I got one of the Blackfin EZ-kits when they were on special offer, and > one of the Stamp kits. Haven't used them much, though. > > Leon Have both boards myself. Using them a bit lately. Working on C6400/DM642 based video systems lately. Find the blackfin boards easier and faster to get things up and running on. The latest book Embedded Media Processing from David Katz and Rick Gentile is quite good but should have gone the next step and given at least a few complete code examples instead of a few snippets. Leaves the book feeling incomplete - difference between a good book and a great book. Useful book with its practical tips. Companian cd only has visualdsp++ and no code examples neither does the books website http://www.theempbook.com/ AlexArticle: 93557
> With the Cesys Spartan3e-500 board we sustained 35MBYTE/second For how long period of time and which driver did you use? DamirArticle: 93558
Has anyone implemented the I2C controller core mentioned in the xapp333 in a FPGA. I have simulated the core to set the address register. and it works in simulation. when i try to that there are problems during synthesis. i think its got something to do with dual INPUTOUTPUT ports. The synthesis tool keeps saying there are multisources and because of which i think something has gone wrong with the DTACK signal and there are problems. I have pasted the part from synthesis report because of which i think the problems arise. meanwhile if anyone else has implemented the I2C controller core and could give me tips it would be really helpful. Thanks in advance vasu WARNING:Xst:2040 - Unit i2c_tb: 8 multi-source signals are replaced by logic (pull-up yes): data_bus<0>, data_bus<1>, data_bus<2>, data_bus<3>, data_bus<4>, data_bus<5>, data_bus<6>, data_bus<7>. WARNING:Xst:2042 - Unit uC_interface: 9 internal tristates are replaced by logic (pull-up yes): data_bus<0>, data_bus<1>, data_bus<2>, data_bus<3>, data_bus<4>, data_bus<5>, data_bus<6>, data_bus<7>, irq. WARNING:Xst:2183 - Unit i2c_control: the following tristate(s) are NOT replaced by logic (Please refer to Answer Record 20048 for more information): scl, sda. WARNING:Xst:1906 - Unit uC_interface is merged (output ports from interface drive multi-sources)Article: 93559
Anton Erasmus wrote: > "Monte Dalrymple" <monted@systemyde.com> wrote: > > [snipped] > >> I doubt that those schematics survive though, as they predated >> the era of document control at Zilog. > > I often wonder how many products never got developed further > because of lost documents at companies. Also how many companies > can truly recover if somwhow they had to start from scratch with > only their documentation in config control. Believe it or not, adequate documentation and control predates the use of computers by a considerable margin. It involved such things as file cabinets with suitably dimensioned drawers to hold original drawings, prepared on paper and mylar, sometimes with India Ink, the use of Ozalid machines, proper parts list, etc. -- "If you want to post a followup via groups.google.com, don't use the broken "Reply" link at the bottom of the article. Click on "show options" at the top of the article, then click on the "Reply" at the bottom of the article headers." - Keith Thompson More details at: <http://cfaj.freeshell.org/google/>Article: 93560
"damir" <dzagar@BRISIsrce.hr> schrieb im Newsbeitrag news:dojl4n$7bo$1@ss405.t-com.hr... >> With the Cesys Spartan3e-500 board we sustained 35MBYTE/second > > For how long period of time and which driver did you use? > > Damir > > > I used the 'cesys API' what they supplied. the bandwith was seen overage 35MB over pretty long time, but I did not do any timeconsuming tasks and there was no other devices on the usb bus either AnttiArticle: 93561
Ok, we are running DSP intensive application on the PC which generates severe load which is probably the reason why data is lost. Damir "Antti Lukats" <antti@openchip.org> wrote in message news:dojls5$4ou$1@online.de... > "damir" <dzagar@BRISIsrce.hr> schrieb im Newsbeitrag > news:dojl4n$7bo$1@ss405.t-com.hr... >>> With the Cesys Spartan3e-500 board we sustained 35MBYTE/second >> >> For how long period of time and which driver did you use? >> >> Damir >> >> >> > > I used the 'cesys API' what they supplied. > > the bandwith was seen overage 35MB over pretty long time, but I did not do > any timeconsuming tasks and there was no other devices on the usb bus > either > > Antti >Article: 93562
"Chuck F. " <cbfalconer@yahoo.com> wrote in message news:D4idnfQAhvXC-TDeRVn-pA@maineline.net... > Anton Erasmus wrote: > > "Monte Dalrymple" <monted@systemyde.com> wrote: > > > > [snipped] > > > >> I doubt that those schematics survive though, as they predated > >> the era of document control at Zilog. > > > > I often wonder how many products never got developed further > > because of lost documents at companies. Also how many companies > > can truly recover if somwhow they had to start from scratch with > > only their documentation in config control. > > Believe it or not, adequate documentation and control predates the > use of computers by a considerable margin. It involved such things > as file cabinets with suitably dimensioned drawers to hold original > drawings, prepared on paper and mylar, sometimes with India Ink, > the use of Ozalid machines, proper parts list, etc. > Oh, the documentation existed, and it was in the control of Shima, the designer. But once he left the company I don't know who, if anyone, inherited his filing cabinet. It wasn't until much later that such design materials were kept in a centralized location with a control number and access/revision control. Even then, sometimes things went in to DC never to be found again, so designers hated to give the original stuff up to DC. MonteArticle: 93563
I suggest that we avoid ambiguous slang exressions in this international newsgroup. Too much danger of miscommunication. Merry Christmas to all. Peter AlfkeArticle: 93564
"Peter Alfke" <alfke@sbcglobal.net> schrieb im Newsbeitrag news:1135443988.491400.119620@g14g2000cwa.googlegroups.com... >I suggest that we avoid ambiguous slang exressions in this > international newsgroup. > Too much danger of miscommunication. > Merry Christmas to all. > Peter Alfke > Hi Peter, right, using shit as s(uper)hit slang can confuse lots of non-english native readers. Merry Christmas ! Antti [shit] I am afraid I have to stop playing with spartan3e for tonight!Article: 93565
"Andy Peters" <Bassman59a@yahoo.com> schrieb im Newsbeitrag news:1135359469.557185.162020@g44g2000cwa.googlegroups.com... > Antti Lukats wrote: >> Hi >> >> I am having extreme trouble with ChipScope and Spartan3e (using the >> Spartan3E Sample Pack PCB from digilent). >> >> ISE 7.1 sample top, CS coregen, ICON+VIO wired up build, then: >> 1 First I tried CS 7.1SP2, no cores found... >> 2 tested with CS analyzer 7.1SP4, no cores found... >> 3 then regenerated the ICON+VIO with 7.1SP4, cores found, I am happy. >> 4 then ISE clean, rebuild, no cores found... >> 5 regenereting the ICON+VIO with CS 8.1 no cores found... >> 6 updating the project to ISE 8.1, cores found, I am happy >> 7 ISE clean, rebuild, no cores found.. >> 8 what should I do next? > > I never instantiate ChipScope in the design. I always use the > ChipScope Core Inserter. Making changes to what you wish to probe is a > lot easier this way. > > I've noticed that, at least with Spartan 2E, you can't configure the > chip from within ChipScope. It always fails. I use Impact to program > the configuration EEPROM, then power-cycle the board, then reconnect > ChipScope. > > When ChipScope works, it's the shit. When it doesn't, lots of cursing > ensues ... > > -a > just to check if it the issue of coregenerator vs core inserter I tested the core inserted flow too same bad luck no cores found AnttiArticle: 93566
I collect classic arcade games and am looking to do a remake of the troublesome Pole Position boardset. I then stumbled on this page: www.fpgaarcade.com and loved the idea. The PPI and PPII boardsets are Z8000 based. -Adam ================ www.onecircuit.com ================Article: 93567
leevv wrote: > No, > Ethernet MAC is hard core and it's free. But, be careful though, there isn't any s/w support for it in EDK yet. Cheers, JonArticle: 93568
How about edif->ngd (using ngdbuild) -> vhd (using netgen)? HTH, Jim <ccon67@netscape.net> wrote in message news:1135278904.039575.269920@g47g2000cwa.googlegroups.com... > Hi all, > > My simple question, is there any tools to auto-generate a vhdl > instantiate template from the netlist file? > > I found an inefficient way by using the ECS :( > > 1) generate ECS symbol from edif, not good, take time to modify bus > format on symbol pins > 2) generate template from symbol > > Many thanks, >Article: 93569
"Jon Beniston" <jon@beniston.com> schrieb im Newsbeitrag news:1135448073.839625.134430@g49g2000cwa.googlegroups.com... > > leevv wrote: >> No, >> Ethernet MAC is hard core and it's free. > > But, be careful though, there isn't any s/w support for it in EDK yet. > > Cheers, > Jon > Thanks Jon, I was sure EDK supports the hardcore EMAC - but afer looking closer it seems that there is no support in edk7.1 :( any info if it is included in EDK 8.1 ? or is it coming in some EDK 8.1 service pack (like DDR2 support) ? AnttiArticle: 93570
Bill Giovino wrote:
> http://Microcontroller.com/Embedded.asp?did=142
>
> I'm taking a fast short survey of Microchip users to help decide what future directions
> development tools should take. The survey is confidential - I don't even ask for your
> email address, O.K.?
>
> It's only 11 short questions that take less than a minute. Unless you really want
> to get opinionated ("Embedded Developers opinionated?!?? Nah!!!") in which case, go
> ahead, "comment" to your heart's content...!
>
> http://Microcontroller.com/Embedded.asp?did=142
>
> I'm basically trying to figure out whose development tools are completely reliable, and
> whose tools really suck. And it's your opportunity to say whatever you want to say -
> really!
>
> If you have problems or praise, for any toolkit, TELL ME NOW or forever hold your, uh,
> peace...
>
> Thanks for your support,
>
> - Bill Giovino
> Executive Editor
> http://Microcontroller.com
> "Stamping out Shoddy Tools since 1995"
>
>
>
For what it's worth I looked at your questionare and gave you some
input. Now for one more bit of input...
I prefer to develop software using tools hosted under Linux rather than
that 'other OS' made by a large company in Redmond WA.
Article: 93571I see,But I need the softcore,and the the softcore provided by xilinx or altera or the third party are too expensive,and there are no the associate projects in the opencores website.Article: 93572
Hi all, I want to buy some chips of Altera Cyclone to do some experiments, but before I proceed, I can't find any reference desing/smallest system available on Altera's website. For example, the datasheet doesn't include the smallest system for me to run with! Anyone can tell me how to find it? Thanks in advance. ABAIArticle: 93573
Hi Tim,
I will second your opinion about PCI bus.
My company Brace Design Solutions did the "like hand building a car,"
and developed a PCI IP core from scratch.
And I agree with you that it was not a trivial project.
The project itself was further complicated by the fact that the PCI IP
core we developed had to be Xilinx LogiCORE PCI compatible pretty much
cycle by cycle.
Obscure features of Xilinx LogiCORE PCI needed to be implemented and
tested against the original.
We finally finished the project, and Verilog version of BDS XPCI PCI IP
core is now available for as little as $100 for non-profit personal use.
VHDL port is continuing, and should be done in a few weeks.
I also agree with your comment that making sure that the PCI IP core
works properly in all unusual corner cases is not easy, and requires a
PCI testbench that is far more elaborate than what most FPGA vendors'
provide with their PCI IP core.
BDS XPCI PCI IP core purchaser gets the same PCI testbench we used for
the verification of the PCI IP core, and is more elaborate than Xilinx's
Ping reference design's testbench.
Looking at the PCI Express specification (Ver. 1.0a), I think
PCI Express has taken the difficulty of developing an I/O (or bus)
interface to a new level.
Not only is the specification longer, the protocol of PCI Express seems
a lot more complicated than the Conventional PCI or even PCI-X.
Another problem of PCI Express I think is the cost of the equipment.
From what I understand, PCI Express requires a bleeding-edge
oscilloscope which normally cost around $60,000, plus around $10,000 for
four FET probes.
Wow, at that cost, one can buy two $35,000 luxury cars for the cost of
one small oscilloscope and several FET probes.
In addition to that, a protocol analyzer is required to understand the
protocol, and that is likely going to cost another nice $20,000 to $30,000.
I will appreciate if someone can confirm the equipment cost of
developing a PCI Express devices, but I suppose it can be lowered
somewhat by leasing the equipment rather than outright buying them.
I guess I don't like the idea of a lease, but perhaps that the only way
to get the equipment in some cases.
Perhaps, this $100,000 minimum (In practice much larger if other costs
like personnel cost is counted.) is the reason why there are so few
companies except for graphic card vendors sell PCI Express cards.
Kevin Brace
Tim Wescott wrote:
> bjzhangwn wrote:
>
>> I wanna to write a pci express endpoint ,and I don't have a idea that
>> if this is too difficult,But the ipcore from the fpga vendor are too
>> expensive!can someone give me some advice!
>>
> I worked on a project not too long ago that involved a PCI (not PCI
> express) core in a Xilinx. I got to look over the shoulder of the guy
> making it all work. We had purchased a PCI core from Xilinx, but he had
> developed PCI cores in the past so he was a real expert.
>
> It was _not_ a trivial project.
>
> The PCI spec covers a lot of ground.
>
> Taking care of all the corner cases takes a lot of work.
>
> Even putting everything into the FPGA to provide the proper care and
> feeding for the PCI core in such a way that the bus could provide the
> speed that we needed wasn't trivial.
>
> In my opinion hand-building a PCI core would be like hand building a car
> -- it's possible, but it's not worth the time.
>
> The only exception would be if you could be absolutely sure that your
> project is only going to use a specific subset of the spec, and that you
> are free to violate unused parts. I wouldn't touch this with a 10 foot
> pole, and there are very few folks that I would trust to "trim" such a
> complex spec.
>
--
Brace Design Solutions
Xilinx (TM) LogiCORE (TM) PCI compatible BDS XPCI PCI IP core available
for as little as $100 for non-commercial, non-profit, personal use.
http://www.bracedesignsolutions.com
Xilinx and LogiCORE are registered trademarks of Xilinx, Inc.
Article: 93574Hi bjzhangwn, Take a look at the reply I made to Tim Wescott. My estimated cost of developing a PCI Express IP core is at least $90,000 ($60,000 for bleeding-edge oscilloscope, $10,000 for four FET probes, and $20,000 to $30,000 for PCI Express protocol analyzer.), and is probably more in practice. Assuming that you wanted to do your own PCB, that's probably another $30,000 to $40,000. (PCB CAD tool + signal integrity analysis tool like HyperLynx.) My guess regarding the high cost of PCI Express IP cores is partially due to the fact that developers need to recover the large investment they made in the equipment, and that pushes up the cost of the IP core. If PCI Express is too expensive to for you, you always got BDS XPCI PCI IP core which can be purchased (licensed) for as little as $100 for non-profit personal use. Visit http://www.bracedesignsolutions.com for more information. Kevin Brace bjzhangwn wrote: > I see,But I need the softcore,and the the softcore provided by xilinx > or altera or the third party are too expensive,and there are no the > associate projects in the opencores website. > -- Brace Design Solutions Xilinx (TM) LogiCORE (TM) PCI compatible BDS XPCI PCI IP core available for as little as $100 for non-commercial, non-profit, personal use. http://www.bracedesignsolutions.com Xilinx and LogiCORE are registered trademarks of Xilinx, Inc.
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