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Hi does anybody have some experience with DVI output using Chrontel DVI transmitter (CH7301) the DVI transmitter works in analog RGB bypass mode OK, I see a pong game on analog monitor but in DVI mode there is nothing on the output, even DVI Clock is missing, DVI hotplug detect works, eg the DVI transmitter shuts down when I unplug the connector except that I can see nothing that tells me anything why the DVI transmitter is not sending anything. All voltage levels seems to correct, the bias voltages are ok, XCLK is 25MHz H/V Sync DE I think are also valid. Chrontel datasheet doesnt tell much, I have set the DVI power control bits to active, and there doesnt seem to be any secret sequence to enable the DVI output Antti PS if someone is able to provide consulting help that helps me to get the CH7301 working I may be able arrange a free eval board with CH7301+V4 as thank you gift. At least I will do my best to arrange it.Article: 93851
>"Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag >news:dpavmu$cb$01$1@news.t-online.com... > Hi > > does anybody have some experience with DVI output using Chrontel DVI > transmitter (CH7301) > > the DVI transmitter works in analog RGB bypass mode OK, I see a pong game > on analog monitor > > but in DVI mode there is nothing on the output, even DVI Clock is missing, > DVI hotplug detect works, eg the DVI transmitter shuts down when I unplug > the connector except that I can see nothing that tells me anything why the > DVI transmitter is not sending anything. All voltage levels seems to > correct, the bias voltages are ok, XCLK is 25MHz H/V Sync DE I think are > also valid. > > Chrontel datasheet doesnt tell much, I have set the DVI power control bits > to active, and there doesnt seem to be any secret sequence to enable the > DVI output > > Antti > > PS if someone is able to provide consulting help that helps me to get the > CH7301 working I may be able arrange a free eval board with CH7301+V4 as > thank you gift. At least I will do my best to arrange it. > > comments to myself - need to learn to use DSO the DVI output signals are there just with a small swing about 180mV peak to peak when the clock mode is set to DDR the I see DVI clock twice the XCLK, when single clock edge mode then the XCLK is seen as DVI clock what sounds proper, also the DVI data lines have something on them what looks like it should like (when using 500MHz bandwith DSO) DVI monitor still fails to detect signal, so something is still too badly wrong, but at least I know there is some signal going out so it makes sense to proceed. anway if there is some trick or advice that helps to get valid DVI out I am all ears AnttiArticle: 93852
Hi One thing at practical side. You should remember about simple analog Low-pass filter before A/D converter. If you'll forget it You will be very surprised. It could be that you'll see signals on your spectrum analyzer that you can't hear at all (Nyquist, aliasing...) Good luck. Jerzy GburArticle: 93853
> Is the signal cnt always initiated to "00000000" at start up (or some random > value)? Or do I have to include a reset signal? Should be zeros, but good practise is using reset, to be sure. > What is best, an a > asynchronous reset or a synchronous reset? IMHO Synchronous. Regards Jerzy GburArticle: 93854
XC4VFX12-10SF363CES is 157$ and XC4VFX12-10FF668CES is 189$ at Avnet. When will be available these devices for full production (MGT ?) ? Does anybody know what is the price after full availability at small quantities? thanks,Article: 93855
<yusufilker@gmail.com> schrieb im Newsbeitrag news:1136207858.137060.197400@g43g2000cwa.googlegroups.com... > XC4VFX12-10SF363CES is 157$ and > XC4VFX12-10FF668CES is 189$ at Avnet. > > > When will be available these devices for full production (MGT ?) ? > Does anybody know what is the price after full availability at small > quantities? > > thanks, > 1) SF363 does not support MGTs at all 2) V4 price in low quantity is around 100USD - do not expect to drop much below 3) for full production MGT info contact your FAE (do it now before committing to any design that required MGT funtion) -- Antti Lukats http://www.xilant.comArticle: 93856
Hi Antti, where are the input signals of the Chrontel coming from ? The active clock edge should be around 1 to 1.5 ns later than the other signals edges. I am using the Chrontel for DVI digital and analog output and it works. The image source is a Silicon Image which sends data to an FPGA. In the FPGA the data are converted to DDR signals. Also the clock adjustment is managed in the FPGA. Rgds Andr=E9Article: 93857
<ALuPin@web.de> schrieb im Newsbeitrag news:1136213073.260732.49510@g49g2000cwa.googlegroups.com... >Hi Antti, > >where are the input signals of the Chrontel coming from ? > >The active clock edge should be around 1 to 1.5 ns later than the >other signals edges. > >I am using the Chrontel for DVI digital and analog output and it works. >The image source is a Silicon Image which sends data to an FPGA. >In the FPGA the data are converted to DDR signals. Also the clock >adjustment is managed in the FPGA. > >Rgds >André Hi Andre thanks for fastreply - well I am only about to test an PCB board that 'functional test' so I implemented some video sync generator and then tested it with CH7301 in analog bypass mode, everything fine. I played a little bit with the clock edges, etc. the problem is that as soon as try to see the same signal on DVI monitor it either remains blank or says no signal detected. As much as I understand in order to enable DVI output 0xC0 write to register 0x49 is sufficent (assuming everything else is ok for the analog mode). But what I see exactly nothing. I assume my signal polarities are ok DE active high H/V sync active low my my signal source in FPGA is way off and the monitor doesnt recognize it, but still weird. At the moment I am not even sure if the DVI clock is accepted by the DVI receiver (eg TFT display). a TFT display is not really a good thing to test bring up of an DVI transmitter :( I created a DVI RX active termination emulation board and measured the signals using it, the signal swing is same as if monitor is attached - well it is way below the standard requirements, but maybe my DSO doesnt measure the signal correctly :( at the monent I would be very happy to have 1) known good DE+h/v sync generator IP that generates valid signals for DVI output to be accepted by the monitor or I can try to check my signal timings and adjust them and hope that one day the monitor will accept the signals AnttiArticle: 93858
Look at the data sheet: The FX12 are the only devices in the FX family that have no MGTs, But they have a PPC microprocessor. The smallest device with MGTs is the FX20. Peter Alfke, from home.Article: 93859
What frequency / resolution are you working with ? Rgds Andr=E9Article: 93860
<ALuPin@web.de> schrieb im Newsbeitrag news:1136217553.293210.133940@g43g2000cwa.googlegroups.com... What frequency / resolution are you working with ? Rgds André basic VGA, 25MHz XCLK after some more testing 1) if I turn monitor off then on again, it remains ON (no auto power off) and does not display loss of signal 2) when I then write 0x00 to 0x49 shutting down the DVI output then monitor does respond with 'loss of signal' so I assume my sync/de signals are messed up - will be fighting again tomorrow AnttiArticle: 93861
> What is best, an a > asynchronous reset or a synchronous reset? That depends. I tend to keep most of my critical logic synchronous, i.e. master state machines, chip enable circuits, etc. But too many modules with reset edge sensitivity can result in timing problems. Lots of synchronous resets throughout a design, in my experience, can cause quite a bit of headache with already tightly-timed designs. I find it best to analyze what portions of a circuit don't really need synchronous resets, and keep them asynchronous. Julian Kain www.juliankain.comArticle: 93862
Dan NITA wrote:
> Hi,
>
> I'm doing a Post-Route Simulation simulation in ModelSim V6.1a and having
> problem with physical paths delays.
http://groups.google.com/groups?q=no+sdf+sim+routed+netlist+needed
-- Mike Treseler
Article: 93863bill wrote: > Hello > > > > Must I always include an reset signal to force all used flip flops to a zero > condition? <snip> > The FPGA that I'm using is a Spartan 3. Before too many people say "yeah, sure, everything's always zero" keep in mind that without the asynchronous reset in your design the synthesizer may feel free to implement more compact logic using the synchronous set and reset in your registers. This will still leave you with 0 startup values for all *reset* registers but those registers that are implemented with synchronous *set* functions will initialize to a LOGIC 1. I have spent time in my code getting the synthesis initial values to match up with the reset-free design's implementation, using xilinx INIT=R attributes for FDS or FDSE primitives that should be reset at startup and INIT=S values for the FD, FDR, FDRS, FDE, FDRE, AND FDRSE registers that neede to initialize to a logic 1. As a Verilog designer I can now take advantage of initial assignments when I declare a register in *some* synthesizers where the reg [7:0] counter = 8'h2f; declaration will set the initial-state for the individual counter bits different than the '00 that should end up there without the initial assignment. XST does this, Synplify does not. XST may not be perfect at this (a register that should have been one SRL broke into several SRLs, one for each binary-one initial value) but may have tweaked the implementation since last I looked into the issue. So, beware the synchronous set when you don't use the INIT attribute.Article: 93864
Hi, This code is not working for me (nothing is shown in hyperterm). Could someone tell me any possible errors? //------------------------------------------------- // RS-232 TX module // (c) fpga4fun.com KNJN LLC - 2003, 2004, 2005 //`define DEBUG // in DEBUG mode, we output one bit per clock cycle (useful for faster simulations) //`define RegisterInput // in RegisterInput mode, the input doesn't have to stay valid while the character is been transmitted module async_transmitter(clk, TxD_start, TxD_data, TxD, TxD_busy); input clk, TxD_start; input [7:0] TxD_data; output TxD, TxD_busy; parameter ClkFrequency = 25000000; // 25MHz parameter Baud = 115200; // Baud generator parameter BaudGeneratorAccWidth = 16; reg [BaudGeneratorAccWidth:0] BaudGeneratorAcc; `ifdef DEBUG wire [BaudGeneratorAccWidth:0] BaudGeneratorInc = 17'h10000; `else wire [BaudGeneratorAccWidth:0] BaudGeneratorInc = ((Baud<<(BaudGeneratorAccWidth-4))+(ClkFrequency>>5))/(ClkFrequency>>4); `endif wire BaudTick = BaudGeneratorAcc[BaudGeneratorAccWidth]; wire TxD_busy; always @(posedge clk) if(TxD_busy) BaudGeneratorAcc <= BaudGeneratorAcc[BaudGeneratorAccWidth-1:0] + BaudGeneratorInc; // Transmitter state machine reg [3:0] state; wire TxD_ready = (state==0); assign TxD_busy = ~TxD_ready; always @(posedge clk) case(state) 4'b0000: if(TxD_start) state <= 4'b0001; 4'b0001: if(BaudTick) state <= 4'b0100; 4'b0100: if(BaudTick) state <= 4'b1000; // start 4'b1000: if(BaudTick) state <= 4'b1001; // bit 0 4'b1001: if(BaudTick) state <= 4'b1010; // bit 1 4'b1010: if(BaudTick) state <= 4'b1011; // bit 2 4'b1011: if(BaudTick) state <= 4'b1100; // bit 3 4'b1100: if(BaudTick) state <= 4'b1101; // bit 4 4'b1101: if(BaudTick) state <= 4'b1110; // bit 5 4'b1110: if(BaudTick) state <= 4'b1111; // bit 6 4'b1111: if(BaudTick) state <= 4'b0010; // bit 7 4'b0010: if(BaudTick) state <= 4'b0011; // stop1 4'b0011: if(BaudTick) state <= 4'b0000; // stop2 default: if(BaudTick) state <= 4'b0000; endcase `ifdef RegisterInput reg [7:0] TxD_dataD; always @(posedge clk) if((state==0) & TxD_start) TxD_dataD <= TxD_data; `else wire [7:0] TxD_dataD =TxD_data; `endif // Output mux reg muxbit; always @(*) case(state[2:0]) 3'd0: muxbit <= TxD_dataD[0]; 3'd1: muxbit <= TxD_dataD[1]; 3'd2: muxbit <= TxD_dataD[2]; 3'd3: muxbit <= TxD_dataD[3]; 3'd4: muxbit <= TxD_dataD[4]; 3'd5: muxbit <= TxD_dataD[5]; 3'd6: muxbit <= TxD_dataD[6]; 3'd7: muxbit <= TxD_dataD[7]; endcase // Put together the start, data and stop bits reg TxD; always @(posedge clk) TxD <= (state<4) | (state[3] & muxbit); // register the output to make it glitch free endmodule //------------------------------------------------------------------ Thanks.Article: 93865
"Nial Stewart" <nial@nialstewartdevelopments.co.uk> schrieb im Newsbeitrag news:43b84d3c$0$29577$da0feed9@news.zen.co.uk... > > "Antti Lukats" <antti@openchip.org> wrote in message > news:dp40cs$65f$02$1@news.t-online.com... >> They looked nice but when actually having >> them in my hands, well I instantly wanted to check something out. >> And I did, and I liked the easyness and fun I had, here is the story >> >> http://xilant.com/content/view/33/55/ > > > That's an interesting read Antti, a couple of questions.... > > "Cutting out some pages from an stupid catalog (the normal office paper is > no good). Replacing the paper in Laser printer with the catalog paper." > I added as promised the pictures of the PCB made with that catalog paper trick it really does work, only need to iron pretty well, I wanted it all to be done very quickly so I did rush a little and did not get the maximu possible quality. One geman guy is able to make track-clearance as small as 3 mil using that technology have fun AnttiArticle: 93866
Could someone also list the proper procedure and a checklist for connecting my Spartan-3 FPGA to PC through serial ports and using hyperterm? Thanks in Advance.Article: 93867
It is always nice to see some one to keep their promises, HT-LAB promised to release the CPU86 RTL sources some time in 2006, but actually they did it already late 2005, they really did ! the download is immediatly available: http://xilant.com/component/option,com_remository/Itemid,53/func,fileinfo/id,7/ please READ THE LICENSE in the download archive, the CPU86 is Aladdin License, not pure GPL! I have unfortunatly have not yet have had time to recheck the RTL version of the core, the EDIF worked 'out of box', some info about our test setup with it is here http://xilant.com/content/view/20/55/ Antti PS Hans THANKS zillion times and be my :) with youArticle: 93868
On Sat, 31 Dec 2005 02:30:19 -0500, Mike Frysinger wrote: > On Fri, 23 Dec 2005 18:05:25 +1100, Alex Gibson wrote: >> uclinux for nios2 >> http://www.enseirb.fr/~kadionik/embedded/uclinux/nios-uclinux.html >> http://www.enseirb.fr/~kadionik/embedded/uclinux/HOWTO_compile_uClinux_for_NIOS.html >> >> http://linuxdevices.com/news/NS9386138954.html > > anyone know where i could find *working* and *up-to-date* toolchain > sources for nios2 ? ok, ive created a patch which adds the missing files ... so if people wish to build their own toolchain, you now can :) (1) grab the niosii-gnutools-src-5.1.tgz tarball from altera's website: http://www.altera.com/support/kdb/2000/11/rd11272000_7307.html (2) apply this patch: http://dev.gentoo.org/~vapier/patches/nios2-5.1.patch (3) build ! -mikeArticle: 93869
hello friends, For better security, I am porting a design from Xilinx (Spartan3) to Actel (ProAsic3E). The Actel part is very nice and works great. The only problem i have had is that the design becomes bigger and slower than expected. Now, I do understand that some parts of this design translate to bigger logic on the Actel part. I also understand that the xilinx part was bigger and faster [1], and there are some fundamental differences between xilinx CLBs and actel VersaTiles. What is really confusing however; is that some changes that i was sure will make the design smaller or faster had the opposite effect. and vice versa: some things i considered to be bottlenecks seems to work very nicely on Actel. To put it simple: i don't anymore know what i am doing and it is driving me crazy. obviously, i need to read more on the subject (and i have read a lot of actel docs already). so please enlighten me with all your actel-specific optimizations tricks, general optimizations guidelines and any other information that may be useful. in fact, any material about coding style and area optimization is most welcome. so hit me please with all your wisdom :) -Burns [1] i had to say that so Xilinx people don't accuse me of being an undercover Altera engineer :)Article: 93870
Hi Antti, There is popular saying in China that if you visited the U.S., but have never been in Las Vegas, you would be counted as one who has not visited the U.S. Because Las Vegas is its crown. I have never been in Las Vegas, but no sorry for it. I would like to say if you want to be a real ASIC/FPGA engineer, you must read CPU86. Because it is the Bible in ASIC. It is the birth place of full CPU industry. Thank you, Antti, for the excellent gift for new 2006. WengArticle: 93871
I agree.
Can anybody clarify its partial reconfiguration abilities (or lack
thereof)? The only clear statement I could find wasn't from Actel:
"In addition, Fusion chips will be run-time reconfigurable, capable of
reprogramming some of their functions as often as every clock cycle."
http://www.mdronline.com/watch/watch_Issue.asp?Volname=Issue+%23081505&on=1
The datasheet talks about the "Flash Memory Blocks", but I can't tell
if this includes the configuration data or if it is strictly user
data.
If this is where the configuration data resides, that's great
-- the FMB's are internally accessible through a pretty decent
interface (very ICAP-like).
If not, then:
1. Do you have to completely blank the device in order to change
any part of the lut/routing configuration [like Altera]?
2. Can you alter the configuration data from within the device
(ie without the JTAG port) [like Xilinx]?
3. Can you reconfigure on a cell granularity [like Atmel]?
Article: 93872> I am going to release the source of the Namco customs I have reverse > engineered some time soon, some of them are on the Pole Position board which > may help. Thanks Mike! That will help a ton. :-) -AdamArticle: 93873
burn.sir@gmail.com wrote: > > so hit me please with all your wisdom :) > -Burns > > [1] i had to say that so Xilinx people don't accuse me of being an > undercover Altera engineer :) .."only the paranoid will survive" (Andy Grove) :-) Peter Alfke, watching you from homeArticle: 93874
Hi all, I am new to equalizer and adaptive filter. My tutor told me to minimize a DFE(decision feedback equalizer)'s area while keep its timing. I got a book named "Pipelined Adaptive Digital Filters" by Parhi. But the book seems aim at high speed. Can you recommend some book or paper on this subject? And is there any available C or Matlab code on DFE(decision feedback equalizer)? Best regards, Davy
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