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oh dear, this turned into a X vs A war. who could have known;) for those who are wondering, we switched to actel due to customer request. furthermore, the security requirements are about tamper-proof has nothing to do with piracy. now back to the subject. how much can things like 3-input LUTs and asynch & synch reset and enable influence the design size? what can i do to make things more efficient? -Burns PS. i am a great fan of both CoolRunner-II and Starix II devices. now, only if they could make one bigger and the other one cheaper...Article: 93926
"Martin" <0_0_0_0_@pacbell.net> schrieb im Newsbeitrag news:LEyuf.51362$6e1.22676@newssvr14.news.prodigy.com... > Read the EDID information off the monitor. You'll need a PC with a DVI > port and the utility found here: > http://www.viewsonic.com/support/drivers/driver_information.cfm?product=all&formName=product&key=87 > > Make sure the FPGA is generating timings supported by the monitor you are > using. > Thanks Martin, I may need the EDID tool later, but my issue did turn out to be missing values for the PLL settings in CH7301 as soon as I fixed both my FPGA design did immediatly start to display a picture on the monitor so the display timing wasnt as critically wrong AnttiArticle: 93927
Doesn't your synthesis tool show you the logic blocks used for your code after targeting the FPGA? In our case at school, uscing a Cyclone II FPGA from Altera, Quartus II synthesis tool gives you a graphical output showing you exaclty how much logic, where and routing. Cheers.Article: 93928
Piotr, A simple waveform-based simulator called the "Lattice Logic Simulator" is provided for low-density (ispGDX and CPLD) devices in ispLEVER Starter. If you need HDL simulation I'd recommend downloading a free evaluation license of ModelSim (www.model.com) or Active-HDL (www.aldec.com). Troy Scott Lattice Semiconductor TMEArticle: 93929
"Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag news:dogidn$96c$02$1@news.t-online.com... > Hi > > I am having extreme trouble with ChipScope and Spartan3e (using the > Spartan3E Sample Pack PCB from digilent). > commenting myself - the all story was an power surge damaged FPGA nothing wrong with ChipScope AnttiArticle: 93930
Dan, I don't think the .TWR example is complete since I'd expect to see some additional delay like clock-to-Q of the first synchronous element in the list. But in general I'd expect to see ROUTE delays of the TRACE report that match the INTERCONNECT delays of the SDF. I wonder if the SDF file is simply out of synch with the TRACE report? Or maybe you're overriding the speed grade with TRACE? See Tools > TRACE Options... in the Project Navigator. Also check the SDF setup in ModelSim. See Simulate > Start Simulation... and the SDF tab where you can specify the Min|Typ|Max delay to be applied. Troy Scott Lattice Semiconductor TMEArticle: 93931
"Leon" <leon_heller@hotmail.com> wrote: >Isaac Newton said something like "If I can see further than other >people it is because I am standing on giants' shoulders." [Off Topic] There are a few variations of that quote. The one I like best, and the most appropriate for several companies I have worked for is: "If I can not see further is because I am standing in the footprint of giants" Roberto Waltman [ Please reply to the group, ] [ return address is invalid. ]Article: 93932
hi thanks for the answers on my last post. unfortunatly i stumbled across another problem: has anybody seen this error: Optimizing unit <rs232> ... Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx. Mapping all equations... ERROR:Xst:2035 - Port <CLK> has illegal connection. Port is connected to input buffer and following ports: Port C of instance I_RS232/s_Receiving in unit top with type FDC CPU : 11.25 / 11.76 s | Elapsed : 11.00 / 11.00 s I searched the xilinx answer database but nothing came up. could anybody help me here. i can also post my design if somebody wants to have a look at it. thanks urbanArticle: 93933
Changing to an install path without embeddd spaces got rid of the error. Xilinx says that this problem MAY get fixed in ISE 8.2. mail@deeptrace.com wrote: > Paul Hartke wrote: > > Was the attempt with 8.1 successful? I can try it as well... > > > > Paul > > > > After getting a reply from Xilinx, it turns out that there is a problem > if you install their software in a path that has embedded spaces, such > as "C:\Program Files\Xilinx71". That is where I have it installed. > They suggested that I re-install in a top level (C:\xilinx) directory. > This is rather involved in that I have to re-install it and then > re-install the service pacs. > > As soon as I have done this, I will post whether it fixed the problem. > > ChrisArticle: 93934
<u_stadler@yahoo.de> schrieb im Newsbeitrag news:1136320538.853966.19250@g49g2000cwa.googlegroups.com... > hi > > thanks for the answers on my last post. > unfortunatly i stumbled across another problem: > > has anybody seen this error: > > Optimizing unit <rs232> ... > Loading device for application Rf_Device from file '3s200.nph' in > environment C:/Xilinx. > > Mapping all equations... > ERROR:Xst:2035 - Port <CLK> has illegal connection. Port is connected > to input buffer and following ports: > Port C of instance I_RS232/s_Receiving in unit top with type FDC > CPU : 11.25 / 11.76 s | Elapsed : 11.00 / 11.00 s > > > I searched the xilinx answer database but nothing came up. could > anybody help me here. > i can also post my design if somebody wants to have a look at it. > > thanks > urban > no need to post your desing its a very common problem, you have connection directly to pad and the there is also an IBUF on that pad you need to make sure that all your signals are connected to the output of the IBUF this sometimes happens wen chipscope is connected to wrong net, but there are many other possible cases where it may happen either make sure that you dont instantiate any IBUF at all, or that all of them really are in the toplevel entitity only hm as it clock signal, maybe the best is to have IBUFG in toplevel and connect all your clock signal to the output of ibufg that should take care of the problem, make sure that the clk iopin is only connected to IBUFG input and nowhere else AnttiArticle: 93935
FYI the Xilinx store has been updated with a Feb 2006 date for the s3e starter kit. Ironically the Xilinx front page has a link to 'Buy Your Full-featured Spartan-3E Starter Kit Today'. Oops. cheers, aaron Antti Lukats wrote: > "Joe Chisolm" <nospam@nospam.org> schrieb im Newsbeitrag > news:pan.2005.12.30.19.47.34.190805@nospam.org... > > On Fri, 30 Dec 2005 20:18:53 +0100, Antti Lukats wrote: > > > >>>"Joe Chisolm" <nospam@nospam.org> schrieb im Newsbeitrag > >>>news:pan.2005.12.30.19.11.56.547536@nospam.org... > >>> On Thu, 29 Dec 2005 17:59:50 +0000, John_H wrote: > >>> > > [snip] > >> Hi Joe, > >> > >> you are right - Xilinx kind of promised that "December is the month" ! > >> > >> and oh I know very good that the "year end money" is something that needs > >> to be used, and its really pan if some item that was scheduled to be > >> ordered before the end of the year can not be ordered. > >> > >> you could try there > >> > >> http://www.xilinx.com/s3ediscount > >> > >> but I am afraid it may as well not lead to the actual online entry form > >> :( > > > > Thanks for the link. You are right, the starter kit link just > > takes you to the online store and you cannot order there. > > > > -- > > Joe Chisolm > > Phoenix Arizona USA > > > ok, sorry, > > I landed somewhere where it told me that I need to complete the order if I > proceed, so I cancelled at that point as I did not want to order, so I did > not know if there was actual order entry or not. Sorry - as time is running > out so it seems that there is nothing more todo. > > -- > Antti Lukats > http://www.xilant.comArticle: 93936
<aholtzma@gmail.com> schrieb im Newsbeitrag news:1136322954.012679.169900@g49g2000cwa.googlegroups.com... > FYI the Xilinx store has been updated with a Feb 2006 date for the s3e > starter kit. Ironically the Xilinx front page has a link to 'Buy Your > Full-featured Spartan-3E Starter Kit Today'. Oops. > > cheers, > aaron > Hi Aaron, give them a brake - and read what they write Xilinx frontpage: "Spartan3 logo" - not 3E! "All Spartan3e in Production" - I dont know about 1200 and 1600 but I have s3e 100, 250 and 500 here, so those at least are real > buy A Starterkit - no reference to S3e or immediate availability !! so the front page has been carefully edited :) dont try to read what is not there, there is no "buy s3e kit now", that text isnt there. hum the development board page says s3e starterkit is available Q405 !!! possible Xilinx webmaster is on vaccation (or fired?) and notice that online store doesnt say that the S3e starterkit will be available Feb 2005, it only says 'targetted' meaning : nothing at all Antti http://www.cesys.com seems to be the only vendor selling and shipping s3e500 based boards today, well at a bit higher price than the starterkitArticle: 93937
You might want to look at UltraController-II (XAPP575, http://www.xilinx.com/bvdocs/appnotes/xapp575.pdf) for an example that uses ISE for a PPC based design. However, even in this example EDK is used to compile software source code. - Peter king_azman wrote: > Hi everyone, > > Is there any way for me to start a project on Virtex2Pro utilizing the > PPC405 core using ONLY ISE (i.e. without EDK)? How do we instantiate > the core in VHDL? > > I'm not really keen on using the EDK: (1) Too many 'black-box-wizards' > - I'd like to know what connections are made and how it is connected. > (2) Sometimes when I made some changes to my custom peripheral, the > whole system becomes not usable - you know, the frustration of waiting > for it to rebuild the system only to find it doesn't work AT ALL! > > Ooh.. by the way, I'm using the ML310 development board (XC2VP30). > > Thanks. > > -Azman- >Article: 93938
> what I found reayll cool is the way the XAPP807 uses the User Access > register > to implement a bitstream "bridge" to the PPC405 internal JTAG register todo > the PPC cache loading from the config bitstream More details on this method can be found in XAPP719 (http://www.xilinx.com/bvdocs/appnotes/xapp719.pdf). - PeterArticle: 93939
OK, assume I'm a helpless manager droid and take pity on me. We have some old Xilinx designs that were done under Foundation, so we have one PC that has Foundation installed, and we do occasional tweaks on it. We used schematic entry, so it's inconvenient to move these designs to ISE; let's not debate that here. So we just got a letter from Xilinx, telling us our ISE version "Base X" is being discontinued and will now be called "Foundation", which is confusing as all get-out. And the annual fee will jump from $1495 to $2495, presumably because people are buying too many Xilinx chips and they find that to be annoying. But the same letter says that WebPack 8.1i is free with "no loss of device support or design tools." Q: Is that true? Q: is WebPack something we can download and keep, or is it some sort of java thing that Xilinx can change or kill at any time? Longterm ability to maintain designs is crucial to us. Q: why would anybody pay $2500 a year if the free version is the same? Thanks, JohnArticle: 93940
Top right under "Tech Spotlight" "Buy Your Full-featured Spartan-3E Starter Kit Today" The big graphic block has the Spartan-3 test with 3e production quote. My grumbling is loud. I didn't get any toys for Christmas this year. I'm wondering if a Spartan-4 starter kit (if ever there will be such a thing) would best be produced by one of us newsgroup folks rather than waiting for the dragging feet. Like many others, I can deal with ECNs on the first boards out of the chute so I'm lost with respect to the delay. "Antti Lukats" <antti@openchip.org> wrote in message news:dpeqd1$qa8$1@online.de... > <aholtzma@gmail.com> schrieb im Newsbeitrag > news:1136322954.012679.169900@g49g2000cwa.googlegroups.com... >> FYI the Xilinx store has been updated with a Feb 2006 date for the s3e >> starter kit. Ironically the Xilinx front page has a link to 'Buy Your >> Full-featured Spartan-3E Starter Kit Today'. Oops. >> >> cheers, >> aaron >> > Hi Aaron, > > give them a brake - and read what they write > > Xilinx frontpage: > > "Spartan3 logo" - not 3E! > > "All Spartan3e in Production" - I dont know about 1200 and 1600 but I have > s3e 100, 250 and 500 here, so those at least are real > >> buy A Starterkit - no reference to S3e or immediate availability !! > > so the front page has been carefully edited :) > > dont try to read what is not there, there is no "buy s3e kit now", that > text isnt there. > hum the development board page says s3e starterkit is available Q405 !!! > possible Xilinx webmaster is on vaccation (or fired?) > > and notice that online store doesnt say that the S3e starterkit will be > available Feb 2005, it only says 'targetted' meaning : nothing at all > > Antti > > http://www.cesys.com seems to be the only vendor selling and shipping > s3e500 based boards today, well at a bit higher price than the starterkitArticle: 93941
Generally Foundation has always covered all current devices. Webpack covered most of low end Spartan families. Base-X covered a little bit more than Webpack - all the low end Spartans and a few higher end Virtex. What they have done if the words are correct is moved Webpack a slight notch to cover a few extra devices. There used to be some tools not supplied in Webpack but that difference appears to be gone as here http://www.xilinx.com/ise/devsys_feature_guide.pdf . John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan-3 Board. http://www.enterpoint.co.uk "John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message news:erqlr1d1bvnu2afghc7vnqmhrtvjfm7ab1@4ax.com... > > OK, assume I'm a helpless manager droid and take pity on me. > > We have some old Xilinx designs that were done under Foundation, so we > have one PC that has Foundation installed, and we do occasional tweaks > on it. We used schematic entry, so it's inconvenient to move these > designs to ISE; let's not debate that here. > > So we just got a letter from Xilinx, telling us our ISE version "Base > X" is being discontinued and will now be called "Foundation", which is > confusing as all get-out. And the annual fee will jump from $1495 to > $2495, presumably because people are buying too many Xilinx chips and > they find that to be annoying. > > But the same letter says that WebPack 8.1i is free with "no loss of > device support or design tools." > > Q: Is that true? > > Q: is WebPack something we can download and keep, or is it some sort > of java thing that Xilinx can change or kill at any time? Longterm > ability to maintain designs is crucial to us. > > Q: why would anybody pay $2500 a year if the free version is the same? > > > Thanks, > > John >Article: 93942
John, Email the hotline directly so we can tell you how we support legacy designs like you describe. We are there to support you. AustinArticle: 93943
thanks for the answer!! problem solved! urbanArticle: 93944
On Tue, 03 Jan 2006 14:22:06 -0800, Austin Lesea <austin@xilinx.com> wrote: >John, > >Email the hotline directly so we can tell you how we support legacy >designs like you describe. > >We are there to support you. > >Austin Thanks, but we're doing fine running the old Foundation stuff once in a while when we have to tweak an old 4000 design or something. But if we go to WebPack, will we be able to archive the software and run it five years from now? Or is it a java type thing? And what's the practical difference between the $2500 version and the free stuff? I sure wish this industry had a standard, portable schematic format. Almost any schematic, pcb or fpga, more than a few years old is a hazard. Not even Actel can modify an old Actel/Orcad design. JohnArticle: 93945
John, See answer 2 on the FAQ page: http://www.xilinx.com/xlnx/xebiz/designResources/contentContainer.jsp?sGlobalNavPick=PRODUCTS&sSecondaryNavPick=Design+Tools&iLanguageID=1&key=webpack_faq#2c or http://tinyurl.com/dj8m5 Austin -snip- > Thanks, but we're doing fine running the old Foundation stuff once in > a while when we have to tweak an old 4000 design or something. > > But if we go to WebPack, will we be able to archive the software and > run it five years from now? Or is it a java type thing?Article: 93946
Also: http://www.xilinx.com/ise/logic_design_prod/classics.htm for all the old "classics" AustinArticle: 93947
u_stadler@yahoo.de wrote: >hi > >I have a question: what is the proper way to generate c slow clock. I >have a spartan 3 development board with a 50 MHz external clock. What i >need is a 4MHz clock for an SPI interface. Since the DCM's can only >deliver 18 MHz output with the frequency synthesiser (CLKFX) I need to >devide this clock some more. how is this done properly? a counter? Or >is ther any other sollution? > > There are 2 ways to go. You can run the 50 MHz clock to all FFs, and use a couple FFs to make a divider to 4 MHz. Of course, there is no integer relationship between 50 and 4 - somewhat of a problem there. You might double the 50 Mhz with a PLL, then divide that by 25 to get your 4 MHz. The 4 Mhz can be used to generate a one-clock-cycle true pulse every 250 ns and used to enable all the FFs that need the 4 MHz clock. This doesn't require skew control, but using a global clock line might save routing resources. The other way is to make the same divider arrangement, and route it over to one of the global clock drivers, and distribute the 4 MHz clock to where it is needed. JonArticle: 93948
We are going away from using Xilinx MGT's for the PCIe function in our product lines. V2Pro worked, sort-of. We are running very hard away from V4 (FX) for OBVIOUS reasons and I would avoid the V4 FX family MGT's at all costs for the moment. I recommend the Genesys Logic Phys. Use the GL9711 for 1-lane and the GL9714 for 4-lane. You can combine two of the 9714's to get 8-lanes, but you have a bandwidth mess between the FPGA and the PCIE Phy.Article: 93949
On Tue, 03 Jan 2006 15:33:24 -0800, Austin Lesea <austin@xilinx.com> wrote: >John, > >See answer 2 on the FAQ page: > >http://www.xilinx.com/xlnx/xebiz/designResources/contentContainer.jsp?sGlobalNavPick=PRODUCTS&sSecondaryNavPick=Design+Tools&iLanguageID=1&key=webpack_faq#2c > >or > >http://tinyurl.com/dj8m5 > >Austin > >-snip- > Hate to seem crabby, but there are three "answer 2's" on that page and, so far, none of then answer my questions. like... >> But if we go to WebPack, will we be able to archive the software and >> run it five years from now? Or is it a java type thing? and >> why would anybody pay $2500 a year if the free version is the same? John
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