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Hi Antti, I am surprised to learn your opinions: 1. "simple things fail too, and too often", I agree. 2. "NO, the chances for an total newbie to get things right are defently better than 1%", I disagree. Let's see what is wrong with his problem. WengArticle: 93776
Can anyone have it?Article: 93777
"bjzhangwn" <bjzhangwn@126.com> schrieb im Newsbeitrag news:1135952990.898044.287390@g14g2000cwa.googlegroups.com... > Can anyone have it? > yes, you can have it if you need it: http://www.pcmcia.org/order.htm 349USD available for online ordering! For your info: "Call for papers" has a special meaning - you should check out to avoid using it again in wrong context -- Antti Lukats http://www.xilant.comArticle: 93778
If I want to know how the cpu work more detail,or if I want to know the internal archetecture in the risc cpu,what material should i read?Can some give me some advice!Article: 93779
I know,but I am astudent,and how can i get it freely?Article: 93780
"bjzhangwn" <bjzhangwn@126.com> schrieb im Newsbeitrag news:1135954545.288345.115490@g43g2000cwa.googlegroups.com... >I know,but I am astudent,and how can i get it freely? > get a job and earn money - this is the way to obtain items that are not free and cost money. If you can not buy the standard then you dont need it either, because if you want to develop something for express card then the price of the specification is very small part of the NRE costs. sure I also dont like that some standards are not available for free :( but that the way it is unfortunatly -- Antti Lukats http://www.xilant.comArticle: 93781
Yes, its in a book somewhere!Article: 93782
king_azman wrote: > Hi everyone, > > Is there any way for me to start a project on Virtex2Pro utilizing the > PPC405 core using ONLY ISE (i.e. without EDK)? How do we instantiate > the core in VHDL? > > I'm not really keen on using the EDK: (1) Too many 'black-box-wizards' > - I'd like to know what connections are made and how it is connected. > (2) Sometimes when I made some changes to my custom peripheral, the > whole system becomes not usable - you know, the frustration of waiting > for it to rebuild the system only to find it doesn't work AT ALL! > You can completely ignore all those black-box-wizards and still use EDK, if you are willing to work in a terminal window typing commands. It is helpful to start with a working EDK created project that is somewhat similar to what you eventually want, and then modify it by hand from that point on. That is the way I do it (I use EDK in Linux, but I assume it is the same in Windows). Fortunately all the files EDK creates that matter are plain text files and reasonably easy to figure out. And EDK amazingly seems to spit out reasonably good error messages when you make a mistake in editing the files, so that you can fix it without much trouble. Basically there are four files created by EDK that matter, and you can find a discussion of these in the EDK docs. system.mhs describes the connection of cores that make the EDK project. system.mss describes any software drivers needed. system.make and system_incl.make actually control the building of the project. In a terminal, you can execute "make" with the appropriate options to build the project. Executing just "make" without any parameters will list the parameters available. Mostly I use "make netlist" and "make program".Article: 93783
Hi all. I'm new to all this FPGA stuff. Recently bought the Xilinx Spartan-3 starter kit (now I regret not waiting 2 months for the newer kit that includes way more for just an extra $50). Anyways, I'm new to designs in VHDL. I have a background on microcontrollers (Microchip) but this is so different I feel lost sometimes. My question is, I implemented a PS/2 mouse interface from opencores.org. This needs a reset signal sometime. If I set this signal to either 0 or 1, the circuit does not work. What I did was keep the circuit in reset until the clock counter reaches a certain value, and then release the reset from this module. This works but it seems kind of nasty. Is there a nicer way to do this? Regards, HernanArticle: 93784
"drg" <drgenio@gmail.com> schrieb im Newsbeitrag news:1135963204.408670.77330@z14g2000cwz.googlegroups.com... > Hi all. I'm new to all this FPGA stuff. Recently bought the Xilinx > Spartan-3 starter kit (now I regret not waiting 2 months for the newer > kit that includes way more for just an extra $50). > Anyways, I'm new to designs in VHDL. I have a background on > microcontrollers (Microchip) but this is so different I feel lost > sometimes. > > My question is, I implemented a PS/2 mouse interface from > opencores.org. This needs a reset signal sometime. If I set this signal > to either 0 or 1, the circuit does not work. What I did was keep the > circuit in reset until the clock counter reaches a certain value, and > then release the reset from this module. This works but it seems kind > of nasty. Is there a nicer way to do this? > > Regards, > Hernan > no, there is not much else, if you need a reset then you need some sort of circuitry that generates the reset pulse if you are using DCM you may also need to start your reset counter after the DCM lock goes high assuring that the system is released from reset when the internal clocks are stable -- Antti Lukats http://www.xilant.comArticle: 93785
linq936@hotmail.com wrote: > Hi, > I am working on a Virtex4 FX design, when the system clock runs at > 100MHz, the memory controller core does not work correctly. Then I > inserted ChipScope trying to identify the problem, but once it is > inserted, the problem is gone! > > I know it is of timing problem since if I lower the system clock to > 50MHz, there is no problem either. > > It looks like that after the chipscope is inserted, somehow the > routing is altered in favor of the memory controller. > > I just wonder if there are any trick so that Chipscope insertion does > not impact design routing? No.Article: 93786
Brad Smallridge wrote: > I would like to capture an display video images > using a Xilinx ML402 development kit. > > I am looking for advice about how to proceed. > > I have the datasheet for the Infineon HYB25D256 > DRAM and I also found XAPP608 that describes > DRAM control for a Micron DRAM module. > > I also noticed that the Platform Studio has a DRAM > controller. I am not sure that I want to get into > Platform Studio or deal with OPB busses however. > > At first, the DRAM controller need only write data > from a camera and read data to the VGA display. > At different clock frequencies so FIFOs will be > needed I suppose. > > Can any one point me in the right direction? If you write your own SDRAM controller, you'll be walking in the footsteps of many a contributor to comp.arch.fpga. I suggest 3 things: 1. Xilinx App notes on SDRAM controllers. I can't seem to get to XAPP608, but it could be the right one. There is one with sample code. 2. Go to the Micron website and get a verilog simulation model for an SDRAM. It does all sorts of error checking and will be invaluable when you start your simulations. 3. Read all the postings about SDRAMs in comp.arch.fpga. As I recall, there were some great discussions about signal integrity as well as controller design. Having read all the recommended texts, I suggest that you write your own controller. An SDRAM controller isn't beyond the ability of a good logic designer, and you'll be able to tailor its performance to your project requirements. --- Joe Samson Pixel VelocityArticle: 93787
bjzhangwn wrote: > If I want to know how the cpu work more detail,or if I want to know the > internal archetecture in the risc cpu,what material should i read?Can > some give me some advice! > If you're talking about a specific chip then read that chip's data sheet, user's guide, etc. If you want to better understand computer architecture go to Amazon.com or Powell's technical books (http://www.powells.com) and search on "Computer Architecture". -- Tim Wescott Wescott Design Services http://www.wescottdesign.comArticle: 93788
Hi, I am trying to use the ADSU8 library element in ISE7.1i. The libraries guide says its inferred by HDL (Verilog in my case) but does not give an example. I can create it with the schematic editor but not with Verilog. I have tried to express the unit in a number of different ways. Rather than embarrass myself by posting bad code, I'll just ask the question - is there a trick to it? Thanks, Paul.Article: 93789
A picture says more then words but having something on your hands is even better. I found lately that an German company is manufacturing small FPGA and PLD boards with an DIP24 (GAL like) socket header. They looked nice but when actually having them in my hands, well I instantly wanted to check something out. And I did, and I liked the easyness and fun I had, here is the story http://xilant.com/content/view/33/55/ full project (from schematic design to working proto!) was done within 6 hours. those tiny modules are made by OHO http://www.oho-elektronik.de/ Ohooo! -- Antti Lukats, who hopes others will have fun too ;) http://www.xilant.com PS if somebody wonders why I am not having some rest - well I am locked in into the office as I left my keys at home. Waiting for the children to fall a-sleep so my wife can sneak out to a rescue mission.Article: 93790
"Paul Marciano" <pm940@yahoo.com> schrieb im Newsbeitrag news:1135968968.926661.91100@z14g2000cwz.googlegroups.com... > Hi, > > I am trying to use the ADSU8 library element in ISE7.1i. The libraries > guide says its inferred by HDL (Verilog in my case) but does not give > an example. > > I can create it with the schematic editor but not with Verilog. > > I have tried to express the unit in a number of different ways. Rather > than embarrass myself by posting bad code, I'll just ask the question - > is there a trick to it? > > Thanks, > Paul. > Hi Paul, there are tricks and 'need to know' things all around. I am using ISE schematic as kinda coregen, inserting a single component onto empty schematic and then looking at functional code of it and copying over the stuff into vhdl or verilog. that way I get allways things done. -- Antti Lukats http://www.xilant.comArticle: 93791
On Thu, 29 Dec 2005 17:59:50 +0000, John_H wrote: > Alex Gibson wrote: >> According to the front page of xilinx's site but not yet in the web >> shop. >> >> http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-SPAR3E-DK >> >> With double the amounts of ram and flash than origonally announced. >> >> Now if only xilinx sold digilentincs addon cards so could get some >> decent shipping charges. >> >> Alex > > It's been front-(wb)page news for 2 days and it's *still* not at the > online store. If it's available, what's the proper way to get hold of > one? Do I need to contact my local sales guy for a development board? > > We're a big account but I don't want to bother with a PO in this "belt > tightening" era so I'll just buy the darned thing myself and use it at > work and home. Best way to do this is the online store. Where else > *should* I go? I was sure hoping this would be available before the end of the year. Money is in the budget for this year, but now it looks like I'll have to go through the budget process again after the first of the year. I wish Xilinx understood the end of year money cycle and would go ahead and let you order. -- Joe Chisolm Phoenix Arizona USAArticle: 93792
>"Joe Chisolm" <nospam@nospam.org> schrieb im Newsbeitrag >news:pan.2005.12.30.19.11.56.547536@nospam.org... > On Thu, 29 Dec 2005 17:59:50 +0000, John_H wrote: > >> Alex Gibson wrote: >>> According to the front page of xilinx's site but not yet in the web >>> shop. >>> >>> http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-SPAR3E-DK >>> >>> With double the amounts of ram and flash than origonally announced. >>> >>> Now if only xilinx sold digilentincs addon cards so could get some >>> decent shipping charges. >>> >>> Alex >> >> It's been front-(wb)page news for 2 days and it's *still* not at the >> online store. If it's available, what's the proper way to get hold of >> one? Do I need to contact my local sales guy for a development board? >> >> We're a big account but I don't want to bother with a PO in this "belt >> tightening" era so I'll just buy the darned thing myself and use it at >> work and home. Best way to do this is the online store. Where else >> *should* I go? > > I was sure hoping this would be available before the end of the year. > Money is in the budget for this year, but now it looks like I'll > have to go through the budget process again after the first of the > year. I wish Xilinx understood the end of year money cycle and > would go ahead and let you order. > -- > Joe Chisolm > Phoenix Arizona USA > Hi Joe, you are right - Xilinx kind of promised that "December is the month" ! and oh I know very good that the "year end money" is something that needs to be used, and its really pain if some item that was scheduled to be ordered before the end of the year can not be ordered. you could try there http://www.xilinx.com/s3ediscount but I am afraid it may as well not lead to the actual online entry form :( -- Antti Lukats http://www.xilant.comArticle: 93793
On Fri, 30 Dec 2005 20:18:53 +0100, Antti Lukats wrote: >>"Joe Chisolm" <nospam@nospam.org> schrieb im Newsbeitrag >>news:pan.2005.12.30.19.11.56.547536@nospam.org... >> On Thu, 29 Dec 2005 17:59:50 +0000, John_H wrote: >> [snip] > Hi Joe, > > you are right - Xilinx kind of promised that "December is the month" ! > > and oh I know very good that the "year end money" is something that needs > to be used, and its really pain if some item that was scheduled to be > ordered before the end of the year can not be ordered. > > you could try there > > http://www.xilinx.com/s3ediscount > > but I am afraid it may as well not lead to the actual online entry form :( Thanks for the link. You are right, the starter kit link just takes you to the online store and you cannot order there. -- Joe Chisolm Phoenix Arizona USAArticle: 93794
"Joe Chisolm" <nospam@nospam.org> schrieb im Newsbeitrag news:pan.2005.12.30.19.47.34.190805@nospam.org... > On Fri, 30 Dec 2005 20:18:53 +0100, Antti Lukats wrote: > >>>"Joe Chisolm" <nospam@nospam.org> schrieb im Newsbeitrag >>>news:pan.2005.12.30.19.11.56.547536@nospam.org... >>> On Thu, 29 Dec 2005 17:59:50 +0000, John_H wrote: >>> > [snip] >> Hi Joe, >> >> you are right - Xilinx kind of promised that "December is the month" ! >> >> and oh I know very good that the "year end money" is something that needs >> to be used, and its really pain if some item that was scheduled to be >> ordered before the end of the year can not be ordered. >> >> you could try there >> >> http://www.xilinx.com/s3ediscount >> >> but I am afraid it may as well not lead to the actual online entry form >> :( > > Thanks for the link. You are right, the starter kit link just > takes you to the online store and you cannot order there. > > -- > Joe Chisolm > Phoenix Arizona USA > ok, sorry, I landed somewhere where it told me that I need to complete the order if I proceed, so I cancelled at that point as I did not want to order, so I did not know if there was actual order entry or not. Sorry - as time is running out so it seems that there is nothing more todo. -- Antti Lukats http://www.xilant.comArticle: 93795
peter.halford@alarmip.com wrote: >Dear All, > >Many thanks for all your suggestions... > >I have tried dividing my incoming 25MHz clock by 2 and voilla! >everything works, albeit 50% slower... > >So now I guess I will have to divide the incoming clock by 2, multiply >it and re-divide it. > >Any ideas why this could be happening? > > Doesn't completely fit the symptoms, but is it possible there are reflections on the clock input? What you are doing is not only dividing the clock, but providing a clean clock from WITHIN the FPGA. Of course, you also could have an extremely slow path in the design somewhere, but that would have to be a huge amount of combinatorial logic or maybe some very slow external path like a RAM, to make it work at 12.5 MHz but fail at 25. JonArticle: 93796
Dear Symon, Today I rewrote the entire module using procedural code and now everything is working perfectly!!! It is odd how the code would work for a bit and then stop for another bit... Anyhow, this is how one learns to make things work... Many thanks to you and to all who offered help. Regards, Peter PS. It is p-ing down here in torrents!!! Corfu is the greenest island in Greece for a very good reason!!!Article: 93797
Hi, I am following patent 6,914,453 by IBM to write claims. I would like to ask another question: What is the difference between 'providing' and 'applying' in a patent claim area for electronic circuit? In the above patent, it writes: 1. A method ... providing a clock input to the logic circuits; providing one or more static signal inputs to the logic circuit; <-- generating one or more dynamic signal inputs ... applying the one or more dynamic signal input to the circuit; ... 4. The method of claim 1, further comprising the step of applying one or more static signal inputs to the logic circuit. >From the above descriptions, I am confused about why claim 4 repeats a step that has already been described, but insead of using 'providing', it uses 'applying' this time. Thank you. WengArticle: 93798
Austin Lesea wrote: > Recently posted on our website: > > http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex4/resources/Virtex-4_Power_Case_Study.pdf > > > Is a case study in which the latest claims of power savings by the > competitor's software are debunked. Well, not quite. Your results DO clearly show a reduction in power ?! Perhaps what you meant to say, was "reality checked, and compared with alternate devices" What is does show, is the mA/MHz slopes are now very similar. It also shows that in the Xilinx test case, Static Icc dominates, and alerts designers to possible ommision of that detail in Altera's stats and claims. -jgArticle: 93799
Jan Panteltje wrote: > On a sunny day (29 Dec 2005 15:27:32 -0800) it happened "Peter Alfke" > <peter@xilinx.com> wrote in > <1135898851.959376.84950@o13g2000cwo.googlegroups.com>: > > >>Martin Schoeberl wrote: >> >>>>Ok, thanks for the clarification. But in this paper the >>> >>>overall power was measured at 25C and the static power was >>>added from some other source for the 85C figure. >>> >> >>Martin, I find it hard to be patient with you. >>If dynamic power is constant with temperature, >>and static power increases monotonically with temperature, >>and total power is always the linear sum of static and dynamic power, >>then I can scientifically state that >> >>Total Power @85 = static power @85 + dynamic power @25 degrees. >> >>And that is not Marketing. (Which we all agree is almost a dirty word >>in our circles). >> >>Happy New Year ! >>Peter Alfke, Xilinx Applications >> > > You should publish true measured values, or just give the fomula. > This is normal practice. I am with Jan and Martin on this - always publish true measured values; [After all, isn't doing otherwise, simply 'marketing BS' ?] but one could ponder WHY Xilinx do not include the 25'C values : Perhaps the Static Icc is CLOSER at 25'C, and so is less dramatic. Especially if you are going to use words like 'debunk', and 'marketing BS', then your examples should be very solid, and not stretch credibility... ? How hard is it to plot BOTH 25'C[actual] and 85'C[derived] curves ? -jg
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