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Threads Starting Jul 2006
104599: 06/07/01: Frank Buss: Problem with SLL: "sll can not have such operands in this context" and bit-testing
104610: 06/07/01: ColmF: Cyclone-II Configuration via a PCI bus
104624: 06/07/02: Antti: Re: Cyclone-II Configuration via a PCI bus
104631: 06/07/03: Alan Myler: Re: Cyclone-II Configuration via a PCI bus
104632: 06/07/03: Antti: Re: Cyclone-II Configuration via a PCI bus
104611: 06/07/01: Guru: Re: Problem to extend Xilinx GSRD Design
104612: 06/07/01: bjzhangwn: register state when power on
104666: 06/07/03: Rob: Re: register state when power on
104614: 06/07/01: <patrik.camilleri@gmail.com>: Xilinx System Generator Part List Problem
104619: 06/07/01: bjzhangwn: stable reset in fpga
104620: 06/07/01: Peter Alfke: Re: stable reset in fpga
104665: 06/07/03: Phil Hays: Re: stable reset in fpga
104695: 06/07/04: Aurelian Lazarut: Re: stable reset in fpga
104696: 06/07/04: Phil Hays: Re: stable reset in fpga
104717: 06/07/05: mk: Re: stable reset in fpga
104752: 06/07/05: Mike Lewis: Re: stable reset in fpga
104653: 06/07/03: StanleyLee: Re: stable reset in fpga
104654: 06/07/03: Antti: Re: stable reset in fpga
104676: 06/07/03: StanleyLee: Re: stable reset in fpga
104716: 06/07/05: <saumyajit_tech@yahoo.co.in>: Re: stable reset in fpga
104778: 06/07/05: <saumyajit_tech@yahoo.co.in>: Re: stable reset in fpga
104780: 06/07/05: Peter Alfke: Re: stable reset in fpga
104800: 06/07/06: Andy: Re: stable reset in fpga
104861: 06/07/07: Stanley Lee: Re: stable reset in fpga
104867: 06/07/07: Peter Alfke: Re: stable reset in fpga
104621: 06/07/02: gary: component instantiation ISE7.1
104625: 06/07/02: MM: Re: component instantiation ISE7.1
104629: 06/07/02: gary: Re: component instantiation ISE7.1
104667: 06/07/03: MM: Re: component instantiation ISE7.1
104673: 06/07/03: gary: Re: component instantiation ISE7.1
104678: 06/07/04: MM: Re: component instantiation ISE7.1
104773: 06/07/05: gary: Re: component instantiation ISE7.1
104775: 06/07/05: MM: Re: component instantiation ISE7.1
104899: 06/07/08: gary: Re: component instantiation ISE7.1
104941: 06/07/10: MM: Re: component instantiation ISE7.1
105011: 06/07/11: gary: Re: component instantiation ISE7.1
105013: 06/07/11: MM: Re: component instantiation ISE7.1
105644: 06/07/27: gary: Re: component instantiation ISE7.1
104628: 06/07/02: ZHI: How to trigger write signal and read sigal
104630: 06/07/03: wuyi316904@gmail.com: how to use the xilinx 18v04 config fpga?
104633: 06/07/03: Antti: Re: how to use the xilinx 18v04 config fpga?
104636: 06/07/03: Yaseen Zaidi: Synthesis changes after ISE upgrade
104638: 06/07/03: Antti: Re: Synthesis changes after ISE upgrade
104647: 06/07/03: StanleyLee: Re: Synthesis changes after ISE upgrade
104637: 06/07/03: Tom: Timing constraints on ISERDES
104639: 06/07/03: Antti: next EDK service pack release date?
104712: 06/07/05: John Williams: Re: next EDK service pack release date?
104715: 06/07/04: Antti: Re: next EDK service pack release date?
104642: 06/07/03: Hampus Thorell: LwIP
104643: 06/07/03: wuyi316904@gmail.com: design in vsprom
104645: 06/07/03: rickman: Chaos in FF metastability
104650: 06/07/03: Ben Jones: Re: Chaos in FF metastability
104660: 06/07/03: Phil Hays: Re: Chaos in FF metastability
104671: 06/07/04: Jim Granville: Re: Chaos in FF metastability
104683: 06/07/03: Phil Hays: Re: Chaos in FF metastability
104691: 06/07/04: Symon: Re: Chaos in FF metastability
104693: 06/07/04: Kolja Sulimma: Re: Chaos in FF metastability
104705: 06/07/04: Jonathan Bromley: Re: Chaos in FF metastability
104786: 06/07/06: Daniel Lang: Re: Chaos in FF metastability
104787: 06/07/06: Jonathan Bromley: Re: Chaos in FF metastability
104707: 06/07/04: John Larkin: Re: Chaos in FF metastability
104710: 06/07/04: Hal Murray: Re: Chaos in FF metastability
104720: 06/07/05: Evan Lavelle: Re: Chaos in FF metastability
104721: 06/07/05: Evan Lavelle: Re: Chaos in FF metastability
104730: 06/07/05: Symon: Re: Chaos in FF metastability
104754: 06/07/05: Evan Lavelle: Re: Chaos in FF metastability
104763: 06/07/05: Ray Andraka: Re: Chaos in FF metastability
104743: 06/07/05: Hal Murray: Re: Chaos in FF metastability
104751: 06/07/05: Evan Lavelle: Re: Chaos in FF metastability
104771: 06/07/06: Jim Granville: Re: Chaos in FF metastability
104813: 06/07/07: Jim Granville: Re: Chaos in FF metastability
104827: 06/07/07: Jim Granville: Re: Chaos in FF metastability
104875: 06/07/08: Jim Granville: Re: Chaos in FF metastability
104876: 06/07/07: Marc Reinig: Re: Chaos in FF metastability
104879: 06/07/07: mk: Re: Chaos in FF metastability
104880: 06/07/07: Jonathan Bromley: Re: Chaos in FF metastability
104892: 06/07/08: Kolja Sulimma: Re: Chaos in FF metastability
104898: 06/07/08: Austin Lesea: Re: Chaos in FF metastability
104918: 06/07/09: Hal Murray: Re: Chaos in FF metastability
104920: 06/07/09: Phil Hays: Re: Chaos in FF metastability
104829: 06/07/06: Phil Hays: Re: Chaos in FF metastability
104842: 06/07/07: Jan Panteltje: Re: Chaos in FF metastability
104890: 06/07/08: rickman: Re: Chaos in FF metastability
104891: 06/07/08: Peter Alfke: Re: Chaos in FF metastability
104893: 06/07/08: rickman: Re: Chaos in FF metastability
104894: 06/07/08: rickman: Re: Chaos in FF metastability
104674: 06/07/03: JJ: Re: Chaos in FF metastability
104675: 06/07/03: Peter Alfke: Re: Chaos in FF metastability
104682: 06/07/03: rickman: Re: Chaos in FF metastability
104684: 06/07/03: Peter Alfke: Re: Chaos in FF metastability
104704: 06/07/04: rickman: Re: Chaos in FF metastability
104753: 06/07/05: Peter Alfke: Re: Chaos in FF metastability
104756: 06/07/05: rickman: Re: Chaos in FF metastability
104767: 06/07/05: Peter Alfke: Re: Chaos in FF metastability
104794: 06/07/06: rickman: Re: Chaos in FF metastability
104823: 06/07/06: Peter Alfke: Re: Chaos in FF metastability
104847: 06/07/07: rickman: Re: Chaos in FF metastability
104863: 06/07/07: Peter Alfke: Re: Chaos in FF metastability
104877: 06/07/07: Peter Alfke: Re: Chaos in FF metastability
104878: 06/07/07: Peter Alfke: Re: Chaos in FF metastability
104936: 06/07/10: rickman: Re: Chaos in FF metastability
104646: 06/07/03: Vassili: Properties of some pins of Vertex4
104651: 06/07/03: Antti: Re: Properties of some pins of Vertex4
104648: 06/07/03: Aurelian Lazarut: Re: can't read device ID xcv200....what about the PROGRAM pin
104657: 06/07/03: Aurelian Lazarut: Re: can't read device ID xcv200....what about the PROGRAM pin
104649: 06/07/03: Antti: Re: can't read device ID xcv200....what about the PROGRAM pin
104664: 06/07/03: blisca: R: can't read device ID xcv200....what about the PROGRAM pin
104652: 06/07/03: Aurelian Lazarut: Re: can't read device ID xcv200....what about the PROGRAM pin
104655: 06/07/03: Antti: Re: can't read device ID xcv200....what about the PROGRAM pin
104656: 06/07/03: blisca: can't read device ID xcv200....what about the PROGRAM pin
104659: 06/07/03: Antti: Re: R: can't read device ID xcv200....what about the PROGRAM pin
104661: 06/07/03: Antti: Re: can't read device ID xcv200....what about the PROGRAM pin
104662: 06/07/03: Bob: Re: can't read device ID xcv200....what about the PROGRAM pin
104669: 06/07/03: blisca: R: can't read device ID xcv200E....what about the PROGRAM pin
104670: 06/07/03: blisca: R: can't read device ID xcv200....what about the PROGRAM pin
104663: 06/07/03: Antti: Re: can't read device ID xcv200....what about the PROGRAM pin
104668: 06/07/03: Antti: Re: R: can't read device ID xcv200E....what about the PROGRAM pin
104658: 06/07/03: Robin Bruce: Inferring multiple-DSP48 pipelined multiplier in VHDL
104672: 06/07/03: Anonymous: PPC and Chipscope?
104681: 06/07/03: Antti: Re: PPC and Chipscope?
104728: 06/07/05: Joseph Samson: Re: PPC and Chipscope?
104732: 06/07/05: Anonymous: Re: PPC and Chipscope?
104736: 06/07/05: Joseph Samson: Re: PPC and Chipscope?
104737: 06/07/05: Ben Jones: Re: PPC and Chipscope?
104725: 06/07/05: Guru: Re: PPC and Chipscope?
104733: 06/07/05: Antti: Re: PPC and Chipscope?
104738: 06/07/05: Antti: Re: PPC and Chipscope?
104677: 06/07/03: Guillermo: UCF File : LOC signal syntax
104679: 06/07/04: MM: Re: Inferring multiple-DSP48 pipelined multiplier in VHDL
104686: 06/07/04: eric: Altium Live Desing Eval and Linux
104689: 06/07/04: Antti: Re: Altium Live Desing Eval and Linux
104783: 06/07/06: eric: Re: Altium Live Desing Eval and Linux
104785: 06/07/06: Antti: Re: Altium Live Desing Eval and Linux
104687: 06/07/04: Ben Jones: Re: Inferring multiple-DSP48 pipelined multiplier in VHDL
104761: 06/07/05: Ray Andraka: Re: Inferring multiple-DSP48 pipelined multiplier in VHDL
104690: 06/07/04: Guru: Re: Problem to extend Xilinx GSRD Design
104692: 06/07/04: Robin Bruce: Re: Inferring multiple-DSP48 pipelined multiplier in VHDL
104694: 06/07/04: Martin Thompson: Re: Inferring multiple-DSP48 pipelined multiplier in VHDL
104718: 06/07/05: Martin Thompson: Re: Inferring multiple-DSP48 pipelined multiplier in VHDL
104762: 06/07/05: Ray Andraka: Re: Inferring multiple-DSP48 pipelined multiplier in VHDL
104697: 06/07/04: Robin Bruce: Re: Inferring multiple-DSP48 pipelined multiplier in VHDL
104698: 06/07/04: srini: ASCI to FPGA - require details
104699: 06/07/04: Alan Myler: Re: ASCI to FPGA - require details
104700: 06/07/04: Subroto Datta: Re: ASCI to FPGA - require details
104701: 06/07/04: Alan Myler: Re: ASCI to FPGA - require details
104714: 06/07/04: srini: Re: ASCI to FPGA - require details
104702: 06/07/04: raso: ADPLL (50Hz to 2kHz)
104703: 06/07/04: Falk Brunner: Re: ADPLL (50Hz to 2kHz)
104708: 06/07/04: Anonymous: single pad to pad timing in ISE
104709: 06/07/04: Anonymous: Re: single pad to pad timing in ISE
104713: 06/07/04: JustJohn: Re: single pad to pad timing in ISE
104719: 06/07/05: misiu: Xilinx ML403 hard mac (xapp443)
104723: 06/07/05: Guru: Re: Xilinx ML403 hard mac (xapp443)
104722: 06/07/05: JL: Weird timing failure
104734: 06/07/05: Gabor: Re: Weird timing failure
104784: 06/07/06: <saumyajit_tech@yahoo.co.in>: Re: Weird timing failure
104724: 06/07/05: mh: using cores exported from Xilinx plan Ahead with verilg design
104727: 06/07/05: Aurelian Lazarut: Re: using cores exported from Xilinx plan Ahead with verilg design
104834: 06/07/06: mh: Re: using cores exported from Xilinx plan Ahead with verilg design
104726: 06/07/05: subint: mig_ddr_controller
104729: 06/07/05: StanleyLee: Can I use all 18bits of a BlockRAM?
104731: 06/07/05: Symon: Re: Can I use all 18bits of a BlockRAM?
104740: 06/07/05: Zara: Re: Can I use all 18bits of a BlockRAM?
104760: 06/07/05: Ray Andraka: Re: Can I use all 18bits of a BlockRAM?
104803: 06/07/06: Symon: Re: Can I use all 18bits of a BlockRAM?
104805: 06/07/06: John_H: Re: Can I use all 18bits of a BlockRAM?
104845: 06/07/07: Symon: Re: Can I use all 18bits of a BlockRAM?
104808: 06/07/06: Thomas Entner: Re: Can I use all 18bits of a BlockRAM?
104872: 06/07/07: David Dye: Re: Can I use all 18bits of a BlockRAM?
104886: 06/07/08: Jan Hansen: Re: Can I use all 18bits of a BlockRAM?
104905: 06/07/09: Hal Murray: Re: Can I use all 18bits of a BlockRAM?
104735: 06/07/05: Stanley Lee: Re: Can I use all 18bits of a BlockRAM?
104744: 06/07/05: PeterSmith1954@googlemail.com: Re: Can I use all 18bits of a BlockRAM?
104801: 06/07/06: Andy: Re: Can I use all 18bits of a BlockRAM?
104896: 06/07/08: Peter Alfke: Re: Can I use all 18bits of a BlockRAM?
104739: 06/07/05: Alex: "Large" memory array in VHDL
104742: 06/07/05: radarman: Re: "Large" memory array in VHDL
104750: 06/07/05: Nial Stewart: Re: "Large" memory array in VHDL
104759: 06/07/05: Ray Andraka: Re: "Large" memory array in VHDL
104811: 06/07/06: Nico Coesel: Re: "Large" memory array in VHDL
104745: 06/07/05: Alex: Re: "Large" memory array in VHDL
104747: 06/07/05: Peter Alfke: Re: "Large" memory array in VHDL
104755: 06/07/05: Ricardo: Re: "Large" memory array in VHDL
104765: 06/07/05: Alex: Re: "Large" memory array in VHDL
104795: 06/07/06: Ricardo: Re: "Large" memory array in VHDL
104741: 06/07/05: <me_2003@walla.co.il>: EDK question - debugging PPC405 and MB..
104746: 06/07/05: Robin Bruce: Re: Inferring multiple-DSP48 pipelined multiplier in VHDL
104748: 06/07/05: Robin Bruce: Re: Inferring multiple-DSP48 pipelined multiplier in VHDL
104749: 06/07/05: billu: High Speed Serial MGTs using Aurora IP
104757: 06/07/05: <rponsard@gmail.com>: xilinx impact : usb failure
104758: 06/07/05: Nitesh: PLB master without xilinx ipif
104764: 06/07/05: Eli Hughes: Re: PLB master without xilinx ipif
104769: 06/07/05: Guru: Re: PLB master without xilinx ipif
104770: 06/07/05: Guru: Incorporating CoreGen files in EDK 8.1 peripheral
104772: 06/07/05: Paulo Dutra: Re: Incorporating CoreGen files in EDK 8.1 peripheral
104774: 06/07/05: Jim Wu: Re: Incorporating CoreGen files in EDK 8.1 peripheral
104782: 06/07/06: =?ISO-8859-1?Q?Johan_Bernsp=E5ng?=: Re: Incorporating CoreGen files in EDK 8.1 peripheral
104789: 06/07/06: Guru: Re: Incorporating CoreGen files in EDK 8.1 peripheral
104776: 06/07/05: Weng Tianxiang: How much time does it need to sort 1 million random 64-bit/32-bit integers?
104777: 06/07/06: Richard Heathfield: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
104781: 06/07/06: Mark McDougall: Re: How much time does it need to sort 1 million random 64-bit/32-bit
104792: 06/07/06: Kolja Sulimma: Re: How much time does it need to sort 1 million random 64-bit/32-bit
104793: 06/07/06: Weng Tianxiang: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
104802: 06/07/06: John_H: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
105043: 06/07/12: Jonathan Bromley: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
105048: 06/07/12: Jonathan Bromley: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
105055: 06/07/12: Jonathan Bromley: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
105141: 06/07/14: Jonathan Bromley: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
105044: 06/07/12: Hal Murray: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
105100: 06/07/13: nospam: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
104809: 06/07/06: JJ: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
104815: 06/07/06: Joe Wright: Re: How much time does it need to sort 1 million random 64-bit/32-bit
104822: 06/07/06: Dann Corbit: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
104831: 06/07/07: Logan Shaw: Re: How much time does it need to sort 1 million random 64-bit/32-bit
104853: 06/07/07: Oliver Wong: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
104874: 06/07/07: Paul Floyd: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
104819: 06/07/06: Weng Tianxiang: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
104820: 06/07/06: Oliver Wong: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
104839: 06/07/07: Kolja Sulimma: Re: How much time does it need to sort 1 million random 64-bit/32-bit
104854: 06/07/07: Kolja Sulimma: Re: How much time does it need to sort 1 million random 64-bit/32-bit
104871: 06/07/07: Dann Corbit: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
104948: 06/07/10: Dann Corbit: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
105001: 06/07/11: Dann Corbit: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
104825: 06/07/06: Weng Tianxiang: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
104835: 06/07/07: Thomas Stanka: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
104841: 06/07/07: robertwessel2@yahoo.com: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
104848: 06/07/07: Weng Tianxiang: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
104849: 06/07/07: Thomas Stanka: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
104855: 06/07/07: dmackay@gmail.com: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
104882: 06/07/07: Weng Tianxiang: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
104987: 06/07/11: Weng Tianxiang: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
105040: 06/07/12: Brannon: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
105051: 06/07/12: Weng Tianxiang: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
105056: 06/07/12: Weng Tianxiang: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
105068: 06/07/12: Weng Tianxiang: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
105096: 06/07/13: Brannon: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
105098: 06/07/13: Brannon: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
105129: 06/07/14: Weng Tianxiang: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
105143: 06/07/14: Brannon: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
105145: 06/07/14: Brannon: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
105157: 06/07/14: Weng Tianxiang: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
105159: 06/07/14: Weng Tianxiang: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
105160: 06/07/14: Brannon: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
105282: 06/07/19: Weng Tianxiang: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
104779: 06/07/05: David: DDR Controller problems
104788: 06/07/06: PeterSmith1954@googlemail.com: Re: DDR Controller problems
104810: 06/07/06: Nico Coesel: Re: DDR Controller problems
104838: 06/07/07: David: Re: DDR Controller problems
104957: 06/07/10: David: Re: DDR Controller problems
104790: 06/07/06: Robin Bruce: Re: Inferring multiple-DSP48 pipelined multiplier in VHDL
104791: 06/07/06: subint: Simulation problem for the DDR controller
104846: 06/07/07: subint: Re: Simulation problem for the DDR controller
104796: 06/07/06: Dario: FPGA interpolated FIR implementation
104798: 06/07/06: Robin Bruce: Re: Inferring multiple-DSP48 pipelined multiplier in VHDL
104799: 06/07/06: Andy: Re: Inferring multiple-DSP48 pipelined multiplier in VHDL
104804: 06/07/06: Ajay: XPS-Microblaze-Xilkernel
104806: 06/07/06: Brian McFarland: debouncing a switch (in hardware)
104807: 06/07/06: Slurp: Re: debouncing a switch (in hardware)
104814: 06/07/07: Jim Granville: Re: debouncing a switch (in hardware)
104817: 06/07/06: Dave: Re: debouncing a switch (in hardware)
104830: 06/07/06: Bob Perlman: Re: debouncing a switch (in hardware)
104832: 06/07/07: Jim Granville: Re: debouncing a switch (in hardware)
104836: 06/07/07: Gregory C. Read: Re: debouncing a switch (in hardware)
104837: 06/07/07: Jim Granville: Re: debouncing a switch (in hardware)
104883: 06/07/08: Rob: Re: debouncing a switch (in hardware)
104961: 06/07/11: aName: Re: debouncing a switch (in hardware)
104997: 06/07/11: aName: Re: debouncing a switch (in hardware)
104979: 06/07/11: Gabor: Re: debouncing a switch (in hardware)
105260: 06/07/19: Karl: Re: debouncing a switch (in hardware)
105261: 06/07/19: Karl: Re: debouncing a switch (in hardware)
104812: 06/07/06: MM: Fastest platform to run ISE?
104818: 06/07/06: mk: Re: Fastest platform to run ISE?
104824: 06/07/06: Tommy Thorn: Re: Fastest platform to run Place & Route?
104826: 06/07/06: JJ: Re: Fastest platform to run ISE?
104885: 06/07/08: Alex Gibson: Re: Fastest platform to run ISE?
104887: 06/07/08: Jan Hansen: Re: Fastest platform to run ISE?
105208: 06/07/18: Philip Freidin: Re: Fastest platform to run ISE?
104888: 06/07/08: Leon: Re: Fastest platform to run ISE?
104889: 06/07/08: Nico Coesel: Re: Fastest platform to run ISE?
104895: 06/07/08: JJ: Re: Fastest platform to run ISE?
104816: 06/07/06: James Morrison: Can a BUFGMUX drive a global clock in the Spartan-3?
104821: 06/07/06: Eric Crabill: Re: Can a BUFGMUX drive a global clock in the Spartan-3?
104828: 06/07/06: Jim Wu: Re: Can a BUFGMUX drive a global clock in the Spartan-3?
104833: 06/07/06: <saumyajit_tech@yahoo.co.in>: Re: DDR Controller problems
104840: 06/07/07: mulligan: Re: DDR Controller problems
104843: 06/07/07: colin: detecting gnd
104844: 06/07/07: Antti: Re: detecting gnd
104850: 06/07/07: Brandon Jasionowski: Obtain old ver ISE Foundation?
104851: 06/07/07: Aurelian Lazarut: Re: Obtain old ver ISE Foundation?
105113: 06/07/13: Ron: Re: Obtain old ver ISE Foundation?
104852: 06/07/07: Subhasri krishnan: recognizing multiple fpga's
104938: 06/07/10: Gabor: Re: recognizing multiple fpga's
105500: 06/07/24: Subhasri krishnan: Re: recognizing multiple fpga's
104856: 06/07/07: <jean-baptiste.nouvel@jdsu.com>: PCI IOs, tiofoi, source sampling bypass
104857: 06/07/07: John_H: Re: PCI IOs, tiofoi, source sampling bypass
104869: 06/07/07: Eric Crabill: Re: PCI IOs, tiofoi, source sampling bypass
104919: 06/07/09: Hal Murray: Re: PCI IOs, tiofoi, source sampling bypass
104944: 06/07/10: Eric Crabill: Re: PCI IOs, tiofoi, source sampling bypass
104870: 06/07/07: John_H: Re: PCI IOs, tiofoi, source sampling bypass
104862: 06/07/07: <jean-baptiste.nouvel@jdsu.com>: Re: PCI IOs, tiofoi, source sampling bypass
104972: 06/07/11: <jean-baptiste.nouvel@jdsu.com>: Re: PCI IOs, tiofoi, source sampling bypass
104973: 06/07/11: <jean-baptiste.nouvel@jdsu.com>: Re: PCI IOs, tiofoi, source sampling bypass
104858: 06/07/07: Guru: Virtex4 Mini-Module GBL Phy
104864: 06/07/07: Antti: Re: Virtex4 Mini-Module GBL Phy
104873: 06/07/07: Guru: Re: Virtex4 Mini-Module GBL Phy
104859: 06/07/07: Stanley Lee: The difference betweeen SLICEM and SLICEL
104860: 06/07/07: John_H: Re: The difference betweeen SLICEM and SLICEL
104865: 06/07/07: savs: FATAL ERROR IN EDK 7.1i
104866: 06/07/07: Antti: Re: FATAL ERROR IN EDK 7.1i
104868: 06/07/07: ZHI: Warning issue!!!
104881: 06/07/07: PeterSmith1954@googlemail.com: Re: DDR Controller problems
104884: 06/07/08: savs: Timing Error in edk 7.1i
104897: 06/07/08: Gavin Scott: Xilinx Xcell Journal received damaged
104923: 06/07/10: Zara: Re: Xilinx Xcell Journal received damaged
104931: 06/07/10: Symon: Re: Xilinx Xcell Journal received damaged
104935: 06/07/10: Zara: Re: Xilinx Xcell Journal received damaged
104900: 06/07/08: <s1r.h3nry@gmail.com>: PPC XMK bootloader for ELF files
104901: 06/07/08: <beagle197@hotmail.com>: Mystery CLKDLL, IBUFG, BUFG modules in verilog src (ISE 6.3.03i)
104902: 06/07/09: John_H: Re: Mystery CLKDLL, IBUFG, BUFG modules in verilog src (ISE 6.3.03i)
104903: 06/07/08: <beagle197@hotmail.com>: Re: Mystery CLKDLL, IBUFG, BUFG modules in verilog src (ISE 6.3.03i)
104908: 06/07/09: johnp: Re: Mystery CLKDLL, IBUFG, BUFG modules in verilog src (ISE 6.3.03i)
104904: 06/07/09: Jan Hansen: SP305- PROM configuration
104906: 06/07/09: Antti: Re: SP305- PROM configuration
104907: 06/07/09: Antti: Weird JTAG lockup issue, where is the BUG?
104909: 06/07/09: Nico Coesel: Re: Weird JTAG lockup issue, where is the BUG?
104913: 06/07/09: Austin Lesea: Re: Weird JTAG lockup issue, where is the BUG?
104930: 06/07/10: David R Brooks: Re: Weird JTAG lockup issue, where is the BUG?
104910: 06/07/09: Antti: Re: Weird JTAG lockup issue, where is the BUG?
104911: 06/07/09: Rob: Re: Weird JTAG lockup issue, where is the BUG?
104917: 06/07/10: Rob: Re: Weird JTAG lockup issue, where is the BUG?
104912: 06/07/09: Antti: Re: Weird JTAG lockup issue, where is the BUG?
104914: 06/07/09: Antti: Re: Weird JTAG lockup issue, where is the BUG?
104928: 06/07/09: Antti: Re: Weird JTAG lockup issue - PROBLEM SOLVED!
104933: 06/07/10: Antti: Re: Weird JTAG lockup issue, where is the BUG?
104915: 06/07/09: thejay: Is while loop synthesizable if the number of iterations is known
104916: 06/07/09: Ben Jackson: Re: Is while loop synthesizable if the number of iterations is known
104921: 06/07/09: Stanley Lee: The FFs with synchronous reset perform worse?
104922: 06/07/10: mk: Re: The FFs with synchronous reset perform worse?
104952: 06/07/10: mk: Re: The FFs with synchronous reset perform worse?
104924: 06/07/09: Stanley Lee: Re: The FFs with synchronous reset perform worse?
104926: 06/07/09: Peter Alfke: Re: The FFs with synchronous reset perform worse?
104934: 06/07/10: KJ: Re: The FFs with synchronous reset perform worse?
104940: 06/07/10: Mike Treseler: Re: The FFs with synchronous reset perform worse?
104945: 06/07/10: Ray Andraka: Re: The FFs with synchronous reset perform worse?
104978: 06/07/11: KJ: Re: The FFs with synchronous reset perform worse?
104925: 06/07/09: PeterC: LUT4 INIT value to implement 2:1 MUX ?
104927: 06/07/09: Antti: Re: LUT4 INIT value to implement 2:1 MUX ?
104937: 06/07/10: Jim Wu: Re: LUT4 INIT value to implement 2:1 MUX ?
104939: 06/07/10: John_H: Re: LUT4 INIT value to implement 2:1 MUX ?
104951: 06/07/10: John_H: Re: LUT4 INIT value to implement 2:1 MUX ?
104949: 06/07/10: Tommy Thorn: Re: LUT4 INIT value to implement 2:1 MUX ?
104950: 06/07/10: Peter Alfke: Re: LUT4 INIT value to implement 2:1 MUX ?
104958: 06/07/10: PeterC: Re: LUT4 INIT value to implement 2:1 MUX ?
104959: 06/07/10: PeterC: Re: LUT4 INIT value to implement 2:1 MUX ?
104929: 06/07/10: Peter: Any *really old* Viewlogic / Xilinx users around here? :)
104932: 06/07/10: Symon: Re: Any *really old* Viewlogic / Xilinx users around here? :)
105109: 06/07/14: joseph2k: Re: Any *really old* Viewlogic / Xilinx users around here? :)
104942: 06/07/10: <jackhab@gmail.com>: PROM files: build .bin for daisy chain on the fly
104943: 06/07/10: Antti: Re: PROM files: build .bin for daisy chain on the fly
104960: 06/07/10: <jackhab@gmail.com>: Re: PROM files: build .bin for daisy chain on the fly
104965: 06/07/11: Antti: Re: PROM files: build .bin for daisy chain on the fly
104946: 06/07/10: Vivek Menon: P160 Communications module 3 with V2PRO--> EDK 7.1 errors
105236: 06/07/18: Vivek Menon: Re: P160 Communications module 3 with V2PRO--> EDK 7.1 errors
105238: 06/07/18: Mike Treseler: Re: P160 Communications module 3 with V2PRO--> EDK 7.1 errors
104953: 06/07/10: rnbrady: High-speed DAC/ADC with FPGA
104954: 06/07/10: PeterSmith1954@googlemail.com: Re: High-speed DAC/ADC with FPGA
104966: 06/07/11: David Brown: Re: High-speed DAC/ADC with FPGA
104967: 06/07/11: Jan Panteltje: Re: High-speed DAC/ADC with FPGA
104971: 06/07/11: Jan Panteltje: Re: High-speed DAC/ADC with FPGA
104981: 06/07/11: MM: Re: High-speed DAC/ADC with FPGA
104998: 06/07/11: MM: Re: High-speed DAC/ADC with FPGA
104955: 06/07/10: Peter Alfke: Re: High-speed DAC/ADC with FPGA
104956: 06/07/10: <bill.sloman@ieee.org>: Re: High-speed DAC/ADC with FPGA
104963: 06/07/11: rnbrady: Re: High-speed DAC/ADC with FPGA
104969: 06/07/11: <bill.sloman@ieee.org>: Re: High-speed DAC/ADC with FPGA
104980: 06/07/11: Andy: Re: High-speed DAC/ADC with FPGA
104982: 06/07/11: <jean-baptiste.nouvel@jdsu.com>: Re: High-speed DAC/ADC with FPGA
104984: 06/07/11: <jean-baptiste.nouvel@jdsu.com>: Re: High-speed DAC/ADC with FPGA
104989: 06/07/11: Andy: Re: High-speed DAC/ADC with FPGA
104993: 06/07/11: PeteS: Re: High-speed DAC/ADC with FPGA
105012: 06/07/11: PeteS: Re: High-speed DAC/ADC with FPGA
104962: 06/07/11: aName: Implementing USB slow protocol into xilink XC95xxx..
104964: 06/07/11: Antti: Re: Implementing USB slow protocol into xilink XC95xxx..
105000: 06/07/11: aName: Re: Implementing USB slow protocol into xilink XC95xxx..
104999: 06/07/11: Andy Peters: Re: Implementing USB slow protocol into xilink XC95xxx..
104968: 06/07/11: Rainer Buchty: Programming the Spartan-3E Starter Kit using Linux?
105022: 06/07/12: Jan Hansen: Re: Programming the Spartan-3E Starter Kit using Linux?
105031: 06/07/12: Rainer Buchty: Re: Programming the Spartan-3E Starter Kit using Linux?
105078: 06/07/13: Kees Bakker: Re: Programming the Spartan-3E Starter Kit using Linux?
105088: 06/07/13: Jan Panteltje: Re: Programming the Spartan-3E Starter Kit using Linux?
104970: 06/07/11: nmn: sopc -apex20ke1500xxxx
104974: 06/07/11: John Adair: Development Boards -Your chance to suggest features
104975: 06/07/11: Eli Hughes: Re: Development Boards -Your chance to suggest features
104985: 06/07/11: John Adair: Re: Development Boards -Your chance to suggest features
104986: 06/07/11: Jonathan Bromley: Re: Development Boards -Your chance to suggest features
104991: 06/07/11: John Adair: Re: Development Boards -Your chance to suggest features
105006: 06/07/11: Eli Hughes: Re: Development Boards -Your chance to suggest features
105094: 06/07/13: Nico Coesel: Re: Development Boards -Your chance to suggest features
105007: 06/07/11: Gabor: Re: Development Boards -Your chance to suggest features
105009: 06/07/11: John Adair: Re: Development Boards -Your chance to suggest features
105010: 06/07/11: John Adair: Re: Development Boards -Your chance to suggest features
105015: 06/07/12: Kryten: Re: Development Boards -Your chance to suggest features
105020: 06/07/12: John Adair: Re: Development Boards -Your chance to suggest features
105017: 06/07/11: radarman: Re: Development Boards -Your chance to suggest features
105021: 06/07/12: John Adair: Re: Development Boards -Your chance to suggest features
105178: 06/07/17: Martin Thompson: Re: Development Boards -Your chance to suggest features
105213: 06/07/18: Martin Thompson: Re: Development Boards -Your chance to suggest features
105049: 06/07/12: Jan Hansen: Re: Development Boards -Your chance to suggest features
105104: 06/07/13: Brannon: Re: Development Boards -Your chance to suggest features
105115: 06/07/13: John Adair: Re: Development Boards -Your chance to suggest features
105116: 06/07/13: John Adair: Re: Development Boards -Your chance to suggest features
105126: 06/07/14: John Adair: Re: Development Boards -Your chance to suggest features
105203: 06/07/17: John Adair: Re: Development Boards -Your chance to suggest features
104976: 06/07/11: 7Up: wrapper file error : ports not on the entity
104977: 06/07/11: pippo: DIFFICULT MULTICYCLE PATH WITH QUARTUS II
104983: 06/07/11: Austin Lesea: Re: DIFFICULT MULTICYCLE PATH WITH QUARTUS II, or any other tool
105032: 06/07/12: Hans: Re: DIFFICULT MULTICYCLE PATH WITH QUARTUS II, or any other tool
105035: 06/07/12: Austin Lesea: Re: DIFFICULT MULTICYCLE PATH WITH QUARTUS II, or any other tool
105002: 06/07/11: Mike Treseler: Re: DIFFICULT MULTICYCLE PATH WITH QUARTUS II
105004: 06/07/11: Subroto Datta: Re: DIFFICULT MULTICYCLE PATH WITH QUARTUS II
105025: 06/07/12: pippo: Re: DIFFICULT MULTICYCLE PATH WITH QUARTUS II, or any other tool
104988: 06/07/11: bjzhangwn@gmail.com: DLL in spartan2e
105008: 06/07/11: Gabor: Re: DLL in spartan2e
104990: 06/07/11: Jarrod Wood: Xilinx Virtex-4 APU Controller Questions
105347: 06/07/20: Dmitriy Bekker: Re: Xilinx Virtex-4 APU Controller Questions
105469: 06/07/24: Justin: Re: Xilinx Virtex-4 APU Controller Questions
104992: 06/07/11: Symon: Virtex-4 Vicm for LVDS with Vcco = 3.3V.
104994: 06/07/11: Austin Lesea: Re: Virtex-4 Vicm for LVDS with Vcco = 3.3V.
105023: 06/07/12: Symon: Re: Virtex-4 Vicm for LVDS with Vcco = 3.3V.
104995: 06/07/11: rnbrady: Assigning unused pins in Quartus II
104996: 06/07/11: Tommy Thorn: Re: Assigning unused pins in Quartus II
105016: 06/07/12: Subroto Datta: Re: Assigning unused pins in Quartus II
105003: 06/07/11: Subroto Datta: Re: Assigning unused pins in Quartus II
105005: 06/07/11: KJ: Re: Assigning unused pins in Quartus II
105067: 06/07/12: Hal Murray: Re: Assigning unused pins in Quartus II
105014: 06/07/11: Tommy Thorn: Re: Assigning unused pins in Quartus II
105027: 06/07/12: rnbrady: Re: Assigning unused pins in Quartus II
105028: 06/07/12: rnbrady: Re: Assigning unused pins in Quartus II
105030: 06/07/12: rnbrady: Re: Assigning unused pins in Quartus II
105019: 06/07/12: <bazarnik@hotmail.com>: Re: ISE8.1 on OpenSUSE 64bit => ISE8.2 works
105024: 06/07/12: Pasacco: how to implement multi-port memory
105026: 06/07/12: =?ISO-8859-1?Q?Michael_Sch=F6berl?=: Re: how to implement multi-port memory
105038: 06/07/12: rickman: Re: how to implement multi-port memory
105090: 06/07/13: Ralf Hildebrandt: Re: how to implement multi-port memory
105039: 06/07/12: John_H: Re: how to implement multi-port memory
105052: 06/07/12: zcsizmadia@gmail.com: Re: how to implement multi-port memory
105073: 06/07/13: Pasacco: Re: how to implement multi-port memory
105074: 06/07/13: Pasacco: Re: how to implement multi-port memory
105083: 06/07/13: rickman: Re: how to implement multi-port memory
105029: 06/07/12: Sean Durkin: Diffenrential I/Os in Virtex-4
105036: 06/07/12: Austin Lesea: Re: Diffenrential I/Os in Virtex-4
105047: 06/07/12: Jim Wu: Re: Diffenrential I/Os in Virtex-4
105054: 06/07/12: Sean Durkin: Re: Diffenrential I/Os in Virtex-4
105057: 06/07/12: Symon: Re: Diffenrential I/Os in Virtex-4
105066: 06/07/12: Sean Durkin: Re: Diffenrential I/Os in Virtex-4
105125: 06/07/14: Symon: Re: Diffenrential I/Os in Virtex-4
105033: 06/07/12: Vassili: Binary Counter Core
105034: 06/07/12: Vivek Menon: Re: Binary Counter Core
105037: 06/07/12: Vassili: Re: Binary Counter Core
105045: 06/07/12: Duane Clark: Re: Binary Counter Core
105060: 06/07/12: Duane Clark: Re: Binary Counter Core
105072: 06/07/13: backhus: Re: Binary Counter Core
105059: 06/07/12: Alain: Re: Binary Counter Core
105133: 06/07/14: Vassili: Re: Binary Counter Core
105041: 06/07/12: Nathan Bialke: Re: Programming the Spartan-3E Starter Kit using Linux?
105042: 06/07/12: <jhouse@btmd.com>: Can't get my Verilog Peripheral to import into XPS! Any tricks?
105065: 06/07/12: MM: Re: Can't get my Verilog Peripheral to import into XPS! Any tricks?
105081: 06/07/13: Joseph Samson: Re: Can't get my Verilog Peripheral to import into XPS! Any tricks?
105092: 06/07/13: Joseph Samson: Re: Can't get my Verilog Peripheral to import into XPS! Any tricks?
105070: 06/07/12: <jhouse@btmd.com>: Re: Can't get my Verilog Peripheral to import into XPS! Any tricks?
105089: 06/07/13: <jhouse@btmd.com>: Re: Can't get my Verilog Peripheral to import into XPS! Any tricks?
105095: 06/07/13: Eli Hughes: Re: Can't get my Verilog Peripheral to import into XPS! Any tricks?
105102: 06/07/13: Joseph Samson: Re: Can't get my Verilog Peripheral to import into XPS! Any tricks?
105046: 06/07/12: Antti: micron Flash controller VHDL disappeared ??
105091: 06/07/13: Antti: Re: micron Flash controller VHDL disappeared ??
105050: 06/07/12: superman321: Help with RBT file
105053: 06/07/12: Antti: Re: Help with RBT file
105061: 06/07/12: Superman321: Re: Help with RBT file
105064: 06/07/12: Superman321: Re: Help with RBT file
105063: 06/07/12: Antti: Re: Help with RBT file
105058: 06/07/12: John Adair: Re: Development Boards -Your chance to suggest features
105062: 06/07/12: Anonymous: reprogram xcf08 serial prom without jtag
105071: 06/07/12: Antti: Re: reprogram xcf08 serial prom without jtag
105069: 06/07/12: <amirhossein.gholamipour@gmail.com>: Micorblaze post place and route simulation...
105075: 06/07/13: <antti.tyrvainen@luukku.com>: Re: Micorblaze post place and route simulation...
105076: 06/07/13: mk: Re: Micorblaze post place and route simulation...
105079: 06/07/13: mk: Re: Micorblaze post place and route simulation...
105077: 06/07/13: <antti.tyrvainen@luukku.com>: Re: Micorblaze post place and route simulation...
105103: 06/07/13: Xesium: Re: Micorblaze post place and route simulation...
105080: 06/07/13: Frank Buss: Spartan 3E starter kit DDR SDRAM code
105087: 06/07/13: Frank Buss: Re: Spartan 3E starter kit DDR SDRAM code
105105: 06/07/13: Scott Schlachter: Re: Spartan 3E starter kit DDR SDRAM code
106231: 06/08/09: Tommy Thorn: Re: Spartan 3E starter kit DDR SDRAM code
105082: 06/07/13: John Adair: Raggedstone1 Ethernet Modules Available
105084: 06/07/13: manoj.rajpoot@gmail.com: Routing Information of Xilinx's Virtex-II FPGA
105085: 06/07/13: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: Programming the Spartan-3E Starter Kit using Linux?
105086: 06/07/13: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: Programming the Spartan-3E Starter Kit using Linux?
105093: 06/07/13: <George.Y.Ma@gmail.com>: Universal Scan with Xilinx's ML403
105097: 06/07/13: Antti: Re: Universal Scan with Xilinx's ML403
105106: 06/07/13: <George.Y.Ma@gmail.com>: Re: Universal Scan with Xilinx's ML403
105099: 06/07/13: Vivek Menon: ADC08D1500 + Virtex-4
105101: 06/07/13: MM: EDK - Debugging software applications located in ISOCM
105124: 06/07/14: Andi: Re: EDK - Debugging software applications located in ISOCM
105107: 06/07/13: rao: issue on on using Xilinx PROMS in conjugation with System ACE;
105108: 06/07/13: <syzygy01@gmail.com>: Cyclone II Power Measurement on DE2 Board
105110: 06/07/13: rickman: Separate enable on address for ram blocks
105112: 06/07/14: John_H: Re: Separate enable on address for ram blocks
105144: 06/07/14: John_H: Re: Separate enable on address for ram blocks
105121: 06/07/14: Symon: Re: Separate enable on address for ram blocks
105122: 06/07/14: rickman: Re: Separate enable on address for ram blocks
105147: 06/07/14: rickman: Re: Separate enable on address for ram blocks
105111: 06/07/13: Nitesh: PLB slaves
105118: 06/07/14: John McCaskill: Re: PLB slaves
105117: 06/07/14: Bram van de Kerkhof: EDK adding custom vhdl with multiple arch/entity
105123: 06/07/14: Andi: Re: EDK adding custom vhdl with multiple arch/entity
105119: 06/07/14: Christian Schleiffer: OPB or FSL?
105127: 06/07/14: Eli Hughes: Re: OPB or FSL?
105137: 06/07/14: Christian Schleiffer: Re: OPB or FSL?
105140: 06/07/14: Aurelian Lazarut: Re: OPB or FSL?
105206: 06/07/18: John Williams: Re: OPB or FSL?
105120: 06/07/14: <shalza.mittal@gmail.com>: design partition across multiple FPGAs
105152: 06/07/14: Hans: Re: design partition across multiple FPGAs
105156: 06/07/14: Brannon: Re: design partition across multiple FPGAs
105185: 06/07/17: Andy: Re: design partition across multiple FPGAs
105128: 06/07/14: Thomas Reinemann: Need for reset in FPGAs
105130: 06/07/14: PeteS: Re: Need for reset in FPGAs
105148: 06/07/14: Mike Treseler: Re: Need for reset in FPGAs
105131: 06/07/14: Noway2: Re: Need for reset in FPGAs
105146: 06/07/14: John_H: Re: Need for reset in FPGAs
105274: 06/07/19: Mike Lewis: Re: Need for reset in FPGAs
105134: 06/07/14: PeteS: Re: Need for reset in FPGAs
105135: 06/07/14: Jochen: Re: Need for reset in FPGAs
105136: 06/07/14: Nial Stewart: Re: Need for reset in FPGAs
105153: 06/07/14: Hans: Re: Need for reset in FPGAs
105154: 06/07/14: Mike Treseler: Re: Need for reset in FPGAs
105162: 06/07/15: Bob Perlman: Re: Need for reset in FPGAs
105179: 06/07/17: Martin Thompson: Re: Need for reset in FPGAs
105132: 06/07/14: <heinerlitz@gmx.de>: Using Samsung DDR2 memory with Xilinx Memory Interface Generator (MIG)
105138: 06/07/14: Joseph Samson: Re: Using Samsung DDR2 memory with Xilinx Memory Interface Generator
105139: 06/07/14: Xesium: Post Place and Route simulation for Microblaze....
105240: 06/07/18: =?ISO-8859-1?Q?G=F6ran_Bilski?=: Re: Post Place and Route simulation for Microblaze....
105930: 06/08/02: Xesium: Re: Post Place and Route simulation for Microblaze....
105155: 06/07/14: Guru: Virtex4 Mini-Module Phy interrupt
105158: 06/07/14: Pete Fraser: Data Logging / FPGA Dev board
105161: 06/07/15: John Adair: Re: Data Logging / FPGA Dev board
105163: 06/07/16: Rashid: An idea for a product (FPGA/ASIC based)
105164: 06/07/16: Frank Buss: Re: An idea for a product (FPGA/ASIC based)
105165: 06/07/16: Rashid: Re: An idea for a product (FPGA/ASIC based)
105166: 06/07/16: Antti: Re: An idea for a product (FPGA/ASIC based)
105167: 06/07/16: Jan Panteltje: Re: An idea for a product (FPGA/ASIC based)
105168: 06/07/16: John Adair: Re: An idea for a product (FPGA/ASIC based)
105170: 06/07/16: Nico Coesel: Re: An idea for a product (FPGA/ASIC based)
105171: 06/07/16: viron: Re: An idea for a product (FPGA/ASIC based)
105312: 06/07/20: przemek klosowski: Re: An idea for a product (FPGA/ASIC based)
105516: 06/07/25: viron: Re: An idea for a product (FPGA/ASIC based)
105534: 06/07/25: Brannon: Re: An idea for a product (FPGA/ASIC based)
105537: 06/07/25: John_H: Re: An idea for a product (FPGA/ASIC based)
105593: 06/07/26: John_H: Re: An idea for a product (FPGA/ASIC based)
105539: 06/07/25: Andy Ray: Re: An idea for a product (FPGA/ASIC based)
105586: 06/07/26: Brannon: Re: An idea for a product (FPGA/ASIC based)
105587: 06/07/26: Brannon: Re: An idea for a product (FPGA/ASIC based)
105591: 06/07/26: Weng Tianxiang: Re: An idea for a product (FPGA/ASIC based)
105619: 06/07/27: Brannon: Re: An idea for a product (FPGA/ASIC based)
105636: 06/07/27: Weng Tianxiang: Re: An idea for a product (FPGA/ASIC based)
105169: 06/07/16: Antti: Xilinx System ACE Player available
105172: 06/07/17: mk: 2048 input or gate ?
105174: 06/07/16: rickman: Re: 2048 input or gate ?
105176: 06/07/16: John Adair: Re: 2048 input or gate ?
105180: 06/07/17: Symon: Re: 2048 input or gate ?
105187: 06/07/17: Symon: Re: 2048 input or gate ?
105188: 06/07/17: John_H: Re: 2048 input or gate ?
105194: 06/07/17: John_H: Re: 2048 input or gate ?
105198: 06/07/17: mk: Re: 2048 input or gate ?
105199: 06/07/17: John_H: Re: 2048 input or gate ?
105189: 06/07/17: Ben Jones: Re: 2048 input or gate ?
105191: 06/07/17: Symon: Re: 2048 input or gate ?
105207: 06/07/18: John_H: Re: 2048 input or gate ?
105214: 06/07/18: Ben Jones: Re: 2048 input or gate ?
105216: 06/07/18: Jim Granville: Re: 2048 input or gate ?
105224: 06/07/18: Ben Jones: Re: 2048 input or gate ?
105219: 06/07/18: Symon: Re: 2048 input or gate ?
105223: 06/07/18: Ben Jones: Re: 2048 input or gate ?
105229: 06/07/18: Symon: Re: 2048 input or gate ?
105186: 06/07/17: rickman: Re: 2048 input or gate ?
105205: 06/07/17: rickman: Re: 2048 input or gate ?
105173: 06/07/16: <hrocarina@gmail.com>: FPGA consultants
105175: 06/07/16: Bryan Hackney: Re: FPGA consultants
105177: 06/07/17: Antti: OpenFire - public domain MicroBlaze clone in verilog
105181: 06/07/17: Sandro: Re: OpenFire - public domain MicroBlaze clone in verilog
105233: 06/07/18: Antti Lukats: Re: OpenFire - public domain MicroBlaze clone in verilog
105182: 06/07/17: Antti: Re: OpenFire - public domain MicroBlaze clone in verilog
105226: 06/07/18: Stephen Craven: Re: OpenFire - public domain MicroBlaze clone in verilog
105228: 06/07/18: Antti: Re: OpenFire - public domain MicroBlaze clone in verilog
105232: 06/07/18: Stephen Craven: Re: OpenFire - public domain MicroBlaze clone in verilog
105280: 06/07/19: Stephen Craven: Re: OpenFire - public domain MicroBlaze clone in verilog
105184: 06/07/17: Andy: Re: Need for reset in FPGAs
105190: 06/07/17: Sean: EDK PowerPC ISS : download errors?
105192: 06/07/17: Antti Lukats: ISE 8.2 WebPack does not support Virtex-5 at all?
105197: 06/07/17: Antti Lukats: Re: ISE 8.2 WebPack does not support Virtex-5 at all?
105200: 06/07/17: John_H: Re: ISE 8.2 WebPack does not support Virtex-5 at all?
105202: 06/07/18: Jim Granville: Re: ISE 8.2 WebPack does not support Virtex-5 at all?
105193: 06/07/17: Antti Lukats: Re: EDK PowerPC ISS : download errors?
105195: 06/07/17: Tommy Thorn: Re: ISE 8.2 WebPack does not support Virtex-5 at all?
105196: 06/07/17: Antti Lukats: Re: ISE 8.2 WebPack does not support Virtex-5 at all?
105201: 06/07/17: PeteS: Re: Need for reset in FPGAs
105204: 06/07/17: Marc Reinig: Virtex 4, LVDS I/O: Sanity check please
105212: 06/07/18: John Adair: Re: Virtex 4, LVDS I/O: Sanity check please
105415: 06/07/22: John Adair: Re: Virtex 4, LVDS I/O: Sanity check please
105444: 06/07/23: Austin Lesea: Re: Virtex 4, LVDS I/O: Sanity check please
105453: 06/07/23: Austin Lesea: Re: Virtex 4, LVDS I/O: Sanity check please
105420: 06/07/22: PeteS: Re: Virtex 4, LVDS I/O: Sanity check please
105447: 06/07/23: PeteS: Re: Virtex 4, LVDS I/O: Sanity check please
105209: 06/07/17: <Jesper.Kristensen@tellabs.com>: Reuse a Speed Grade -8 Stratix image in Speed Grade -6 ...?
105231: 06/07/18: Slurp: Re: Reuse a Speed Grade -8 Stratix image in Speed Grade -6 ...?
105262: 06/07/19: Fredrik: Re: Reuse a Speed Grade -8 Stratix image in Speed Grade -6 ...?
105265: 06/07/19: Bob Perlman: Re: Reuse a Speed Grade -8 Stratix image in Speed Grade -6 ...?
105290: 06/07/19: Subroto Datta: Re: Reuse a Speed Grade -8 Stratix image in Speed Grade -6 ...?
105210: 06/07/17: subint: Opencore ddr_controller
105215: 06/07/18: =?ISO-8859-1?Q?Michael_Sch=F6berl?=: Re: Opencore ddr_controller
105217: 06/07/18: KJ: Re: Opencore ddr_controller
105243: 06/07/18: Nico Coesel: Re: Opencore ddr_controller
105221: 06/07/18: subint: Re: Opencore ddr_controller
105211: 06/07/18: =?iso-8859-1?B?RmRvLkxl824=?=: noob question: reset problem
105220: 06/07/18: sjulhes: JED file translator
105245: 06/07/19: Jim Granville: Re: JED file translator
105379: 06/07/21: sjulhes: Re: JED file translator
105222: 06/07/18: <sgfallows@gmail.com>: Burnig flash image with Xilinx EDK flashwriter tool
105225: 06/07/18: =?ISO-8859-1?Q?Johan_Bernsp=E5ng?=: Partial shift register extraction in ISE
105242: 06/07/18: Gabor: Re: Partial shift register extraction in ISE
105264: 06/07/19: =?ISO-8859-1?Q?Johan_Bernsp=E5ng?=: Re: Partial shift register extraction in ISE
105315: 06/07/20: =?ISO-8859-1?Q?Johan_Bernsp=E5ng?=: Re: Partial shift register extraction in ISE
105272: 06/07/19: Gabor: Re: Partial shift register extraction in ISE
105227: 06/07/18: <baker.ea@gmail.com>: NAND flash hangs
105230: 06/07/18: Antti: Re: NAND flash hangs
105246: 06/07/18: Marc Battyani: Re: NAND flash hangs
105254: 06/07/18: Andy Peters: Re: NAND flash hangs
105266: 06/07/19: <baker.ea@gmail.com>: Re: NAND flash hangs
105234: 06/07/18: PeteS: Re: Virtex 4, LVDS I/O: Sanity check please
105241: 06/07/18: Marc Reinig: Re: Virtex 4, LVDS I/O: Sanity check please
105248: 06/07/19: Tim: Re: Virtex 4, LVDS I/O: Sanity check please
105249: 06/07/18: Marc Reinig: Re: Virtex 4, LVDS I/O: Sanity check please
105235: 06/07/18: Brian McFarland: Which PCI core for Cyclone II board?
105239: 06/07/18: Antti Lukats: Re: Which PCI core for Cyclone II board?
105259: 06/07/19: antonio bergnoli: Re: Which PCI core for Cyclone II board?
105268: 06/07/19: antonio bergnoli: Re: Which PCI core for Cyclone II board?
105295: 06/07/19: Antti Lukats: Re: Which PCI core for Cyclone II board?
105251: 06/07/19: Mark McDougall: Re: Which PCI core for Cyclone II board?
105293: 06/07/19: Eric Crabill: Re: Which PCI core for Cyclone II board?
105306: 06/07/19: Hal Murray: Re: Which PCI core for Cyclone II board?
105307: 06/07/20: Mark McDougall: Re: Which PCI core for Cyclone II board?
105505: 06/07/25: Mark McDougall: Re: Which PCI core for Cyclone II board?
105506: 06/07/25: Mark McDougall: Re: Which PCI core for Cyclone II board?
105600: 06/07/27: Mark McDougall: Re: Which PCI core for Cyclone II board?
105605: 06/07/27: Mark McDougall: Re: Which PCI core for Cyclone II board?
105258: 06/07/19: Karl: Re: Which PCI core for Cyclone II board?
105263: 06/07/19: Antti: Re: Which PCI core for Cyclone II board?
105277: 06/07/19: Brian McFarland: Re: Which PCI core for Cyclone II board?
105294: 06/07/19: bart: Re: Which PCI core for Cyclone II board?
105399: 06/07/21: Brian McFarland: Re: Which PCI core for Cyclone II board?
105574: 06/07/26: Brian McFarland: Re: Which PCI core for Cyclone II board?
105602: 06/07/26: johnp: Re: Which PCI core for Cyclone II board?
105244: 06/07/18: Antti Lukats: ISE 8.2 - time to crash 20 minutes
105252: 06/07/19: Jim Granville: Re: ISE 8.2 - time to crash 20 minutes
105255: 06/07/19: Antti Lukats: Re: ISE 8.2 - time to crash 20 minutes
105256: 06/07/19: Jim Granville: Re: ISE 8.2 - time to crash 20 minutes
105247: 06/07/18: Dan: Virtex 4 ACE Compact Flash configuration problem
105250: 06/07/18: Siva Velusamy: Re: Virtex 4 ACE Compact Flash configuration problem
105253: 06/07/18: Dan: Re: Virtex 4 ACE Compact Flash configuration problem
105286: 06/07/19: Ed McGettigan: Re: Virtex 4 ACE Compact Flash configuration problem
105291: 06/07/19: Dan: Re: Virtex 4 ACE Compact Flash configuration problem
105308: 06/07/19: Ed McGettigan: Re: Virtex 4 ACE Compact Flash configuration problem
105356: 06/07/20: Ed McGettigan: Re: Virtex 4 ACE Compact Flash configuration problem
105395: 06/07/21: Ed McGettigan: Re: Virtex 4 ACE Compact Flash configuration problem
105470: 06/07/24: Ed McGettigan: Re: Virtex 4 ACE Compact Flash configuration problem
105495: 06/07/24: Ed McGettigan: Re: Virtex 4 ACE Compact Flash configuration problem
105555: 06/07/25: Ed McGettigan: Re: Virtex 4 ACE Compact Flash configuration problem
105585: 06/07/26: Ed McGettigan: Re: Virtex 4 ACE Compact Flash configuration problem
105296: 06/07/19: Dan: Re: Virtex 4 ACE Compact Flash configuration problem
105299: 06/07/19: Dan: Re: Virtex 4 ACE Compact Flash configuration problem
105357: 06/07/20: EEngineer: Re: Virtex 4 ACE Compact Flash configuration problem
105401: 06/07/21: EEngineer: Re: Virtex 4 ACE Compact Flash configuration problem
105475: 06/07/24: EEngineer: Re: Virtex 4 ACE Compact Flash configuration problem
105476: 06/07/24: EEngineer: Re: Virtex 4 ACE Compact Flash configuration problem
105477: 06/07/24: EEngineer: Re: Virtex 4 ACE Compact Flash configuration problem
105552: 06/07/25: EEngineer: Re: Virtex 4 ACE Compact Flash configuration problem
105576: 06/07/26: EEngineer: Re: Virtex 4 ACE Compact Flash configuration problem
105578: 06/07/26: EEngineer: Re: Virtex 4 ACE Compact Flash configuration problem
105257: 06/07/18: Antti: Re: Virtex 4 ACE Compact Flash configuration problem
105267: 06/07/19: homoalteraiensis: Synthesis Problems with Quartus II Version 6.x
105292: 06/07/19: Derek Simmons: Re: Synthesis Problems with Quartus II Version 6.x
105269: 06/07/19: homoalteraiensis: corrupted data when accessing dual port bram in Cyclone II
105270: 06/07/19: KJ: Re: corrupted data when accessing dual port bram in Cyclone II
105271: 06/07/19: homoalteraiensis: Re: corrupted data when accessing dual port bram in Cyclone II
105273: 06/07/19: Colin Paul Gloster: Re: corrupted data when accessing dual port bram in Cyclone II
105279: 06/07/19: Subroto Datta: Re: corrupted data when accessing dual port bram in Cyclone II
105301: 06/07/20: Jim Granville: Re: corrupted data when accessing dual port bram in Cyclone II
105310: 06/07/20: KJ: Re: corrupted data when accessing dual port bram in Cyclone II
105288: 06/07/19: homoalteraiensis: Re: corrupted data when accessing dual port bram in Cyclone II
105297: 06/07/19: KJ: Re: corrupted data when accessing dual port bram in Cyclone II
105328: 06/07/20: <dkarchmer@gmail.com>: Re: corrupted data when accessing dual port bram in Cyclone II
105418: 06/07/22: homoalteraiensis: Re: corrupted data when accessing dual port bram in Cyclone II
105275: 06/07/19: <jackhab@gmail.com>: Virtex-4 PowerPC and Trace32 ICD - start up help wanted
105276: 06/07/19: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: PCIe: use 8*x1 PHY devices to form x8
105278: 06/07/19: Antti: Re: PCIe: use 8*x1 PHY devices to form x8
105367: 06/07/20: Aashish Malhotra: Re: PCIe: use 8*x1 PHY devices to form x8
105281: 06/07/19: Alex: VHDL Data Buffer on Spartan-3E
105283: 06/07/19: Frank Buss: Re: VHDL Data Buffer on Spartan-3E
105284: 06/07/19: <heinerlitz@gmx.de>: Sorting algorithm for FPGA availlable?
105285: 06/07/19: homoalteraiensis: Re: Sorting algorithm for FPGA availlable?
105289: 06/07/19: Eric Crabill: Re: Sorting algorithm for FPGA availlable?
105909: 06/08/02: Eric Crabill: Re: Sorting algorithm for FPGA availlable?
105918: 06/08/02: Eric Crabill: Re: Sorting algorithm for FPGA availlable?
105305: 06/07/19: Ray Andraka: Re: Sorting algorithm for FPGA availlable?
105309: 06/07/19: JJ: Re: Sorting algorithm for FPGA availlable?
105751: 06/07/31: Kolja Sulimma: Re: Sorting algorithm for FPGA availlable?
105340: 06/07/20: Weng Tianxiang: Re: Sorting algorithm for FPGA availlable?
105350: 06/07/20: JJ: Re: Sorting algorithm for FPGA availlable?
105364: 06/07/20: Weng Tianxiang: Re: Sorting algorithm for FPGA availlable?
105837: 06/08/01: <fpga_toys@yahoo.com>: Re: Sorting algorithm for FPGA availlable?
105855: 06/08/01: Weng Tianxiang: Re: Sorting algorithm for FPGA availlable?
105915: 06/08/02: Weng Tianxiang: Re: Sorting algorithm for FPGA availlable?
105938: 06/08/03: Weng Tianxiang: Re: Sorting algorithm for FPGA availlable?
105287: 06/07/19: Patrik Eriksson: Specify Clock Correction Sequence for Virtex-II ProX MGT (Rocket
105298: 06/07/19: Subhasri krishnan: xess board problem (error downloading into ram)
105338: 06/07/20: Josep Durán: Re: xess board problem (error downloading into ram)
105351: 06/07/20: Subhasri krishnan: Re: xess board problem (error downloading into ram)
105300: 06/07/19: Antti Lukats: Yet another MicroBlaze clone !!
105302: 06/07/19: Brad Smallridge: Inferring a Xilinx FIFO
105304: 06/07/19: Mike Treseler: Re: Inferring a Xilinx FIFO
105318: 06/07/20: KJ: Re: Inferring a Xilinx FIFO
105303: 06/07/20: Per Jensen: Combining Schematic and VHDL code in Webpack 8.1 ??
105311: 06/07/19: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: Re: Combining Schematic and VHDL code in Webpack 8.1 ??
105589: 06/07/26: Nevo: Re: Combining Schematic and VHDL code in Webpack 8.1 ??
105313: 06/07/20: Phil Tomson: [ANN] RHDL-0.5.0 released
105314: 06/07/19: Antti: Re: RHDL-0.5.0 released
105316: 06/07/20: Antti: Virtex-5: SoftCore processors at 200MHz !
105317: 06/07/20: Frank Buss: Re: Virtex-5: SoftCore processors at 200MHz !
105321: 06/07/20: Symon: Re: Virtex-5: SoftCore processors at 200MHz !
105354: 06/07/21: Jim Granville: Re: Virtex-5: SoftCore processors at 200MHz !
105369: 06/07/20: <kempaj@yahoo.com>: Re: Virtex-5: SoftCore processors at 200MHz !
105373: 06/07/21: Jim Granville: Re: Virtex-5: SoftCore processors at 200MHz !
105959: 06/08/03: Antti Lukats: Re: Virtex-5: SoftCore processors at 200MHz !
105319: 06/07/20: John Adair: Last Chance for Tarfessock1 Features
105348: 06/07/20: Tommy Thorn: Re: Last Chance for Tarfessock1 Features
105349: 06/07/20: Bob Perlman: Re: Last Chance for Tarfessock1 Features
105394: 06/07/21: John_H: Re: Last Chance for Tarfessock1 Features
105408: 06/07/21: John_H: Re: Last Chance for Tarfessock1 Features
105383: 06/07/21: John Adair: Re: Last Chance for Tarfessock1 Features
105407: 06/07/21: Nico Coesel: Re: Last Chance for Tarfessock1 Features
105409: 06/07/21: John_H: Re: Last Chance for Tarfessock1 Features
105384: 06/07/21: John Adair: Re: Last Chance for Tarfessock1 Features
105385: 06/07/21: John Adair: Re: Last Chance for Tarfessock1 Features
105403: 06/07/21: John Adair: Re: Last Chance for Tarfessock1 Features
105412: 06/07/22: John Adair: Re: Last Chance for Tarfessock1 Features
105413: 06/07/22: John Adair: Re: Last Chance for Tarfessock1 Features
105416: 06/07/22: John Adair: Re: Last Chance for Tarfessock1 Features
105320: 06/07/20: <stenasc@yahoo.com>: ANN: Tyd-IP Code Generator adds NCO design capability
105322: 06/07/20: <heinerlitz@gmx.de>: MIG DDR2 controller does not work (reset problems?)
105332: 06/07/20: ALuPin@web.de: Re: MIG DDR2 controller does not work (reset problems?)
105334: 06/07/20: Antti: Re: MIG DDR2 controller does not work (reset problems?)
105362: 06/07/20: Joseph Samson: Re: MIG DDR2 controller does not work (reset problems?)
105387: 06/07/21: Joseph Samson: Re: MIG DDR2 controller does not work (reset problems?)
105398: 06/07/21: Joseph Samson: Re: MIG DDR2 controller does not work (reset problems?)
105430: 06/07/22: Joseph Samson: Re: MIG DDR2 controller does not work (reset problems?)
105437: 06/07/23: Sylvain Munaut: Re: MIG DDR2 controller does not work (reset problems?)
107748: 06/08/31: Bob: Re: MIG DDR2 controller does not work (reset problems?)
105386: 06/07/21: <heinerlitz@gmx.de>: Re: MIG DDR2 controller does not work (reset problems?)
105391: 06/07/21: <heinerlitz@gmx.de>: Re: MIG DDR2 controller does not work (reset problems?)
105414: 06/07/22: <heinerlitz@gmx.de>: Re: MIG DDR2 controller does not work (reset problems?)
105323: 06/07/20: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: ISE 8.2i and EDK8.1i
105325: 06/07/20: Antti: Re: ISE 8.2i and EDK8.1i
105329: 06/07/20: rsg: Re: ISE 8.2i and EDK8.1i
105361: 06/07/20: MM: Re: ISE 8.2i and EDK8.1i
105333: 06/07/20: Antti: Re: ISE 8.2i and EDK8.1i
105376: 06/07/20: Antti: Re: ISE 8.2i and EDK8.1i
105615: 06/07/27: Joseph Samson: Re: ISE 8.2i and EDK8.1i
105324: 06/07/20: Vivek Menon: High-speed ADC+ Rocket I/O capability FPGA board
105331: 06/07/20: Benjamin Todd: Re: High-speed ADC+ Rocket I/O capability FPGA board
105345: 06/07/20: John Adair: Re: High-speed ADC+ Rocket I/O capability FPGA board
105752: 06/07/31: Kolja Sulimma: Re: High-speed ADC+ Rocket I/O capability FPGA board
105352: 06/07/20: Vivek Menon: Re: High-speed ADC+ Rocket I/O capability FPGA board
105326: 06/07/20: Davy: Hardware book like "Code Complete"?
105359: 06/07/20: fp: Re: Hardware book like "Code Complete"?
105446: 06/07/23: KJ: Re: Hardware book like "Code Complete"?
105482: 06/07/24: Mike Treseler: Re: Hardware book like "Code Complete"?
105492: 06/07/24: Mike Treseler: Re: Hardware book like "Code Complete"?
105543: 06/07/25: Mike Treseler: Re: Hardware book like "Code Complete"?
105685: 06/07/28: Mike Treseler: Re: Hardware book like "Code Complete"?
105691: 06/07/28: Mike Treseler: Re: Hardware book like "Code Complete"?
105893: 06/08/02: Mike Treseler: Re: Hardware book like "Code Complete"?
105363: 06/07/20: Eric: Re: Hardware book like "Code Complete"?
105366: 06/07/20: Mike Treseler: Re: Hardware book like "Code Complete"?
105372: 06/07/20: Jonathan Bromley: Re: Hardware book like "Code Complete"?
105388: 06/07/21: Symon: Re: Hardware book like "Code Complete"?
105404: 06/07/21: Mike Treseler: Re: Hardware book like "Code Complete"?
105375: 06/07/21: Phil Tomson: Re: Hardware book like "Code Complete"?
105377: 06/07/20: Bob Perlman: Re: Hardware book like "Code Complete"?
105471: 06/07/24: J o h n _ E a t o n (at) hp . com (no spaces): Re: Hardware book like "Code Complete"?
106810: 06/08/20: David Ashley: Re: Hardware book like "Code Complete"?
105397: 06/07/21: Jon Forrest: Re: Hardware book like "Code Complete"?
105479: 06/07/24: Andy Glew: Re: Hardware book like "Code Complete"?
105483: 06/07/24: Mike Treseler: Re: Hardware book like "Code Complete"?
105485: 06/07/24: Dean Kent: Re: Hardware book like "Code Complete"?
105496: 06/07/24: Paul Floyd: Re: Hardware book like "Code Complete"?
105662: 06/07/28: Christer Ericson: Re: Hardware book like "Code Complete"?
106849: 06/08/21: Tom Lucas: Re: Hardware book like "Code Complete"?
105365: 06/07/20: Weng Tianxiang: Re: Hardware book like "Code Complete"?
105368: 06/07/20: Andy: Re: Hardware book like "Code Complete"?
105370: 06/07/20: JJ: Re: Hardware book like "Code Complete"?
105371: 06/07/20: <mikegurche@yahoo.com>: Re: Hardware book like "Code Complete"?
105390: 06/07/21: Ted: Re: Hardware book like "Code Complete"?
105402: 06/07/21: Tommy Thorn: Re: Hardware book like "Code Complete"?
105457: 06/07/24: Ian Bell: Re: Hardware book like "Code Complete"?
105466: 06/07/24: radarman: Re: Hardware book like "Code Complete"?
105468: 06/07/24: KJ: Re: Hardware book like "Code Complete"?
105478: 06/07/24: Andy: Re: Hardware book like "Code Complete"?
105480: 06/07/24: radarman: Re: Hardware book like "Code Complete"?
105486: 06/07/24: David Kanter: Re: Hardware book like "Code Complete"?
105488: 06/07/24: KJ: Re: Hardware book like "Code Complete"?
105489: 06/07/24: KJ: Re: Hardware book like "Code Complete"?
105491: 06/07/24: KJ: Re: Hardware book like "Code Complete"?
105494: 06/07/24: KJ: Re: Hardware book like "Code Complete"?
105497: 06/07/24: KJ: Re: Hardware book like "Code Complete"?
105515: 06/07/25: Davy: Re: Hardware book like "Code Complete"?
105689: 06/07/28: Mike Treseler: Re: Hardware book like "Code Complete"?
105700: 06/07/28: Paul Floyd: Re: Hardware book like "Code Complete"?
105536: 06/07/25: Andy: Re: Hardware book like "Code Complete"?
105540: 06/07/25: Andy: Re: Hardware book like "Code Complete"?
105541: 06/07/25: KJ: Re: Hardware book like "Code Complete"?
105542: 06/07/25: KJ: Re: Hardware book like "Code Complete"?
105547: 06/07/25: KJ: Re: Hardware book like "Code Complete"?
105584: 06/07/26: Andy: Re: Hardware book like "Code Complete"?
105652: 06/07/27: Weng Tianxiang: Re: Hardware book like "Code Complete"?
105666: 06/07/28: Weng Tianxiang: Re: Hardware book like "Code Complete"?
105687: 06/07/28: BobG: Re: Hardware book like "Code Complete"?
105688: 06/07/28: Weng Tianxiang: Re: Hardware book like "Code Complete"?
105697: 06/07/28: <mikegurche@yahoo.com>: Re: Hardware book like "Code Complete"?
105703: 06/07/28: Weng Tianxiang: Re: Hardware book like "Code Complete"?
105891: 06/08/02: Andy: Re: Hardware book like "Code Complete"?
106797: 06/08/19: vijayvithal jahagirdar: Re: Hardware book like "Code Complete"?
106812: 06/08/20: Colin Marquardt: Re: Hardware book like "Code Complete"?
106816: 06/08/20: vijay: Re: Hardware book like "Code Complete"?
106826: 06/08/20: larwe: Re: Hardware book like "Code Complete"?
105327: 06/07/20: David: tutorial searching
105341: 06/07/20: motty: Re: tutorial searching
105343: 06/07/20: Bob Perlman: Re: tutorial searching
105380: 06/07/20: David: Re: tutorial searching
105330: 06/07/20: oopere: clock hold time problems reported in quartus II
105335: 06/07/20: <kayrock66@yahoo.com>: Re: clock hold time problems reported in quartus II
105374: 06/07/21: Rob: Re: clock hold time problems reported in quartus II
105381: 06/07/21: oopere: Re: clock hold time problems reported in quartus II
105382: 06/07/21: oopere: Re: clock hold time problems reported in quartus II
105426: 06/07/22: Subroto Datta: Re: clock hold time problems reported in quartus II
105336: 06/07/20: wuyi316904@gmail.com: system design
105378: 06/07/20: Tim Wescott: Re: system design
105337: 06/07/20: Robin Bruce: Creating EDIF from Verilog, then using VHDL wrapper
105339: 06/07/20: Antti: Re: Creating EDIF from Verilog, then using VHDL wrapper
105405: 06/07/21: John Adair: Re: Creating EDIF from Verilog, then using VHDL wrapper
105342: 06/07/20: junaidabidi: Using DCM-Virtex-II Pro
105344: 06/07/20: Vivek Menon: Re: Using DCM-Virtex-II Pro
105346: 06/07/20: John_H: Re: Using DCM-Virtex-II Pro
105353: 06/07/20: EEngineer: Re: Virtex 4 ACE Compact Flash configuration problem
105355: 06/07/20: EEngineer: Re: Virtex 4 ACE Compact Flash configuration problem
105358: 06/07/20: EEngineer: Re: Virtex 4 ACE Compact Flash configuration problem
105360: 06/07/20: scotto: Linux on an XUP board - cant access user IP!
105389: 06/07/21: Deefoo: Spartan III development: which tools, what kind of PC?
105417: 06/07/22: Kishore: Re: Spartan III development: which tools, what kind of PC?
105392: 06/07/21: <patrick.melet@dmradiocom.fr>: PLL clock in in Stratix
105393: 06/07/21: <stephaneo@gmail.com>: IIR FPGA 'crosspost'
105442: 06/07/22: Ray Andraka: Re: IIR FPGA 'crosspost'
105396: 06/07/21: Geronimo Stempovski: XMatchPRO algorithm on FPGA
105400: 06/07/21: Rube Bumpkin: HW Debug tools
105406: 06/07/21: John Adair: Re: HW Debug tools
105422: 06/07/22: Nico Coesel: Re: HW Debug tools
105410: 06/07/22: Per Jensen: Using BUS'es in ISE WebPACK 3.3WP8.1 ???
105419: 06/07/22: Per Jensen: Re: Using BUS'es in ISE WebPACK 3.3WP8.1 ???
105425: 06/07/22: Mike Treseler: Re: Using BUS'es in ISE WebPACK 3.3WP8.1 ???
105434: 06/07/23: Per Jensen: Re: Using BUS'es in ISE WebPACK 3.3WP8.1 ???
105438: 06/07/23: Jim Granville: Re: Using BUS'es in ISE WebPACK 3.3WP8.1 ???
105440: 06/07/23: Per Jensen: Re: Using BUS'es in ISE WebPACK 3.3WP8.1 ???
105435: 06/07/23: Per Jensen: Re: Using BUS'es in ISE WebPACK 3.3WP8.1 ???
105421: 06/07/22: radarman: Re: Using BUS'es in ISE WebPACK 3.3WP8.1 ???
105411: 06/07/21: Wojciech Zabolotny: fpgadbg - a free & open source tool for FPGA debugging
105682: 06/07/28: Wojciech Zabolotny: New version of fpgadbg available - with serial port support
105683: 06/07/28: RobJ: Re: New version of fpgadbg available - with serial port support
105423: 06/07/22: Weng Tianxiang: How to print a state flow graph for a state machine using Xilinx ISE or ModelSim
105424: 06/07/22: Mike Treseler: Re: How to print a state flow graph for a state machine using Xilinx
105441: 06/07/23: Jan Hansen: Re: How to print a state flow graph for a state machine using Xilinx ISE or ModelSim
105527: 06/07/25: Weng Tianxiang: Re: How to print a state flow graph for a state machine using Xilinx ISE or ModelSim
105427: 06/07/22: fp: Why 8 clock trees in Xilinx Spartan-3 device?
105428: 06/07/22: Eric Smith: Re: Why 8 clock trees in Xilinx Spartan-3 device?
105429: 06/07/22: Sylvain Munaut: Re: Why 8 clock trees in Xilinx Spartan-3 device?
105432: 06/07/22: Nico Coesel: Re: Why 8 clock trees in Xilinx Spartan-3 device?
105445: 06/07/23: Austin Lesea: Re: Why 8 clock trees in Xilinx Spartan-3 device?
105450: 06/07/23: Tim: Re: Why 8 clock trees in Xilinx Spartan-3 device?
105455: 06/07/23: Austin Lesea: Re: Why 8 clock trees in Xilinx Spartan-3 device?
105452: 06/07/23: fp: Re: Why 8 clock trees in Xilinx Spartan-3 device?
105465: 06/07/24: Martin Thompson: Re: Why 8 clock trees in Xilinx Spartan-3 device?
105467: 06/07/24: fp: Re: Why 8 clock trees in Xilinx Spartan-3 device?
105431: 06/07/22: manu: version control of ISE+EDK projects with CVS and/or SVN
105459: 06/07/24: homoalteraiensis: Re: version control of ISE+EDK projects with CVS and/or SVN
105461: 06/07/24: Sean Durkin: Re: version control of ISE+EDK projects with CVS and/or SVN
105522: 06/07/25: <pbdelete@spamnuke.ludd.luthdelete.se.invalid>: Re: version control of ISE+EDK projects with CVS and/or SVN
105525: 06/07/25: Frank van Eijkelenburg: Re: version control of ISE+EDK projects with CVS and/or SVN
105433: 06/07/22: <adamou@gmail.com>: KASUMI source code in VHDL
105443: 06/07/23: Antti: Re: KASUMI source code in VHDL
105436: 06/07/22: MM: Trouble meeting EMAC RGMII timing in V4FX
105439: 06/07/22: Roger: MGT RXPOLARITY setting
105448: 06/07/23: Marco T.: Delta sigma Modulator Interface
105449: 06/07/23: Pasacco: <EDK> PORT .... not found in MPD
105565: 06/07/26: Felix Pang: Re: <EDK> PORT .... not found in MPD
105451: 06/07/23: Antti: ANN: MicroBlaze simulator available
105454: 06/07/23: eejw: Microblaze: how to determine remainder after integer division
105472: 06/07/24: Siva Velusamy: Re: Microblaze: how to determine remainder after integer division
105532: 06/07/25: eejw: Re: Microblaze: how to determine remainder after integer division
105456: 06/07/24: Clifford Heath: ByteBlasterMV?
105464: 06/07/24: Leon: Re: ByteBlasterMV?
105490: 06/07/24: Ben Jackson: Re: ByteBlasterMV?
105458: 06/07/24: gollum: ROM implementation
105460: 06/07/24: ALuPin@web.de: Re: ROM implementation
105463: 06/07/24: KJ: Re: ROM implementation
105484: 06/07/24: Andy: Re: ROM implementation
105740: 06/07/31: gollum: Re: ROM implementation
105462: 06/07/24: Frank van Eijkelenburg: chipscope opb monitor
105473: 06/07/24: Siva Velusamy: Re: chipscope opb monitor
105510: 06/07/25: Frank van Eijkelenburg: Re: chipscope opb monitor
105499: 06/07/24: <sunwei388@gmail.com>: Re: chipscope opb monitor
105513: 06/07/25: Frank van Eijkelenburg: Re: chipscope opb monitor
105723: 06/07/30: <sunwei388@gmail.com>: Re: chipscope opb monitor
105474: 06/07/24: <pauljbennett@gmail.com>: Xilinx Corgen & Synplicity... Anyone? Help?
105690: 06/07/28: Arnaud: Re: Xilinx Corgen & Synplicity... Anyone? Help?
105692: 06/07/28: Austin Lesea: Re: Xilinx Corgen & Synplicity... Anyone? Help?
105481: 06/07/24: Kyle H.: EDK Using External Ports to toggle FPGA pins
105503: 06/07/24: MM: Re: EDK Using External Ports to toggle FPGA pins
105504: 06/07/24: MM: Re: EDK Using External Ports to toggle FPGA pins
105564: 06/07/26: Felix Pang: Re: EDK Using External Ports to toggle FPGA pins
105622: 06/07/27: Kyle H.: Re: EDK Using External Ports to toggle FPGA pins
105487: 06/07/24: baboonspanker@fastmail.fm: Soft processor performance
105498: 06/07/24: =?ISO-8859-1?Q?G=F6ran_Bilski?=: Re: Soft processor performance
105493: 06/07/24: Vivek Menon: Correlator block
105528: 06/07/25: Vivek Menon: Correlator block along with ADC08D1500 Dev board?? Xilinx grp??
105501: 06/07/24: Subhasri krishnan: impact.log files
105512: 06/07/25: Antti: Re: impact.log files
105529: 06/07/25: Subhasri krishnan: Re: impact.log files
105502: 06/07/24: Andy Peters: Re: version control of ISE+EDK projects with CVS and/or SVN
105507: 06/07/24: Nevo: Connecting two buses in Xilinx ISE
105508: 06/07/25: backhus: Re: Connecting two buses in Xilinx ISE
105509: 06/07/24: <vlsi_kida@math.net>: EDK + Assembly Output Files + External Memory Usage
105511: 06/07/24: Antti: Re: EDK + Assembly Output Files + External Memory Usage
105519: 06/07/25: <MKULTRA2@gmail.com>: Re: EDK + Assembly Output Files + External Memory Usage
105563: 06/07/26: Felix Pang: Re: EDK + Assembly Output Files + External Memory Usage
105738: 06/07/30: wflee: Re: EDK + Assembly Output Files + External Memory Usage
105514: 06/07/25: Francesco Verdicchio: Calculate CRC in Virtex-Spartan II bitstream
105517: 06/07/25: Antti: Re: Calculate CRC in Virtex-Spartan II bitstream
105594: 06/07/26: <jbnote@gmail.com>: Re: Calculate CRC in Virtex-Spartan II bitstream
105518: 06/07/25: <MKULTRA2@gmail.com>: Xilkernel: Using the shared memory API
105520: 06/07/25: <MKULTRA2@gmail.com>: Re: Xilkernel: Using the shared memory API
105521: 06/07/25: raso: 2Khz clock signal from 50Hz main frequency with ADPLL
105523: 06/07/25: Symon: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
105524: 06/07/25: Jan Panteltje: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
105531: 06/07/25: Jan Panteltje: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
105533: 06/07/25: Falk Brunner: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
105550: 06/07/26: Jim Granville: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
105557: 06/07/26: Jim Granville: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
105575: 06/07/26: Falk Brunner: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
105590: 06/07/26: Falk Brunner: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
105595: 06/07/27: Jim Granville: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
105596: 06/07/26: Falk Brunner: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
105598: 06/07/27: Jim Granville: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
105583: 06/07/26: RobJ: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
105530: 06/07/25: raso: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
105546: 06/07/25: Jon Elson: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
105588: 06/07/26: Falk Brunner: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
105638: 06/07/28: Jim Granville: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
105716: 06/07/29: Falk Brunner: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
105553: 06/07/25: raso: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
105554: 06/07/25: raso: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
105581: 06/07/26: <panteltje@yahoo.com>: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
105618: 06/07/27: raso: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
105526: 06/07/25: Symon: Virtex4 Rocket I/O. Power filtering.
105538: 06/07/25: Symon: Re: Virtex4 Rocket I/O. Power filtering.
105556: 06/07/26: Mark McDougall: Re: Virtex4 Rocket I/O. Power filtering.
105570: 06/07/26: Symon: Re: Virtex4 Rocket I/O. Power filtering.
105535: 06/07/25: Vivek Menon: FFT module with Virtex-4 xc4vlx15
105544: 06/07/25: Javi: Clock signal remains HIGH forever in Spartan-3 Starter Kit from Digilent
105548: 06/07/25: Javi: Re: Clock signal remains HIGH forever in Spartan-3 Starter Kit from Digilent
105545: 06/07/25: billu: Issues w/ 8 lane Aurora sample design
105549: 06/07/25: Falk Brunner: Re: Issues w/ 8 lane Aurora sample design
105714: 06/07/29: Falk Brunner: Re: Issues w/ 8 lane Aurora sample design
105722: 06/07/29: Duane Clark: Re: Issues w/ 8 lane Aurora sample design
105641: 06/07/27: billu: Re: Issues w/ 8 lane Aurora sample design
105721: 06/07/29: billu: Re: Issues w/ 8 lane Aurora sample design
105844: 06/08/01: billu: Re: Issues w/ 8 lane Aurora sample design
105551: 06/07/25: Guru: uClinux on Virtex-4 Mini-Module
105562: 06/07/25: Antti: Re: uClinux on Virtex-4 Mini-Module
105571: 06/07/26: Eli Hughes: Re: uClinux on Virtex-4 Mini-Module
105599: 06/07/27: Antti Lukats: Re: uClinux on Virtex-4 Mini-Module
105566: 06/07/26: Guru: Re: uClinux on Virtex-4 Mini-Module
105567: 06/07/26: Guru: Re: uClinux on Virtex-4 Mini-Module
105569: 06/07/26: Antti: Re: uClinux on Virtex-4 Mini-Module
105592: 06/07/26: Guru: Re: uClinux on Virtex-4 Mini-Module
105558: 06/07/25: sirisha.aluru@gmail.com: Designing a matrix multpier block using existing xilinx toolbox
105559: 06/07/25: rickman: Spartan 3 clock to output tristate timing
105560: 06/07/26: RobJ: Re: Spartan 3 clock to output tristate timing
105561: 06/07/26: John_H: Re: Spartan 3 clock to output tristate timing
105579: 06/07/26: Symon: Re: Spartan 3 clock to output tristate timing
105582: 06/07/26: Nico Coesel: Re: Spartan 3 clock to output tristate timing
105607: 06/07/27: KJ: Re: Spartan 3 clock to output tristate timing
105614: 06/07/27: John_H: Re: Spartan 3 clock to output tristate timing
105606: 06/07/26: rickman: Re: Spartan 3 clock to output tristate timing
105667: 06/07/28: rickman: Re: Spartan 3 clock to output tristate timing
105568: 06/07/26: Martin Thompson: Re: Designing a matrix multpier block using existing xilinx toolbox
105572: 06/07/26: subint: How to phase align a 10MHz clock using V4LX60 DCM
105573: 06/07/26: Gabor: Re: How to phase align a 10MHz clock using V4LX60 DCM
105580: 06/07/26: Aurelian Lazarut: Re: How to phase align a 10MHz clock using V4LX60 DCM
105577: 06/07/26: vssumesh: Re: How to phase align a 10MHz clock using V4LX60 DCM
105597: 06/07/26: PeteS: Re: How to phase align a 10MHz clock using V4LX60 DCM
105601: 06/07/26: TT: Hold violation in Virtex 4
105603: 06/07/27: Bob: Re: Hold violation in Virtex 4
105604: 06/07/27: Bob: Re: Hold violation in Virtex 4
105623: 06/07/27: TT: Re: Hold violation in Virtex 4
105608: 06/07/27: Olli: EDK : *.bit and *.elf Files
105609: 06/07/27: Ron: Re: EDK : *.bit and *.elf Files
105610: 06/07/27: Olli: Re: EDK : *.bit and *.elf Files
105616: 06/07/27: MM: Re: *.bit and *.elf Files
105663: 06/07/28: Olli: Re: EDK : *.bit and *.elf Files
105673: 06/07/28: MM: Re: EDK : *.bit and *.elf Files
105737: 06/07/30: Olli: Re: EDK : *.bit and *.elf Files
105764: 06/07/31: MM: Re: EDK : *.bit and *.elf Files
105748: 06/07/31: Mateen: Re: EDK : *.bit and *.elf Files
105762: 06/07/31: MM: Re: EDK : *.bit and *.elf Files
105611: 06/07/27: RobertP.: IOBDELAY and DCM
105612: 06/07/27: Gabor: Re: IOBDELAY and DCM
105613: 06/07/27: RobertP.: Re: IOBDELAY and DCM
105661: 06/07/28: Bob: Re: IOBDELAY and DCM
105678: 06/07/28: RobJ: Re: IOBDELAY and DCM
105617: 06/07/27: MM: Guided MAP/PAR in ISE
105620: 06/07/27: Brannon: Re: Guided MAP/PAR in ISE
105624: 06/07/27: MM: Re: Guided MAP/PAR in ISE
105631: 06/07/27: RobJ: Re: Guided MAP/PAR in ISE
105643: 06/07/27: Eric Crabill: Re: Guided MAP/PAR in ISE
105647: 06/07/27: MM: Re: Guided MAP/PAR in ISE
105649: 06/07/28: Jim Granville: Re: Guided MAP/PAR in ISE
105650: 06/07/27: Eric Crabill: Re: Guided MAP/PAR in ISE
105651: 06/07/27: Ray Andraka: Re: Guided MAP/PAR in ISE
105656: 06/07/27: Ray Andraka: Re: Guided MAP/PAR in ISE
105633: 06/07/27: Petter Gustad: Re: Guided MAP/PAR in ISE
105653: 06/07/27: johnp: Re: Guided MAP/PAR in ISE
105659: 06/07/27: mh: Re: Guided MAP/PAR in ISE
105621: 06/07/27: Benjamin Todd: Rocket IO as a high speed sampler
105625: 06/07/27: Antti Lukats: Re: Rocket IO as a high speed sampler
105627: 06/07/27: Austin Lesea: Re: Rocket IO as a high speed sampler
105630: 06/07/27: Antti Lukats: Re: Rocket IO as a high speed sampler
105626: 06/07/27: Austin Lesea: Re: Rocket IO as a high speed sampler
105632: 06/07/27: Antti Lukats: Re: Rocket IO as a high speed sampler
105635: 06/07/27: Austin Lesea: Re: Rocket IO as a high speed sampler
105758: 06/07/31: Kolja Sulimma: Re: Rocket IO as a high speed sampler
105639: 06/07/27: John_H: Re: Rocket IO as a high speed sampler
105668: 06/07/28: Benjamin Todd: Re: Rocket IO as a high speed sampler
105741: 06/07/31: Alvaro Combo: Re: Rocket IO as a high speed sampler
105775: 06/07/31: Benjamin Todd: Re: Rocket IO as a high speed sampler
105628: 06/07/27: Paul Urbanus: Wanted: CPU config register code generator
105655: 06/07/27: <pmaupin@gmail.com>: Re: Wanted: CPU config register code generator
105629: 06/07/27: Andy: Re: Rocket IO as a high speed sampler
105634: 06/07/27: Kyle H.: Re: *.bit and *.elf Files
105637: 06/07/27: Kyle H.: Re: *.bit and *.elf Files
105640: 06/07/27: Dave Pollum: OT (2nd try): do you get paid for your travel time?
105642: 06/07/27: Mike Treseler: Re: OT (2nd try): do you get paid for your travel time?
105645: 06/07/27: Austin Lesea: Re: OT (2nd try): do you get paid for your travel time?
105646: 06/07/27: John_H: Re: OT (2nd try): do you get paid for your travel time?
105648: 06/07/27: Ray Andraka: Re: OT (2nd try): do you get paid for your travel time?
105657: 06/07/27: Tim Wescott: Re: OT (2nd try): do you get paid for your travel time?
105658: 06/07/28: Anonymous: Re: OT (2nd try): do you get paid for your travel time?
105660: 06/07/28: RobJ: Re: OT (2nd try): do you get paid for your travel time?
105669: 06/07/28: Dave Pollum: Re: OT (2nd try): do you get paid for your travel time?
105670: 06/07/28: fred: Re: OT (2nd try): do you get paid for your travel time?
105654: 06/07/27: Sophi: Does MAC FIR filter need special care?
105686: 06/07/28: MM: Re: Does MAC FIR filter need special care?
105726: 06/07/30: MM: Re: Does MAC FIR filter need special care?
105732: 06/07/30: MM: Re: Does MAC FIR filter need special care?
105710: 06/07/28: Sophi: Re: Does MAC FIR filter need special care?
105730: 06/07/30: Sophi: Re: Does MAC FIR filter need special care?
105793: 06/07/31: Sophi: Re: Does MAC FIR filter need special care?
105664: 06/07/28: yy: Spartan3 5V PCI
105665: 06/07/28: PeteS: Re: Spartan3 5V PCI
105695: 06/07/28: John Adair: Re: Spartan3 5V PCI
105701: 06/07/28: yy: Re: Spartan3 5V PCI
105671: 06/07/28: ba@jb.man.ac.uk: 4VSX35 LOC placements?
105672: 06/07/28: Jim Wu: Re: 4VSX35 LOC placements?
105674: 06/07/28: ba@jb.man.ac.uk: Re: 4VSX35 LOC placements?
105698: 06/07/28: Jim Wu: Re: 4VSX35 LOC placements?
105675: 06/07/28: rickman: Verilog case statements
105676: 06/07/28: John_H: Re: Verilog case statements
105677: 06/07/28: Ralf Hildebrandt: Re: Verilog case statements
105681: 06/07/28: Ralf Hildebrandt: Re: Verilog case statements
105684: 06/07/28: John_H: Re: Verilog case statements
105711: 06/07/29: Ralf Hildebrandt: Re: Verilog case statements
105679: 06/07/28: rickman: Re: Verilog case statements
105680: 06/07/28: RobJ: Re: Verilog case statements
105731: 06/07/31: luiguo: Re: Verilog case statements
105770: 06/07/31: Ralf Hildebrandt: Re: Verilog case statements
105704: 06/07/28: rickman: Re: Verilog case statements
105705: 06/07/28: rickman: Re: Verilog case statements
105706: 06/07/28: Josh Rosen: Re: Verilog case statements
105708: 06/07/29: RobJ: Re: Verilog case statements
105717: 06/07/29: Josh Rosen: Re: Verilog case statements
105713: 06/07/29: rickman: Re: Verilog case statements
105719: 06/07/29: rickman: Re: Verilog case statements
105733: 06/07/30: rickman: Re: Verilog case statements
105772: 06/07/31: deepak.lala@gmail.com: Re: Verilog case statements
105693: 06/07/28: Nevo: "This design element is inferred rather than instantiated" (newbie)
105694: 06/07/28: Nevo: Re: "This design element is inferred rather than instantiated" (newbie)
105712: 06/07/29: Ralf Hildebrandt: Re: "This design element is inferred rather than instantiated" (newbie)
105696: 06/07/28: Brian McFarland: Re: "This design element is inferred rather than instantiated" (newbie)
105699: 06/07/28: Ben Jackson: Re: "This design element is inferred rather than instantiated" (newbie)
105725: 06/07/30: Nevo: Re: "This design element is inferred rather than instantiated" (newbie)
105727: 06/07/30: Frank Buss: Re: "This design element is inferred rather than instantiated" (newbie)
105729: 06/07/30: Ben Jackson: Re: "This design element is inferred rather than instantiated" (newbie)
105728: 06/07/30: radarman: Re: "This design element is inferred rather than instantiated" (newbie)
105702: 06/07/28: mpierrotb: large data access to SDRAM at fixed frequency
105715: 06/07/29: Falk Brunner: Re: large data access to SDRAM at fixed frequency
105768: 06/07/31: Gabor: Re: large data access to SDRAM at fixed frequency
106026: 06/08/05: homoalteraiensis: Re: large data access to SDRAM at fixed frequency
105707: 06/07/28: Nevo: Can I get 840HZ from a Xilinx Spartan-3's DCM? Phase locked?
105709: 06/07/29: RobJ: Re: Can I get 840HZ from a Xilinx Spartan-3's DCM? Phase locked?
105724: 06/07/30: Nevo: Re: Can I get 840HZ from a Xilinx Spartan-3's DCM? Phase locked?
105720: 06/07/29: Frank Buss: Re: Can I get 840HZ from a Xilinx Spartan-3's DCM? Phase locked?
105718: 06/07/29: yy: Interfacing Spartan3 FPGA to 5V PCI
105735: 06/07/30: <Sudhir.Singh@email.com>: Re: Interfacing Spartan3 FPGA to 5V PCI
105739: 06/07/31: yy: Re: Interfacing Spartan3 FPGA to 5V PCI
105796: 06/07/31: <Sudhir.Singh@email.com>: Re: Interfacing Spartan3 FPGA to 5V PCI
105734: 06/07/31: Mr. Ken: In a function, how to I do bit-extension on temp variables:
105736: 06/07/30: Ron: Re: In a function, how to I do bit-extension on temp variables:
105742: 06/07/31: Mr. Ken: Re: In a function, how to I do bit-extension on temp variables:
105754: 06/07/31: RobJ: Re: In a function, how to I do bit-extension on temp variables:
105743: 06/07/31: Mr. Ken: How do I create a clock with random starting phase?
105761: 06/07/31: Gabor: Re: How do I create a clock with random starting phase?
105744: 06/07/31: Ben_M: Accessing one SDRAM from two MicroBlazes
105773: 06/07/31: PeteS: Re: Accessing one SDRAM from two MicroBlazes
105778: 06/07/31: Siva Velusamy: Re: Accessing one SDRAM from two MicroBlazes
105786: 06/07/31: Siva Velusamy: Re: Accessing one SDRAM from two MicroBlazes
105850: 06/08/01: Siva Velusamy: Re: Accessing one SDRAM from two MicroBlazes
105781: 06/07/31: <quickwayne@gmail.com>: Re: Accessing one SDRAM from two MicroBlazes
105836: 06/08/01: <quickwayne@gmail.com>: Re: Accessing one SDRAM from two MicroBlazes
105858: 06/08/01: <quickwayne@gmail.com>: Re: Accessing one SDRAM from two MicroBlazes
105876: 06/08/02: Ben_M: Re: Accessing one SDRAM from two MicroBlazes
105745: 06/07/31: al99999: Problem with assigning package pins using PACE
105746: 06/07/31: <aijazbaig1@gmail.com>: Problems compiling with ISE Webpack 8.2.01i
105750: 06/07/31: Frank Buss: Re: Problems compiling with ISE Webpack 8.2.01i
105769: 06/07/31: Frank Buss: Re: Problems compiling with ISE Webpack 8.2.01i
105755: 06/07/31: <aijazbaig1@gmail.com>: Re: Problems compiling with ISE Webpack 8.2.01i
105785: 06/07/31: <quickwayne@gmail.com>: Re: Problems compiling with ISE Webpack 8.2.01i
105803: 06/08/01: <aijazbaig1@gmail.com>: Re: Problems compiling with ISE Webpack 8.2.01i
105831: 06/08/01: Duane Clark: Re: Problems compiling with ISE Webpack 8.2.01i
105894: 06/08/02: Duane Clark: Re: Problems compiling with ISE Webpack 8.2.01i
105886: 06/08/02: <aijazbaig1@gmail.com>: Re: Problems compiling with ISE Webpack 8.2.01i
105747: 06/07/31: maxascent: Core Generator
105757: 06/07/31: Jim Wu: Re: Core Generator
105749: 06/07/31: John Adair: Low Cost FPGA Charge Pump Power supply
105753: 06/07/31: Jan Panteltje: Re: Low Cost FPGA Charge Pump Power supply
105756: 06/07/31: John Adair: Re: Low Cost FPGA Charge Pump Power supply
105759: 06/07/31: jvdh: 100m JTAG cable
105763: 06/07/31: Tim: Re: 100m JTAG cable
105777: 06/07/31: Uwe Bonnes: Re: 100m JTAG cable
105822: 06/08/01: Uwe Bonnes: Re: 100m JTAG cable
105832: 06/08/01: Falk Brunner: Re: 100m JTAG cable
105841: 06/08/01: Uwe Bonnes: Re: 100m JTAG cable
105846: 06/08/02: Jim Granville: Re: 100m JTAG cable
105848: 06/08/01: Austin Lesea: Re: 100m JTAG cable
105856: 06/08/02: Jim Granville: Re: 100m JTAG cable
105863: 06/08/02: Uwe Bonnes: Re: 100m JTAG cable
106063: 06/08/07: Daniel O'Connor: Re: 100m JTAG cable
106077: 06/08/07: Uwe Bonnes: XC3SPROG, was: Re: 100m JTAG cable
105838: 06/08/02: Jim Granville: Re: 100m JTAG cable
105992: 06/08/04: Austin Lesea: Re: 100m JTAG cable
106032: 06/08/06: Simon Peacock: Re: 100m JTAG cable
106037: 06/08/06: Austin Lesea: Re: 100m JTAG cable
106047: 06/08/07: Simon Peacock: Re: 100m JTAG cable
105766: 06/07/31: jvdh: Re: 100m JTAG cable
105782: 06/08/01: Jim Granville: Re: 100m JTAG cable
105787: 06/07/31: Uwe Bonnes: Re: 100m JTAG cable
105802: 06/08/01: jvdh: Re: 100m JTAG cable
105816: 06/08/01: c d saunter: Re: 100m JTAG cable
105840: 06/08/01: jvdh: Re: 100m JTAG cable
105842: 06/08/01: jvdh: Re: 100m JTAG cable
105862: 06/08/02: Daniel O'Connor: Re: 100m JTAG cable
105962: 06/08/03: Antti: Re: 100m JTAG cable
105986: 06/08/04: <jetmarc@hotmail.com>: Re: 100m JTAG cable
105760: 06/07/31: misiu: Ethernet wrapper IP core with ML403
105765: 06/07/31: Vivek Menon: Information required on FPGAs and ARM evaluation boards
105783: 06/07/31: Ron: Re: Information required on FPGAs and ARM evaluation boards
105784: 06/07/31: Vivek Menon: Re: Information requested on FPGAs and ARM evaluation boards
105818: 06/08/01: rao: Re: Information requested on FPGAs and ARM evaluation boards
105767: 06/07/31: <heinerlitz@gmx.de>: MIG 1.6 DDR2 testing problems (FIFO16 related?)
105794: 06/08/01: Joseph Samson: Re: MIG 1.6 DDR2 testing problems (FIFO16 related?)
105811: 06/08/01: Joseph Samson: Re: MIG 1.6 DDR2 testing problems (FIFO16 related?)
105825: 06/08/01: Ray Andraka: Re: MIG 1.6 DDR2 testing problems (FIFO16 related?)
106029: 06/08/05: Joseph Samson: Re: MIG 1.6 DDR2 testing problems (FIFO16 related?)
106239: 06/08/09: Joseph Samson: Re: MIG 1.6 DDR2 testing problems (FIFO16 related?)
106289: 06/08/10: Joseph Samson: Re: MIG 1.6 DDR2 testing problems (FIFO16 related?)
105798: 06/08/01: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: MIG 1.6 DDR2 testing problems (FIFO16 related?)
105804: 06/08/01: <heinerlitz@gmx.de>: Re: MIG 1.6 DDR2 testing problems (FIFO16 related?)
105824: 06/08/01: <heinerlitz@gmx.de>: Re: MIG 1.6 DDR2 testing problems (FIFO16 related?)
106020: 06/08/05: =?iso-8859-1?B?R2FMYUt0SWtVc5k=?=: Re: MIG 1.6 DDR2 testing problems (FIFO16 related?)
106049: 06/08/07: <heinerlitz@gmx.de>: Re: MIG 1.6 DDR2 testing problems (FIFO16 related?)
106204: 06/08/09: <heinerlitz@gmx.de>: Re: MIG 1.6 DDR2 testing problems (FIFO16 related?)
106261: 06/08/09: <heinerlitz@gmx.de>: Re: MIG 1.6 DDR2 testing problems (FIFO16 related?)
105771: 06/07/31: <eric.amundsen@gmail.com>: DDR2 SRAM Stratix II questions
105774: 06/07/31: Mike Treseler: Re: DDR2 SRAM Stratix II questions
106056: 06/08/07: KJ: Re: DDR2 SRAM Stratix II questions
106095: 06/08/07: Thomas Entner: Re: DDR2 SRAM Stratix II questions
106108: 06/08/07: John: Re: DDR2 SRAM Stratix II questions
106109: 06/08/07: Thomas Entner: Re: DDR2 SRAM Stratix II questions
105776: 06/07/31: Tommy Thorn: Re: DDR2 SRAM Stratix II questions
105780: 06/07/31: Noway2: Re: DDR2 SRAM Stratix II questions
105788: 06/07/31: <eric.amundsen@gmail.com>: Re: DDR2 SRAM Stratix II questions
106059: 06/08/07: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: DDR2 SRAM Stratix II questions
106093: 06/08/07: KJ: Re: DDR2 SRAM Stratix II questions
106105: 06/08/07: KJ: Re: DDR2 SRAM Stratix II questions
106107: 06/08/07: KJ: Re: DDR2 SRAM Stratix II questions
105779: 06/07/31: Guru: S3E USB2.0 port
105799: 06/08/01: Antti: Re: S3E USB2.0 port
105800: 06/08/01: bijoy: Re: S3E USB2.0 port
105801: 06/08/01: Antti: Re: S3E USB2.0 port
105805: 06/08/01: Guru: Re: S3E USB2.0 port
105821: 06/08/01: Antti: Re: S3E USB2.0 port
105933: 06/08/03: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: S3E USB2.0 port
105936: 06/08/03: Antti: Re: S3E USB2.0 port
105789: 06/07/31: bart: Lattice Blogs
105790: 06/07/31: Uwe Bonnes: Re: Lattice Blogs
106346: 06/08/12: Ben Popoola: Re: Lattice Blogs
105791: 06/07/31: bart: Re: Lattice Blogs
106514: 06/08/14: bart: Re: Lattice Blogs
105792: 06/07/31: Brad Smallridge: Quick way to change Xilinx BRAM init values
105808: 06/08/01: <jbnote@gmail.com>: Re: Quick way to change Xilinx BRAM init values
105809: 06/08/01: backhus: Re: Quick way to change Xilinx BRAM init values
105815: 06/08/01: Vivian Bessler: Re: Quick way to change Xilinx BRAM init values
105819: 06/08/01: <jbnote@gmail.com>: Re: Quick way to change Xilinx BRAM init values
105795: 06/07/31: Venkat: Usage of DDR IOBs
105806: 06/08/01: <heinerlitz@gmx.de>: Re: Usage of DDR IOBs
105817: 06/08/01: Venkat: Re: Usage of DDR IOBs
105820: 06/08/01: Jim Wu: Re: Usage of DDR IOBs
105828: 06/08/01: johnp: Re: Usage of DDR IOBs
105797: 06/07/31: bijoy: FPGA : BUG in ISE- View RTL Schematics ?
105812: 06/08/01: krishna.janumanchi@gmail.com: Re: FPGA : BUG in ISE- View RTL Schematics ?
105814: 06/08/01: backhus: Re: FPGA : BUG in ISE- View RTL Schematics ?
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