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Frank Buss wrote: > For implementing the higher level protocols for my Spartan 3E starter kit > TCP/IP stack implementation, I plan to use a CPU, because I think this > needs less gates than in pure VHDL. The instruction set could be limited, > because more instructions and less gates is good, and it doesn't need to be > fast, so I can design a very orthogonal CPU, which maybe needs even less > gates. The first draft: > > http://www.frank-buss.de/vhdl/cpu.html > > It is some kind of a 68000 clone, but much easier. What do you think of it? > Any ideas to reduce the instruction set even more, without the drawback to > need more instructions for a given task? > > -- > Frank Buss, fb@frank-buss.de > http://www.frank-buss.de, http://www.it4-systems.de There are a number of RISC cores at opencores.org. The full featured (complete with GNU toolchain) is OpenRisc1000, but that may be way more than you need. Do you want a processor you can simply instantiate, or are you willing to tweak so you get the features you want? If so, you could take one of the less ambitious cores and adjust the instruction set to optimise it for your application. Cheers PeteSArticle: 106826
Andy Glew wrote: > Care to estimate the size of the market? > > I.e. how much would the author expect to make, given typical publishing contracts? Speaking as someone who's written three speciality-ish engineering books (go to www.larwe.com and look down the left-hand column for links to the books), the point of writing a volume like this is one of two things: 1. Get it picked up as a textbook or training book in college or by one of the major semi manufacturers. 2. Treat it as advertising. Route 1 can lead to respectable direct profits. Route 2 leads to indirect profits through consultancy and so forth. Do not expect to make your fortune through route 1; the real money is in route 2 but requires more work to realize. Your book is the dynamite that exposes a seam of gold. Significant pick-work is necessary to extract the gold and bring it to town for conversion into cash.Article: 106827
FlyingPenguin schrieb: > The real problem, is with the Area optimisation, that, according to > xst's Synthesis Report, often produces a circuit with more flipflops, > used slices, and bonded IOBs than Speed optimisation. The only > unchanged or lower values are the number of BELs and LUTs used. The number of used slices is irrelevant. The circuit is mostly implemented by LUTs. Two LUTs can be placed in the same slice (1 slice used) or in two different slices (2 slices used) for the same circuit. As your FPGA gets more and more crowded more and more slices will have two used LUTs. In an extreme case, you can have a circuit that uses 98% of slices but only 49% of LUTs. Two of these circuits will fit in the same FPGA. ----- DFF usage is irrelevant as long as there are less DFFs than LUTs. ----- Bottom line: Count LUTS. Kolja SulimmaArticle: 106828
zwsdotcom@gmail.com wrote: > Mark McDougall wrote: > > > category. I've done a few years work with Altera and have recently > > cracked open ISE to play with a Spartan-3. I'm finding it an unpleasant > > experience but I'm sure that I went through similar over the years when > > getting my head around Quartus too?!? So I admit I'm biased atm... > > I'm going through the same thing, except that I _clearly_ remember how > difficult I found it to use Altera's stuff. I think all this software > is used by such a tiny number of people that you're just expected to > get the ritual tattoos and piercings in order to join the cult that > understands it. Since the developer community for each product is so > small, usability is no priority at all. > > I wrestled with ISE for more than an hour just trying to put down > something other than an ACC_16. At that time, I discovered that if you > open ISE at 1024x768 resolution, the controls autosize themselves in > such a way that the drop-down list to select a different part is > invisible. > > I've yet to be convinced that the software is even functional... There are things to dislike in each vendor's tools. The download size for the Xilinx webpack (full install - see below) is close on 1GByte - that's not a typo. Although Quartus is smaller, the memory footprint to do anything is horrendous. The reason for a full download is that the web install fails regularly with a message that the Xilinx server can not be found and perhaps I should check my internet connection - the problem is with the Xilinx servers, not my connection (I checked and it happens multiple times). That said, there are other things - Altera insists on knowing your ethernet card MAC address (old habits die hard) even for the freely downloadable version, and they install a daemon (service in W2K) that does not need to be there. (jtagserver is the name of said service). All in all, the tools are roughly the same - Altera can have ease of use (once you get used to them), but far fewer freebies (at least as far as I can find) and horrendous performance (even on this system with 2GByte physical DDR); Xilinx tools have a less than natural flow, but I do like the fact that Xilinx ships FPGA Express. I have had designs where the native tools could not fit a design where FPGA Express could - it at least gives me another option. So from my point of view, there's not much between the vendors when you take everything into account. Cheers PeteSArticle: 106829
Frank Buss wrote: > Peter Alfke wrote: > > >>Why not use PicoBlaze, which is freely available ? >>Or MicroBlaze if you need more speed? > > > PicoBlaze looks a bit like my idea: > > http://www.xilinx.com/bvdocs/ipcenter/data_sheet/picoblaze_productbrief.pdf > > But it has more instructions and it is not as much orthogonal as my CPU, so > I think I can synthesize my CPU with less gates. But using memory instead > of registers means that it is slower than PicoBlaze, but this is no problem > for me. But maybe the main reason is, that it is fun to design CPUs :-) Also look at the Lattice Mico8, and PacoBlaze. The CPU is the easy part, finding a compiler and debug software will be harder. You also need to match the memory interface to the core, once you go out of block ram, these CPUs get less elegent. One idea that appeals to me, is to optimise a FPGA_CPU to operate from the Fast serial flash that are very cheap and small, with negligable pin cost. That probably means 16 bit opcodes ( down from the 18 allowed by Block Ram), and 32 bit registers, with plenty of size-extended opcodes, and skip opcodes. Next would be a way to load and lock a BRAM or 2 with interrupt and speed critical codes. -jgArticle: 106830
Antti wrote: > 1) PicoBlaze is too small For me it looks like it is too large :-) > the OP is really going to try to make a full SoC with DDR memory > controller and ethernet! as much as I have understood his reasons. Yes, and mainly for learning VHDL, so using finished products doesn't help me and is not as much fun as doing it all by myself. > well doing some 16 bit doesnt make much sense, a small 32 bit RISC isnt > much larger. The first use case for this CPU will be executing programs from block RAM, for accessing all the hardware of the Spartan 3E starter kit. For this 32 bit is not needed, but I'll use generics for the bit width, because when using more memory than 64 kB or for more complicated tasks, 32 bit may be more useful. > you could also use OpenFire Do you have a link? Searching for OpenFire at Google returns only ads for fireplaces :-) > BTW - 16 bit, I was looking at ColdFire, and well there is no coldfire > FPGA clone yet, but that may make sense (kind 68000, but more RISClike, > 16 bit instruction bus) ColdFire looks interesting, but even more complicated than PicoBlaze, with all the old 68000 commands, like traps. Looks like all these CPUs are using registers. I know it is faster to do calculations with registers instead in memory and opcodes may be a bit smaller, when using registers as source or destination, but are there any other drawbacks using no registers? I really like my idea using only memory. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 106831
PeteS wrote: > zwsdotcom@gmail.com wrote: > > Mark McDougall wrote: > > > > > category. I've done a few years work with Altera and have recently > > > cracked open ISE to play with a Spartan-3. I'm finding it an unpleasant > > > experience but I'm sure that I went through similar over the years when > > > getting my head around Quartus too?!? So I admit I'm biased atm... > > > > I'm going through the same thing, except that I _clearly_ remember how > > difficult I found it to use Altera's stuff. I think all this software > > is used by such a tiny number of people that you're just expected to > > get the ritual tattoos and piercings in order to join the cult that > > understands it. Since the developer community for each product is so > > small, usability is no priority at all. > > > > I wrestled with ISE for more than an hour just trying to put down > > something other than an ACC_16. At that time, I discovered that if you > > open ISE at 1024x768 resolution, the controls autosize themselves in > > such a way that the drop-down list to select a different part is > > invisible. > > > > I've yet to be convinced that the software is even functional... > > There are things to dislike in each vendor's tools. The download size > for the Xilinx webpack (full install - see below) is close on 1GByte - > that's not a typo. Although Quartus is smaller, the memory footprint to > do anything is horrendous. > > The reason for a full download is that the web install fails regularly > with a message that the Xilinx server can not be found and perhaps I > should check my internet connection - the problem is with the Xilinx > servers, not my connection (I checked and it happens multiple times). > > That said, there are other things - Altera insists on knowing your > ethernet card MAC address (old habits die hard) even for the freely > downloadable version, and they install a daemon (service in W2K) that > does not need to be there. (jtagserver is the name of said service). > > All in all, the tools are roughly the same - Altera can have ease of > use (once you get used to them), but far fewer freebies (at least as > far as I can find) and horrendous performance (even on this system with > 2GByte physical DDR); Xilinx tools have a less than natural flow, but I > do like the fact that Xilinx ships FPGA Express. > > I have had designs where the native tools could not fit a design where > FPGA Express could - it at least gives me another option. > > So from my point of view, there's not much between the vendors when you > take everything into account. > > Cheers > > PeteS One more thing - the update from ISE 7.1 to 8.1 completely changed a lot of things, making me try to figure out where everything had gone. A 'legacy' mode would have been nice for when I was dealing with a fairly large design from an older unit so I didn't waste hours on end just trying to figure out where all the menu items went (this goes for the accessories too). If you are starting, then you merely have to learn the existing tool, but it is less useable (imo) than the previous versions. Cheers PeteSArticle: 106832
Frank Buss <fb@frank-buss.de> wrote: >For implementing the higher level protocols for my Spartan 3E starter kit >TCP/IP stack implementation, I plan to use a CPU, because I think this >needs less gates than in pure VHDL. The instruction set could be limited, >because more instructions and less gates is good, and it doesn't need to be >fast, so I can design a very orthogonal CPU, which maybe needs even less >gates. The first draft: > >http://www.frank-buss.de/vhdl/cpu.html > >It is some kind of a 68000 clone, but much easier. What do you think of it? >Any ideas to reduce the instruction set even more, without the drawback to >need more instructions for a given task? A few years ago I made a programmable DMA controller on a system that had no interrupt capability (too many sources) so all I/O needed to be polled and packed into larger chunks of data. It has a few instructions like read, mask and, mask or, jump conditionally, write to the host. It is smart enough to be able to deal with an E1 chip. As I write this, this controller is at work in thousands of cards... -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 106833
PeteS wrote: > Frank Buss wrote: > > For implementing the higher level protocols for my Spartan 3E starter kit > > TCP/IP stack implementation, I plan to use a CPU, because I think this > > needs less gates than in pure VHDL. The instruction set could be limited, > > because more instructions and less gates is good, and it doesn't need to be > > fast, so I can design a very orthogonal CPU, which maybe needs even less > > gates. The first draft: > > > > http://www.frank-buss.de/vhdl/cpu.html > > > > It is some kind of a 68000 clone, but much easier. What do you think of it? > > Any ideas to reduce the instruction set even more, without the drawback to > > need more instructions for a given task? > > > > -- > > Frank Buss, fb@frank-buss.de > > http://www.frank-buss.de, http://www.it4-systems.de > http://indi.joox.net for ISAArticle: 106834
jacko schrieb: > PeteS wrote: > > Frank Buss wrote: > > > For implementing the higher level protocols for my Spartan 3E starter kit > > > TCP/IP stack implementation, I plan to use a CPU, because I think this > > > needs less gates than in pure VHDL. The instruction set could be limited, > > > because more instructions and less gates is good, and it doesn't need to be > > > fast, so I can design a very orthogonal CPU, which maybe needs even less > > > gates. The first draft: > > > > > > http://www.frank-buss.de/vhdl/cpu.html > > > > > > It is some kind of a 68000 clone, but much easier. What do you think of it? > > > Any ideas to reduce the instruction set even more, without the drawback to > > > need more instructions for a given task? > > > > > > -- > > > Frank Buss, fb@frank-buss.de > > > http://www.frank-buss.de, http://www.it4-systems.de > > > http://indi.joox.net for ISA ALL project folder are EMPTY !! :( AnttiArticle: 106835
Frank Buss wrote: <snip> >>BTW - 16 bit, I was looking at ColdFire, and well there is no coldfire >>FPGA clone yet, but that may make sense (kind 68000, but more RISClike, >>16 bit instruction bus) > > > ColdFire looks interesting, but even more complicated than PicoBlaze, with > all the old 68000 commands, like traps. > > Looks like all these CPUs are using registers. I know it is faster to do > calculations with registers instead in memory and opcodes may be a bit > smaller, when using registers as source or destination, but are there any > other drawbacks using no registers? I really like my idea using only > memory. Look at a uC like the Zilog Z8 - that has registers, but also a register frame pointer. So you use 4 opcode bits, but can shift that window, a across all memory. The Intel 196 used a 256 byte register file Registers are used to keep the opcodes smaller, but you are right that it is a simple trade off. PICs use only RAM and accumulator. A drawback of registers is that the step-up from reg to memory can give quite a code hit, and with FPGA BRAM, there is no speed penalty in a memory block much larger than most uC register fields. Some processors allowed a split register frame, so you could (eg) half-shift the register map, giving 8 scratch registers, and 8 register parameters, in a procedure call. To me a very good idea, but seems to not be widely used - would map very well onto FPGA BRAM. -jgArticle: 106836
Hi, I am new to XILINX ISE webpack software. The map file of its "freqm" VHDL example has two warnings (see below) N77 and N78 signals. I have the following questions: 1. This kind of warning is normal? Where to suppress it? 2. In which file, I can see N77 and N78 net? Or, block "XST_VCC" and "XST_GND"? I have generated the map file in its detail form, basically it is the same the warning. Thank you very much. Section 2 - Warnings -------------------- WARNING:LIT:243 - Logical network N77 has no load. WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 1 more times for the following (max. 5 shown): N78 To see the details of these warning messages, please use the -detail switch. Section 3 - Informational ------------------------- INFO:MapLib:562 - No environment variables are currently set. INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0: BUFGP symbol "F_INPUT_BUFGP" (output signal=F_INPUT_BUFGP), BUFGP symbol "F_PATTERN_BUFGP" (output signal=F_PATTERN_BUFGP) INFO:LIT:244 - All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs in the schematic. Section 4 - Removed Logic Summary --------------------------------- 2 block(s) removed 2 signal(s) removed Section 5 - Removed Logic ------------------------- The trimmed logic report below shows the logic removed from your design due to sourceless or loadless signals, and VCC or ground connections. If the removal of a signal or symbol results in the subsequent removal of an additional signal or symbol, the message explaining that second removal will be indented. This indentation will be repeated as a chain of related logic is removed. To quickly locate the original cause for the removal of a chain of logic, look above the place where that logic is listed in the trimming report, then locate the lines that are least indented (begin at the leftmost edge). The signal "N77" is loadless and has been removed. Loadless block "XST_VCC" (ONE) removed. The signal "N78" is loadless and has been removed. Loadless block "XST_GND" (ZERO) removed.Article: 106837
Another problem. When I try to run FPGA editor and Floorpanner, there is a warning from the firewall of my computer. It says it will block some functions of the two software. Is it normal? I can ignore the warning? I havn't seen any explaination on Xilinx website.Article: 106838
In article <1156100604.972937.26240@m73g2000cwd.googlegroups.com>, Antti <Antti.Lukats@xilant.com> wrote: > the OP is really going to try to make a full SoC with DDR memory > controller and ethernet! as much as I have understood his reasons. > > sure it would be WAY CHEAPER to just use MicroBlaze !!! cheaper means > in terms of money. The time and effort to make anything comparable to > what you can achive with EDK and a few mouseclicks, defenetly costs > more than 495USD unless your personal time doesnt count at all. Ethernet is not included in the MicroBlaze price, but is $1500 extra. (Still a lot cheaper than doing it yourself if you place any reasonable value on your time, and if you don't want to learn from it.) OpenCores has several CPUs that include full gcc support. I am pushing around pieces of Opencores to try to get a CPU + Ethernet + DDR + Application-specific system together on Wishbone. I am being stymied by just learning VHDL and knowing no Verilog at all, and not being able to understand the various error messages the ISE spits out. It would be nice if there were an assembled system that I could take apart and modify. (I found a more restricted system under OpenCores as rs232_syscon that includes a PIC microcontroller and a serial-port-device that lets you prod at the Wishbone bus, which might help.) -- David M. Palmer dmpalmer@email.com (formerly @clark.net, @ematic.com)Article: 106839
Antti wrote: > jacko schrieb: > > > http://indi.joox.net for ISA > > ALL project folder are EMPTY !! :( > > Antti i'm only one person, and so i am doing the documentation first cheers. feel free to contribute.Article: 106840
Jim Granville wrote: > A drawback of registers is that the step-up from reg to memory can give > quite a code hit, and with FPGA BRAM, there is no speed penalty in a > memory block much larger than most uC register fields. I wonder if there is some more scientific study about this. When I'm trying to write a typical piece of code, it looks like registers are really better: ; swap 6 byte source and destination MACs .base = 0x1000 p1: .dw 0 p2: .dw 0 tmp: .db 0 move #5, p1 move #11, p2 loop: move.b (p1), tmp move.b (p2), (p1) move.b tmp, (p2) sub.b p2, #1 sub.b p1, #1 bcc.b loop 40 bytes with my instruction set. The same with something like a 68000 instruction set: move #5, a0 loop: move.b $0(a0), d0 xchg.b $6(a0), d0 move.b d0, $0(a0)- ; register indirect with displacement and post-dec bcc.b loop 12 bytes, if I need 2 bytes per instruction for the larger range of addressing modes with registers. How much logic gates do I need for supporting registers? Maybe not too much, if I can design it without too much special cases. I don't need it, but for a really fast CPU something like MIPS should work: http://www.mrc.uidaho.edu/mrc/people/jff/digital/MIPSir.html Every instruction, including arguments, is 32 bit. When reading it from 32 bit block RAM, this should be really fast. How much memory needs a program? xor $1, $1, $1 addi $1, $0, #6 loop: lb $3, ($1) sb $3, ($2) addi $1, $1, #1 addi $2, $2, #1 xori $1, $4, #6 bne loop 32 bytes (but maybe shorter, I don't know MIPS assembler very good). And something like the good old 6502: ldx# 6 loop: lda 0, x tay lda 6, x sta 0, x tya sta 6, x decx bcc loop 13 bytes. Maybe a CPU like MIPS, with fixed 32 bit instructions, but as easy to write assembler for it like for the 68000 would be a good idea? Forth looks interesting, too: http://www.ultratechnology.com/f21cpu.html -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 106841
Frank Buss wrote: > Peter Alfke wrote: > > >> Why not use PicoBlaze, which is freely available ? >> Or MicroBlaze if you need more speed? > > > > PicoBlaze looks a bit like my idea: > > http://www.xilinx.com/bvdocs/ipcenter/data_sheet/picoblaze_productbrief.pdf > > But it has more instructions and it is not as much orthogonal as my CPU, so > I think I can synthesize my CPU with less gates. But using memory instead > of registers means that it is slower than PicoBlaze, but this is no problem > for me. But maybe the main reason is, that it is fun to design CPUs Also look at the Lattice Mico8, and PacoBlaze. The CPU is the easy part, finding a compiler and debug software will be harder. You also need to match the memory interface to the core, once you go out of block ram, these CPUs get less elegent. One idea that appeals to me, is to optimise a FPGA_CPU to operate from the Fast serial flash that are very cheap and small, with negligable pin cost. That probably means 16 bit opcodes ( down from the 18 allowed by Block Ram), and 32 bit registers, with plenty of size-extended opcodes, and skip opcodes. Next would be a way to load and lock a BRAM or 2 with interrupt and speed critical codes. -jgArticle: 106842
On 20 Aug 2006 12:33:20 -0700, "Raymond" <raybakk@yahoo.no> wrote: > if(reset <= '1') then did you mean reset = '1' here ?? GerhardArticle: 106843
> > XPS% Evaluating file > c:/xilprj/myproject/project_navigator/__projnav/system.synth.tcl > system.make:171: *** target pattern contains no `%'. Stop > ERROR:MDT - Error while running "make -f system.make netlist" > No changes to be saved in MSS file > No changes to be saved in XMP file > > It's hard to imagine a more vanilla installation than the one I'm > using, it's a WinXP install with everything defaulted. However I have a > spare unused laptop in its box here, with NOTHING but WinXP on it - so > I'm going to while away the hours installing the Xilinx software on > that machine. > > By the way, line 171 of system.make is the @mkdir line in the following > stanza: > > ################################################################# > # BOOTLOOP ELF FILES > ################################################################# > > $(PPC405_0_BOOTLOOP): $(PPC405_BOOTLOOP) > @mkdir -p $(BOOTLOOP_DIR) > cp -f $(PPC405_BOOTLOOP) $(PPC405_0_BOOTLOOP) Which version of cygwin and make are you using? If I recall correctly, the newest version of cygwin make does not allow windows style paths unless they are in quotes, and EDK has not yet fixed that. /SivaArticle: 106844
Gerhard Hoffmann wrote: > On 20 Aug 2006 12:33:20 -0700, "Raymond" <raybakk@yahoo.no> wrote: > > > > if(reset <= '1') then > > did you mean reset = '1' here ?? > > Gerhard Gerhard, Thank you Thank you Thank you :) :) :) I have been completly blind!!! RaymondArticle: 106845
Frank Buss wrote: > For implementing the higher level protocols for my Spartan 3E starter kit > TCP/IP stack implementation, I plan to use a CPU, because I think this > needs less gates than in pure VHDL. The instruction set could be limited, > because more instructions and less gates is good, and it doesn't need to be > fast, so I can design a very orthogonal CPU, which maybe needs even less > gates. The first draft: > > http://www.frank-buss.de/vhdl/cpu.html > > It is some kind of a 68000 clone, but much easier. What do you think of it? > Any ideas to reduce the instruction set even more, without the drawback to > need more instructions for a given task? > Before you comparing ISA for size, you need to look into the actual FPGA area needed for different ISA. A full 68000 would most likely fill up most of your Spartan3E device and that is without the ethernet MAC. Also the Ethernet MAC is usually much larger size than the CPU. On the opencores IP, just add the size of the CPU and Ethernet MAC before you do any decision. Unless you want to spend hours and hours hand-assemble the TCP/IP stack code, you need to find a CPU which has a full C compiler. If your ethernet speed doesn't need to be at maximum speed, I would pick the ethernet lite from Xilinx since the size is much smaller than most available cores. If you need maximum ethernet performance then you need the full ethernet MAC which is much larger than the lite version. You will need a TCP/IP stack and lwip is most likely the best choice. For the CPU, a MicroBlaze will most likely be the smallest choice for you. The decision also depends on how you value your time and how money you want to spend on this. If the interesting part is to create this solution without any time limits than you should create most from scratch. If the interesting part is to use the solution than I would spend money to speed up the development. Göran BilskiArticle: 106846
I just didn't knew that I have to use the bootloop load the program via xmd from memory. Thougt that would work via Download Bitstream .... Thanks for your help. Regards, Peter Kampmann Alan Nishioka schrieb: > peter.kampmann@googlemail.com wrote: > > I also want to run my program out of the memory of the sdram of my > > Xilinx Virtex 2 Pro, unfortunately I get outputs from stdout/stdin only > > in the debug mode. > > But I can live with that, the more serious problem is, that the code > > seems not to work as it should, when running it from sdram. > > Is the code running at all or do you just see no packets so the ppc > could be dead? > > > > I use the Ethernet-MAC on the Board together with LWIP and I get no > > packets send, when running the board in the normal way. When I switch > > into debug mode, I get the right behaviour and I receive packets send > > by the board. > > sdram cannot be loaded from the config prom. You have to write your > own loader. > How are you loading the sdram with code in non-debug mode? > > By debug, do you mean XMD? > XMD *does* load code into sdram. > > Alan NishiokaArticle: 106847
Jim Granville wrote: > Austin Lesea wrote: > > > ... > > http://direct.xilinx.com/bvdocs/publications/ds123.pdf > > claims 20,00 program/erase cycles. > > ... >... > If those are what's on the PCB under discussion, thanks. > That sounds like a few design iterations ! :) >... Jim, I think Austin lost a "zero" the ds123 claims: "Endurance of 20,000 Program/Erase Cycles" (20 thousands) bye SandroArticle: 106848
Hi, I use Modelsim SE 6.0 simulator for my projects. My Project is very big and it takes nearly 15 min for compilation. As the license is network one, after compilation, it says simulation license error - if license is not available. Is there a command available in modelsim to check license on network? Next, In my project only 3 to 4 files are changed frequently. Rest other files are not disturbed at all. But still I am recompiling all files. Are there any commands available so that I can skip compiling files which are not changed at all? Please help.. Regards, JKArticle: 106849
"larwe" <zwsdotcom@gmail.com> wrote in message news:1156102639.513866.80000@i3g2000cwc.googlegroups.com... > > Andy Glew wrote: > >> Care to estimate the size of the market? >> >> I.e. how much would the author expect to make, given typical >> publishing contracts? > > Speaking as someone who's written three speciality-ish engineering > books (go to www.larwe.com and look down the left-hand column for > links > to the books), the point of writing a volume like this is one of two > things: > > 1. Get it picked up as a textbook or training book in college or by > one > of the major semi manufacturers. > > 2. Treat it as advertising. > > Route 1 can lead to respectable direct profits. Route 2 leads to > indirect profits through consultancy and so forth. Do not expect to > make your fortune through route 1; the real money is in route 2 but > requires more work to realize. > > Your book is the dynamite that exposes a seam of gold. Significant > pick-work is necessary to extract the gold and bring it to town for > conversion into cash. > Must it always be about the money? Won't somebody think of the children ;-)
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