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Hi can someone suggest what version of ISE would be best candidate not to fail on XC95xxXL fitting? ISE 8.2SP3 fails badly - I was hoping not have to install older versions and check with WebFitter, but: "WebFITTER has been replaced by ISE WebPACK" !!!! and latest ISE fails badly with XC95xxXL as target, the same VHDL design reports different number of pins being used if XC95xxXL is selected, eg FPGA targets, Coolrunner/II - all report no issues with the desgin, but as soon as it run with XC95xxXL selected then different number of input pins are reported as not there. There is no clue why they are disappearing and what else may be wrong. Stepping back ISE history and installing 7.x then 6.x ...etc and retesting in the hope that maybe some older version works is really painful :( AnttiArticle: 110276
Hi all, I looking for a Spartan-3/3E based board with the following features (other features are also welcome): - 8-way 10-16bits ADC. 8 way 10-16bits DAC. - Rich interconnect (RS232, CAN, USB, ETH, ...) - Rich memory (DDR SDRAM+FLASH) The SP305 is almost perfect but it's no longer sold by Xilinx :( CheersArticle: 110277
On 13 Oct 2006 00:56:00 -0700, "Antti" <Antti.Lukats@xilant.com> wrote: >Hi > >can someone suggest what version of ISE would be best candidate not to >fail on XC95xxXL fitting? > >ISE 8.2SP3 fails badly - I was hoping not have to install older >versions and check with WebFitter, but: "WebFITTER has been replaced by >ISE WebPACK" !!!! > >and latest ISE fails badly with XC95xxXL as target, the same VHDL >design reports different number of pins being used if XC95xxXL is >selected, eg FPGA targets, Coolrunner/II - all report no issues with >the desgin, but as soon as it run with XC95xxXL selected then different >number of input pins are reported as not there. There is no clue why >they are disappearing and what else may be wrong. > >Stepping back ISE history and installing 7.x then 6.x ...etc and >retesting in the hope that maybe >some older version works is really painful :( > >Antti I am using ise 8.1sp3 on an xc9572xl-10VQ64. But I do rememeber I had to play a little with settings until the project imported from 7.1 worked ok. I am not sure, but may be it was Optimization Effort (turned to High) the point I changed. I suppose that it should work also with 8.2, but if you keep on having problems, I may take a deepest look at the project under 7.1 and compare it to the project under 8.1, to see the real changes I made. I am installing 8.2 in a couple of weeks, I will the see if there arise new problems. Best regards, ZaraArticle: 110278
Could you please give me a reference for those? thanks a lot Al > This isn't different from the "normal" async reset, however, where the > reset signal isn'f filtered. The solution usually used is an external > reset circuit (they come packed in nice tiny ICs these days) that > provides a clean reset signal of 200 ms (or whatever you set it to) > whenever there's a problem with the supplies, and as a byproduct, when > the power is going up. > > Eli >Article: 110279
Antti wrote: > Hi > > can someone suggest what version of ISE would be best candidate not to > fail on XC95xxXL fitting? > > ISE 8.2SP3 fails badly - I was hoping not have to install older > versions and check with WebFitter, but: "WebFITTER has been replaced by > ISE WebPACK" !!!! > > and latest ISE fails badly with XC95xxXL as target, the same VHDL > design reports different number of pins being used if XC95xxXL is > selected, eg FPGA targets, Coolrunner/II - all report no issues with > the desgin, but as soon as it run with XC95xxXL selected then different > number of input pins are reported as not there. There is no clue why > they are disappearing and what else may be wrong. > > Stepping back ISE history and installing 7.x then 6.x ...etc and > retesting in the hope that maybe > some older version works is really painful :( > > Antti Is this a design that did fit, and work, once on an (older) webpack, or is this a new design, that you hope will get better on an older system ? Did you try the non-XL versions, (or have they now gone off the choices ? ) -jgArticle: 110280
icegray@gmail.com wrote: > > You can try: > > http://www.tkk.fi/Misc/Electronics/faq/vga2rgb/calc.html > > This calculator is very good. Thanks for it. > Also do you have any idea for polarization??? icegray, ...search and read, search and read.... ;-) btw: http://www.tkk.fi/Misc/Electronics/faq/vga2rgb/basics.html bye SandroArticle: 110281
Hello, Don't know if this is the right place to report this, but... While reading some xilinx docs I came across the following typos: * ug071 v1.4, table 7-5 page 91, the column address spans bits 13:6 * ug191 v1.2, table 6-7 page 103, the block type 001 / 010 should correspond to block RAM routing and block RAM content, not block RAM contents twice. This is just a guess, I've not checked this. * ug191 v1.2, table 6-4 page 98, the CBC register address is wrong. This is a small problem, but as all register addresses are not consecutive, this may be misleading. These docs were the latest version I could find. Jean-BaptisteArticle: 110282
Hey, I have 2 LVDS clock signals and both are terminated with the DIFF_TERM attribute on the LVDS25 input buffer IBUFGDS but i only use 1 of them ... now i want both buffers to stay in my design and not optimized away. Is there a constraint that i can place on that buffer? i guess that it should be a UCF constraint since when i look into the RTL viewer of planahead and ISE i still see the buffer. I know that there is an option in NGBuild -u which keeps the unused logic, but i do not want to use it just for that 1 buffer ... thanks in advance, kind regards, tim p.s. i'm using ISE8.2SP2 and a V4SX55-FF1148CArticle: 110283
avionion@gmail.com schrieb: > As mentioned by Antti, its not issue of uncompressing tar.gz or zip > files, i am unable to get anything downloaded. just read the mesage > that i get whenever i click on any link. i even wrote to webmaster, but > its about a month ,and with 2 reminds, still no response from > webmaster. > Jon Beniston wrote: > > avionion@gmail.com wrote: > > > Hi Antti > > > i am unable to get any download from lattice website and get the > > > following message: > > > "The file you have attempted to retrieve is not available at this time. > > > > > > We apologize for the inconvenience. > > > > > > If you continue to experience this difficulty, please contact the > > > Webmaster" > > > i have an account with lattice website as well. i am unable to download > > > any zip or exe file but pdf files open correctly. anyone else facing > > > this problem? any solution to it? > > > > The file you download is a tar.bz2, not zip or exe. You need to extract > > it with: > > > > tar xjf src.tar.bz2 > > > > Cheers, > > Jon try here, http://www.microfpga.com/files/Mico32DevTool_Installer_6_0_1_15.exe 200MB, full set of the LM32 distro (except datasheets and GCC sources) AnttiArticle: 110284
Jim Granville schrieb: > Antti wrote: > > Hi > > > > can someone suggest what version of ISE would be best candidate not to > > fail on XC95xxXL fitting? > > > > ISE 8.2SP3 fails badly - I was hoping not have to install older > > versions and check with WebFitter, but: "WebFITTER has been replaced by > > ISE WebPACK" !!!! > > > > and latest ISE fails badly with XC95xxXL as target, the same VHDL > > design reports different number of pins being used if XC95xxXL is > > selected, eg FPGA targets, Coolrunner/II - all report no issues with > > the desgin, but as soon as it run with XC95xxXL selected then different > > number of input pins are reported as not there. There is no clue why > > they are disappearing and what else may be wrong. > > > > Stepping back ISE history and installing 7.x then 6.x ...etc and > > retesting in the hope that maybe > > some older version works is really painful :( > > > > Antti > > Is this a design that did fit, and work, once on an (older) webpack, or > is this a new design, that you hope will get better on an older system ? > Did you try the non-XL versions, (or have they now gone off the choices ? ) > > -jg Jim, its a new design. it seems to work as of reports for any other familes except XC95xx (XL nonXL both fail). I am hoping to find some older version that has functional XC95 fitter. For what I see the 8.2SP3 just isnt doing much useful for XC95 family and as that is the oldest device still supported I guess there is not much hope the problems being ever fixed. Hopefully I dont have to write my own fitter (I am capable of that). Zara - changin some options changed the count of pins that go lost 3 => 8, (and yes only for XC95!) but its still not doing proper fit as much as I understand. AnttiArticle: 110285
Tim Verstraete schrieb: > Hey, > > I have 2 LVDS clock signals and both are terminated with the DIFF_TERM > attribute on the LVDS25 input buffer IBUFGDS but i only use 1 of them > ... now i want both buffers to stay in my design and not optimized > away. Is there a constraint that i can place on that buffer? i guess > that it should be a UCF constraint since when i look into the RTL > viewer of planahead and ISE i still see the buffer. > > I know that there is an option in NGBuild -u which keeps the unused > logic, but i do not want to use it just for that 1 buffer ... > > thanks in advance, > > kind regards, > > tim > > p.s. i'm using ISE8.2SP2 and a V4SX55-FF1148C the best thing possible is to use it without using it :) 1) like route the unused input to non-bonded IO, 2) or use in some net in way that the signal isnt really used but XST fails to optimize it out 3) or if you dont use BSCAN you can also route it to TDO pin all those tricks would keep the net alive. sure it would use some interconnect resources. AnttiArticle: 110286
"Isaac Bosompem" <x86asm@gmail.com> wrote in message news:1160712667.864828.182490@b28g2000cwb.googlegroups.com... > Hi Peter, > > Yes that is important information. I apologize for not including it. > > I am currently in my 3rd year of Electrical Engineering undergrad at > Ryerson University in Toronto, Ontario, Canada. The internship (if > acquired) is slated to start right after this academic year. > This effectively delays my graduation by 1 yr, but I think that is a > really small price to pay for the experience. I would definitely recommend the year out - the difference between graduates that had industrial experience and those who don't is huge and employers really take notice of that. I would look at Dy4 Systems who I think are now part of a different group (simple google to find I'm sure) who I believe are based around Toronto or maybe somewhere else but Canada is a pretty small place ;-) They are into single board computers for aerospace and make some interesting things and work with some good technology on interesting projects. Your skills would fit pretty well into their picture but I have no idea about whether they do internships. <snip resumé>Article: 110287
hello Subroto Datta i triesd your suggestion and its work nicely i want to thank you very much you help me a lot and save a lot of time. i have one more quastion that you maybe can help me: i generating hex file from matlab, can i transfer data directly from matlab to Quartus Tcl? now i do this by generating files and reading them from quartus Tcl thank you david Subroto Datta wrote: > quartus_stp.exe is an executable file, not a TCL package. This > executable provides a TCL shell environment that loads a number of TCL > packages. When you click on the insystem_memory_edit package in the > TCL API Help window which is started up by quartus_sh --qhelp, you > will read this information: "This package is loaded by default in the > following executable: quartus_stp". That means that you can run TCL > commands in this package using quartus_stp.exe. > > "update_content_to_memory_from_file" command in the > insystem_memory_edit package is likely what you want. Saving the > example usage in that command's help topic into a file, example.tcl. > For example, > > # Initiate a editing sequence > begin_memory_edit -hardware_name "USB-Blaster \[USB-0\]" -device_name > "@1: EP1S25/_HARDCOPY_FPGA_PROTOTYPE (0x020030DD)" > > # Write memory content using the hex memory file > update_content_to_memory_from_file -instance_index 0 -mem_file_path > "image_8x1024.hex" -mem_file_type hex > > # End the editing sequence > end_memory_edit > > Customized the file based on your environment. Then, you can run that > TCL script in command line as "quartus_stp.exe -t example.tcl" > > Hope this helps, > Subroto Datta > Altera Corp. > > > > On Oct 6, 8:03=C2=A0am, "david" <1024.da...@gmail.com> wrote: > > this is a good idea, thanks > > i am trying to load the quartus_stp package, the file exist in the > > qurtus/bin libarry > > =C2=A0but i can't load it, i am not using external logic analyzer > > how can i load the file? all the commands that belong to the in memorry > > edit is not available > > so' how can i load it? > > > > thank you very much > > david > > > > SubrotoDatta =D7=9B=D7=AA=D7=91: > > > > > > > > > Hello David, > > > > > You can use the TCL interface to automate the memory update. =C2=A0Use > > > quartus_sh --qhelp to get the help on the "insystem_memory_edit" TCL > > > package. =C2=A0This package is only available in the shell provided by > > > quartus_stp.exe. > > > > > If you are using an external logic analyzer, you can install the free > > > small standalone programmer > > > (https://www.altera.com/support/software/download/programming/quartus= 2=2E..) > > > with SignalTap II on the logic analyzer. =C2=A0This package includes = the > > > quartus_stp.exe executable. =C2=A0If you are using SignalTap II Logic > > > Analyzer, the acquisition can be started in quartus_stp.exe as well > > > using the TCL command from the "stp" package. > > > > > Hope this helps, > > >SubrotoDatta > > > Altera Corp. > > > > > On Oct 5, 1:54=C2=A0am, "david" <1024.da...@gmail.com> wrote: > > > > hello > > > > thank you for your replay > > > > > > we allready tried this option before, but we have a problam, becaus= e we > > > > need to modify the data in the memory while the system is runing ( = the > > > > in system memory size is to small for ower application), every 512 > > > > clock cycles. > > > > can we update the memory automaticly with new data from predefine f= iles > > > > (hex files) while the system is runing? (it's not practiclly to rew= rite > > > > manually every 512 clocks cycles, we need the system to run at least > > > > for 32768 clock cycles continusly, we can spend clock cycles as nee= d to > > > > rewrite the content of the memory) > > > > > > thanks > > > > david > > > > > >SubrotoDatta =D7=9B=D7=AA=D7=91: > > > > > > > It is definitely possible to update the memory and constants in a= programmed > > > > > device from Quartus using the In System Memory Content Editor. De= tails can > > > > > be found at: > > > > > > >http://www.altera.com/literature/hb/qts/qts_qii53012.pdf > > > > > > > You can use this in conjunction wiith SignalTap II Embedded logic= analyzer > > > > > to debug your work. > > > > > > > Hope this helps, > > > > >SubrotoDatta > > > > > Altera Corp. > > > > > > > "david" <1024.da...@gmail.com> wrote in message > > > > >news:1159976602.300018.42380@e3g2000cwe.googlegroups.com... > > > > > > hello > > > > > > i am a student, working on development kit nios 2 cyclone editi= on. > > > > > > i want to use the logic analyzer to import data to the fpga fro= m the > > > > > > logic analyzer, can i do it?- Hide quoted text -- Show quoted t= ext -- Hide quoted text -- Show quoted text -Article: 110288
Zara schrieb: > On 13 Oct 2006 00:56:00 -0700, "Antti" <Antti.Lukats@xilant.com> > wrote: > > >Hi > > > >can someone suggest what version of ISE would be best candidate not to > >fail on XC95xxXL fitting? > > > >ISE 8.2SP3 fails badly - I was hoping not have to install older > >versions and check with WebFitter, but: "WebFITTER has been replaced by > >ISE WebPACK" !!!! > > > >and latest ISE fails badly with XC95xxXL as target, the same VHDL > >design reports different number of pins being used if XC95xxXL is > >selected, eg FPGA targets, Coolrunner/II - all report no issues with > >the desgin, but as soon as it run with XC95xxXL selected then different > >number of input pins are reported as not there. There is no clue why > >they are disappearing and what else may be wrong. > > > >Stepping back ISE history and installing 7.x then 6.x ...etc and > >retesting in the hope that maybe > >some older version works is really painful :( > > > >Antti > > > I am using ise 8.1sp3 on an xc9572xl-10VQ64. > > But I do rememeber I had to play a little with settings until the > project imported from 7.1 worked ok. > > I am not sure, but may be it was Optimization Effort (turned to High) > the point I changed. > > I suppose that it should work also with 8.2, but if you keep on having > problems, I may take a deepest look at the project under 7.1 and > compare it to the project under 8.1, to see the real changes I made. > > I am installing 8.2 in a couple of weeks, I will the see if there > arise new problems. > > Best regards, > > Zara got it working (or deliver reasonable reports at least) with ISE 8.1SP3 but only when synthesis goal is set to "area" all attempts to play with settings in 8.2 have failed so far, eg the input pins are missing no matter how much I have randomized the synthesis/fit options. maybe a perl script (similar to xplorer) that re-reruns the design with different options and monitors when the missing pin appear again in report and then stops? Ok, 8.1 seems to work - so case closed this time. AnttiArticle: 110289
axalay@gmail.com schrieb: > May I use rocketIO (Virtex2PRO) in custom mode for > serialize/deserialize STM-1 (155.52 Mb) ? the data-rate is too slow for RIO - you need to oversample your signal and do a reconstruction afterwards ... do you really want to do that?? bye, MichaelArticle: 110290
We don't have everything you want on a single board but have a look at our Hollybush1 and Tarfessock1 boards. Also look at the other Spartan-3 boards MINI-CAN, Broaddown2, Raggedstone1 with available modules. There are 2 more concepts kicking around the office that are going to be closer but I not going to release details on that yet or give any real timescales till we are much closer to launch. John Adair Enterpoint Ltd. - Home of Hollybush1. The PCI104 Spartan-3 Development Board. http://www.enterpoint.co.uk "GaLaKtIkUsT" <taileb.mehdi@gmail.com> wrote in message news:1160727030.659336.317610@h48g2000cwc.googlegroups.com... > Hi all, > I looking for a Spartan-3/3E based board with the following features > (other features are also welcome): > - 8-way 10-16bits ADC. 8 way 10-16bits DAC. > - Rich interconnect (RS232, CAN, USB, ETH, ...) > - Rich memory (DDR SDRAM+FLASH) > > The SP305 is almost perfect but it's no longer sold by Xilinx :( > > Cheers >Article: 110291
http://www.sierraic.com/pnresults.asp?part=XC5VLX50T1FF1136CES there is status "available" - and full order code as well ! surprisingly Xilinx website doesnt even list device codes for V5LX(T) devices yet. to what I understand all T parts (LXT, SXT and FXT) have 4 TEMACs and 1 PCIe MAC AnttiArticle: 110292
Antti schrieb: > http://www.sierraic.com/pnresults.asp?part=XC5VLX50T1FF1136CES > > there is status "available" - and full order code as well ! > > surprisingly Xilinx website doesnt even list device codes for V5LX(T) > devices yet. > > to what I understand all T parts (LXT, SXT and FXT) have 4 TEMACs and 1 > PCIe MAC > > Antti !? virtex-5 LXT PCIe has passed PCISIG compliance testing as well !! see here http://www.pcisig.com/developers/compliance_program/integrators_list/pcie/ so I assume the parts are actually obtainable already? AnttiArticle: 110293
Hi, though not directly releated to the topic but i have similar problem with webpack ise. the follow code runs ok on 6.3i but fails on 8.2i. can anyone help me out why its so and whats the solution? addr_r <= unsigned(addr_nxt(15 downto 1)); addr_r is declared unsigned(22 downto 0) while addr_nxt is std_logic_vector(15 downto 0) i have also included libraries as : library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; with exactly the same files, this code compiles ok on ise 6.3i but gives error on 8.2i, the error is that actual size is 23 while the operand on right hand side has size 16. Antti wrote: > Zara schrieb: > > > On 13 Oct 2006 00:56:00 -0700, "Antti" <Antti.Lukats@xilant.com> > > wrote: > > > > >Hi > > > > > >can someone suggest what version of ISE would be best candidate not to > > >fail on XC95xxXL fitting? > > > > > >ISE 8.2SP3 fails badly - I was hoping not have to install older > > >versions and check with WebFitter, but: "WebFITTER has been replaced by > > >ISE WebPACK" !!!! > > > > > >and latest ISE fails badly with XC95xxXL as target, the same VHDL > > >design reports different number of pins being used if XC95xxXL is > > >selected, eg FPGA targets, Coolrunner/II - all report no issues with > > >the desgin, but as soon as it run with XC95xxXL selected then different > > >number of input pins are reported as not there. There is no clue why > > >they are disappearing and what else may be wrong. > > > > > >Stepping back ISE history and installing 7.x then 6.x ...etc and > > >retesting in the hope that maybe > > >some older version works is really painful :( > > > > > >Antti > > > > > > I am using ise 8.1sp3 on an xc9572xl-10VQ64. > > > > But I do rememeber I had to play a little with settings until the > > project imported from 7.1 worked ok. > > > > I am not sure, but may be it was Optimization Effort (turned to High) > > the point I changed. > > > > I suppose that it should work also with 8.2, but if you keep on having > > problems, I may take a deepest look at the project under 7.1 and > > compare it to the project under 8.1, to see the real changes I made. > > > > I am installing 8.2 in a couple of weeks, I will the see if there > > arise new problems. > > > > Best regards, > > > > Zara > > got it working (or deliver reasonable reports at least) with ISE 8.1SP3 > > but only when synthesis goal is set to "area" > > all attempts to play with settings in 8.2 have failed so far, eg the > input pins are missing no matter how much I have randomized the > synthesis/fit options. > > maybe a perl script (similar to xplorer) that re-reruns the design with > different options and monitors when the missing pin appear again in > report and then stops? > > Ok, 8.1 seems to work - so case closed this time. > > AnttiArticle: 110294
Thanks Antti it works! but i still wonder what the lattice people are doing. no response in more than a month time. Antti wrote: > avionion@gmail.com schrieb: > > > As mentioned by Antti, its not issue of uncompressing tar.gz or zip > > files, i am unable to get anything downloaded. just read the mesage > > that i get whenever i click on any link. i even wrote to webmaster, but > > its about a month ,and with 2 reminds, still no response from > > webmaster. > > Jon Beniston wrote: > > > avionion@gmail.com wrote: > > > > Hi Antti > > > > i am unable to get any download from lattice website and get the > > > > following message: > > > > "The file you have attempted to retrieve is not available at this time. > > > > > > > > We apologize for the inconvenience. > > > > > > > > If you continue to experience this difficulty, please contact the > > > > Webmaster" > > > > i have an account with lattice website as well. i am unable to download > > > > any zip or exe file but pdf files open correctly. anyone else facing > > > > this problem? any solution to it? > > > > > > The file you download is a tar.bz2, not zip or exe. You need to extract > > > it with: > > > > > > tar xjf src.tar.bz2 > > > > > > Cheers, > > > Jon > try here, > > http://www.microfpga.com/files/Mico32DevTool_Installer_6_0_1_15.exe > > 200MB, full set of the LM32 distro > (except datasheets and GCC sources) > > AnttiArticle: 110295
avion...@gmail.com schrieb: > Hi, > though not directly releated to the topic but i have similar problem > with webpack ise. > the follow code runs ok on 6.3i but fails on 8.2i. can anyone help me > out why its so and whats the solution? > > addr_r <= unsigned(addr_nxt(15 downto 1)); > addr_r is declared unsigned(22 downto 0) while addr_nxt is > std_logic_vector(15 downto 0) > i have also included libraries as : > library ieee; > use ieee.std_logic_1164.all; > use ieee.std_logic_arith.all; > use ieee.std_logic_unsigned.all; > use ieee.numeric_std.all; > with exactly the same files, this code compiles ok on ise 6.3i but > gives error on 8.2i, the error is that actual size is 23 while the > operand on right hand side has size 16. > thats correct (by ISE 8.2) it does more checks - just add the (15 downto 0) to the lefthand operand should work then AnttiArticle: 110296
avionion@gmail.com schrieb: > Thanks Antti it works! > but i still wonder what the lattice people are doing. no response in > more than a month time. > Antti wrote: > > avionion@gmail.com schrieb: maybe their webmaster is learning at Xilinx? AnttiArticle: 110297
ElectronicDesignNet wrote: > In article <1160689402.959973.55670@k70g2000cwa.googlegroups.com>, > "jacko" <jackokring@gmail.com> wrote: > > i would be interested in construction contractors, who build to design > > and ship. didn't try the distributors list, as i have no built design > > yet. does such a service exsist? > > I might be able to get some ideas for you, but I would need to know a > little more about what it is you want to build, and what the contractor > would need to do (i.e. what they are given, and what do they produce). > > Thanks, > > Patrick > Webmaster > http://www.ElectronicDesignNet.com http://indi.microfpga.com for the start of the design, but the product will be toy like, and about as complicated as one of those kidi-vidi games. Not fully designed, still a way to go, but if i had the designs today, then i would be looking for? cheers p.s. give me about a year, and a lot of market research ....Article: 110298
Most onnounces are made by Xilinx on monday, perhaps next monday? Antti wrote: > Antti schrieb: > > > http://www.sierraic.com/pnresults.asp?part=XC5VLX50T1FF1136CES > > > > there is status "available" - and full order code as well ! > > > > surprisingly Xilinx website doesnt even list device codes for V5LX(T) > > devices yet. > > > > to what I understand all T parts (LXT, SXT and FXT) have 4 TEMACs and 1 > > PCIe MAC > > > > Antti > > !? virtex-5 LXT PCIe has passed PCISIG compliance testing as well !! > see here > > http://www.pcisig.com/developers/compliance_program/integrators_list/pcie/ > > so I assume the parts are actually obtainable already? > > AnttiArticle: 110299
So I asked Altera when they would release a version of Quartus that would support multi-threaded place and route (this takes the most time on the designs I have worked on) I also asked them about the best (fastest) PC to run quartus on. here's my questions followed by their answers. ------------------------------------------------------------------------------------------------------------- Q: at the end of year I am thinking of purchasing a new PC to do my quartus and EDA development on. I was wondering how the system requirements will change with the release of vista, and what the ideal system configuration for running fast synthesis and place and route will be. Right now I am having to wait between 15 minutes and two hours for various designs to compile. What system components will most contribute to faster place and route and synthesis (eg, more ram, more processors, faster ram, faster processors, 32 vs 64 bit architecture?, any specific CPU more highly rated then others?) A: Altera does not have recommendations for CPUs/Mother Board. About the choice for AMD or Intel processor, Altera does not have testcases to show one way or another. However, the compile time is mostly related to CPU speed and physical memory size. For detailed information on memory requirements for compilation targeting different device architectures, please refer to the readme file by clicking Quartus II menu "Help -> Readme File". If system memory is enough and Quartus II don't use hard disk as virtual memory, you could try to upgrade your CPU speed for good performance. However, if memory is not enough and hard disk virtual memory is frequently used, the compilation time will increase more. Therefore, I think we could firstly satisfy the physical memory requirement of Quartus II compilation and then try to upgrade CPU speed. Multi processor system or multi-thread CPU will help you run other applications at the same time as running the Quartus II compile, but not necessarily will help with the compile time. Quartus II can support 64 bit system. Generally, 64 bit Quartus II can run faster than 32 bit if memory is adequately large (> 2G). However, the performance upgrade is dependent on specific design project and we can't provide detailed benchmark. 64-bit Quartus II version 6.0 can be installed in UNIX Workstations (64-bit) (Solaris 8 and 9 only) or Linux Workstations (64-bit AMD64/EM64T processors) (Red Hat Enterprise Linux 3.0/4.0 WS 64-bit for AMD64/EM64T only). ------------------------------------------------------------------------------------------------------------------- Q: when will quartus be certified as being windows vista compatible, and is a 64 bit windows/vista version planned? secondly, with the rise of multicore and multiprocessor systems, is work being done to parallelize the algorithms for synthesis and place and route in order to achieve speed benefits available through multiprocessor systems as they become the norm in the PC market. A: I can't provide the exact schedule about Quartus II certification on Windows Vista. It's also due to the maturity of the OS. However, Altera software surely can support those operations systems if they are popular. Our roadmap for Quartus II software also includes multi thread or multiprocessor system support. However, the release schedule is also not determined by now. But it might be no later than the end of next year. Thanks for your understanding. --------------------------------------------------------------------------------------------------------------------------
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