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tbrown wrote: > Instead of using the environment variable, try renaming the license file > "license.dat" and place in it the directory c:\flexlm. > > My purchased version of Modelsim, which had worked for months, suddenly > quit working even though the environment variable and license file were > properly set. Making this changed fixed it. > > Remember, Mentor doesn't really want you to run their tool, they just want > you to buy it :) > > > > On Sun, 15 Oct 2006 11:45:29 -0700, jacko wrote: > > > hi > > > > got the tester of model sim from altera, but it seem even though i set > > the environment var from the system control panel, it don't appear > > hence con not find file. this is both quartus II which has other > > methods so no problem, and modelsim which does not find any environment > > variable. > > > > don't work from command.exe either. > > > > any help would be appreciated. > > > > cheers I'm not convinced that ModelSim 6.x uses the lm_license_file environment variable. I have two versions of Lattice ispLever on my Windows XP system, and I suddenly lost my ability to use ModelSim when the older license file ran out. I ran through my entire registry and made sure no keys or data pointed to the old license file, but only by moving the newer file to the old directory could I run ModelSim. I also looked around for .ini files that might hold this information but didn't find anything. So the bottom line is that it's best to place the license file in the default location (whatever that is)... Good Luck, GaborArticle: 110526
wolflame wrote: > how to change the CCLK frequency for FPGA in master-serial mode? I try to set the clock rate to higher rate in ISE when generating PROM file, but it always start as 2M clock.. If you need to program the part at the maximum allowable rate, your best bet is to use slave-serial mode and generate the clock with a more accurate oscillator. Usually the maximum rate of programming will be limited by the PROM, not the FPGA. The clock rates listed in the configuration settings are approximate, and you need to take into account the maximum rate when selecting the frequency for a particular PROM. If the short portion of the configuration which takes place at 2MHz makes a difference to your application, it seems you are trying to push the master-serial beyond its useful range. just my 2 cents, GaborArticle: 110527
Hi,
take a look at
Shared Memory Multiprocessing Using the Virtex II PPC:
Sharing Memory, Sharing a UART, and Synchronization
A Guide for the XUP Development Board
John K. Bennett1
University of Colorado at Boulder
November 2005
Beside shared memory to connect two or more Microblaze cores you can use
the FSL interface.
For example see
A MicroBlaze Based Multiprocessor SoC
P.HUERTA, J.CASTILLO, J.I.MÁRTINEZ, V.LÓPEZ
HW/SW Codesign Group
Universidad Rey Juan Carlos
28933 Móstoles, Madrid
SPAIN
{pablo.huerta, javier.castillo, joseignacio.martinez, victor.lopez }@urjc.es
One obstacle is the limited support of the Xilinx EDK for multiple
cores. You can add multiple cores and their peripherals to your EDK
design but you have to craft the memory map by hand for example.
If you target Virtex-4 instead of Virtex-IIPro you can use the APU of
the PPC core to connect PPC and Microblaze cores via an APU-FSL bridge.
This has the advantage that the software for PPC and Microblaze can be
quite similar.
In my opinion the main challenge is to build a software which makes
efficient use of multiple cores. On-chip memory is quite limited if
distributed among a number of cores. Depending on your application data
distribution and scheduling can add quite an overhead so you might run
out of on-chip memory.
Regards,
Andreas
Article: 110528For now, just to de-modulate, and de-interleave PCS. I know those cores are in the core generator for Xilinx, but I guess I was looking for a group so that I could speed up the process a little bit on trying to actually make sense of the signals. So I am actually looking for suggestions on anywhere from board suggestions to making sense of the BCCH. Thanks for straightening me out on the google topic. Didn't know it was such a sore subject. pbdelete@spamnuke.ludd.luthdelete.se.invalid wrote: > karrelsj <karrelsj@gmail.com> wrote: > >Does anyone have any good links to groups/companies working on GSM or > >CDMA IP cores? Or maybe something like a GSM SDR?... Thought I would > >start here prior to my google search, after all it is a google group. > > This is NOT a google group. > Google Inc. Just happens to archive posts, and provide an webinterface. > Get yourself a proper nntp server + client and you will see the light. > > As for GSM/CDMA.. what is your objective?Article: 110529
I *was* asking ddrinkard about the Lattice parts. I had forgotten about the MACO since my recent attention has been on the ECP2M devices. Yes, the new Xilinx parts do the endpoint *and* the SERDES. That's what started the conversation. Aurelian Lazarut wrote: > Both > Aurash > John_H wrote: > >> Built-in PCIe or built-in SERDES? >> >> >> "ddrinkard" <dale.drinkard@gmail.com> wrote in message >> news:1161035523.262190.222240@k70g2000cwa.googlegroups.com... >> >> >>> Hmmm, first in industry with built-in PCI-express? Lattice SCM devices >>> have built-in PCI express, have had since Feb (along with a boat-load >>> of other stuff too). 100mW per channel, finally catching up with >>> Altera and Lattice... S3A may have built-in Flash...seen that before >>> too. It's kinda fun watching Xilinx playing catch-up.... ;)Article: 110530
Antti wrote:
>Aurelian Lazarut schrieb:
>
>
>
>>Both
>>Aurash
>>John_H wrote:
>>
>>
>>
>>>Built-in PCIe or built-in SERDES?
>>>
>>>
>>>
>
>
>
Antti,
Agree 100%, maybe it worth to be mentioned that SERDES is PCIe compliant
but not only,
when we say "PCIe compliant SERDES" some users will assume dedicated
ser/des is for PCIe only, which is not the case, users have the freedom
to program the MGTs in many other standards (it's more like, PCIe
capable MGTs)
Aurash
>Aurash,
>
>correct would be
>
>built in PCIe compliant SERDES
>AND
>PCIe endpoint
>
>if PCIe host or hub is required then it must be implemented 100% in
>FPGA fabric, eg full soft-core
>
>Antti
>
>
>
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 110531I am a student working on a simple MPEG-2 encoder and want to use the Xilinx DCT in Application note 610. The DCT has 8 bit input and 12 bit output, but if I connect a DCT and IDCT in series to test them the result is wrong. I get about the right result for the 7 lowest bits, but I miss the highest bit. If i compere the result of the DCT and Matlab I also get different results. Have any of you used this reference design? Anders Rustad Student, NTNU Trondheim, NorwayArticle: 110532
Both Xilinx (http://www.xilinx.com) and Altera (http://www.altera.com) offer 'web-pack' versions of their commercial software. If you haven't already, pick a vendor and down load the free version and work through the tutorials. Derek leeaby@gmail.com wrote: > Hi everyone, > > I am new to the FPGA, and would like to know more about how we can > program an FPGA to do a complex task. > > Please suggest the steps or any website relevant to this which aids in > studying. > > Thanks to all in advanceArticle: 110533
Hi folks, I am just trying my first steps with the picoblaze. And I feel alone with some questions. My situation [to avoid unnecessary tips :-)]: I don't use ISE gui or core generator, only a self-made flow consisting of a few nice shell scripts. What I am able to to is to use Block ram (RAMB16 on Spartan 3 and 3e) in a n*8 bit width configuration and initialize it via data2mem. Once I wrote a suitable .bmm file. But as of today I cannot anymore find the data2mem documentation which I used back then again :-( -> Question: Where to get the full docs on data2mem? Now I want to hook up a picoblaze to a block ram. The picoblaze uses 18 bits width, that means 16 bit plus parity. -> Question: How do I initialize that with data2mem? I have kpicosim which outputs a .mem file. But I don't know how to write the appropriate .bmm file. I also don't know anything detailed about kpicosim as I cannot find ANY docs about it. Anyone experience with kpicosim? I would appreciate having a "vhdl template file" for it. -> Question: Can I use data2mem for simulation (by generating a vhdl configuration for example)? Any hints, code samples, suitable .bmm-files are very welcome. Thanks a lot! Best regards, Philipp :-)Article: 110534
1) I even tried RAMB18 in the *.bmm file but unfortunately this results in the same wrong data. 2) Why the parity bits aren's used if my block ram use more than 4 BRAMs? I actually need a number of seperate 16*1024 Block RAMs in my project and can't use 4 or more BRAMs for one of my Block RAMs. Someone has an idea if the bit mapping error is done by data2mem or by the Block Memory Generator?Article: 110535
Ben schrieb: > 1) I even tried RAMB18 in the *.bmm file but unfortunately this results in the same wrong data. > > 2) Why the parity bits aren's used if my block ram use more than 4 BRAMs? I actually need a number of seperate 16*1024 Block RAMs in my project and can't use 4 or more BRAMs for one of my Block RAMs. > > Someone has an idea if the bit mapping error is done by data2mem or by the Block Memory Generator? option 3 instantiate BRAM from HDL code, that works AnttiArticle: 110536
Hi again, sorry for asking silly questions.... I already found SOME answers: I found the data2mem doc again. And I found a note in this usegroup's archive that I can tell data2mem something about RAMB18. Ok, but I still have to use RAMB16 in my design, is that correct? And if I do, where and how to use the parity data lines? Possibilities to form the picoblaze input are: 15 0 10 DDDDDDDDDDDDDDDD PP and 10 15 0 PP DDDDDDDDDDDDDDDD Of course I could also twist the parity bits. So how to do it correct the first time? What kind of vhdl file is output by data2mem? does it handle the 18 bit things correctly when used that way? Best regards, Philipp :-) Philipp Hachtmann wrote: > Hi folks, > > I am just trying my first steps with the picoblaze. And I feel alone > with some questions. > > My situation [to avoid unnecessary tips :-)]: > I don't use ISE gui or core generator, only a self-made flow consisting > of a few nice shell scripts. > What I am able to to is to use Block ram (RAMB16 on Spartan 3 and 3e) in > a n*8 bit width configuration and initialize it via data2mem. Once I > wrote a suitable .bmm file. But as of today I cannot anymore find the > data2mem documentation which I used back then again :-( > > -> Question: Where to get the full docs on data2mem? > > Now I want to hook up a picoblaze to a block ram. The picoblaze uses 18 > bits width, that means 16 bit plus parity. > > -> Question: How do I initialize that with data2mem? > > I have kpicosim which outputs a .mem file. But I don't know how to write > the appropriate .bmm file. I also don't know anything detailed about > kpicosim as I cannot find ANY docs about it. Anyone experience with > kpicosim? I would appreciate having a "vhdl template file" for it. > > -> Question: Can I use data2mem for simulation (by generating a vhdl > configuration for example)? > > Any hints, code samples, suitable .bmm-files are very welcome. > > Thanks a lot! > > Best regards, > > Philipp :-)Article: 110537
I have a number of Dual-Port Rams and FIFOs that I've implemented with Quartus II 6.0 sp#1, targeting a Stratix II device. When I simulate with my test bench in the "functional" world, everything acts as expected. When I compile the .vho/.sdo files and run against a slightly modified test bench (differences in output file names and the test bench calling out the VITAL version of the FPGA implementation), it appears that there is an additional register delay that has been introduced into the Dual-Port/Fifo implementations. Is this normal? Or do I need to make some type of adjustment for this behavior? I don't quite know how to explain/justify the differences at this point. I had specified in the Megawizard setup for each of the memory types, that the output was registered -- I'd think that the functional model would work the same as the gate level implementation of the Fifos/Rams.Article: 110538
Hi, Paul Uiterlinden wrote: > Davy wrote: > > > Hi all, > > I don't know if Synopsys's VMM is open document and open source > > code. > > As far as I know the VMM book is not an open document: > http://www.vmm-sv.com/ > I don't understand this - perhaps you are mixing "open" with "free"? VMM is a published book so why is it not open? Infact we wrote a book on "pragmatic approach to VMM adoption" based on that book. (See www.systemverilog.us if interested). BTW, VMM also ships under $VCS_HOME/doc. > The AVM cookbook clearly is. > > The same goes for VMM and AVM itself. AVM is opensource, VMM source is > heavily licensed (word choice from Verification Horizons). > Quoting from: http://www.synopsys.com/news/announce/press2005/snps_sourcode_licsvpr.html SNPS gives source code to VCS users if they request for the same. Now having said all this, given the status of SV implementation by major eda vendors, neither VMM nor AVM is truly "portable" as of today - tools support different subsets just to fit into their individual methodology, perhaps the tool development was driven by the methodology team. So when 100% SV implementation is available across vendors, users may not have an issue of AVM vs. VMM as both will work in any simulator. Now, I'm teaching myself AVM and am finding it quite similar to VMM. Sure VMM has much more stuff, also maturity (given their RVM legacy), AVM has some "new" concepts such as analysis ports etc. I asked Mentor if I can openly debate on AVM, no reply yet... Regards Ajeetha, CVC www.noveldv.com > -- > Paul.Article: 110539
dd, No ruffled feathers, I assure you. Just thought I might have missed something. Marketing hyperbole aside. Austin ddrinkard wrote: > The Lattice parts have hard IP for the MAC and LTSSM (MACO), I'll look > more deeply into the LXT, complete endpoint huh? I suppose that has > some value. (is this where I'm supposed to cry Uncle?) One might > assert it's splitting hairs suggesting other players have nada...but > marketing is marketing...and Xilinx didn't get to be a billion dollar > company by doing it badly....Since Xilinx is the only one talking about > their 65nm products I suppose they are, by default, the defacto leader > in that arena. > > I just wanted to point out that the LXT is not the first FPGA with > hardened communications IP blocks, that's all. Sorry to have ruffled > your feathers. Those Xilinx parts, they're pretty nice too....and I > acknowledged that a long time ago.... ;) > > > Austin Lesea wrote: >> dd, >> >> Hardened PCIe (in V5). Not a core. Don't see any hardened PCIe on >> Lattice website. Am I missing something? >> >> Not that the Lattice SC products are not nice, they are, and I have >> acknowledged that a long time ago. But I don't see any hardened PCIe >> core(s). Is this something they are keeping secret? >> >> Austin >> >> ddrinkard wrote: >>> Hmmm, first in industry with built-in PCI-express? Lattice SCM devices >>> have built-in PCI express, have had since Feb (along with a boat-load >>> of other stuff too). 100mW per channel, finally catching up with >>> Altera and Lattice... S3A may have built-in Flash...seen that before >>> too. It's kinda fun watching Xilinx playing catch-up.... ;) >>> >>> >>> Antti wrote: >>>> Antti schrieb: >>>> >>>>> http://www.xilinx.com/prs_rls/2006/silicon_vir/0696v5lxt.htm >>>>> >>>>> already pricing given for 1000qty not bad at all. >>>>> >>>>> unfortunatly the LXT related user guides >>>>> ug194 EMAC >>>>> ug196 GTP >>>>> ug197 PCIe >>>>> >>>>> are all deadlinks at the moment but hopefully those documents become >>>>> available shortly. >>>>> >>>>> new eval boards (besides ML501) are >>>>> >>>>> ML505 - allows PCIe testing >>>>> ML523 - GTP characterization board >>>>> ML555 - 8x PCIe card >>>>> >>>>> GTP has OOB support for PCIe/SATA and supports spread spectrum clocking >>>>> as well. >>>>> >>>>> Antti >>>> correction ug194 and ug196 are already available (appearead 6 minutes >>>> after the post), so the only missing one is the PCIe UG >>>> >>>> myself >Article: 110540
Al wrote:
> I had never had this approach, in the sense that I always checked syntax
> directly with the Synplify, moreover I always used the testbench just
> for the post-synthesis simulation, never for the functional,
This is the default path laid out by the device vendors,
but it seems backwards to me.
> can help me quicker to find out "functional" problems.
I expect that it will.
-- Mike Treseler
Article: 110541What a lesson, that's a good one! But I think you missed step 11: 11. make your 'complex task' working with something else's 'complex task' and if not...let's step back to #4 alltogether!! Al KJ wrote: > <leeaby@gmail.com> wrote in message > news:1161080895.017982.164240@m73g2000cwd.googlegroups.com... > >>Hi everyone, >> >>I am new to the FPGA, and would like to know more about how we can >>program an FPGA to do a complex task. >> >>Please suggest the steps or any website relevant to this which aids in >>studying. > > > 1. If you haven't done so already, learn a design language (VHDL and Verilog > come to mind). > 2. If you haven't done so already, learn how to use a simulator for the > above chosen language. > 3. If you haven't done so already, learn how to use a synthesis tool which > turns code written in the above chosen language into a file that you'll > download into the FPGA. > 4. Code up your 'complex task' in the above chosen language. > 5a. Simulate the code to make sure that it is functioning how you want it > to. > 5b. Run the code through the synthesis tool every now and then just to make > sure that the code you are writing and debugging is synthesizable. > 6. Once simulation is nearly complete, run it through the synthesis tool to > get timing numbers. If they are not acceptable go back to step 4 and > rewrite it in such a way that the timing performance numbers have been met. > 7. Keep going back to step 4 until the simulation says that you've > implemented what you intended....only then can you continue on to #8. > 8. Synthesize the code one last time to produce the bitstream to load into > the FPGA. > 9. Load the bitstream into the FPGA which is presumably on a board that has > the necessary input and output connections to meet the needs of your > 'complex task'. > 10. If the end result doesn't work as intended, debug to find out why. Then > beef up your simulation testbench to catch this type of problem. Verify in > simulation that you can recreate the problem. Go back to step #4 and figure > out what the fix is. > > KJ > > -- Alessandro Basili CERN, PH/UGC Hardware DesignerArticle: 110542
> correct would be > > built in PCIe compliant SERDES > AND > PCIe endpoint so can anyone tell me what this means? what can I save from that? right now one could use a virtex4 and buy a PCIe core. The plda solution eats up half of your FPGA and takes >1h just for synthesis ... This is not very flexible :-/ How much logic ressources will be needed with Virtex5 LXT? will there be any software support? drivers? .. so the LXT parts have serdes? so I could do other high speed signals with that as well? or will there be a FX part in the future with real RocketIOs? I saw a V5 HD-SDI board at the xilinx booth at IBC last month - they didn't want to tell me much about it ... the announcement was close was that with LXT? or even FX? bye, MichaelArticle: 110543
Michael Sch=F6berl schrieb: > > correct would be > > > > built in PCIe compliant SERDES > > AND > > PCIe endpoint > > so can anyone tell me what this means? what can I save from that? > > right now one could use a virtex4 and buy a PCIe core. The plda solution > eats up half of your FPGA and takes >1h just for synthesis ... This is > not very flexible :-/ > > How much logic ressources will be needed with Virtex5 LXT? > will there be any software support? drivers? > > > .. so the LXT parts have serdes? so I could do other high speed signals > with that as well? or will there be a FX part in the future with real > RocketIOs? > I saw a V5 HD-SDI board at the xilinx booth at IBC last month - they > didn't want to tell me much about it ... the announcement was close > was that with LXT? or even FX? > > > bye, > Michael all "T" parts eg LXT, SXT, FXT have the same serdes. 100MBit/s to 3.2GBit/s analog PLL (was not there before more flexible) supports spread spectrum clocking OOB support for at least SATA and PCIe (maybe other as well) LUT requirement to implement PCIe endpoint in V5xxT : 100 LUTs AnttiArticle: 110544
Al wrote: > > 11. make your 'complex task' working with something else's 'complex > task' and if not...let's step back to #4 alltogether!! > I meant someone else's 'complex task'!! -- Alessandro Basili CERN, PH/UGC Hardware DesignerArticle: 110545
Jim Granville schrieb: > Antti wrote: > > Hi > > > > the sysmon is really available in ALL Virtex-5 devices > > below is voltage and temperature monitoring log screenshot from > > Chipscope > > > > http://www.xilant.com/downloads/cs82_sysmon.jpg > > > > the temperature drops seen in the log are my finger pressed to the top > > of the Virtex-5 package > > So, was this doing anything, or is that just self-heating gets it > to +28'C above ambient ? > > -jg it had the ML501 reference design loaded. You can look at the ref design manuals at Xilinx website to see what stuff is all included. the LX50 is 38% full AnttiArticle: 110546
I recently purchased the sp3e starter to teach myself VHDL, and later realized that the EDK came with the pacakge. I then started to use the EDK and I am very happy with the tool. I've implemented the Micoblaze processor and I've started using it with uClinux and FreeRTOS. I am still trying to deal with all of the nuances; there are some fundamental bugs that will prevent you from generating the bitstream unless you know the workarounds. Email me if you have questions. CMOS wrote: > i already have starter board for xilinix spartan 3, which i bought > directly from digilent (so i did't receive EDK CD). im planning to buy > started kit for spartan 3E from xilinx this time, which include EDK > evaluation CD. Is this worth? > > are there any other freely available packages similar to MacroBlaze / > EDK/ platform studio combination? > > > thanksArticle: 110547
I am finally at the synthesis portion of the course. My code "compiles", simulates, sythesisizes and implements correctly (with green check mark). But I am to get some info from the XST reports that I may not understand fully. I'm fairly certian I've collected all the data the professor requires aside from the list below. - "netlist shematic" (where do I find/how do I generate this?) - "waveforms from timing simulation" (are these sythesis specific, or are these just my modelsim simulation waveforms?) and he also asks for the min/max clock freq, with slack times after a) sythesis, b) mapping and c) p&r I will have to define a clock period I assume? Do I enter this via the constraint editor? If so, maybe a syntax example of how I might do this? After that I just need to view the timing reports after each process (a,b and, c)? I hope these questions are fair. I've read through some provided Xilinx literature, but I'm still a little lost...obviously. Thanks, KyleArticle: 110548
> > This is NOT a google group. > Google Inc. Just happens to archive posts, and provide a web interface. > Get yourself a proper nntp server + client and you will see the light. > I don't know what your problem is and you're right some people access the news groups using Google. This is place for people to come to share and exchange information. All the guy was looking for was the benefit of someone else's experience to start his research. So, chill out and give the guy a break. BTW - I have been using the news groups for about 20 years. My preferred method used to be using rn (read news) but recently Outlook Express. But because of SPAM and I don't always have my laptop with me but I can find a free computer, I have been using Google more. DerekArticle: 110549
Lattice is holding a webcast tomorrow Wednesday, October 18, "Embedded Design with LatticeMico32 Open, Free 32-bit Soft Processor." The presenter will be Amr El-Shimi, from our IP marketing group. If you're interested, the event takes place live at 11am Pacific, 18:00 GMT. In addition, you will be able to view this webcast archive on-demand, at your convenience, starting a 24 hours after the live event takes place. You can register by clicking: http://www.latticesemi.com/corporate/webcasts/embeddeddesignwithlattice/index.cfm Bart Borosky, Lattice
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