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212 wrote: > Required a book or web reference or examples suitable for xilinx xc9635 > familiy. > Thanks. http://turing.une.edu.au/~comp283/cdrom/Content/Tutorials/Verilog/VOL/main.htm and http://www-ee.eng.hawaii.edu/~msmith/ASICs/HTML/Verilog/Verilog.htm Nothing specifically for Xilinx CPLD's, but Verilog should work the same as for other hardware...Article: 113701
"chriskoh" <chrisdekoh@yahoo.com> wrote in message news:1166549588.432486.37750@73g2000cwn.googlegroups.com... > Hi, > I am pretty new to the arena of interrupt handling and would need > some help. I am currently using microblaze v4.00a and with Xilinx > platform studio 7.1 to develop some UART handling routines. what I am > not sure, is > > 1) whether the important registers (eg, stack pointers and other > registers) are saved during an interrupt handling, or do I have to > explicitly save them myself. > > I dun think this is handled by the microblaze and am wondering if > the mb-gcc C compiler would be smart enough to do the same. > > kindly advice. thanks! > Chris I have just been looking at the FreeRTOS.org Microblaze demo to see how that configured the interrupts. It seems that the development environment handles all the interrupt prologue and epilogue code for you. From the FreeRTOS.org documentation: "An interrupt service routine that does not cause a context switch has no special requirements and can be written as a normal function." and looking through the code the serial port interrupt is just written as: void vSerialISR( void *pvBaseAddress ) The fact that it takes a parameter means it cannot be called directly in response to an interrupt, but indirectly after some processing. So I would conclude - you have to write your ISR like a standard function without having to worry about the save and restore of any of the registers. Saving of general purpose registers is handled by the tool. Saving of other registers is handled by the hardware itself. Once you have written your ISR you have to somehow tell the tool about it through the GUI. The file xintc_g.c is then automatically generated to contain the interrupt table and references to your ISR functions. Sorry I cannot remember specifics but I hope this is a pointer. Regards, Richard. + http://www.FreeRTOS.org + http://www.SafeRTOS.com for Cortex-M3, ARM7, ARM9, HCS12, H8S, MSP430 Microblaze, Coldfire, AVR, x86, 8051, PIC24 & dsPICArticle: 113702
212 wrote: > Required a book or web reference or examples suitable for xilinx xc9635 > familiy. > Thanks. I'm a VHDL guy, so I don't have any Verilog book recommendations (try comp.arch.verilog), but look at books that describe counters, shift registers, state-machines, PWM generators, switch debouncer, etc. You could also use the XC9536 to drive LEDs. If you're concerned about finding packages that you can solder or put into a socket, XC9536 and XC9572 are available in a PLCC-44 package. The XC95108 is the largest XC9500 part that is available in a PLCC (84) package. PLCC-44 and PLCC-84 sockets can be soldered to a PCB with 0.1" spaced holes. You may want to take a look at digilent's CMOD which has a XC9572XL soldered on a board that plugs into a standard 0.6" wide 40-pin IC socket <www.digilentinc.com>. Note the the XL part requires 3.3 volts, but its IO can handle 5 volt CMOS and TTL parts. HTH -Dave PollumArticle: 113703
MM <mbmsv@yahoo.com> wrote: > I am trying to run 2 ChipScope instances connected to two different boards. > Unfortunately, Xilinx doesn't support more than one USB cable... I found in > the past that you can actually have 2 cables running at the same time if one > of them is parallel... My problem now is that my new Dell PC doesn't have a > parallel port There are PCI parallel ports, and probably not to expensive. Parallel ports used for other than printers often use the status bits in unusual ways. Writing the device driver to emulate a parallel port used that way through USB would be more work than most want to put into one. -- glenArticle: 113704
"Jim Granville" <no.spam@designtools.maps.co.nz> schrieb im Newsbeitrag news:45885149$1@clear.net.nz... > Antti Lukats wrote: > >> PicoBlaze C compiler has been available for some time already, >> but until yesterday I never tried it. >> But today when I type: >> the evaluation package is ready for download > <snip> >> >> http://www.microfpga.com/joomla/index.php?option=com_remository&Itemid=27&func=fileinfo&id=3 > > Interesting, but light on specifics :) > > Which PicoBlaze C is this using, and what other tools do the bitstream > insertion ? Up to what Code size ? > > -jg > Hi Jim, original PCCOMP is used to generate the object file for the KCPSM3 so pccomp generates assembly for kcpsm3.exe that emits hex or actually "MEM" directly suitable for DATA2MEM so only vendor tool used is really only data2mem - there is open-source project in progress to offer 3rd party data2mem like services so it could be that the all process to final bitstream uses no vendor supplied tools at all. .. kcpsm3 has 1k word code size this version is only 'get it going with PicoBlaze' version - the main reason why I did is was the wish to support _all_ Xilinx FPGA starting from XC2S15 in all spartan3, virtex-2/P/4/5 based systems an MicroBlaze is already useable. sorry for sparse docs - I was just little impressed to see the picoblaze c compiler to be working in action so I packaged the stuff and made available for downloads the actual documentation is being prepared as well, and will be released when microblaze based system are ready to release AnttiArticle: 113705
"glen herrmannsfeldt" <gah@seniti.ugcs.caltech.edu> wrote in message news:em9nqn$3hf$3@naig.caltech.edu... > MM <mbmsv@yahoo.com> wrote: > > There are PCI parallel ports, and probably not to expensive. PCI is out of fashion too :) This PC of mine only has PCI Express and only 2 slots altogether. I guess I will go this route if I can't find another solution, but I hoped there is a proper USB-to-Parallel adapter somewhere... /MikhailArticle: 113706
MM schrieb: > I am trying to run 2 ChipScope instances connected to two different boards. > Unfortunately, Xilinx doesn't support more than one USB cable... I found in > the past that you can actually have 2 cables running at the same time if one > of them is parallel... My problem now is that my new Dell PC doesn't have a > parallel port (neither does it have a serial port )... So I got myself a USB > to Parallel adapter, but the ChipScope doesn't want to work through it... It > seems that it is only good for a printer. It doesn't even create a proper > virtual LPT port... So, I was wondering if someone knows of an adapter that > will work? > > Thanks, > /Mikhail NO way. cable III/IV will **NOT** work over USB2LPT adapter AnttiArticle: 113707
Grant Edwards wrote: > On 2006-12-19, CBFalconer <cbfalconer@yahoo.com> wrote: >> chriskoh wrote: >>> >>> I am pretty new to the arena of interrupt handling and would need >>> some help. I am currently using microblaze v4.00a and with Xilinx >>> platform studio 7.1 to develop some UART handling routines. what I >>> am not sure, is >>> >>> 1) whether the important registers (eg, stack pointers and other >>> registers) are saved during an interrupt handling, or do I have to >>> explicitly save them myself. >>> >>> I dun think this is handled by the microblaze and am wondering if >>> the mb-gcc C compiler would be smart enough to do the same. >> >> That depends on the machine you are using. Read its >> documentation. For example, an X86 saves the return address and >> the program status (flags, interrupt enables, etc.) automatically. >> Others may differ. > > The 68HC11 for example saves all registers on the stack. > Others (e.g. NIOS2) save nothing on the stack and just swap a > couple registers. Another variation is delay in re-enabling interrupts. This is often intended to allow the system to return to the interrupted code before executing another interrupt. -- Chuck F (cbfalconer at maineline dot net) Available for consulting/temporary embedded and systems. <http://cbfalconer.home.att.net>Article: 113708
Antti <Antti.Lukats@xilant.com> wrote: > NO way. > cable III/IV will **NOT** work over USB2LPT adapter It would if one made a true emulation of a parallel port, including the virtual device driver that would execute on I/O to the real I/O port. I agree that isn't likely. Though many printers do bidirectional I/O that would require the hardware to do some of that. -- glenArticle: 113709
Antti <Antti.Lukats@xilant.com> wrote: > MM schrieb: > > I am trying to run 2 ChipScope instances connected to two different > > boards. Unfortunately, Xilinx doesn't support more than one USB > > cable... I found inthe past that you can actually have 2 cables > > running at the same time if one of them is parallel... My problem > > now is that my new Dell PC doesn't have a parallel port (neither > > does it have a serial port )... So I got myself a USB to Parallel > > adapter, but the ChipScope doesn't want to work through it... It > > seems that it is only good for a printer. It doesn't even create > > a proper virtual LPT port... So, I was wondering if someone knows > > of an adapter that will work? > > > NO way. > cable III/IV will **NOT** work over USB2LPT adapter Even if the adapter would work, it would crawl like a snail. Bit-banging via USB isn't a good idea. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 113710
212 wrote: > Required a book or web reference or examples suitable for xilinx xc9635 > familiy. > Thanks. > > Xilinx has app notes for both VHDL and Verilog to get the most out of the XC9536. Is there some specific application you are looking at? Cheers PeteSArticle: 113711
MM wrote: > I am trying to run 2 ChipScope instances connected to two different boards. > Unfortunately, Xilinx doesn't support more than one USB cable... I found in > the past that you can actually have 2 cables running at the same time if one > of them is parallel... My problem now is that my new Dell PC doesn't have a > parallel port (neither does it have a serial port )... So I got myself a USB > to Parallel adapter, but the ChipScope doesn't want to work through it... It > seems that it is only good for a printer. It doesn't even create a proper > virtual LPT port... So, I was wondering if someone knows of an adapter that > will work? I had a similar problem with my MacPro. It only has PCI Express, and I had 2 parallel dongles, one for HyperLynx and one for MXE. The HyperLynx people swapped my parallel dongle for a USB with no problem - they even FedEx'd it to me at their own expense. Xilinx refused to do the same for MXE. I use the LF652KB PCI-E parallel port board from Axxon. http://www.softio.com/ic0652kb.htm They also make a parallel port/ serial port board for PCI-E. --- Joe Samson Pixel VelocityArticle: 113712
Try a USB dock like: http://www.tigerdirect.com/applications/SearchTools/item-details.asp?EdpNo=1597389&CatId=604 -Clark "MM" <mbmsv@yahoo.com> wrote in message news:4ur36rF19cplaU1@mid.individual.net... > I am trying to run 2 ChipScope instances connected to two different boards. > Unfortunately, Xilinx doesn't support more than one USB cable... I found in > the past that you can actually have 2 cables running at the same time if one > of them is parallel... My problem now is that my new Dell PC doesn't have a > parallel port (neither does it have a serial port )... So I got myself a USB > to Parallel adapter, but the ChipScope doesn't want to work through it... It > seems that it is only good for a printer. It doesn't even create a proper > virtual LPT port... So, I was wondering if someone knows of an adapter that > will work? > > Thanks, > /Mikhail > >Article: 113713
I couldn't find any rules for this group, so I am sorry if this is inappropriate. I just finished up a project I was working on in grad school. Now I have all of this hardware I am not going to use. I figured I would post it here prior to trying the eBay thing. 1 XUPv2P board (XC2VP30) 1 Kingston KVR266X64C25/512 1 Xilinx Parallel Cable IV Shoot me an email if you are interested. ThanksArticle: 113714
Hi Jerzy,
jerzy.zielinski wrote:
> I was abble to compile working uClinux core for the Spartan-3e
> Starter Kit. I was abble to program on board Flash Memory so the
> system.bit starts by itself.
>
> Can anyone help me with the bootloader, so the whole project may start
> after power-on? I need to place the system.bit and linux core somewhere
> on the board so it may boot by itself...
You need two things -
1. Get the kernel image (image.bin) into onboard flash memory
2. A trivial bootloader that resides in the FPGAs on-chip BRAM. This
bootloader simply copies the kernel iamge from flash to the correct address in
SDRAM, and jumps to the start of the image. Justa few lines of code.
There is a sample bootloader in the S3E-1600 and S3E-500 reference designs at
PetaLogix.com:
http://www.petalogix.com/resources/reference_designs/xilinx
In addition to the EDK projects, in the binary demo packages you will also find
scripts and documents describing how to get the kernel image into the flash.
Regards,
John
From dave@comteck.com Tue Dec 19 21:13:21 2006
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From: Dave <dave@comteck.com>
Subject: Spartan 3E Starter Kit Woes
Date: Wed, 20 Dec 2006 00:13:21 -0500
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I'm using ISE 8.2i and XPS 8.2i with a new Xilinx Starter Kit (the
XC3S500efg320-4 FPGA on a Rev D board) and can not get the DDR SRAM to
pass any memory tests. I have built four or five different memory test
projects including at least one tutorial, all with the same results. The
MicroBlaze communicates to a terminal window, but always reports failures
on the 32-bit, 16-bit, and 8-bit memory tests. :-(
Does anyone have a known good MicroBlaze memory test project .bit file I
could try just to check that there is no hardware problem?
It certainly would be nice if Xilinx shipped a few .bit files with the
board just for cases like this. Hint, hint, Xilinx.
Thanks,
~Dave~
Article: 113715Antti.. so how to make it go into RTI... any suggestions Antti wrote: > gomsi schrieb: > > > thanks for the replies.. > > But As stated by you TAP is working fine.. Since i just wanted to > > bypass any effect of TRST on TAP. I followed two ways to bypass trst: > > 1. Ties TRST to 1 from zero simulation time and then after the power on > > of the design i made TMS = 1 for 5 positive edges of TCK. The TAP > > does'nt enter RTI. > > OF COURSE it does not enter RTI when shift in TMS=1 > > when you clock 5 times TMS=1 then the TAP enter TLR not RTI !! > > AnttiArticle: 113716
gomsi schrieb: > Antti.. so how to make it go into RTI... any suggestions > Antti wrote: > > gomsi schrieb: from TLR 1) TMS=0 2) apply 1 (one) TCK pulse state will be RTI AnttiArticle: 113717
MM wrote: > I am trying to run 2 ChipScope instances connected to two different boards. > Unfortunately, Xilinx doesn't support more than one USB cable... I found in > the past that you can actually have 2 cables running at the same time if one > of them is parallel... My problem now is that my new Dell PC doesn't have a > parallel port (neither does it have a serial port )... So I got myself a USB > to Parallel adapter, but the ChipScope doesn't want to work through it... It > seems that it is only good for a printer. It doesn't even create a proper > virtual LPT port... So, I was wondering if someone knows of an adapter that > will work? > > Thanks, > /Mikhail > > We have tried a lot of USB-Parallel adapters for our Chameleon POD. No result. Why, the USB-to-parallel are dedicated for parallel PRINTER port ! Do you have PCMCIA, use the Quartech SPP-100. It work nice for your Chameleon Pod ! Regards, Laurent www.amontec.comArticle: 113718
thanks to all! 1) i've already posted it in the niosforum, before i posted here. (cause i needed to solve the problem before xmas :-) 2) thanks, the "using existing acc.." works fine :-) by the way i solved the problem: i thought that the whole flow which has been started by the c2h compiler includes downloading the sof file .... and i didn't recognise the difference, because i always downloaded the standard.sof file and not the time limited sof file (i just have an evaluation license at the moment) so this topic can be closed merry xmas and thanks again AndreasArticle: 113719
Uzytkownik "Johannes Hausensteiner" <johannes.hausensteiner@pcl.at> napisal
w wiadomosci news:1166448726.27101@news.aic.at...
> Hi there,
>
> The "unpredictable behaviour" manifests itself most
> prominently in this clock generator module; although I assume that
> there might be other effects as well. The sequence is this:
>
> uart_divider : process (rst, clk_in)
> begin
> if rst = '1' then
> uart_cnt <= 0;
> uart_clk <= '0';
> elsif rising_edge (clk_in) then
> uart_cnt <= uart_cnt + 1;
> if uart_cnt >= ((SYS_FREQ/2) / UART_FREQ) then
> uart_clk <= '0';
> else
> uart_clk <= '1';
> end if;
> if uart_cnt >= ((SYS_FREQ / UART_FREQ) - 1) then
> uart_cnt <= 0;
> end if;
> end if;
> end process;
>
Hi,
I advice use of following code for generating signal UART CLK enable.
Output is signal pulse which is active for one clock per N pulse of clock.
This signal is using for enable your component, for example UART Core (in my
projects: http://www.xilinx.com/bvdocs/appnotes/xapp223.pdf This IP block
has 2 dedicated inputs: CLK and EN_16X_BAUD - this is the same enable
signal). Eatch FPGA project which you create, must be synchronous - That
means, that should have one global source clock (FPGA usually has several
global lines for clock, reset, etc.) and lot of enable signals.
--UART_CLK
--CLK = 32.768 MHz
--UART BaudRate = 9600 => UART_CLK = 16 * BaudRate = 16 * CLK/x = CLK/N => N
= 213, UART_CLK = ~153.84 kHz, UART BaudRate = ~9615 Hz
process(CLK)
variable CNT: std_logic_vector(8 downto 0) := (others => '0');
begin
if (CLK = '1' and CLK'event) then
if (CNT(CNT'left) = '1') then
CNT := '0' & x"D3"; --N = 213 - 2
else
CNT := CNT - 1;
end if;
end if;
UART_EN_CLK <= CNT(CNT'left);
end process;
If you need some other clock frequency (for ex. LCD controller used 1 MHz
clk), you must create enable signal and use global clock (for ex. 25 MHz).
LCD_EN_CLK: 1 pulse per 25 clock of signal CLK.
process(CLK)
variable CNT: std_logic_vector(5 downto 0) := (others => '0');
begin
if (CLK = '1' and CLK'event) then
if (CNT(CNT'left) = '1') then
CNT := '0' & x"17"; --N = 25 - 2
else
CNT := CNT - 1;
end if;
end if;
LCD_EN_CLK <= CNT(CNT'left);
end process;
In architecture body of LCD_CTRL component you must write:
process(CLK)
...
begin
if (CLK = '1' and CLK'event) then
if (LCD_EN_CLK = '1') then
DO SOMETHING :)
...
end if;
end if;
end process;
In this way, it is possible to achieve lot of different source clocks in
FPGA architecture. This method is recommended and I think, that is correct
solution for achieving best performance (max clock frequency).
I apologize for my weak english.
Mirko.
Article: 113720On 2006-12-19, Martin Thompson <martin.j.thompson@trw.com> wrote: > "Sylvain Munaut <SomeOne@SomeDomain.com>" <246tnt@gmail.com> writes: > >> > --------------------------------------------------------------------------- >> > xdlanalyze.pl: >> > >> > >> > Shows statistics about an XDL file (or NCD file) as in the following >> > example: (I'm not aware of any Xilinx command that will print this kind >> > of (hierarchical) information about a place and routed design, please >> > enlighten me if I've missed something.) >> >> Interesting, I didn't find it either and write my own tool that does >> exactly >> the same thing, just a few weeks ago ;) >> > > Funnily enough - so did I! Must be the time of year for it :-) This makes me wonder about all the other tools that have been written in the dark without any outsider knowing about them :) /AndreasArticle: 113721
one last question... what should be the state of TRST in this case? tied to low or high thanks Antti wrote: > gomsi schrieb: > > > Antti.. so how to make it go into RTI... any suggestions > > Antti wrote: > > > gomsi schrieb: > > from TLR > > 1) TMS=0 > 2) apply 1 (one) TCK pulse > > state will be RTI > > AnttiArticle: 113722
On Post Map and Post Route model simulations intermittently I get few X bytes. I set up a trace check for source in ModelSim and found out that it leads to X_BUF with 658 ps pathpulse which connects to vitalbehavior (gsr, prld, dly of clk, set, rst etc). It's only bit 0 of the bus that goes to X at times. What do I do to get consistent timing? Best wishes.Article: 113723
On Post Map and Post Route model simulations intermittently I get few X bytes. I set up a trace check for source in ModelSim and found out that it leads to X_BUF with 658 ps pathpulse which connects to vitalbehavior (gsr, prld, dly of clk, set, rst etc). It's only bit 0 of the bus that goes to X at times. What do I do to get consistent timing? Best wishes.Article: 113724
"Gabor" <gabor@alacron.com> wrote in message news:1166554766.794947.316770@f1g2000cwa.googlegroups.com... > Ndf wrote: >> Hello all, >> >> I would like to multiply by 4 a USB chip 12MHz clock. The phase shift is >> not >> important. >> >> I cannot use LatticeXP PLL because minimum input clock frequency is >> 25MHz. >> >> There is a way to work around this problem? I would like to save space >> and >> money avoiding an external oscillator. >> >> Thanks, >> Dan. > > I see two possibilities: > > 1) Cheat a little bit (assume that 24 MHz works in most cases) and > double the clock input using LUT delays (and hope it's close enough > to 50% duty cycle for this to work). > > 2) Add an external PLL frequency multiplier chip. ICS has some small > (8-pin SOIC) cheap (cheaper than a crystal oscillator) parts that work > at this frequency. ICS570B comes to mind... Hi Dan, Gabor's blinkered ideas would work. However, they're not as much fun as accelerating the LatticeXP PLL to about 0.8773 of the speed of light. If you do that, the stationary oscillator appears to the PLL to be going at 25MHz. IME, this method involves messing around with enormous gravitational fields at event horizons, so watch out for evil red robots. HTH, Syms.
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