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Symon, I am not sure why that would not work, as even the dedicated pins have IBIS models, and the software knows about the dedicated pins, and thus should write out models for them as well. The CCLK pin is a dedicated pin, and it can be both an input, and an output, so it is a normal IO cell, just like all the others, except that its programming is not an option from the bitstream, but set by its function as the CCLK pin (either a LVCMOS input, or a LVCMOS output). So its capacitance will be the nominal 8pF or so in V4 of any IOB pin. Since we like to use identical cells, there would be no reason to go in hack off the unused bits just because it is a CCLK pin, and then require a different ESD protection scheme, and more testing later ... Austin Symon wrote: > "Austin Lesea" <austin@xilinx.com> wrote in message > news:embsp1$1kk1@cnn.xsj.xilinx.com... >> Symon, >> >> The ISE software will create a pin specific IBIS model for your design. >> >> Austin >> > Hi Austin, > Thanks, but I don't think that works for the CCLK pin on V4 which is used to > clock configuration data into the device. (CCLK can't be used as general I/O > AFAIK.) > Thanks, Symon. > >Article: 113751
"Austin Lesea" <austin@xilinx.com> wrote in message news:emc0i1$nn1@cnn.xsj.xilinx.com... > Symon, > > I am not sure why that would not work, as even the dedicated pins have > IBIS models, and the software knows about the dedicated pins, and thus > should write out models for them as well. > > The CCLK pin is a dedicated pin, and it can be both an input, and an > output, so it is a normal IO cell, just like all the others, except that > its programming is not an option from the bitstream, but set by its > function as the CCLK pin (either a LVCMOS input, or a LVCMOS output). > So its capacitance will be the nominal 8pF or so in V4 of any IOB pin. > > Since we like to use identical cells, there would be no reason to go in > hack off the unused bits just because it is a CCLK pin, and then require > a different ESD protection scheme, and more testing later ... > > Austin > OK, I understand, it all makes sense now! Thanks, Syms.Article: 113752
"Ben Jackson" <ben@ben.com> schrieb im Newsbeitrag news:slrneoj0qr.dou.ben@saturn.home.ben.com... > On 2006-12-20, Antti <Antti.Lukats@xilant.com> wrote: >> >> I wonder - if there are so many issues with DDR on the 3E starterkit >> how reliable will be the DDR2 memory on the new Spartan-3A kit? > > DDR2 is simpler than DDR. > > -- > Ben Jackson AD7GD > <ben@ben.com> > http://www.ben.com/ NO WAY I have plenty of boards with DDR memories on them, and all they work and I dont recall having problems DDR memory controllers and with all DDR2 boards I see trouble... xilinx recommends speed grade -12 for Virtex-4 DDR2 200mhz solution. getting DDR2 working with spartan-3, well doable I guess, but I would be glad to see my problems with Virtex-4 based board solved first before I belive Spartan-3 DDR2 solution is easy e.g simpler as DDR maybe its only with Xilinx DDR2 solutions so, cant say as I dont have any lattice or altera DDR2 boards AnttiArticle: 113753
"Antti Lukats" <antti@openchip.org> wrote:
>PicoBlaze C compiler has been available for some time already,
>but until yesterday I never tried it.
>But today when I type:
>
>>start build.bat
>
>then the following C file
>
>----- cut -----
>// This is first PCCOMP Program tested on MicroFpga!
>// Target was S3-200 with KCPSM3_256S MF-Core
>
>#include "..\inc\padmap.h"
>#include "..\inc\board.h"
>#include "..\lib\pinapi.h"
>
>unsigned int i;
>
>// Delay
>void ledelay() { for (i=0;i<65000;i++) {} }
>
>void main()
>{
> // blink a LED forever !
> while (1) {
> SetPin(LED1, 0); ledelay();
> SetPin(LED1, 1); ledelay();
> }
>}
What I'm really interested in is whether the assembly code generated
by the compiler is well optimized or not. Can you post the generated
assembly code?
--
Reply to nico@nctdevpuntnl (punt=.)
Bedrijven en winkels vindt U op www.adresboekje.nl
Article: 113754Nico Coesel schrieb: > "Antti Lukats" <antti@openchip.org> wrote: > > >PicoBlaze C compiler has been available for some time already, > >but until yesterday I never tried it. > >But today when I type: > > > What I'm really interested in is whether the assembly code generated > by the compiler is well optimized or not. Can you post the generated > assembly code? > no. the PicoBlaze C compiler is not very optimizing. so dont expect miracles. but still it was fun to see that it is useable and produces working code. if you want to test out you can download the PCCOMP from the authors site or download the MicroFpga demo package where it is included, the script there deletes all interim files, so just uncomment the call kcspm3_clean.bat and you will have the assembly file left in place i have written one REALLY optimizing risc compiler once, it was pretty hard task as I wanted the compiler to take advantage of all the resources the best way actually i have partially ported that compiler to produce picoblaze code, but that isnt finished, maybe/hopefully i have time to revise my compiler, but no promises right now AnttiArticle: 113755
Hello, I am starting with fpga and I have some questions, My first question is do I need a clock input? I want to build the xilinx cpld. I found a tutorial on the web where a clock can be generate like this: always begin #5 clk = ~clk; end Will this really work? what will be the frequency? Where do I find the schematic diagram of the xilinx xc9536 which indicate power/gnd, io pins, and jtag pins? Karren.Article: 113756
I have created a Xilinx Project using EDK8.2 on the Virtex2 development board . In my project I use an ethernet MACLite peripheral. I have properly assigned the NETS as per the board manual and modified entries in the ucf file accordingly. But when I try to update the bitstream I get a message saying that ALL the nodes that I had listed out in the System Assembly View ( connecting the MAC to the PHY ) do not exist. I am getting an error on all the constraints in which I map these MAC to PHY signals onto port pins Anyone else faced this problem before thanks venuArticle: 113757
Hi, > My first question is do I need a clock input? Unless you have purely combinational logic, yes. > I want to build the xilinx cpld. I found a tutorial > on the web where a clock can be generate like > this: > > always > begin > #5 clk = ~clk; > end > > Will this really work? Only in simulation. On a real board you will need a clock module. > what will be the frequency? Depends on the `timescale directive. > Where do I find the schematic diagram of the > xilinx xc9536 which indicate power/gnd, io > pins, and jtag pins? http://www.xilinx.com Cheers, JonArticle: 113758
Antti Lukats wrote: > > NO WAY > > I have plenty of boards with DDR memories on them, and all they work > and I dont recall having problems DDR memory controllers > > and with all DDR2 boards I see trouble... > > xilinx recommends speed grade -12 for Virtex-4 DDR2 200mhz solution. > getting DDR2 working with spartan-3, well doable I guess, but I would > be glad to see my problems with Virtex-4 based board solved first before > I belive Spartan-3 DDR2 solution is easy e.g simpler as DDR > > maybe its only with Xilinx DDR2 solutions so, cant say as I dont > have any lattice or altera DDR2 boards > > Antti > > Antti, I've got 4 banks of QDR-2 RAM working reliably at a 200 MHz clock rate with a Virtex4SX55-10 on a custom board. The interface uses the idelays and training. We had no problems bringing it up. The interface is not the Xilinx DDR IP discussed in the app notes though. The board design has to be done carefully in regards to signal integrity.Article: 113759
Ray Andraka schrieb: > Antti Lukats wrote: > > > > > Antti, I've got 4 banks of QDR-2 RAM working reliably at a 200 MHz clock > rate with a Virtex4SX55-10 on a custom board. The interface uses the > idelays and training. We had no problems bringing it up. The interface > is not the Xilinx DDR IP discussed in the app notes though. The board > design has to be done carefully in regards to signal integrity. sure, I get DDR2 200mhz also working (V4 speed -10), but occasionally there are board related issues and there are also fpga timing issues with -10 speed grade. if the idelay-+training works OK, and the board is really carefully designed then there are no real issues with DDR2, but so far when working with not so carefully designed boards and Xilinx IP cores * OPB_MCH_DDR2 * PLB_DDR * MPMC2 * MIG then there are defenetly issues getting things working at 200mhz (or meet fpga timings) BTW, I do not have seen issues related to idelay, eg reading is ok but mostly errors are of type that 8 bits are not written, eg like one DQS is gone lost or something, from x16 device 8 bits are written and 8 bits hold old value, and readback is same many time, eg write succeeded but only to one half of the chip. this is with MPMC2 design that is on the board to meet the timing, and worst delay is in one DQS path so I am not sure if the problem is fpga timings or pcb layout AnttiArticle: 113760
Antti wrote: > Ray Andraka schrieb: > >>Antti Lukats wrote: >> >> >>Antti, I've got 4 banks of QDR-2 RAM working reliably at a 200 MHz clock >>rate with a Virtex4SX55-10 on a custom board. The interface uses the >>idelays and training. We had no problems bringing it up. The interface >>is not the Xilinx DDR IP discussed in the app notes though. The board >>design has to be done carefully in regards to signal integrity. > > > sure, I get DDR2 200mhz also working (V4 speed -10), but occasionally > there are board related issues and there are also fpga timing issues > with -10 speed grade. > > if the idelay-+training works OK, and the board is really carefully > designed then there are no real issues with DDR2, but so far when > working with not so carefully designed boards and Xilinx IP cores > * OPB_MCH_DDR2 > * PLB_DDR > * MPMC2 > * MIG > then there are defenetly issues getting things working at 200mhz (or > meet fpga timings) > > BTW, I do not have seen issues related to idelay, eg reading is ok but > mostly errors are of type that 8 bits are not written, eg like one DQS > is gone lost or something, from x16 device 8 bits are written and 8 > bits hold old value, and readback is same many time, eg write succeeded > but only to one half of the chip. this is with MPMC2 design that is on > the board to meet the timing, and worst delay is in one DQS path so I > am not sure if the problem is fpga timings or pcb layout > > Antti > Well, first off the signals *must* be registered at the IOB or all bets are off. You need pretty consistent timing across all the IOBs, AND the pcb traces need to be matched for delay. The timing across the IOBs is pretty easy to get consistent if you register the IOBs (I know you already know that). Check the spec for the memory to see if the DQS edges need to be aligned with the write data edges or aligned with the data centers. I can never remember which it is, but somewhere along the line you wind up using a 90 degree clock to make the timing all work out. I'm not sure the Xilinx IP has that right or not. If your worst case delay on the board is one one of the DQS paths, it is possible the DQS is arriving too late to properly validate the write data.Article: 113761
Ray Andraka schrieb: > Antti wrote: > > > Ray Andraka schrieb: > > > >>Antti Lukats wrote: > >> > Well, first off the signals *must* be registered at the IOB or all bets > are off. You need pretty consistent timing across all the IOBs, AND the > pcb traces need to be matched for delay. The timing across the IOBs is > pretty easy to get consistent if you register the IOBs (I know you > already know that). Check the spec for the memory to see if the DQS > edges need to be aligned with the write data edges or aligned with the > data centers. I can never remember which it is, but somewhere along the > line you wind up using a 90 degree clock to make the timing all work > out. I'm not sure the Xilinx IP has that right or not. If your worst > case delay on the board is one one of the DQS paths, it is possible the > DQS is arriving too late to properly validate the write data. signal *ARE* registered in IOBs, the worst case delay is in one of the DQS paths between 200MHz and 200MHz_90_degree clocks timing analyzer says 0 LUT levels and still doesnt meet the timing! but the thing is not properly validatin the data, I mean threre is not the case that wrong data gets written, there is no write at all! it is temperature dependant, after power up less errors, within few minutes more the error is that 8 bits do not get written, eg they hold old data like write never happened, while the other 8 bits in the same chip work all the time. its also not DM related i have checked that the same board works at lower DDR2 clock what is a small puzzle is the fact that xilinx does not use DIFFerential I/O primitives for the DDR2 core (not at least in MPMC2) but that sould also possible cause only reading errors if the single ended DQS calibrate is not perfect and I have no read errors AnttiArticle: 113762
"Jon Beniston" <jon@beniston.com> wrote in message news:1166646176.713858.99070@a3g2000cwd.googlegroups.com... > Hi, > > > My first question is do I need a clock input? > > Unless you have purely combinational logic, yes. > > > I want to build the xilinx cpld. I found a tutorial > > on the web where a clock can be generate like > > this: > > > > always > > begin > > #5 clk = ~clk; > > end > > > > Will this really work? > > Only in simulation. On a real board you will need a clock module. > > > what will be the frequency? > > Depends on the `timescale directive. > > > Where do I find the schematic diagram of the > > xilinx xc9536 which indicate power/gnd, io > > pins, and jtag pins? > > http://www.xilinx.com > Hi Jon, thanks for your reply, I had a look in xilinx.com but could not find which datasheet carrys the schematic of the package, I know it's a PLCC configuration, but need to know which pins are which if you know what I mean. Any suggestions? > Cheers, > Jon >Article: 113763
Hi, I am unable to come across any material that critically examines the reasons I must go in for Microblaze or Powerpc. Is processor obsolesence the only reason why an FPGA designer would go in for Microblaze? Could the present PowerPC architecture could become obsolete? Regards, SandyArticle: 113764
Antti wrote: > Ray Andraka schrieb: > >>Antti wrote: >> >> >>>Ray Andraka schrieb: >>> >>> >>>>Antti Lukats wrote: >>>> >> >>Well, first off the signals *must* be registered at the IOB or all bets >>are off. You need pretty consistent timing across all the IOBs, AND the >>pcb traces need to be matched for delay. The timing across the IOBs is >>pretty easy to get consistent if you register the IOBs (I know you >>already know that). Check the spec for the memory to see if the DQS >>edges need to be aligned with the write data edges or aligned with the >>data centers. I can never remember which it is, but somewhere along the >>line you wind up using a 90 degree clock to make the timing all work >>out. I'm not sure the Xilinx IP has that right or not. If your worst >>case delay on the board is one one of the DQS paths, it is possible the >>DQS is arriving too late to properly validate the write data. > > > signal *ARE* registered in IOBs, the worst case delay is in one of the > DQS paths between > 200MHz and 200MHz_90_degree clocks timing analyzer says 0 LUT levels > and still doesnt meet the timing! > > but the thing is not properly validatin the data, I mean threre is not > the case that wrong data gets written, there is no write at all! > > it is temperature dependant, after power up less errors, within few > minutes more the error is that 8 bits do not get written, eg they hold > old data like write never happened, while the other 8 bits in the same > chip work all the time. its also not DM related i have checked that the > same board works at lower DDR2 clock > > what is a small puzzle is the fact that xilinx does not use > DIFFerential I/O primitives for the DDR2 core (not at least in MPMC2) > but that sould also possible cause only reading errors if the single > ended DQS calibrate is not perfect and I have no read errors > > Antti > Antti, check the relationship between DQS and the address and bank selects. sounds like the address/BS lines may not be meeting the setup or hold to DQS so the write is going somewhere else or getting blocked. As I recall, the xilinx reference design had the address out clocked by the wrong clock (270 degree vs 0 degree). You might have to hand place the FF's going from 0 to 90 degree, or possibly duplicate registers if you have the crossing going to more than one destination. All of the current parts are capable of a 1.25ns connect between ff's, BUT, you have to have fanout of 1 and good placement to make it work out in the slower parts.Article: 113765
David wrote: > Does anyone know if it is possible to define the values in a lookup > table using VHDL compatible with Xilinx tools? If so, does anyone have > an example? > > Thanks, > > David > I'm not sure which you are asking for: A generic look-up containing your data coded as RTL, or instantiating a LUT-4 primitive with your init data. For the former: type int_array is array(natural range <>) of integer; constant lut_data: int_array(0 to 15):= (0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0); signal lut_addr: unsigned(3 downto 0); signal lut_out: unsigned(7 downto 0); attribute syn_keep of lut_out: signal is true; begin LUT_out <= to_unsigned(lut_data(to_integer(lut_addr))); will infer a LUT with a 4 bit address and an 8 bit output containing the data specified by the constant lut_data. This of course can also be an array of std_logic_vectors or whatever. The syn_keep will force it into a LUT-4 when it is synthesized (you may need also to put syn_keeps on the address in order to keep it from absorbing any combinatorial logic on the address lines).Article: 113766
hattangady@gmail.com wrote: > Hi, > > I am unable to come across any material that critically examines the > reasons I must go in for Microblaze or Powerpc. Is processor > obsolesence the only reason why an FPGA designer would go in for > Microblaze? No. To be honest, that's probably the last reason. > Could the present PowerPC architecture could become > obsolete? More chance of MicroBlaze becoming obsolete first to be honest. If you can't think of a reason why you must choose one over the other, then it probably doesn't matter. Cheers, JonArticle: 113767
bg wrote: > I need a CIC-Filter, where I can change the decimation factor during > runtime.So I inserted a BlackBox-Block in the SystemGenerator Model > with the vdh and edn-file from Core-Generator. It works , but the > output has a bitwidth of e.g. UFIX_43_0 and I have to convert this to > Fix_16_15. I use the Force-Block to force the signed format, but now > here is the problem: > Where is the binary point? It's always like guessing. There are some > formulas of bitgrowth, but I dont get helpful results. I know it works > because for some factors I found the correct conversion, but there is > no link. Thanks for answering! > A decimating CIC has a DC gain of (N*R)^M where N is the number of clocks delay in the comb section, R is the decimation ratio (i.e. decimate by R), and M is the order of the filter (i.e. the number of cascaded stages). When you change the decimation ratio, the gain changes, and for a typical filter with M=4 or 5, the change can be substantial even for small changes in R. The placement of the binary point depends on where it is on the input. Assuming you aren't truncating any bits internally, then the input and output have the same number of bits to the right of the radix point before compensating for the gain. Note the gain is not constrained to a power of 2, so just shifting the output (by truncating lsbs) is not enough to entirely correct for the filter gain. You'll need a multiplier to fully compensate the gain. The efficient way to do this is to put a barrel shift between the integrator and comb sections to take care of the coarse gain (to the largest power of two less than the CIC gain), and then use a multiplier and look-up addressed by the decimation ratio to accomplish the fine gain adjustment. The fine gain can be done either after the barrel shift or on the filter output.Article: 113768
"Antti" <Antti.Lukats@xilant.com> wrote: >Nico Coesel schrieb: > >> "Antti Lukats" <antti@openchip.org> wrote: >> >> >PicoBlaze C compiler has been available for some time already, >> >but until yesterday I never tried it. >> >But today when I type: >> > >> What I'm really interested in is whether the assembly code generated >> by the compiler is well optimized or not. Can you post the generated >> assembly code? >> > >no. >the PicoBlaze C compiler is not very optimizing. so dont expect >miracles. but still it was fun to see that it is useable and produces >working code. if you want to test out you can download the PCCOMP from >the authors site or download the MicroFpga demo package where it is >included, the script there deletes all interim files, so just uncomment Antti, Just a comment: I've looked around your website a bit, but I can't really figure out what MicroFpga (which is your product?) is intended to do and how it may help me. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 113769
Jon, It is true that some soft processors have become obsolete (Nios is now Nois II). So you have reason to doubt that another one would be successful. However, both MicroBlaze and PicoBlaze are doing very well, azs measured by the thousands of downloads. Each download may be just one person "kicking the tires" or it may be one download that gets placed in tens of thousands of boards, we have no way to know. We have decided that whatever we support, Power PC, MicroBlaze, or PicoBlaze, it can not change such that old code doesn't work! That is the death of any processor. Rather, all old machines may evolve, but they must evolve in a way that allows old code to move with the changes (similar to Intel and the x86). A processor needs to exist, it needs an eco-system (compilers, linkers, loaders, debuggers, etc), it needs to meet the needs (speed, power, cost), and it needs to last the intended length of the company that wishes to use it (it is a printer every 6 months? or a new network switch every three years? or a new spacecraft once a decade?). Many questions. Look up the answers, AustinArticle: 113770
Hi Karen, Following on from the previous post - the verilog code you've written will only work during simulation. The reason being is that CPLD's have no real way of determining time periods i.e. your code details a time peiod of 5, at least without some oscillator module such as IQXO-36C-16.384MHz from C-MAC connected to one of the GCLK pins. As stated in the previous post you can find the pin out of the device from the Xilinx website, but I've got the link for the device you've mentioned; http://direct.xilinx.com/bvdocs/publications/ds064.pdf The link will open a pdf and on sheet 6 the power and clock pins are detailed depending upon the package you're after. Hope this helps Chris Karen Halgren wrote: > Hello, > I am starting with fpga and I have some questions, > > My first question is do I need a clock input? > I want to build the xilinx cpld. I found a tutorial > on the web where a clock can be generate like > this: > > always > begin > #5 clk = ~clk; > end > > Will this really work? what will be the frequency? > > Where do I find the schematic diagram of the > xilinx xc9536 which indicate power/gnd, io > pins, and jtag pins? > > Karren.Article: 113771
Hi all,
I have the following question, this is my program,
`timescale 1ns / 1ps
module oscdiv10(in,out);
input in;
output out;
reg out;
reg [3:0] cnt;
always @ (in)
begin
cnt=cnt+1;
if (cnt ==9)
begin
cnt = 0;
out = !out;
end
end
endmodule
I have checked this program on the xilinx ISE and it seems
to synthesise. Can someone explain what is the .timescale
directive and where I can find its help screen (I tried the
help from the ISE, but this simply opens my browser somewhere
on the xilinx website, and there is no help for it there.
Secondly, since I am using blocking assignments, what does it
actually mean, will I have propagation delay issues or what?
Thirdly, can someone write a short test bench to simulate this
on the ISE (shouldn't be too difficult with just one input and
one output) and lastly, can someone explain how I can implement
this program with a schematic instead of hdl, my problem is what
logic devices correspons to 'always' and also to 'if/else'?
thanks.
Article: 113772What you need is a good beginners book on Digital Logic Design and another one on Verilog How will you ever learn if you don't at least try and figure out the answers to your questions yourself? <223> wrote in message news:4589e808$1_2@mk-nntp-2.news.uk.tiscali.com... > Hi all, > I have the following question, this is my program, > > `timescale 1ns / 1ps > module oscdiv10(in,out); > input in; > output out; > reg out; > reg [3:0] cnt; > always @ (in) > begin > cnt=cnt+1; > if (cnt ==9) > begin > cnt = 0; > out = !out; > end > end > endmodule > > I have checked this program on the xilinx ISE and it seems > to synthesise. Can someone explain what is the .timescale > directive and where I can find its help screen (I tried the > help from the ISE, but this simply opens my browser somewhere > on the xilinx website, and there is no help for it there. > Secondly, since I am using blocking assignments, what does it > actually mean, will I have propagation delay issues or what? > Thirdly, can someone write a short test bench to simulate this > on the ISE (shouldn't be too difficult with just one input and > one output) and lastly, can someone explain how I can implement > this program with a schematic instead of hdl, my problem is what > logic devices correspons to 'always' and also to 'if/else'? > thanks. > >Article: 113773
Jon Beniston wrote: > hattangady@gmail.com wrote: > >> I am unable to come across any material that critically examines the >>reasons I must go in for Microblaze or Powerpc. Is processor >>obsolesence the only reason why an FPGA designer would go in for >>Microblaze? > > No. To be honest, that's probably the last reason. I agree - unless you are in a super long-lifetime industry, obsolescence is probably a long way down the list. > If you can't think of a reason why you must choose one over the other, > then it probably doesn't matter. I think it's the old favourites price and performance/features. If you really need a PPC (or MGTs, or lots of DCMs, or...), then you have to be prepared to pay for it. Things may change with V5, but the price disparity of a V4FX vs an S3/S3E is enormous. If you can do the job with a MicroBlaze in a Spartan3/3E you'll save a fortune. You can clock the PPCs faster, so in terms of raw benchmarking MIPs lies^H^H^H numbers it will always look superior. But, remember there's an entire FPGA sitting next to it - the performance critical stuff should be in hardware anyway! Earlier this year I did some back of the envelope estimates of replacing a mass-produced PPC single board computer with a V4FX-based solution. In the 1K-10K qty we could buy the entire SBC with memory and interfaces for about the same price as just the V4FX25 device on its own. The need for FPGA fabric wasn't really there, so we didn't proceed. JohnArticle: 113774
Antti wrote: > what is a small puzzle is the fact that xilinx does not use > DIFFerential I/O primitives for the DDR2 core (not at least in MPMC2) > but that sould also possible cause only reading errors if the single > ended DQS calibrate is not perfect and I have no read errors I had to use the differential DQS signalling to get DDR2 going on a V4FX100 board with 512mbit Micron DDR2. Without them I saw issues like you describe - 8 bits of a word failing here and there. I don't remember if it was write failures or read failures. Note there's a typo in the mch_opb_ddr2 MPD file (EDK8.2 all service packs) that makes it impossible for BSB-created platforms to connect the DQSn signals correctly. Plus, BSB's DDR clocking structures leave a lot to be desired - you always need to rework them. Cheers, John
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