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Authors (M)
M:
12855: 98/11/02: Q: fifo flags
13164: 98/11/18: Re: Q: fifo flags
35292: 01/09/27: Fastest way to become a Verilog samurai?
m:
31725: 01/06/04: Re: EPC2: no output signals
123028: 07/08/14: Delaying a pulse train
123030: 07/08/14: Re: Delaying a pulse train
123037: 07/08/14: Re: Delaying a pulse train
123044: 07/08/15: Re: Delaying a pulse train
123119: 07/08/16: Re: Delaying a pulse train
123132: 07/08/16: Re: Delaying a pulse train
125995: 07/11/11: Programming connection
125996: 07/11/11: Re: Programming connection
126008: 07/11/12: Re: Programming connection
126025: 07/11/12: Re: Programming connection
128969: 08/02/11: Re: Virtex5 DCM lower limit
129672: 08/03/02: Re: Software for FPGA-based PC scope
134502: 08/08/14: Re: EBAY: XC2V1000-5FG456C
134503: 08/08/14: Re: EBAY: XC2V1000-5FG456C
135086: 08/09/15: Moving to Altera from Xilinx
135211: 08/09/20: Altera and DDR3
135256: 08/09/23: Re: Altera and DDR3
135829: 08/10/16: Linux on Microblaze
137530: 09/01/21: DVI, HDMI, DisplayPort
137744: 09/01/28: Microblaze and NAND flash
M E:
110565: 06/10/17: 8B/10B vs. Start/Stop for SERDES
117456: 07/03/31: ISE on Fedora?
117758: 07/04/09: Re: ISE on Fedora?
M & J:
17926: 99/09/17: Re: PCI core for Orca 3T
m burgess:
6325: 97/05/15: Job vacancies for ASIC/VHDL/FPGA Engineers
6326: 97/05/15: Job vacancies for ASIC/VHDL/FPGA Engineers
M Burgess:
864: 95/03/16: Specialist Vacancies
M H:
11685: 98/08/31: Re: CPLD/FPGA software
M Ihsan Baig:
114943: 07/01/27: Higher studies
117934: 07/04/13: SoC
119383: 07/05/17: video soltion provider
119430: 07/05/18: Re: video soltion provider
122841: 07/08/08: Ph.D in France
M Kartheepan:
12231: 98/10/06: Re: FIR Filter Design
12253: 98/10/07: Re: FIR Filter Design
m m:
134648: 08/08/23: Digital-to-Analog Converter LTC 2624, Spartan-3A
134699: 08/08/26: Re: Digital-to-Analog Converter LTC 2624, Spartan-3A
134845: 08/09/03: LED lights flashing while LCD shows chars, Spartan-3A
134966: 08/09/08: Re: Digital-to-Analog Converter LTC 2624, Spartan-3A
135135: 08/09/17: Two-complement value from ADC, Spartan-3A, 3E
135314: 08/09/25: Re: LED lights flashing while LCD shows chars, Spartan-3A
135720: 08/10/13: Testing Analog-to-Digital Converter, Spartan-3A, LTC1407-A
M Murphy:
17657: 99/08/19: Digital Design Engineer needed - Please read
17905: 99/09/16: Chip Level Ciruit Designers needed, please read
M Pedley:
34247: 01/08/17: Atmel CPLD - JEDEC to ABEL
34279: 01/08/18: Re: Atmel CPLD - JEDEC to ABEL
34872: 01/09/12: Programming Delays in ABEL
34878: 01/09/12: Re: Programming Delays in ABEL
34879: 01/09/12: Re: Xilinx Foundation Base(DS-ISE-XB2). Exactly what do you get?
48647: 02/10/22: High Performance FPGA's - Xilinx and ??????
48713: 02/10/23: Re: High Performance FPGA's - Xilinx and ??????
49427: 02/11/12: Re: The "Do"s and "Don't"s of Synthesizing VHDL?
M R Wheeler:
10504: 98/05/25: Altera MaxPlus using third party programmer
21721: 00/03/30: MaxPlus9.5 License and Fitter problems
21765: 00/03/31: Re: MaxPlus9.5 License and Fitter problems
22330: 00/05/05: MaxPlus9.5/6 License problems
M Schreiber:
40318: 02/03/05: exceeding 2GB limits in xilinx
42393: 02/04/22: Using LogiBlox in Virtex2
45008: 02/07/09: Bi-Directional Bus problem in Xilinx FPGA
45048: 02/07/10: Re: Bi-Directional Bus problem in Xilinx FPGA
48796: 02/10/24: Pin locking Virtex 2 FPGA
49563: 02/11/15: Re: Registering inputs or outputs of modules
51581: 03/01/16: FPGA Express FSM state ordering
52074: 03/01/30: Re: Floor Planning DCM
M Shehzad Hanif:
71311: 04/07/14: Xilinx Virtex-II Configuration in Slave Serial
M Smith:
34337: 01/08/21: Help the clueless guy....
M Sweger:
6927: 97/07/09: Re: Generating Sine/Cosine digitally
15437: 99/03/24: Re: Reconfigurable computing thesis on the web
M Wirtzfeld:
30505: 01/04/11: Introductory Question - LSB to MSB Conversion.
<m-gupta@nwu.edu>:
14687: 99/02/11: Mentor-Alliance Interface
m.:
57055: 03/06/22: vga controller
M. Aberbour:
9054: 98/02/17: System Gates and Logic Cells...
M. Bodnar:
71471: 04/07/19: Boards Comparable to Alpha-Data's ADM-XRC-II
M. Boin:
10733: 98/06/14: Metrology Software- Survey
M. Hamed:
117503: 07/04/02: X_OBUF and other error messages with ModelSim
117549: 07/04/03: Re: X_OBUF and other error messages with ModelSim
117744: 07/04/09: Modelsim Low and High violations
117861: 07/04/11: Timing violations though constraints have been met
117887: 07/04/12: Re: Timing violations though constraints have been met
117891: 07/04/12: SETUP & HOLD time confusion
117944: 07/04/13: Re: SETUP & HOLD time confusion
118117: 07/04/17: Block RAM strange behavior, address off by one
118145: 07/04/18: Re: Block RAM strange behavior, address off by one
118151: 07/04/18: Re: Block RAM strange behavior, address off by one
118163: 07/04/18: Re: Block RAM strange behavior, address off by one
118169: 07/04/18: Re: Block RAM strange behavior, address off by one
118192: 07/04/19: Re: Compiling a library
118393: 07/04/25: Modelsim simulation progress in batch/command line mode?
118400: 07/04/25: Timing constraints with asynchronous clocks
118438: 07/04/26: Re: Modelsim simulation progress in batch/command line mode?
118442: 07/04/26: Re: Timing constraints with asynchronous clocks
118493: 07/04/27: Placement error for adjacent pins
118512: 07/04/28: Re: Placement error for adjacent pins
128650: 08/02/01: Keeping Xilinx tool from Optimizing out Debugging signals
128655: 08/02/01: Re: Keeping Xilinx tool from Optimizing out Debugging signals
129012: 08/02/12: Re: Timing Constraint not met
130098: 08/03/14: Detecting a pulse with minimum width
130105: 08/03/14: Re: Detecting a pulse with minimum width
138513: 09/02/25: Converting state machine encoding to std_logic_vector
M. Movahedin:
712: 95/02/14: Synopsys FPGA Compiler
717: 95/02/16: Re: Synopsys FPGA Compiler
2265: 95/11/15: Re: Looking for large circuit
3769: 96/07/29: A Survey on Design Errors
3806: 96/08/05: A Survey on Design Errors, Now by E-mail
4144: 96/09/18: A Survey on Design Errors
M. Norton:
146549: 10/03/22: Re: Why hardware designers should switch to Eclipse
146595: 10/03/23: Re: Why hardware designers should switch to Eclipse
M. Praekelt:
35636: 01/10/12: Lattice discontinues all smaller MACH circuits and other devices
M. Randelzhofer:
44731: 02/06/28: Re: blank CPLD
44750: 02/06/29: Re: blank CPLD
44795: 02/07/01: Re: blank CPLD
45624: 02/07/29: Re: xilinx ISE 4.2, xst, cpld 95144xl, tristate
45699: 02/08/01: Re: xilinx ISE 4.2, xst, cpld 95144xl, tristate
45999: 02/08/13: Re: Xilinx XST inferred Block-RAM Initialization
50177: 02/12/04: Re: Low Speed Serial Bus Suggestions
M. Sachemo:
37985: 01/12/28: instruction processor
M. Sherman:
6391: 97/05/21: Engineering Opportunity - http://www.digjobs.com
M. Simon:
26413: 00/10/15: Re: palasm
26414: 00/10/15: Re: FPGA PCB design examples
28123: 00/12/21: Re: FPGA and Board for Microprocessor Design?
28251: 01/01/03: Re: Boston/Senior Software engineer FPGA/ Well Funded Start up/100k+++/Hot Data Storage Market
29809: 01/03/12: Re: Configuration devices
M. Spicker:
6918: 97/07/09: Re: Generating Sine/Cosine digitally
M.+M. Monhart:
25094: 00/08/25: experiences with USB core vendors
<m.adithya@gmail.com>:
98177: 06/03/06: Asynchronous FIFO design question
98182: 06/03/06: Re: Asynchronous FIFO design question
<m.afgani@gmail.com>:
115770: 07/02/20: Xilinx ML402 Virtex-4 Eval kit - I2C Bus
M.B.:
26495: 00/10/18: Re: Announce: Free HC11 CPU Core
30846: 01/05/01: ccd imaging with fpga
30918: 01/05/03: Re: ccd imaging with fpga
32665: 01/07/04: FPGA projects
38309: 02/01/11: Re: FPGA and CCD : any experience?
<m.beard@vertex-solutions.co.uk>:
20359: 00/02/07: ASIC Opportunities
<m.bodenbach@ifen.com>:
86939: 05/07/10: Re: Running prog from PROM
m.khairy:
147644: 10/05/11: ModelSim XE III error
M.Kmann:
95240: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95243: 06/01/21: Re: OT:Shooting Ourselves in the Foot
M.Randelzhofer:
54611: 03/04/15: Re: Xilinx has released SpartanIII
55717: 03/05/17: Re: smallest embedded cpu.
56595: 03/06/10: Re: XC95288 programming problem
56729: 03/06/12: Analog signals connected to xilinx spartan2
56734: 03/06/13: Re: Analog signals connected to xilinx spartan2
57282: 03/06/26: Re: Low-power FPGA
57503: 03/07/01: Re: Cyclone vs Spartan-3
58791: 03/08/01: Re: 5 volt tolerant Xilinx parts
71358: 04/07/15: Re: MUXCY-based multiplexers
71826: 04/08/01: SPARTANII pinout table mysteries ???
71871: 04/08/03: SPARTAN-3 VCCAUX supply current
71897: 04/08/03: Re: SPARTAN-3 VCCAUX supply current
71898: 04/08/03: Re: SPARTAN-3 VCCAUX supply current
72223: 04/08/11: new XILINX 9500XL datasheets
74667: 04/10/16: Re: which xilinx CPLD to select?
77514: 05/01/08: WebPack download problem
79552: 05/02/21: WYSIWYG option in xilinx webpack 6.3
79587: 05/02/21: Re: WYSIWYG option in xilinx webpack 6.3
80495: 05/03/07: Re: Cheap alternatives to Mach 210s
84848: 05/05/30: Xilinx CPLD fitter trouble, OK in Foundation4.1, bad in 6.3,7.1
90384: 05/10/11: Re: Question regarding FPGA startup ROMs
90874: 05/10/24: Re: Implementing five stage pipeline
91554: 05/11/08: Re: Need some help with interfacing spartan III to a computer...
91555: 05/11/08: Re: Suggestions/Recommendations with CPLD's and Software
92260: 05/11/25: Re: XC2000
93306: 05/12/19: Re: Mixing XC9500 and XC9500XL, also small qty suppliers
93309: 05/12/20: Re: Mixing XC9500 and XC9500XL, also small qty suppliers
98355: 06/03/08: Re: 5v Xilinx development board
98630: 06/03/13: Re: PROBLEMS WITH COOLRUNNER XPLA3
104569: 06/06/30: Re: How to evaluate the space efficiency of a historic design.
108789: 06/09/16: Re: XPLA3 going obsolete?
109334: 06/09/24: Re: Spartan 3 or 3E ?
129715: 08/03/03: Re: my Spartan-4 wishlist
132392: 08/05/25: New Xilinx device package options for S3E & S3A
132819: 08/06/07: Re: 1 Pin MTE Cable
133905: 08/07/18: Re: Which FPGA has most ram in a TQFP144 or smaller non-BGA?
133909: 08/07/19: Re: Which FPGA has most ram in a TQFP144 or smaller non-BGA?
133998: 08/07/21: Re: audio serial port i2s
135034: 08/09/11: Re: Spartan-II, config pins 5V tolerant? (slave serial)
135041: 08/09/12: Re: Spartan-II, config pins 5V tolerant? (slave serial)
135826: 08/10/17: Re: A couple of CPLD design challenges for the group
137407: 09/01/14: Re: ttl compatible
138624: 09/03/02: Re: Antti-Brain issue 6 released
142455: 09/08/12: Re: Spartan-6 Boards - Your Wish List
145243: 10/02/03: Re: What MAXIM chip is used on Spartan 3E 1600E Microblaze Board for RS232 communication?
148399: 10/07/18: Xilinx License BS
M.S.Gaur:
30643: 01/04/20: XSV boards memory addressing
30613: 01/04/19: Looking for digital video to VGA RGB conversion
M.Simon:
14060: 99/01/11: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
15211: 99/03/13: Re: Infidels Invited, Heathens Highly Welcome !
15550: 99/03/30: Re: IP cores and software industry
15646: 99/04/06: Re: newbie: FPGA suggestion
15725: 99/04/10: Re: FPGA testing board
15742: 99/04/11: Re: FPGA vs CPLD? Any Experts out there?
15888: 99/04/19: Re: Forth Processor
16110: 99/05/04: Re: Anyone use 27256 for config?
17680: 99/08/23: Re: microcontroller vs FPGA
M.Sivanandan:
28770: 01/01/23: fpga: regarding startup virtex
M.Stekelenburg:
11140: 98/07/21: Re: How to write a VHDL counter of up & down
<M.Vasilko@computer.org>:
11136: 98/07/21: ANNOUNCE: Dynamically Reconfigurable Hardware WWW Library
16250: 99/05/12: Re: High speed reconfigurability
17509: 99/08/03: Re: Partial Reconfiguration?
M.Z.:
140261: 09/05/06: Re: Setting top level VHDL generics in XST
m0:
41479: 02/03/29: Re: Homebuilt Altera-programmer totally dead...
42969: 02/05/08: Re: "free" tools ... ?
43011: 02/05/09: Re: VirtexII : Reserving IO Pins as inputs
43012: 02/05/09: Re: VirtexII : Reserving IO Pins as inputs
43355: 02/05/20: Re: Anyody else get spam about "FPGA Video Seminar"?
43373: 02/05/20: Re: Architecture for high-level reconfigurable computing
43579: 02/05/24: Re: FPGA, VHDL : RAM initialization
43890: 02/06/05: Re: VIRTEX-E XCV405E Orcad schematic required
M6:
89603: 05/09/20: picoblaze IDE for Linux
89696: 05/09/22: Re: picoblaze IDE for Linux
89706: 05/09/22: Re: picoblaze IDE for Linux
<m>:
53341: 03/03/11: Re: Are there any FPGA magazines/journals?
53345: 03/03/11: Can you recommend a text on...?
m_l_g3:
137060: 08/12/21: Re: Bit width in CPU cores
137088: 08/12/22: Re: Bit width in CPU cores
137089: 08/12/22: Re: Bit width in CPU cores
<m_oylulan@hotmail.com>:
84386: 05/05/18: CORDIC bit-serial vs. bit-parallel
85201: 05/06/06: Xilinx ISE 7.1i
85292: 05/06/07: Re: CORDIC bit-serial vs. bit-parallel
86340: 05/06/25: interfacing to multiple converters
86349: 05/06/26: Re: interfacing to multiple converters
103273: 06/05/30: Mains pick-up on I/O pins
103396: 06/06/01: Re: Mains pick-up on I/O pins
103728: 06/06/09: Current from FPGA pins to ADC
103887: 06/06/14: Re: Current from FPGA pins to ADC
<m_rajanikant@my-deja.com>:
22640: 00/05/16: c -> FPGA netlist compiler
ma:
83782: 05/05/06: newbie question
83823: 05/05/07: Re: newbie question
83841: 05/05/07: Re: newbie question
94173: 06/01/06: Programming Xilinx PowerPC
94176: 06/01/06: Re: Programming Xilinx PowerPC
94179: 06/01/06: Re: Programming Xilinx PowerPC
94181: 06/01/07: Re: Programming Xilinx PowerPC
108654: 06/09/14: Developing new blocks for sysgen
112415: 06/11/21: CORDIC FM Demodulation
112437: 06/11/22: Re: CORDIC FM Demodulation
112441: 06/11/22: Re: CORDIC FM Demodulation
112730: 06/11/28: Digital PLL and FM demodulation
112756: 06/11/28: Re: Digital PLL and FM demodulation
113413: 06/12/13: IQ multiplier
113437: 06/12/13: Re: IQ multiplier
113440: 06/12/13: Complex mixer
Ma. Jose Avedillo de Juan:
12653: 98/10/22: state assignment & fpgas
Maaf:
87850: 05/08/02: 5V non-volatile reprogrammable FPGA/CPLD
87892: 05/08/03: Re: 5V non-volatile reprogrammable FPGA/CPLD
mabs239:
153030: 11/11/18: Xilinx ISE 13.2 Verilog behavioural simulation in Command Line
mac:
144714: 09/12/27: Re: Info on heritage Nallatech board?
145638: 10/02/16: Re: using an FPGA to emulate a vintage computer
146072: 10/03/05: Re: Laptop for FPGA design?
146928: 10/04/02: Re: Which is the most beautiful and memorable hardware structure in a CPU?
147374: 10/04/24: Re: Need to run old 8051 firmware
148885: 10/09/07: Re: Want to get into FPGA
150899: 11/02/20: Re: Mathematical definition of an FPGA
151336: 11/03/24: Re: pcb&bitstream
156260: 14/01/25: Re: my first microZed board
159515: 16/11/29: Re: Phrasing!
159521: 16/12/01: Re: Phrasing!
159672: 17/01/27: Re: Anyone use 1's compliment or signed magnitude?
160543: 18/03/20: Re: How to handle a data packet while calculating CRC.
Mac:
64384: 03/12/31: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
65698: 04/02/04: Re: Design Flow: PCI or any other high-speed PC interface ?
77754: 05/01/16: Re: What is the difference between ASIC and FPGA?.
80858: 05/03/12: Re: ISE build dependencies
80882: 05/03/14: Re: ISE build dependencies
81001: 05/03/16: Re: LVDS as general differential input ?
81264: 05/03/20: Re: RS 232 receiver using spartan 3 board
81270: 05/03/21: Re: RS 232 receiver using spartan 3 board
82680: 05/04/16: Re: Hobby or job? (FPGA User's groups anyone?)
82681: 05/04/16: Re: salary ballpark please guys
82704: 05/04/16: Re: salary ballpark please guys
82746: 05/04/17: Re: salary ballpark please guys
82748: 05/04/17: Re: salary ballpark please guys
83345: 05/04/28: Re: XC9500 - creating RS485 Mux
83350: 05/04/28: Re: Virtex slow clock multiply options?
83396: 05/04/29: Re: Virtex slow clock multiply options?
83397: 05/04/29: Re: Virtex slow clock multiply options?
83678: 05/05/05: Re: Does this group allow JobPostings?
84780: 05/05/27: Re: Ethernet / digital logic questions
84887: 05/05/31: Re: What is a typical job scope when FPGAs are involved?
85023: 05/06/03: Re: PCI master clock trace
85024: 05/06/03: Re: need a book: Hilbert transform
85229: 05/06/07: Re: Sch & Layout Free Program
95163: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95166: 06/01/21: Re: OT:Shooting Ourselves in the Foot
mac teh knife:
44294: 02/06/16: new computer
44327: 02/06/17: Re: Which Synthesis tool for XILINX
MACEI'S:
56888: 03/06/18: BCH or Hamming Code
56986: 03/06/20: Is this is possible???
57855: 03/07/08: Multiple Files to Synthesis in Make File ?
57858: 03/07/08: Books
57910: 03/07/09: Make file ...........Help Please
57991: 03/07/11: how to compile .vhd files one by one using makefile
58112: 03/07/15: how to remove this error
58114: 03/07/15: Make file ...........Help Please
58265: 03/07/18: bit to rbt conversion
60262: 03/09/09: AWGN in VHDL
Maciej (@):
55567: 03/05/12: GSR
Maciej Bartkowiak:
18781: 99/11/15: Need advice on interfacing SDRAM modules
18844: 99/11/18: Re: Need advice on interfacing SDRAM modules
Maciej Witaszek:
68777: 04/04/17: NIOS: Run program from SDRAM
68779: 04/04/18: Re: Nios - cyclone toolchain questions
68910: 04/04/21: Re: NIOS: Run program from SDRAM
Maciejos:
75888: 04/11/18: Spartan-3 configuring problem
75892: 04/11/18: Re: Spartan-3 configuring problem
75896: 04/11/18: Re: Spartan-3 configuring problem
Maciek:
42589: 02/04/28: Xilinx
43059: 02/05/11: dual port fifo
43063: 02/05/11: Re: dual port fifo
45725: 02/08/02: spartan i/o
45755: 02/08/05: Re: spartan i/o
58527: 03/07/25: Re: Should I use ABEL?
58531: 03/07/25: Quartus and memory initialization
58532: 03/07/25: Re: Quartus and memory initialization
59932: 03/09/02: Altera Devices
59945: 03/09/02: Re: Altera Devices
Maciek Kudla:
26166: 00/10/06: Problem Foundation 3.1 sp 3
Mack:
109567: 06/09/29: Interfacing second bram port to user logic?
109579: 06/09/29: Re: Interfacing second bram port to user logic?
110838: 06/10/24: DDR SDRAM access with MPMC2, Databus Width
110887: 06/10/25: Re: DDR SDRAM access with MPMC2, Databus Width
110976: 06/10/26: Re: DDR SDRAM access with MPMC2, Databus Width
mack:
72957: 04/09/08: AMBA AHB
73001: 04/09/09: Re: AMBA AHB
73094: 04/09/14: AHB-Slave
73108: 04/09/14: EDK
73358: 04/09/20: AHB_SLAVE
75477: 04/11/07: Mixed RTL ,XILINX EDK
75505: 04/11/08: Re: Mixed RTL ,XILINX EDK
Mad I.D.:
118530: 07/04/29: DS18B20 connection on FPGA?
138138: 09/02/07: [VHDL] Simple syntax error, but why ?
138139: 09/02/07: Re: Simple syntax error, but why ?
138141: 09/02/07: Re: Simple syntax error, but why ?
138751: 09/03/08: Dual port RAM on Spartan
138752: 09/03/08: Re: Dual port RAM on Spartan
138897: 09/03/13: XST: Unconnected output pins
<madaan@my-dejanews.com>:
12436: 98/10/12: I2C Core
15808: 99/04/15: JPEG Codec
madair:
114434: 07/01/15: Constraining Multiple clock design
maddy:
84895: 05/05/31: Re: FPGA Boards
Madeleine Delaat:
<MadHatter7@myself.com>:
139806: 09/04/14: Re: Low-cost Altera FPGA roadmap
140711: 09/05/22: Re: SPAM?
<madhav1111@gmail.com>:
83458: 05/04/30: using cadence tool
madhu:
39215: 02/02/04: Glitch detect
Madhu:
39385: 02/02/07: Re: conv_integer problem ???
39861: 02/02/21: Here is an argument and can anyone help me out
64515: 04/01/06: How do you initialize signals in VHDL?
79614: 05/02/22: Re: BACK to FPGA
madhukar:
71698: 04/07/28: Dcm clock for fpga
<MadhuPankaj11@gmail.com>:
129498: 08/02/26: Re: Interrupt Handler page missing in from software platform settings
Madhura:
36609: 01/11/13: FPGA synthesis
36749: 01/11/19: Re: FPGA synthesis
36759: 01/11/19: Re: FPGA synthesis
73744: 04/09/28: Microblaze : ilmb_Cntrl
73814: 04/09/29: Re: Microblaze : ilmb_Cntrl
73611: 04/09/25: Re: Microblaze:ISE-EDK
73420: 04/09/21: Microblaze:ISE-EDK
Madhura Bokil:
38454: 02/01/15: FPGA : VHDL netlist for simulation
Madhura P:
56918: 03/06/18: Design Validation
<madhurk@my-deja.com>:
17611: 99/08/13: Re: Philips Semiconductors (NL) seeks digital designers
Madison:
20159: 00/01/28: Testbenches
<madisonfff@usa.net>:
27164: 00/11/13: Clear AND Preset Pins
<madmarsu@mygale.org>:
11394: 98/08/10: Re: Food poison
madQ:
18290: 99/10/12: Download Ia.n.i.!!! It's free!
18293: 99/10/12: Download Ia.n.i.!!! It's free!
18336: 99/10/16: Download Ia.n.i.!!! It's free!
18354: 99/10/18: Download Ia.n.i.!!! It's free!
18402: 99/10/22: Download Ia.n.i.!!! It's free!
Mads Ulrik Kristoffersen:
55175: 03/04/29: Xilinx XAct
MaEs:
64148: 03/12/18: Re: www.fpga-faq.com
66647: 04/02/24: Re: FPGA vendors and their patents
maespin:
22702: 00/05/18: verilog modules into viewlogic designs
Maf:
36672: 01/11/15: Re: Prototyping Board
Magali Oudard:
29718: 01/03/06: School project
magic:
149523: 10/11/02: Nios 2 Cyclone II board problem with simple logic
149526: 10/11/02: Re: Nios 2 Cyclone II board problem with simple logic
149531: 10/11/02: Re: Nios 2 Cyclone II board problem with simple logic
149830: 10/11/25: NIOS 2 + linux + DE2 Board
149831: 10/11/25: Re: NIOS 2 + linux + DE2 Board
Magne Munkejord:
115460: 07/02/12: Problem with floating inputs on LVDS ports
115490: 07/02/12: Re: Problem with floating inputs on LVDS ports
115551: 07/02/13: Re: Problem with floating inputs on LVDS ports
145700: 10/02/19: Re: System design in FPGA
146252: 10/03/10: Re: Some Active-HDL questions
146253: 10/03/10: Re: Some Active-HDL questions
146332: 10/03/12: Re: how can i add memory
146374: 10/03/15: Re: ERROR: overlaps section...
146380: 10/03/15: Re: Why doesn't this situation generate a latch?
146401: 10/03/16: Re: Why doesn't this situation generate a latch?
146420: 10/03/17: Re: Why doesn't this situation generate a latch?
146572: 10/03/23: Re: Confusion in address generation for MIG generated DDR2 interface
146573: 10/03/23: Re: Writing Hex values to file in VHDL?
146580: 10/03/23: Re: Confusion in address generation for MIG generated DDR2 interface
146590: 10/03/23: Re: Writing Hex values to file in VHDL?
<magne.munkejord@gmail.com>:
132139: 08/05/15: question about high speed serial links with clock forwarding in
Magnus Danielson:
67186: 04/03/08: 66B mode of VirtexII-ProX Rocket I/O
67258: 04/03/09: Re: 66B mode of VirtexII-ProX Rocket I/O
68745: 04/04/16: Re: 66B mode of VirtexII-ProX Rocket I/O
68746: 04/04/16: Re: 66B mode of VirtexII-ProX Rocket I/O
Magnus Homann:
8470: 97/12/18: md5 in a FPGA?
8480: 97/12/20: Re: md5 in a FPGA?
8572: 98/01/09: Re: Xilinx Configuration Problem
8771: 98/01/25: Re: UART Spec
8844: 98/02/01: FPGA/ASIC - same difference?
9011: 98/02/13: PLD programming and board testing (JTAG)
9574: 98/03/24: Re: "CORE Competency" ???
10356: 98/05/14: Re: Chicken & egg problem in PCI/CardBus designs using FPGA
12387: 98/10/10: Schematic entry?
13488: 98/12/05: Re: XILINX FPGA reaches GHz speeds
13665: 98/12/17: Re: Fast *Industrial* 22V10?
13726: 98/12/21: Re: Fast *Industrial* 22V10?
13728: 98/12/21: Re: Fast *Industrial* 22V10?
13753: 98/12/22: Re: Fast *Industrial* 22V10?
13799: 98/12/28: Re: 22V10 Metastability - help please
13805: 98/12/28: Re: 22V10 Metastability - help please
13836: 98/12/29: Re: 22V10 Metastability - help please
13843: 98/12/29: Re: 22V10 Metastability - help please
13852: 98/12/29: Re: 22V10 Metastability - help please
13883: 98/12/31: Re: 22V10 Metastability - help please
13884: 98/12/31: Re: 22V10 Metastability - help please
13885: 98/12/31: Re: 22V10 Metastability - help please
13920: 99/01/02: Re: IS: 2001, A Logic Odyssey (WAS: 22V10 Metastability - help please)
14048: 99/01/09: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
14051: 99/01/09: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
13999: 99/01/06: Re: Gömmer grisöron...
14042: 99/01/08: Re: Field Applications Engineers: ASIC/Field Programable Gate Arrays
15184: 99/03/11: Re: Infidels Invited, Heathens Highly Welcome !
16080: 99/04/30: Re: Double Port ram for Altera EPF10K20
16545: 99/05/27: Re: Virtex based PCI cards
16323: 99/05/16: Re: Synchronizer design?
16427: 99/05/21: Re: How synthesize tools concern with size of the design?
16476: 99/05/25: Re: How synthesize tools concern with size of the design?
16700: 99/06/03: Re: virtex vs apex20k family comparison for DSP ?
17564: 99/08/10: Re: Designing a Virtex board
17999: 99/09/22: Dual-port RAM in Apex
18335: 99/10/16: Re: VITERBI
18345: 99/10/16: Re: Xilinx 4k and DPRAM for leonardo question
18951: 99/11/22: Re: Virtex: Getting flip-flops into the pads
19084: 99/11/28: Re: Virtex: Getting flip-flops into the pads
19139: 99/12/02: Re: data serializer/decoder FPGA solution
19303: 99/12/11: Re: Altera APEX lpm modules in Synplify
19534: 99/12/29: Re: USB2 core call for Volunteers
19546: 99/12/30: Re: IRDY/TRDY Dedicated or Special Pin Name
19548: 99/12/30: Re: PCI slot 3.3V pins.
19553: 99/12/30: Re: USB2 core call for Volunteers
19562: 99/12/31: Re: PCI slot 3.3V pins.
19678: 00/01/07: Re: Design security
20101: 00/01/27: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
20115: 00/01/27: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
20496: 00/02/11: Re: Spartan and timing analyzer: clock nets using non-dedicated resources
20498: 00/02/11: A FPGA hickup
20506: 00/02/12: Re: A FPGA hickup
20526: 00/02/13: Re: A FPGA hickup
20578: 00/02/15: Re: A FPGA hickup
20585: 00/02/15: Re: Xilinx Virtex Reset
20586: 00/02/15: Using SRL16 for synching asynch inputs?
20642: 00/02/16: Re: Xilinx hold time problems...
20649: 00/02/16: Re: Xilinx hold time problems...
21160: 00/03/08: Re: antifuse fpga's replacing xilinx
21174: 00/03/09: Re: antifuse fpga's replacing xilinx
21175: 00/03/09: Re: antifuse fpga's replacing xilinx
21182: 00/03/09: Re: antifuse fpga's replacing xilinx
21211: 00/03/10: Re: antifuse fpga's replacing xilinx
21673: 00/03/28: Re: FPGA & single point failure
21905: 00/04/06: Re: JTAG programming
22796: 00/05/24: Re: Xilinx Virtex E
23045: 00/06/10: Re: XILINX RAM Useless
23047: 00/06/10: Re: math help needed
24539: 00/08/12: Re: QuickLogic PCI/FPGA chip (QL5064)...experiences?
24540: 00/08/12: Re: Who needs all those printed ac parameters?
25078: 00/08/25: Re: largest fpga in the industry
26567: 00/10/20: Re: Very Lucrative FPGA Jobs
26587: 00/10/21: Re: UCF Question
26612: 00/10/22: Re: UCF Question
26616: 00/10/22: Re: UCF Question
26625: 00/10/23: Re: UCF Question
26757: 00/10/27: Re: Lazio Promises End to Long Island FPGA Crisis
26804: 00/10/30: Re: Very Lucrative FPGA Jobs
27336: 00/11/18: Re: In the news
27383: 00/11/20: Re: In the news
27413: 00/11/21: Re: In the news
27449: 00/11/22: Re: Clock Skew : Does Xilinx know what they're doing?
27464: 00/11/22: Re: Clock Skew : Does Xilinx know what they're doing?
27472: 00/11/23: Re: Clock Skew : Does Xilinx know what they're doing?
27485: 00/11/23: Re: Clock Skew : Does Xilinx know what they're doing?
27489: 00/11/24: Re: How to reduce the Tco
27493: 00/11/24: Re: How to reduce the Tco
27623: 00/11/30: Re: 150MHz LVDS vs. 75MHz TTL
27634: 00/11/30: Re: Synplify Benchmarks
27646: 00/12/01: Re: Synplify Benchmarks
27647: 00/12/01: Re: Synplify Benchmarks
27671: 00/12/01: Re: Synplify Benchmarks
27672: 00/12/01: Re: Synplify Benchmarks
27842: 00/12/12: Re: dual port ram for altera
27846: 00/12/12: Re: Synplify PRO 6.1 + Foundation 3.1i
28141: 00/12/22: Re: really fast counter in SpartanXL?
28146: 00/12/22: Re: Synplicity and multiple input IOB flops...how to specify which one goes in the IOB?
28164: 00/12/23: Re: Synplicity and multiple input IOB flops...how to specify which one goes in the IOB?
29579: 01/02/27: Re: Spartan II power
30191: 01/03/27: Re: What's new in Synplify 6.20 than 6.13
29654: 01/03/04: Re: Metastability
29792: 01/03/10: Re: Metastability
29875: 01/03/14: Re: Again Spartan II power
29876: 01/03/15: Re: Metastability
29877: 01/03/15: Re: Metastability
29878: 01/03/15: Re: Metastability
30033: 01/03/21: Re: Looking for Skew information
30150: 01/03/26: Re: No inputs on XC9536XL
30298: 01/04/02: Re: xapp258 question
30335: 01/04/03: Re: xapp258 question
30735: 01/04/26: Re: Something about the counter
30779: 01/04/28: Re: C++ To Gates
30793: 01/04/29: Re: C++ To Gates
30794: 01/04/29: Re: C++ To Gates
30820: 01/04/30: Re: C++ To Gates
30821: 01/04/30: Re: C++ To Gates
30822: 01/04/30: Re: C++ To Gates
30836: 01/05/01: Re: C++ To Gates
30839: 01/05/01: Re: Multiple state machines in altera AHDL
30957: 01/05/04: Re: Virtex-E HDL -- Possible to clock register directly from ibuf?
31675: 01/06/02: Re: Spartan2 PCI-IP Core @ power-up
31678: 01/06/02: Re: Spartan2 PCI-IP Core @ power-up
31966: 01/06/10: Re: Help in FIFO design
31967: 01/06/10: Re: problem: bahavior simulation of xilinx's coregen cores
31968: 01/06/10: Re: Flash programming via FPGA's JTAG ????
32410: 01/06/26: Re: Register balancing in FPGA Express
32479: 01/06/27: Re: clock speed in XC95288XL
32502: 01/06/28: Clock muxes
32551: 01/06/29: Re: Date/Time at synthesis -> std_logic_vector => just use a ROM
32657: 01/07/04: Re: Date/Time at synthesis -> std_logic_vector => just use a ROM
32788: 01/07/09: Re: SpartanII: non clock pad drives clock net ?
32892: 01/07/11: Re: Handel-C
32954: 01/07/12: Re: PCI arbiter core
32976: 01/07/13: Re: Xilinx BRAM failures
32978: 01/07/13: Re: Design entry
34203: 01/08/16: Re: Replication of FFs in Xilinx XC4000
35405: 01/10/03: Re: Which Cable for the Xilinx 3064XL ?
35422: 01/10/04: Re: Which Cable for the Xilinx 3064XL ?
35917: 01/10/23: Re: Verilog vs. VHDL
36423: 01/11/08: Re: Xilinx dedicated IO pins
36461: 01/11/09: Re: Xilinx dedicated IO pins
36837: 01/11/21: Re: slew rate of virtex output buffers figures
36929: 01/11/26: Re: ALTERA's Mercury CDR
37114: 01/11/30: Re: SpartanIIE
38369: 02/01/12: Re: Repost: Should clock skew be included for setup time analysis?
38440: 02/01/14: Re: Repost: Should clock skew be included for setup time analysis?
38441: 02/01/14: Re: Repost: Should clock skew be included for setup time analysis?
38490: 02/01/15: Re: Repost: Should clock skew be included for setup time analysis?
39132: 02/02/01: Re: APEX-II vs VIRTEX-II
39133: 02/02/01: Re: Spartan II power-up current - again
39351: 02/02/07: Re: CLKDLL x4 problem
40147: 02/02/28: Re: Altera's new family Stratix
40315: 02/03/05: Re: Constraining help required for clk_enable
40789: 02/03/15: Re: where to start with constraining..
40790: 02/03/15: Re: High speed clock routing
40802: 02/03/15: Re: High speed clock routing
40834: 02/03/16: Re: High speed clock routing
40835: 02/03/16: Re: High speed clock routing
40872: 02/03/17: Re: just bought...
40873: 02/03/17: Re: To Falk Brunner
40919: 02/03/18: Re: just bought...
41930: 02/04/11: Re: regarding gate count of the design
41931: 02/04/11: Re: Built in multipliers in Virtex 2000E?
42494: 02/04/25: Re: Using 74HCT245N between Spartan-II and ISA
42717: 02/05/01: Re: Availability of XC2S150E-6FG456I
44538: 02/06/22: Re: 12 years experience in Digital HW/ FPGA design, looking for job in the US
51768: 03/01/21: Re: Schematic design approach compared to VHDL entry approach
51769: 03/01/21: Re: Schematic design approach compared to VHDL entry approach
55355: 03/05/05: Re: Virtex2 BUFGMUX problem ?
56091: 03/05/28: Re: JTAG madness
56128: 03/05/29: Re: JTAG madness
56232: 03/05/31: Re: FPGA's an Flash
60217: 03/09/08: Re: CMOS camera w/ USB2 -- crazy?
60497: 03/09/15: Re: Xilinx S3 I/O robustness question
60994: 03/09/26: Re: Regulator for Spartan 2
61507: 03/10/06: Re: Digesting runs of ones or zeros "well"
61658: 03/10/08: Re: BF957C Application
65344: 04/01/25: Re: changing values in a fifo
66241: 04/02/15: Re: Pricing, 101
66713: 04/02/25: How would you...
66750: 04/02/26: Re: How would you...
67558: 04/03/14: Re: Issues in Rocket I/O
Magnus Jacobsson:
50243: 02/12/06: *Exactly* How and when does attribute DESKEW_ADJUST affect the DCM
50253: 02/12/06: Re: *Exactly* How and when does attribute DESKEW_ADJUST affect the DCM
mah@k-space.org:
151373: 11/03/29: MCode Block Problem
mahalingamv@gmail.com:
117292: 07/03/27: is edk 8.1 availabe for download
119298: 07/05/16: Re: Interfacing DDR RAMs to Virtex 2 Pro on Digilent boards
120197: 07/06/02: ngdbuild error : multiple drivers and driving non buffer primitives
120248: 07/06/04: Re: ngdbuild error : multiple drivers and driving non buffer primitives
120249: 07/06/04: Re: any experiences concerning xup and digilent inc.?
120318: 07/06/05: Re: ngdbuild error : multiple drivers and driving non buffer primitives
120732: 07/06/15: edk clock problem
120834: 07/06/18: Re: edk clock problem
<mahalingamv@gmail.com>:
99914: 06/03/30: design compiler optimization
Mahboob Ahmed:
17989: 99/09/21: FPGA Compiler II/FPGA Express User's Manual
17988: 99/09/21: FPGA Compiler II/FPGA Express User's Manual
18319: 99/10/14: Virtex FPGA PCI select I/O Characteristics.
19072: 99/11/27: Siemens HSCX development tools.
19467: 99/12/23: PCI slot 3.3V pins.
mahdavi:
37053: 01/11/29: Test Bench for MaxPlus ?
mahdi:
115443: 07/02/11: CLOCK GENERATOR
115753: 07/02/19: ROC PORT
115867: 07/02/22: Re: ROC PORT
115868: 07/02/22: 2x technique
115869: 07/02/22: internal DCM
115883: 07/02/22: Re: internal DCM
115884: 07/02/22: Re: 2x technique
Mahei:
109488: 06/09/27: Re: Looking for ispMACH4000 eval boards
<mahenreddy@gmail.com>:
115921: 07/02/25: Edge vs Level triggering
maher:
137841: 09/01/31: Re: LUT design / Transmission gates or pass transistors?
137847: 09/01/31: Re: LUT design / Transmission gates or pass transistors?
137850: 09/01/31: Re: LUT design / Transmission gates or pass transistors?
mahesh:
106979: 06/08/23: Re: PCIe latency
133222: 08/06/20: Re: Error while doing 'Generate Netlist' in xilinx 9.2i
133446: 08/06/29: Re: ANNOUNCE: TimingAnalyzer version beta 0.85
133461: 08/06/30: Re: ANNOUNCE: TimingAnalyzer version beta 0.85
133475: 08/06/30: Re: ANNOUNCE: TimingAnalyzer version beta 0.85
Mahesh M. Bandi:
52336: 03/02/06: Re: Quartus II 2.2 doesn't run when installed to a newly transferred hard drive
52343: 03/02/07: Re: Quartus II 2.2 doesn't run when installed to a newly transferred hard drive
52344: 03/02/07: Re: Quartus II 2.2 doesn't run when installed to a newly transferred hard drive
52345: 03/02/07: Re: Quartus II 2.2 doesn't run when installed to a newly transferred hard drive
52363: 03/02/07: Re: NIOS and ACEX1K
Mahim Mishra:
66563: 04/02/22: Help with Xilinx EDK 6.1
66672: 04/02/24: Re: Help with Xilinx EDK 6.1
66858: 04/02/27: Xilinx ISE Impact crashes during configuration
66892: 04/02/28: Re: Xilinx ISE Impact crashes during configuration
66893: 04/02/28: Xilinx iMPACT error: "Done did not go high"
66908: 04/02/29: Re: Xilinx iMPACT error: "Done did not go high"
67685: 04/03/17: Xilinx bit-file format?
73043: 04/09/11: JBits 3.0 and Virtex-II Pro
73238: 04/09/16: xdl tool, or Xilinx Design Language
Mahmoud:
94939: 06/01/19: Re: newbie question about Xillinx JTAG cable
94831: 06/01/18: Xilinx 8.1i: Testbench waveform from VHDL netlist does not work ??
95457: 06/01/23: Re: Xilinx ISE & StateCad
95601: 06/01/24: Re: Verilog tutorial by John Sanguinetti
96050: 06/01/28: Re: Digilent FPGA & Handel-C
96349: 06/02/02: Re: How will synthesizers handle these statements?
Mahmut C. Genceli:
18180: 99/10/05: Re: Free Hardware "CPLD board"
mahshid:
123354: 07/08/24: Dynamic power estimation using Xpower
123368: 07/08/25: Re: Dynamic power estimation using Xpower
<mahurshi@gmail.com>:
98193: 06/03/06: A few questions about FPGAs
<mai99drh@studserv.uni-leipzig.de>:
76847: 04/12/14: Re: pausing execution on ppc405
Maik:
144672: 09/12/22: Xilinx S3A DSP Video Starter Kit, IP Cores not working
Maik H.:
132762: 08/06/06: Re: Your favourite DSP textbooks/websites?
144254: 09/11/23: Re: EDK11 under 64-bit OS
144862: 10/01/08: Re: new PC specs for Xilinx tools
145740: 10/02/22: Re: EDK 11,1 on Windows 7, 32 Bit
Maik Ritter:
117907: 07/04/13: Are there Quartus II Web Edition limitations?
117913: 07/04/13: Re: Are there Quartus II Web Edition limitations?
117977: 07/04/15: Re: Are there Quartus II Web Edition limitations?
<Maik>:
135209: 08/09/20: Re: Peter says Good Bye
Mail Delivery Service:
85190: 05/06/06: Delivery Status Notification
<mail83870@pop.net>:
11431: 98/08/13: Newbie seeks cheap fun w/FPGAs
<mail@deeptrace.com>:
93551: 05/12/24: Xilinx ISE Simulator
93719: 05/12/28: Re: Xilinx ISE Simulator
93933: 06/01/03: Re: Xilinx ISE Simulator
94932: 06/01/19: Disabling cross domain checking for Xilinx ISE
94938: 06/01/19: Re: Disabling cross domain checking for Xilinx ISE
94964: 06/01/19: Bogus Hold Violations with 2X clock on Xilinx ISE 7.1
mailmekaran:
103472: 06/06/03: VHDL code For Floating point adder and Multiplier
<mailsatishv@gmail.com>:
121714: 07/07/11: New board JTAG error
121735: 07/07/12: Re: New board JTAG error
<mailservice@bulkmail.net>:
7232: 97/08/17: Do you like to receive $2 million ?
maimuna:
45939: 02/08/12: changing width of array
46096: 02/08/19: to reduce the circuit design
46222: 02/08/21: Re: to reduce the circuit design
46262: 02/08/23: Re: to reduce the circuit design
Mainak Sen:
66128: 04/02/12: xsa-50 board
76065: 04/11/23: Xilinx Multimedia Board
Maire:
36861: 01/11/22: Synplicity & BlockRAMs
maisk:
54858: 03/04/20: Re: test
majordomo@att.net:
7125: 97/08/03: HELP!!NEED A CACHE SIMULATOR A.S.A.P
majsta:
152372: 11/08/15: 5V FCT TO Cyclone II
152375: 11/08/16: Re: 5V FCT TO Cyclone II
152457: 11/08/25: Re: 5V FCT TO Cyclone II
152521: 11/08/30: Re: 5V FCT TO Cyclone II
153469: 12/03/05: Error JTAG chain problem detected
153490: 12/03/11: Re: Error JTAG chain problem detected
Mak:
83291: 05/04/27: Re: PCI plug n play and Graphics card implementation
89042: 05/09/03: High baud rate chips for RS232 protocol
107773: 06/09/01: Interface of 8051 microcontroller with FPGA Block RAM
107789: 06/09/01: Re: Interface of 8051 microcontroller with FPGA Block RAM
107791: 06/09/01: Re: Interface of 8051 microcontroller with FPGA Block RAM
108681: 06/09/14: Critcal path in XILINX ISE (XST)
110585: 06/10/18: EDIF netlist timing simulation
110587: 06/10/18: Re: EDIF netlist timing simulation
<mak@cromp.ernet.in>:
4677: 96/11/28: Reconfigurable FPGAs in Networking
makarand:
133571: 08/07/03: Free Webinars on PMP Certification Awareness and Roadmap
Makarand Joshi:
13588: 98/12/10: Re: Array Range Legal?
13594: 98/12/10: Re: Array Range Legal?
Make Money Fast:
Makesh Soundarajan:
71020: 04/07/05: Has anybody used the DAC in the new Nu Horizons Spartan 3 development board
71056: 04/07/06: Re: Has anybody used the DAC in the new Nu Horizons Spartan 3 development board
71070: 04/07/07: Re: spartan3 board for newbie: xilinx XC3S200 starter kit or nu-horizons XC3S400 board???
makeuptest:
149740: 10/11/21: Procedures and Registers
149751: 10/11/22: Re: Procedures and Registers
makhan:
112529: 06/11/23: For those starting with Cypress Ez USB FX2LP and FPGA interfaces -- PART 1
113910: 06/12/28: For those starting with Cypress Ez USB FX2LP and FPGA interfaces -- PART 2
122746: 07/08/06: Re: how to test the FPGA on the board
122748: 07/08/06: Re: Download the contents of the FPGA's RAM block
122835: 07/08/08: Re: Download the contents of the FPGA's RAM block
131105: 08/04/10: Probelms simulating Xilinx FFT version 3.2 core in ModelSim SE
131115: 08/04/11: Re: Probelms simulating Xilinx FFT version 3.2 core in ModelSim SE
Maki:
33285: 01/07/22: Re: Maxplus II download sites
34135: 01/08/15: Re: Building a clock out of a PLD
75779: 04/11/15: Re: Gap between layers in PCB
88185: 05/08/11: LatticeXP availability
89949: 05/09/30: Lattice XP availability
89951: 05/09/30: Re: Lattice XP availability
99534: 06/03/26: Re: BlockROM inference in XST - This is just plain silly
100159: 06/04/04: Lattice ispLever Starter Download
100235: 06/04/05: Re: Lattice ispLever Starter Download
124299: 07/09/18: Re: Tristate bus on spartan FPGA
125885: 07/11/08: Re: Non-volatile FPGA in a small package
125907: 07/11/08: Re: Non-volatile FPGA in a small package
127813: 08/01/08: Re: True Dual Port RAM
127901: 08/01/10: Re: How to program and initialize Lattice XP devices
127931: 08/01/10: Re: True Dual Port RAM
128489: 08/01/28: Re: My first Flash FPGA
128503: 08/01/29: Re: My first Flash FPGA
makmorbi:
52713: 03/02/19: FPGA's at High Temperatures
67654: 04/03/16: Re: Quartus II 4.0 Web Edition Software & Documentation - Available for download
70314: 04/06/11: Low Power FPGA Design Seminar
73368: 04/09/20: Altera Max II
makni:
156362: 14/03/18: data read write to DDR2 SDRAM memory between microblaze and custom IP using PLB Bus
156475: 14/04/09: Soft-Cores processors
156645: 14/05/22: Microblaze and MBLite
Makoto Honda:
54461: 03/04/11: Re: Dynamic Reconfigurable FPGAs
Malachy Devlin:
16372: 99/05/19: Re: Virtex based PCI cards
16424: 99/05/21: Re: Virtex based PCI cards
19062: 99/11/26: Programming Virtex device via JTAG
20919: 00/02/28: PCI 64 bit / 66 MHz
22673: 00/05/17: appropriate ASIC Prototyping Board
22674: 00/05/17: Reccomend an ASIC emulation board
malavica:
137644: 09/01/26: How to make a ram shared?
malcolm:
143084: 09/09/18: Re: Actel dropped ARM7, when comes Xilinx ARM enabled silicon?
144012: 09/11/06: Re: OK Xilinx users, it's time I was let in on the joke...
144304: 09/11/25: Re: 32KHz RTC for FPGA
150278: 11/01/07: Re: Detecting cold reset on flash FPGA
150312: 11/01/09: Re: Low slewrate, abnormal current consumption.
150316: 11/01/09: Re: Strange issue wih a very simple VHDL code and Spartan 3A Starter
150319: 11/01/10: Re: Low slewrate, abnormal current consumption.
150855: 11/02/16: Re: PLD suggestions for classroom use
Malcolm Bugler:
6994: 97/07/20: AM186 to P/C104 PLD design
Malcolm Reeves:
28457: 01/01/13: ANN: Test Bench tool V2.01 - powerful and cheap
malgi:
47876: 02/10/06: Re: Low power design
<malino@primenet.com>:
18763: 99/11/12: Re: FPGA Expess vs. Synplify vs. Leonardo Spectrum
19008: 99/11/23: Re: VHDL vs. schematic entry
Malki:
14703: 99/02/12: Re: Board for XC4085XL
mammo:
101836: 06/05/07: Funky experiment on a Spartan II FPGA
101839: 06/05/07: Re: Funky experiment on a Spartan II FPGA
101857: 06/05/07: Re: Funky experiment on a Spartan II FPGA
Mamoon Hamid:
16276: 99/05/12: Re: Can use pullup in XC9500XL?
mamtachalana:
70610: 04/06/21: system verilog
mamu:
132140: 08/05/15: Re: Camera link interface
134999: 08/09/10: Re: IDELAYCTRL Locking problem with ISE10.1i
139467: 09/03/31: Dedicated clock routes in Xilinx FPGA
147594: 10/05/05: Re: rtl simulation model for microblaze
man cheng:
5207: 97/01/31: What is the different between FPGA and CPLD?
Man`y:
6974: 97/07/18: looking for a contract opening
Manan:
20476: 00/02/11: HELP ! Problems in mapping
<manan.kathuria@gmail.com>:
79941: 05/02/26: setup-hold time problems
<Mancini =?iso-8859-1?q?St=E9phane=22?= <stephane.mancini@inpg.fr>>:
48581: 02/10/21: Nios and quartus linux version
48655: 02/10/22: Re: Nios and quartus linux version
48979: 02/10/28: Leonardo and lpm (Altera)
49791: 02/11/21: Altera Logick lock newbie
49912: 02/11/25: Re: Altera Logick lock newbie
54918: 03/04/22: Re: quartus_cmd under Linux
57892: 03/07/09: Xilinx price question
Mancini Stephane:
60991: 03/09/26: your opinion about Avnet (Silica) VirtexII Pro evaluation board
61421: 03/10/03: Re: your opinion about Avnet (Silica) VirtexII Pro evaluation board
61815: 03/10/13: Quartus 2.2, SOPC builder and leonardo
61850: 03/10/14: Re: Quartus 2.2, SOPC builder and leonardo
62212: 03/10/22: NIOS simulation with modelsim -> strange behaviour
64263: 03/12/23: Avnet Virtex II Pro Dvpt board : linux drivers ??
65219: 04/01/22: Virtex II Pro, powerpc 405 and ucOSII
67588: 04/03/15: Virtex II Pro default I/O mode
68603: 04/04/09: I2C bus and tristate interface for V2pro
72890: 04/09/07: EDK 3.2 and modelsim ppc simulation
73060: 04/09/13: Re: EDK 3.2 and modelsim ppc simulation
73067: 04/09/13: Xilinx EDK and plb master
73113: 04/09/14: Re: Xilinx EDK and plb master
73272: 04/09/17: Xilinx EDK & IPIF performance
75395: 04/11/04: Xilinx EDK PLB/OPB bridge (and IPIF)
87162: 05/07/18: EDK and powerpc-eabi compiler
89448: 05/09/15: Xilinx V2Pro & SATA hard disk
89454: 05/09/15: Re: Xilinx V2Pro & SATA hard disk
<mandana@physics.ubc.ca>:
85462: 05/06/09: JTAG programming: JAM files versus ISC (IEEE1532) files
85719: 05/06/14: Re: JTAG programming: JAM files versus ISC (IEEE1532) files
85816: 05/06/16: Re: JTAG programming: JAM files versus ISC (IEEE1532) files
Mandeep Singh:
15583: 99/03/31: Reconfigurable Computing
Mandilas Antony:
56714: 03/06/12: error compiling
57385: 03/06/29: clock signals
57386: 03/06/29: memory
57387: 03/06/29: Re: memory
MANDY & DOUGLAS:
39204: 02/02/04: Re: RAM question
40010: 02/02/25: Re: IIR. convolution
<maneri@my-dejanews.com>:
15539: 99/03/29: PAMette for Rapid Prototyping
15644: 99/04/05: Re: How to implement Matched Filter in FPGA?
Manfred:
141191: 09/06/10: Virtex 2 Pro IO Banks Vcco
Manfred Aigner:
3381: 96/05/23: XACT Memgen + Mentor
3438: 96/05/30: Re: how to use memgen
3498: 96/06/11: Double Port Ram - Xact Libs
3559: 96/06/21: Routing
Manfred Balik:
62331: 03/10/27: Altera ACEX1K configuration and initialisation
63212: 03/11/18: Re: Acek 1K - Quartus II - timing issues
67699: 04/03/17: PC104 Evaluation Board
71261: 04/07/13: Quartus II 4.0 SP1 Warning: Can't find design file .../projectname0.rtl.mif
71745: 04/07/29: Re: Implementing control registers (VHDL)
72577: 04/08/25: Altera Quartus II 4.1 double-click on QPF-File doesn't work
72928: 04/09/08: i2c-core from opencores.org
75680: 04/11/12: DualPortRAM serial IN - parallel OUT
80182: 05/03/02: Altera APEX20KE clock problem
80289: 05/03/03: Altera Quartus II 4.2 SP1 fit problem and Altera APEX20KE clock problem
80334: 05/03/04: Re: Altera Quartus II 4.2 SP1 fit problem and Altera APEX20KE clock problem
86961: 05/07/11: output-value isn't stored
89340: 05/09/13: Migration Altera APEX20KE to ???
91449: 05/11/07: which Altera CPLD?
92082: 05/11/22: Quartus Problem
96248: 06/02/01: Re: Quartus Fitter Warning
104150: 06/06/20: Quartus 6.0 Fitter Critical Warning
104188: 06/06/21: Re: Quartus 6.0 Fitter Critical Warning
104203: 06/06/21: Re: Quartus 6.0 Fitter Critical Warning
107782: 06/09/01: bidirectional connection between two bidirectional ports
107801: 06/09/01: Re: bidirectional connection between two bidirectional ports
108078: 06/09/05: Re: bidirectional connection between two bidirectional ports
108082: 06/09/05: Re: bidirectional connection between two bidirectional ports
112536: 06/11/24: Altera MAX3000A OE and GCLR-Pins
112647: 06/11/27: Re: Altera MAX3000A OE and GCLR-Pins
113725: 06/12/20: CPLD speed/temperature equivalent
114127: 07/01/05: Altera Cyclone II die revision?
116722: 07/03/16: old Quartus project files
118176: 07/04/19: Altera M4K memory usage
118181: 07/04/19: Re: Altera M4K memory usage
Manfred Kraus:
10909: 98/06/30: Re: Xilinx file compression
10994: 98/07/09: Re: question on combinational logic synthesis for FPGA
12014: 98/09/24: Re: How to reduce ringing/ground bounce from FPGA output pin?
12881: 98/11/03: Re: New free FPGA CPU
12883: 98/11/03: Re: Digital Sine Generator
13067: 98/11/14: Re: Problem with the ABEL to Macro convertion in XILINX FB1.3
14419: 99/01/29: Re: PLL in FPGA
14658: 99/02/09: Re: dual port RAM on XC4000
19131: 99/12/01: data serializer/decoder FPGA solution
19148: 99/12/02: Re: data serializer/decoder FPGA solution
25993: 00/09/29: Xilinx Logicore Generator
28575: 01/01/17: Re: Looking for prototyping board
28640: 01/01/19: Re: Best design for asyn. interface DSP <-> FPGA?
29835: 01/03/13: 64 simultan A/D Converters in an SPARTAN-II
29846: 01/03/13: Re: 64 simultan A/D Converters in an SPARTAN-II
32534: 01/06/29: Re: FPGA Boards
32673: 01/07/04: clock frequency synthesizer for FPGA
32726: 01/07/06: Re: Spartan-II (XC2S200) Configuration Help~ DONE doesn't go HIGH
32734: 01/07/06: Re: Xilinx PCI development board
35428: 01/10/04: CoreGenerator and WebPack ISE
35550: 01/10/10: Re: CoreGenerator and WebPack ISE
35647: 01/10/12: Re: PWM Signal in VHDL ?
36096: 01/10/29: Re: University project: DSO
36567: 01/11/12: Re: Quadrature Encoder Sampling Time
39950: 02/02/22: Replacing expensive configuration SPROM
40460: 02/03/07: Re: DDR-Interface
40755: 02/03/14: Re: use virtex2 DCM as delay line
40756: 02/03/14: Re: Xilinix FPGA width 5V IO
40757: 02/03/14: Re: Proto boards for labs
40991: 02/03/19: Re: 1,5V power supply?
40992: 02/03/19: Re: virtex 2 orcad symbols?
40993: 02/03/19: Re: Unused I/Os + External Clock on Virtex II
40995: 02/03/19: Re: Xilinx JTAG Cables
42230: 02/04/18: Re: fpga limitation
42421: 02/04/23: Re: Prototyping Boards for Hobbyist CPU/System Designs
42652: 02/04/30: Re: Frequency synthesiser
42823: 02/05/03: Re: Frequency synthesiser
42824: 02/05/03: DDR SDRAM controller for VIRTEX-II
43968: 02/06/07: Re: Problem with spartan2 vhdl code
44014: 02/06/10: Re: Looking for FPGA board with USB interface
44302: 02/06/17: Which Synthesis tool for XILINX
44338: 02/06/18: Re: Which Synthesis tool for XILINX
44339: 02/06/18: Re: Which Synthesis tool for XILINX
44347: 02/06/18: Re: Pls Recommend a Development Board - Have you checked out the CESYS boards ?
44401: 02/06/19: Re: Pls Recommend a Xilinx development Board
44700: 02/06/27: Re: Applying voltage to FPGA I/O while FPGA is not powered
44916: 02/07/05: Re: Routing Virtex-II 256 pin BGA on 4 layers
44962: 02/07/08: Re: Newbie FPGA recommedation
45302: 02/07/18: Re: Advice on tools and question on Virtex2
45611: 02/07/29: Re: Programming FLASH with Xilinx Parallel Cable III
45612: 02/07/29: Re: secure FPGA
45728: 02/08/02: Re: lots of shift registers
46073: 02/08/16: Re: Fun FPGA system
46074: 02/08/16: Re: Testing the X2S_USB Spartan 2 board
54341: 03/04/08: Re: Power Supply for Spartan II FPGA
56481: 03/06/06: Re: Virtex 2 evaluation board
56482: 03/06/06: Re: Level Converters
56665: 03/06/11: A way to copy Modelsim waveforms into word documents
56674: 03/06/11: Re: A way to copy Modelsim waveforms into word documents
56675: 03/06/11: Re: A way to copy Modelsim waveforms into word documents
57642: 03/07/03: Spartan-3 availability
57648: 03/07/03: Re: Spartan-3 availability
57713: 03/07/04: Re: Spartan-3 availability
59103: 03/08/08: Re: clock management on SPARTAN2
60418: 03/09/12: Re: CMOS camera w/ USB2 -- crazy?
64163: 03/12/18: Re: Spartan3 availability
64780: 04/01/13: Re: SDRAM Controller timing problem
65801: 04/02/06: Virtex-3 PRO
66535: 04/02/21: Re: Can FPGA bootstrap itself?
66782: 04/02/26: Re: Suggestions: Eval/Demo Board.
88405: 05/08/17: Re: Easy USB2.0 hi-speed device solutions ?
120619: 07/06/12: Re: Affordable pcie card ?
Manfred Kuhland:
21013: 00/03/02: Re: Error in Xilinx application note XAPP131?
Manfred Muecke:
43570: 02/05/24: SOPC for machine vision
43572: 02/05/24: Re: SOPC for machine vision
43608: 02/05/27: Re: SOPC for machine vision
72409: 04/08/18: Re: What schematic tool (VHDL) is the best?
72422: 04/08/18: Re: What schematic tool (VHDL) is the best?
80776: 05/03/11: Re: New in C to RTL
<manfredk@internode.on.net>:
130245: 08/03/18: Re: vhdl type conversions
Manfredo:
26864: 00/11/01: Re: I need some VHDL/Synthesis Design BOOK recommendations!!
mani:
129724: 08/03/03: reconfiguration of virtex 2 pro
Manish:
75541: 04/11/08: FPGA as "Differential SSTL_2" clock driver
75577: 04/11/10: Re: FPGA as "Differential SSTL_2" clock driver
98272: 06/03/07: Crosstalk Analysis on a FPGA
Manish_Shrivastava:
14062: 99/01/11: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
14179: 99/01/18: Re: Reed-Muller99 CFP
<manishr@softjin.com>:
81960: 05/04/05: DCM LOCKED as reset
Manjunath:
35331: 01/09/29: Re: Meta-stability
manjunath.rg@gmail.com:
98300: 06/03/08: FPGA imple. of aes
98376: 06/03/08: Re: FPGA imple. of aes
98504: 06/03/11: Re: FPGA imple. of aes
98563: 06/03/12: Re: FPGA imple. of aes
MANJUNATHAN:
29944: 01/03/19: about placement and routing
Manjunathan:
29922: 01/03/16: about core generator
30104: 01/03/22: PLACE and ROUTE
30108: 01/03/23: Timing analysis after implementation
30272: 01/03/30: VIRTEX BLOCK RAM
30332: 01/04/03: to add macro in the design
33775: 01/08/04: how to replicate the Logic through VHDL attribut ?
33823: 01/08/06: how to give timing constraint in an hierarchy des
34008: 01/08/10: how to acheive high frquency in Xinlinx Virtex E
35303: 01/09/27: Meta-stability
<mankin18@gmail.com>:
113905: 06/12/28: SPI slave problem
113909: 06/12/28: Re: SPI slave problem
113916: 06/12/29: Re: SPI slave problem
113917: 06/12/29: Re: SPI slave problem
114020: 07/01/02: Re: SPI slave problem
114025: 07/01/02: Re: SPI slave problem
Mankit Wong:
7421: 97/09/09: Re: Which FPGA ?
11403: 98/08/11: Re: Gray code counter in ABEL HDL?
11616: 98/08/27: Re: CPLD/FPGA software
12770: 98/10/29: 8051 VHDL Model
17550: 99/08/10: Re: Lattice cable for 2032?
Manmohan:
147090: 10/04/13: Implementing bidirectional bus inside the FPGA
147091: 10/04/13: Re: Implementing bidirectional bus inside the FPGA
147096: 10/04/14: Re: Implementing bidirectional bus inside the FPGA
147097: 10/04/14: Re: Implementing bidirectional bus inside the FPGA
147104: 10/04/14: Re: Implementing bidirectional bus inside the FPGA
147136: 10/04/15: Re: Implementing bidirectional bus inside the FPGA
148206: 10/06/28: Using Xilinx TFT controller IP for normal VGA port on Spartan 3E 1600
manmohan singh:
67155: 04/03/07: licence for Xilinx 2.1i
67306: 04/03/09: Re: licence for Xilinx 2.1i
mann!:
79950: 05/02/26: Re: setup-hold time problems
79969: 05/02/27: maximum frequency of operation
79970: 05/02/27: maximum freq of operation of a circuit
Mann`y:
3634: 96/07/05: Looking for a PCI bus model
4938: 97/01/02: Re: NT 4.0, ViewOffice 7.2 and Xilinx tools...96->97 problem...
4943: 97/01/03: Usb Cores ( synthesisable ) and ( simulation models )
Manny:
110240: 06/10/12: Glitches in post-layout (PAR) simulation
110249: 06/10/12: Re: Glitches in post-layout (PAR) simulation
110255: 06/10/12: Re: Glitches in post-layout (PAR) simulation
110259: 06/10/12: Re: Glitches in post-layout (PAR) simulation
110262: 06/10/12: Re: Glitches in post-layout (PAR) simulation
110263: 06/10/12: Re: Glitches in post-layout (PAR) simulation
110265: 06/10/12: Re: Glitches in post-layout (PAR) simulation
110307: 06/10/13: Xilinx FPGAs in battery-powered scenarios
110317: 06/10/13: Re: Xilinx FPGAs in battery-powered scenarios
110344: 06/10/13: Re: Xilinx FPGAs in battery-powered scenarios
111894: 06/11/12: Xilinx platform cable USB
111994: 06/11/14: Re: Xilinx platform cable USB
113822: 06/12/23: IEEE fixed-point package FATAL_ERROR
115118: 07/01/31: Synthesis of DSP algorithms
115274: 07/02/05: Re: moving data from slower to faster clock domain
116340: 07/03/07: Re: Query regarding Project.Plz help very urgent
116372: 07/03/07: Re: Introducing picosecond delay between two output signals
118326: 07/04/23: Slave PLB core interrupt
118364: 07/04/24: Re: Slave PLB core interrupt
118645: 07/05/01: Read 64-bit value over PLB
118956: 07/05/08: Re: Read 64-bit value over PLB
119000: 07/05/09: Re: Xilinx software quality - how low can it go ?!
119140: 07/05/12: downto usage in EDK
119310: 07/05/16: Re: Xilinx EDK: Slow OPB write speeds
119312: 07/05/16: Re: Xilinx EDK: Slow OPB write speeds
119314: 07/05/16: Re: seeking insights for potential reconfigurable computing application platforms
120279: 07/06/04: System Generator installation
120775: 07/06/15: Simulating analogue signal using ISE simulator
120795: 07/06/16: Re: Simulating analogue signal using ISE simulator
123245: 07/08/21: Re: Synthesizing fixed_pkg in ISE 9.2
123246: 07/08/21: Spartan-3A DSP vs. Cyclone III Power-wise
123285: 07/08/22: Re: Spartan-3A DSP vs. Cyclone III Power-wise
124229: 07/09/14: Virtex II pro design question
124236: 07/09/15: Re: Virtex II pro design question
124422: 07/09/21: Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!
124424: 07/09/21: Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!
125035: 07/10/15: Re: FPGA quiz: what can be wrong
125054: 07/10/15: Re: FPGA quiz: what can be wrong
125066: 07/10/16: Re: FPGA quiz: what can be wrong
125078: 07/10/16: Re: FPGA quiz: what can be wrong
125156: 07/10/16: gold code - seed value
134496: 08/08/13: XMD & Ultracontroller
134549: 08/08/17: Ultracontroller-2 on ML403
138012: 09/02/03: Core interface protocol
138106: 09/02/06: Re: Core interface protocol
139673: 09/04/08: Re: Modulo-10 counter
139674: 09/04/08: Re: Modulo-10 counter
139676: 09/04/08: Re: ANN: Antti-Brain March issue released
140400: 09/05/12: Lockable shared memory co-simulation
140522: 09/05/15: Re: Lockable shared memory co-simulation
141504: 09/06/25: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
148526: 10/07/29: Re: Data-path accuracy in IIR filters?
148582: 10/08/03: Re: Xilinx ISE Webpack and Pipeline Optimization
148817: 10/08/28: Re: Plotting sampled data in Matlab
148821: 10/08/28: Re: Plotting sampled data in Matlab
148822: 10/08/28: Re: Plotting sampled data in Matlab
Manoj Chaubal:
2170: 95/10/25: Re: PLD in small package ?? anyone
2418: 95/12/02: New ALDEC tools for XACT 6.0
Manoj K Krishnan:
33667: 01/08/01: Building ROM and RAM blocks - Xilinx Foundation Series 3.1i
manoj.rajpoot@gmail.com:
105084: 06/07/13: Routing Information of Xilinx's Virtex-II FPGA
<manojb.jgi@gmail.com>:
157607: 15/01/02: Re: Open source Verilog BCH encoder/decoder
<manolete@discontrol.net>:
123393: 07/08/27: Re: Newbie with ISE 9_2_02i_lin gets error : Process "Translate" failed
Manolis Stratakis:
4498: 96/11/06: PCB Handling of chip packages greater than 100 pins?
Manpreet:
99754: 06/03/28: Re: need help,test on Spartan3 starter kit
99755: 06/03/28: how to immitate clock behavior----Please guide
mans (myname_here):
118024: 07/04/16: Matlab Simulink HDL coder generated code interface.
118112: 07/04/17: creating library in ISE 9
118130: 07/04/18: ISE Smart Ident
118133: 07/04/18: Compiling a library
118167: 07/04/18: VHDL source code for polyphase filter
118184: 07/04/19: Re: VHDL source code for polyphase filter
118281: 07/04/21: simulating with OSe 9.1.3
118294: 07/04/23: VHDL editing with UltraEdit
118382: 07/04/25: Re: VHDL editing with UltraEdit
mans (use_my_name_here):
117438: 07/03/30: Sysgen compilation target
117753: 07/04/09: record type port in vhdl and simulation in ISE
Mansih Mahajan:
15982: 99/04/24: Looking for FPGA/ASIC design/verification position
Mansoor Naseer:
54518: 03/04/12: Some suggestions on system design on PCB
mansoor.naseer@gmail.com:
83218: 05/04/26: PCI plug n play and Graphics card implementation
<mansoor.naseer@gmail.com>:
138546: 09/02/26: Re: Where can a cheap programmer for Xilinx Virtex II XC2V1500 be
139580: 09/04/05: Re: clock multipliers, dividers, and more clocks...
139766: 09/04/13: Re: buy XSA-50
manu:
99235: 06/03/21: Re: BRAM for virtex-4
99634: 06/03/27: Re: C-based FPGA programming/mixed languages
99976: 06/03/31: Re: ISE 8.1, EDK 8.1 installation
100332: 06/04/07: Re: xilinx xc2vp30
100337: 06/04/07: Re: OPB master
105431: 06/07/22: version control of ISE+EDK projects with CVS and/or SVN
143427: 09/10/11: Re: Xilinx xps interrupt controller
Manuel:
55823: 03/05/20: modulators and demodulators help
Manuel Alejandro Jimenez-Cede:
718: 95/02/16: Looking for Tech Info
Manuel Bessler:
95247: 06/01/21: Re: Raggedstone specifications ...
95813: 06/01/26: Re: Spartan-3 Starter Board
Manuel Gericota:
46190: 02/08/21: ERA60100 Data Sheet
Manuel Zaera Sanz:
47305: 02/09/23: MTBF
<manuel-lozano@mixmail.com>:
115254: 07/02/05: problem with microblaze gcc toolchain
117473: 07/04/01: broken mb-gcc -O2 ?
117482: 07/04/02: Re: broken mb-gcc -O2 ?
122722: 07/08/04: mb-gdb: problem simulating memory mapped i/o devices
129743: 08/03/04: FPGA for a DVB common interface implementation
129744: 08/03/04: FPGA for a DVB common interface implementation
133524: 08/07/02: minipci breadboard with fpga
133541: 08/07/03: Re: minipci breadboard with fpga
<manuel.bessler@gmail.com>:
94874: 06/01/18: Re: Raggedstone specifications ...
Manusha:
151610: 11/04/25: advice needed for FPGA chip selection
151611: 11/04/25: Re: advice needed for FPGA chip selection
151621: 11/04/26: Re: advice needed for FPGA chip selection
151652: 11/05/02: help with a power pc processor based software
151654: 11/05/02: Re: help with a power pc processor based software
151713: 11/05/09: USB support for XUPV2P
<manusha1980@gmail.com>:
153673: 12/04/14: recomendation on a processor core
153675: 12/04/15: Re: recomendation on a processor core
<manygates>:
72483: 04/08/20: GAL,PAL,PLD, CPLD,FPGA
72487: 04/08/21: Re: GAL,PAL,PLD, CPLD,FPGA
72501: 04/08/21: Re: GAL,PAL,PLD, CPLD,FPGA
72502: 04/08/21: Re: GAL,PAL,PLD, CPLD,FPGA
2mao:
115215: 07/02/02: Re: Xilinx Interconnects/Routing
<mar@tcelectronic.com>:
18791: 99/11/16: Re: Need advice on interfacing SDRAM modules
marada:
110987: 06/10/26: Re: Microblaze : FSL bus
112649: 06/11/27: Re: Microblaze : FSL bus
Marc:
26922: 00/11/03: Re: New (worse!) timing parameters in Quartus 2000.09 for APEX devices
28929: 01/01/30: Clocking system with CPLD? - timing.JPG (0/1)
29096: 01/02/06: switching Matrix, FPGA or CPLD? - smatrix.JPG (0/1)
29097: 01/02/06: switching Matrix, FPGA or CPLD? - smatrix.JPG (1/1)
29119: 01/02/06: Re: Switching matrix, FPGA or CPLD? - smatrix.JPG (0/1)
29121: 01/02/06: Re: switching Matrix, FPGA or CPLD? - smatrix.JPG (0/1)
29124: 01/02/07: Re: Switching matrix, FPGA or CPLD? - smatrix.JPG (0/1)
37877: 01/12/22: Beginners question: several circuits in one chip
38166: 02/01/08: Re: Suitability of Atmel for project?
61996: 03/10/16: Re: Running Quartus II on ReadHat Linux 9.0
62626: 03/11/03: Re: Altera "my support" :-(
64219: 03/12/21: Re: advantages of ethernet MAC ip core
64320: 03/12/28: Re: advantages of ethernet MAC ip core
67776: 04/03/18: Re: Problems with Memory Initialization Files in Modelsim
68969: 04/04/23: 64-bit SODIMM module on 32-bit SDRAM-controller?
71427: 04/07/18: Re: FPGA Development board with onboard Ethernet PHY
71820: 04/08/01: Re: FPGA prototype board with ethernet interfaces
73541: 04/09/23: Cyclone FPGA as Cardbus controller
82972: 05/04/20: Re: Differential timing specification in Xilinx FPGA
83811: 05/05/07: Re: Parallel Cable IV opened in "Compatibility Mode"
87052: 05/07/13: Re: Virtex 300: what could cause pin to short?
marc:
33351: 01/07/24: Register Chain
Marc 'Nepomuk' Heuler:
6903: 97/07/07: Re: Generating Sine/Cosine digitally
7836: 97/10/20: Re: Download Cable for In-System programming of LATTICE ispLSI, ....
7837: 97/10/20: [Reposted due to Enlow UCE cancel]: Re: Download Cable for In-System programming of LATTICE ispLSI, ....
7838: 97/10/20: [Reposted due to Enlow UCE cancel]: Re: Download Cable for In-System programming of LATTICE ispLSI, ....
Marc A. Baker:
103536: 06/06/05: Re: Documentation miss? (sp3/xilinx)
125877: 07/11/07: Re: Non-volatile FPGA in a small package
Marc Baker:
3871: 96/08/12: Re: Using Carry logic in XC4000...
4042: 96/09/05: Re: Address of ALTERA & XILINX
4221: 96/10/01: Re: XilinX XC5200 address pointer based FIFO
4319: 96/10/14: Re: Xilinx XACT Performance Appl. Note?
4335: 96/10/17: Re: Xilinx xchecker.exe and Windows NT
4383: 96/10/22: Re: What are I/O's doing prior to configuration?
4713: 96/12/05: Re: XACT under WinNT is very slow
13949: 99/01/04: Re: 1.5i changes
23814: 00/07/10: Re: Xilinx Data memory
24891: 00/08/21: Re: power consumption for spartan xcs05(XL)
25172: 00/08/29: Re: Spartan II vs. Virtex
25213: 00/08/30: Re: Xilinx and CD databooks (rant)
29029: 01/02/02: Re: JTAG Programming with SpartanII demo card
29090: 01/02/05: Re: JTAG Programming with SpartanII demo card
37125: 01/11/30: Re: SpartanIIE
37127: 01/11/30: Re: SpartanIIE
37532: 01/12/13: Re: FPGA introduction
39664: 02/02/15: Re: Spartan-II becomes Vertex.
46982: 02/09/13: Re: number of IOBs in Spartan IIE is fishy
46984: 02/09/13: Re: number of IOBs in Spartan IIE is fishy
48679: 02/10/22: Re: FPGA XC4005E
50419: 02/12/10: Re: [Spartan-IIE] Additional DLL input pins
50760: 02/12/18: Re: Errors in Xilinx pinout spreadsheet
51280: 03/01/09: Re: External RAM...
52675: 03/02/18: Re: What's the difference between LUT and RAM?
52676: 03/02/18: Re: Easy links to Xilinx documentation
55606: 03/05/13: Re: Missing App Notes
60622: 03/09/17: Re: How to contact the writer of Xilinx FPGA application notes?
60623: 03/09/17: Re: Original (5V) Xilinx Spartan ?
62232: 03/10/22: Re: Spartan 3 pinout typo?
62234: 03/10/22: Re: SpartanXL
63932: 03/12/09: Re: SPARTAN-II, busy signal
64031: 03/12/12: Re: Spartan IIE daisy chain problems
64032: 03/12/12: Re: Xilinx Spartan II pull-up, simple questions
66981: 04/03/02: Re: Xilinx : RLOC ORIGIN
67502: 04/03/12: Re: ISE 6.2 issues
71473: 04/07/19: Re: Understanding Xilinx Spartan 3 datasheet IOB timing information
Marc Battyani:
19319: 99/12/14: State machine ok with binary encoding but unstable with one hot encoding
19330: 99/12/14: Re: State machine ok with binary encoding but unstable with one hot encoding
19463: 99/12/22: Re: State machine ok with binary encoding but unstable with one hot encoding
19645: 00/01/06: BGA sockets and Virtex
22087: 00/04/20: Fast (> 100Mb) serial link to PC
22966: 00/06/06: Re: 3.3V I/O TO 5V LOGIC?
25895: 00/09/25: Using the xilinx "pull-up to 5V" in VHDL
25913: 00/09/26: Re: Using the xilinx "pull-up to 5V" in VHDL
25914: 00/09/26: Re: Using the xilinx "pull-up to 5V" in VHDL
25918: 00/09/26: Re: Using the xilinx "pull-up to 5V" in VHDL
25920: 00/09/26: Re: Using the xilinx "pull-up to 5V" in VHDL
25966: 00/09/28: FPGA Express pb
25974: 00/09/28: Re: FPGA Express pb
25977: 00/09/28: Re: FPGA Express pb
25995: 00/09/29: Xilinx 2.1 to 3.1 pb
25998: 00/09/29: Re: Xilinx 2.1 to 3.1 pb
29715: 01/03/06: Re: Parallel Port EPP
30162: 01/03/26: Logic trimmed (XCS40 F3.1)
30170: 01/03/27: Re: Logic trimmed (XCS40 F3.1)
30421: 01/04/07: Synchronous demodulation in FPGA
34199: 01/08/16: Virtex-II and 5V devices
34219: 01/08/16: Re: Virtex-II and 5V devices
34228: 01/08/16: Re: Virtex-II and 5V devices
34241: 01/08/17: Re: Virtex-II and 5V devices
34266: 01/08/17: Re: Virtex-II and 5V devices
34945: 01/09/14: Re: A vs. X
34955: 01/09/15: Re: A vs. X
35850: 01/10/20: what is carry mode INC-F-CI ?
48362: 02/10/16: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
53030: 03/02/28: Re: PCB board design software vs outsourcing?
54727: 03/04/16: Re: Xilinx has released SpartanIII
57840: 03/07/08: phase noise in NCO
57867: 03/07/09: Re: phase noise in NCO
57868: 03/07/09: Re: phase noise in NCO
57869: 03/07/09: Re: phase noise in NCO
58052: 03/07/13: Re: phase noise in NCO
58053: 03/07/13: Re: phase noise in NCO
58055: 03/07/14: Re: phase noise in NCO
87421: 05/07/23: Fastest way to compute floating point log and exp
87452: 05/07/24: Re: Fastest way to compute floating point log and exp
87453: 05/07/24: Re: Fastest way to compute floating point log and exp
88486: 05/08/19: Best FPGA for floating point performance
88493: 05/08/19: Re: Best FPGA for floating point performance
88495: 05/08/19: Re: Best FPGA for floating point performance
88496: 05/08/19: Re: Best FPGA for floating point performance
88500: 05/08/20: Re: Best FPGA for floating point performance
88711: 05/08/25: Re: Best FPGA for floating point performance
89018: 05/09/02: SI considerations for single chip memory configurations
105246: 06/07/18: Re: NAND flash hangs
111543: 06/11/05: Re: Scientific Computing on FPGA
111575: 06/11/06: Re: Scientific Computing on FPGA
116191: 07/03/04: Large power planes vs. power islands vs. slits for decoupling
116225: 07/03/05: Re: Large power planes vs. power islands vs. slits for decoupling
116227: 07/03/05: Re: Large power planes vs. power islands vs. slits for decoupling
116259: 07/03/06: Re: Bypass caps, X2Y and 'puddles'.
116279: 07/03/06: Re: Bypass caps, X2Y and 'puddles'.
116280: 07/03/06: Re: Large power planes vs. power islands vs. slits for decoupling
116284: 07/03/06: Re: Bypass caps, X2Y and 'puddles'.
116290: 07/03/06: Re: Large power planes vs. power islands vs. slits for decoupling
118162: 07/04/18: Any recommendation for proto PCB
121008: 07/06/21: Re: Nios II problem
121010: 07/06/21: Re: Interesting problems about high performance computing
121820: 07/07/13: Re: highly-parallel highspeed connection between two FPGA boards
121858: 07/07/13: What is the resistance of a big FPGA for VCCINT (unpowered)
121873: 07/07/14: Re: What is the resistance of a big FPGA for VCCINT (unpowered)
121940: 07/07/15: Re: What is the resistance of a big FPGA for VCCINT (unpowered)
122198: 07/07/23: Re: FPGA for HPC
128349: 08/01/22: Re: FPGA decoupling calculation
128367: 08/01/23: Re: FPGA decoupling calculation
Marc Boulais:
4458: 96/10/31: Re: Weird pre-config VCC-GND short in Altera or Xilinx
5198: 97/01/30: Re: Altera support better than Xilinx
10967: 98/07/07: Re: Need to know Xilinx M1.4's routing times -- large(?) designs
Marc D Bumble:
30548: 01/04/13: Re: pseudo random numbers
Marc Daumas:
9398: 98/03/09: Re: Floating point representation on FPGA
9566: 98/03/24: Re: New radix-4 CORDIC for computing sine and cosine
Marc David Bumble:
2997: 96/03/11: Reconfigurable Computing Languages
6141: 97/04/16: Re: Exponential function architecture
Marc Delvaux:
13200: 98/11/19: Re: Content Addressable Memorys
17491: 99/07/31: Re: Semi-deterministic behaviour in FPGA's
17498: 99/08/02: Re: Semi-deterministic behaviour in FPGA's
Marc Elpel:
21819: 00/04/02: Re: 82C54
Marc Faure:
30914: 01/05/03: Re: FPGA based PCI cards
Marc Guardiani:
50001: 02/11/27: Re: Frequency multiplier with digital h/w
56709: 03/06/11: Re: Xilinx Spartan 2 and global reset/clock buffer
56831: 03/06/16: Re: XILINX Error Message
57926: 03/07/09: Re: okay what am I missing??? Please
58608: 03/07/28: Re: help neede-----Error Pack 1107 -Unable to combine the following
58688: 03/07/30: Re: ALTERA Byte BlasterII
58689: 03/07/30: Re: tri-State buffer troubles ...
58865: 03/08/03: Re: Unused Pins on big Virtex-II
59235: 03/08/12: Re: Xilinx ISE error
60444: 03/09/13: Re: Webpack Vs. ISE
60445: 03/09/13: Re: What are Pull ups?
60459: 03/09/13: Re: Webpack Vs. ISE
60660: 03/09/19: Re: HDL Bencher for ISE5.1 Version
61247: 03/10/01: Re: ISE WebPack 6.1 Impact problem
61316: 03/10/01: Re: ISE WebPack 6.1 Impact problem
61392: 03/10/02: Re: ISE 6.1 Dies Out of the Gate
62083: 03/10/18: Re: ISE5.2 to ISE6.1
62359: 03/10/28: Re: Altera ACEX1K configuration and initialisation
62580: 03/11/02: Re: Xilinx Weback 6.1i - Java Exception
62908: 03/11/11: Re: ISE 5.2 to 6.1
63078: 03/11/14: Re: Archiving Projects
63349: 03/11/20: Re: Apex power calculator
64786: 04/01/14: Re: Xilinx ECS - connecting a single net to multiple bus lines?
64891: 04/01/15: Re: Please help with Xilinx ISE Schematic question
65835: 04/02/07: Re: Xilinx webpack
66407: 04/02/19: Re: regarding synchronization
66731: 04/02/26: Re: Xilinx webpack 6.1.03i error
66880: 04/02/28: Re: Xilinx ISE Impact crashes during configuration
67932: 04/03/23: Re: XC95288 easy to crack?
68298: 04/04/01: Re: XAPP134's VHDL code
69236: 04/05/01: Re: Connecting a crystal to a Cyclone or Max PLD
69723: 04/05/19: Re: IBUFG incapable of driving both CLKDLL and BUFG simultaneously?
69889: 04/05/23: Re: strange behaviour of the design
71808: 04/07/31: Re: Xilinx is still in YEAR 2003 ?
94166: 06/01/06: Re: Schematic Entry, Xilinx or Altera?
94313: 06/01/09: Re: Beginner help with VHDL, Xilinx 9536XL, and ISE7.1
94749: 06/01/17: Re: Just want to program Xilinx CPLD device from JEDEC file using ISE8.1
98772: 06/03/16: Re: Why Xilinx does not specify clock to output MINIMUM time???
99500: 06/03/25: Re: Installing ISE 8.1i - don't use a space in the install path
103459: 06/06/02: Re: clockless arbiters on fpgas?
107549: 06/08/29: Re: Quartus software and dual-purpose pins
108398: 06/09/10: Re: bidirectional connection between two bidirectional ports
111820: 06/11/10: Re: Non deterministic behaviour in quartus II ?
113267: 06/12/09: Re: JTAG programming of Altera Cyclone and CONF_DONE
113552: 06/12/16: Re: JTAG programming of Altera Cyclone and CONF_DONE
147260: 10/04/21: Re: Xilinx no longer ships with Modelsim MXE?
152399: 11/08/18: Re: Spartan6 PCB debugging: how badly do you have to screw up for
Marc Heuler:
7997: 97/11/05: ABEL HDL state machine question
8201: 97/11/26: Re: what is metastability time of a flip_flop
11393: 98/08/09: Gray code counter in ABEL HDL?
Marc Jet:
141326: 09/06/18: ISC_DNA over JTAG in Spartan3A-DSP?
142008: 09/07/21: Re: Is it possible to encrypt an existing bit file with BitGen?
143517: 09/10/14: Power consumption of FF
143661: 09/10/20: Re: Dealing with SPI ADC timings
146699: 10/03/26: Re: Newbie Coding Question
146960: 10/04/05: Re: XSVF player that writes V4 key
147103: 10/04/14: Re: Module wise FPGA resource utilization report
147429: 10/04/27: Re: Booting Linux from my own bootloader
147471: 10/04/28: Re: Booting Linux from my own bootloader
147894: 10/05/31: Effect of fanout on route delay (Spartan3)
147905: 10/06/01: Re: Anyone else need bigger parts in small (low pin count) packages
147918: 10/06/02: Re: Anyone else need bigger parts in small (low pin count) packages
148783: 10/08/23: Re: TCP Client using lwIP API
150134: 10/12/16: Re: Xilinx support makes me want to scream
150756: 11/02/09: Re: FPGA changes behaviour when the resource's usage percentage changes
150870: 11/02/17: Re: Simulation vs. Hardware mismatch
151262: 11/03/18: Re: pcb&bitstream
151326: 11/03/23: Re: Xilinx EDK - max array size
151474: 11/04/12: Re: Source of Dynamic Power Consumption in FPGAs
151615: 11/04/26: Re: advice needed for FPGA chip selection
151661: 11/05/03: Re: help with a power pc processor based software
151667: 11/05/03: Re: about slices in xilinx
152091: 11/07/05: Re: How do they handle shorts during the dynamic reconfiguration?
152595: 11/09/16: Re: clock enable for fixed interval
152596: 11/09/16: Re: clock enable for fixed interval
Marc K.:
22638: 00/05/15: Re: ? economical SPROM programmer for Xilinx
22453: 00/05/09: Re: virtex e lvds clock recovery
22637: 00/05/15: Re: CLKing external RAM from FPGA (Virtex E)
22639: 00/05/15: Re: Virtex clock buffers
22649: 00/05/16: Re: CLKing external RAM from FPGA (Virtex E)
22662: 00/05/16: Re: Propogation Delay
22707: 00/05/18: Re: Propogation Delay
22709: 00/05/19: Re: CLKing external RAM from FPGA (Virtex E)
22765: 00/05/23: Re: CLKing external RAM from FPGA (Virtex E)
22818: 00/05/25: Re: PCI core
22820: 00/05/25: Re: CRC
Marc Kelly:
53326: 03/03/10: Xilinx Post Place & Route VHDL output.
70484: 04/06/17: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
75199: 04/10/28: Xilinx V-II BUFGMUX oddities..
75232: 04/10/30: Re: Xilinx V-II BUFGMUX oddities..
104125: 06/06/19: Virtex-4FX embeded MAC and Rocket-IO data corruption??
104131: 06/06/19: Re: Virtex-4FX embeded MAC and Rocket-IO data corruption??
104132: 06/06/19: Re: Virtex-4FX embeded MAC and Rocket-IO data corruption??
104135: 06/06/19: Re: Virtex-4FX embeded MAC and Rocket-IO data corruption??
104178: 06/06/20: Re: Virtex-4FX embeded MAC and Rocket-IO data corruption??
106365: 06/08/12: Xilinx V4FX Embedded MAC.
115901: 07/02/24: Interfacing to 10Gig ethernet with Xilinx FPGAs
115905: 07/02/24: Re: Interfacing to 10Gig ethernet with Xilinx FPGAs
115907: 07/02/24: Re: Interfacing to 10Gig ethernet with Xilinx FPGAs
141055: 09/06/04: Help with Remote debugging ideas.
141080: 09/06/04: Re: Help with Remote debugging ideas.
141084: 09/06/04: Re: Help with Remote debugging ideas.
141126: 09/06/07: Re: Help with Remote debugging ideas.
Marc Klingelhofer:
23331: 00/06/22: Re: Problem copying text from the Spartan II data sheet
24358: 00/08/04: Packaging info overwhelms timing (was Who needs ... printed ac parameters?)
24999: 00/08/23: Re: Mealy vs Moore FSM model
28122: 00/12/21: Parallel clock termination (Was: 3V -> 5V clock signal level conversion)
38207: 02/01/08: Re: Repost: Should clock skew be included for setup time analysis?
39389: 02/02/07: Re: Xilinx ISE 3.3 upgrade to 4.1
Marc Le Roy:
67526: 04/03/13: Re: about edif
67848: 04/03/21: Re: Added example VC++ program to download XIlinx FPGAs
82687: 05/04/16: Differential timing specification in Xilinx FPGA
Marc Levy:
13878: 98/12/30: Re: Xilinx XC4000 cinfigured from EPC2?
Marc Matthey:
25196: 00/08/30: Re: Synthesis
marc Nance:
40925: 02/03/18: Re: How do I simulate two separate designs simutaneously in ModelSim XE?
Marc Palmarini:
3631: 96/07/05: FPGA vs CPLD
Marc Patrick Kelly:
53348: 03/03/11: Re: Xilinx Post Place & Route VHDL output.
Marc Peter:
14368: 99/01/27: Cheap P&R tool for Xilinx 3K series?
Marc R:
72972: 04/09/09: JTAG Connection For PPC Using VisonProbe V2PRO V2P30
Marc Randolph:
41411: 02/03/27: Re: Maximum device usage for successful PAR
42630: 02/04/29: Re: DCM off chip deskew
42675: 02/04/30: Re: Xilinx Easypath- Selling parts with known defects
43420: 02/05/21: Re: How to generate fractional-N clock ?
43624: 02/05/27: Re: footprint competabilty in virtex-II devices
43698: 02/05/29: Re: virtex 2 : DCM divided clock
44021: 02/06/10: Re: Cascaded PROMS
44536: 02/06/22: Re: Bad Virtex2 devices - any similar experiences
44581: 02/06/24: Re: Clock enable & Synplify 7.1
44646: 02/06/25: Re: Clock enable & Synplify 7.1
44695: 02/06/27: Re: Clock enable & Synplify 7.1
44896: 02/07/04: Re: Virtex II - IO TILE, IOB PAD #4
45562: 02/07/26: Re: Xilinx DCMs, RST, and phase coherence
45754: 02/08/04: Re: a chip which can trans ethenet data through E1 interface
47352: 02/09/24: Re: Altera Cyclone low-cost FPGA chips?
47385: 02/09/24: Re: Altera Cyclone low-cost FPGA chips?
47421: 02/09/25: Re: Unpredictable Place and Route
47455: 02/09/25: Re: Altera Cyclone low-cost FPGA chips?
47492: 02/09/26: Re: Altera Cyclone low-cost FPGA chips?
48062: 02/10/10: Re: Why can Xilinx sw be as good as Altera's sw?
48384: 02/10/16: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
48424: 02/10/17: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
48716: 02/10/23: Re: Silly Virtex 2 Pro question...
49546: 02/11/14: Re: Has anyone tried Lattice's chips?
50353: 02/12/09: Re: virtex output pin voltage
50551: 02/12/12: Re: VirtexII pin assignments/signal flow
50565: 02/12/12: Re: VirtexII pin assignments/signal flow
51269: 03/01/09: Re: External RAM...
51415: 03/01/13: Re: DLL/PLL with global clock net
51638: 03/01/17: Re: How can I use DCM to 1/24 freq-division?
51714: 03/01/20: Re: How can I use DCM to 1/24 freq-division?
52537: 03/02/12: Re: USB2 or firewire or 100Mb ethernet link to FPGA design
52677: 03/02/18: Re: Flop count..
52745: 03/02/20: Re: PCB Design for a Xilinx Spartan-II FPGA
52800: 03/02/22: Re: spartan III what is it?
52990: 03/02/27: Re: several fpga high bandwidth questions
53077: 03/03/03: Re: Virtex II - Driving more than one global clock net from one incoming clock pin
53219: 03/03/06: Re: Issues in Outsourcing?
53262: 03/03/08: Re: Clocking a spartanIIE with a 5V signal?
53455: 03/03/13: Re: RESET --- Synchronous Vs Asynchronous
53887: 03/03/26: Re: Virtex II pro board design question
53914: 03/03/27: Re: Virtex II pro board design question
53978: 03/03/28: Re: Spartan vs. Cyclone for arithmetic functions
54071: 03/04/01: Re: Spartan vs. Cyclone for arithmetic functions
54329: 03/04/08: Re: Q: Constraints for high speed I/O signals.
54716: 03/04/16: Re: spartan 3 pin compatible with 2E?
54980: 03/04/23: Re: Xilinx has released SpartanIII
55007: 03/04/24: Re: Xilinx has released SpartanIII
55183: 03/04/29: Re: Virtex-II DCM frequency synthesizer
55191: 03/04/29: Re: Virtex-II DCM frequency synthesizer
55548: 03/05/12: Re: CRC Generator for 6Byte serial Transmission
55573: 03/05/12: Re: Exploting the DDR input registers in Virtex2
55926: 03/05/23: Re: Virtex2 DCM CLKIN_PERIOD
56142: 03/05/29: Re: 20 to 5 encoder optimization?
56147: 03/05/29: Re: FIFO Controller
56171: 03/05/29: Re: FIFO Controller
56275: 03/06/02: Re: SONET/SDH chipset on FPGA
56500: 03/06/06: Re: Quartus II time delay
56580: 03/06/09: Re: Shift registers
56604: 03/06/10: Re: Shift registers
56855: 03/06/17: Re: Implementaion of Mux-DFF with Virtex ..
57142: 03/06/24: Re: Transfer between clock domains at 350 MHz
57241: 03/06/26: Re: Xilinx Webpack bugs bugs bugs
57319: 03/06/27: Re: multiple asychronous resets
57672: 03/07/03: Re: Cyclone vs Spartan-3
57715: 03/07/04: Re: DCM usage question
58597: 03/07/28: Re: CRC questions
58776: 03/08/01: Re: 5 volt tolerant Xilinx parts
59272: 03/08/13: Re: Xilinx DLL driving multiple off chip clocks
60396: 03/09/11: Re: Paging Peter Alfke (3S1000 pricing)
60890: 03/09/24: Re: Configuration Options:
61212: 03/09/30: Re: Bit error rate
61511: 03/10/06: Re: Timing from 1x to 2x and back
61523: 03/10/06: Re: Should I worry about metastability
61557: 03/10/06: Re: Should I worry about metastability
61627: 03/10/08: Re: Xilinx DCMs, DDR, CLK0, and CLK180
62572: 03/11/02: Re: Some FPGA questions
62765: 03/11/07: Re: Crossing/muxing clocks thru TBUF mux (w/DLL "stunts")
62814: 03/11/08: Re: Virtex II DCM & ZBT SRAM
62832: 03/11/09: Re: FPGAs and DRAM bandwidth
62882: 03/11/10: Re: Unconstrained net to DLL's
63065: 03/11/13: Re: How to bring PLL's output to Pin_F1
63118: 03/11/15: Re: Do I need to connect all Vref in a bank together?
63367: 03/11/20: Re: How to RLOC adders in VHDL/Synplify to avoid broken carry chains?
63375: 03/11/20: Re: State Machines....
63376: 03/11/20: Re: How to RLOC adders in VHDL/Synplify to avoid broken carry chains?
63435: 03/11/21: Re: verification vs validation
63495: 03/11/24: Re: Aurora_401 reference allows 8B/10B bypass?
63662: 03/11/27: Re: [VirtexII + DCM + newbie] problems with the clocksignals from
63715: 03/12/01: Re: programmable fir and simulation
63761: 03/12/03: Re: Xilinx Virtex-II: DCM int & ext feedback
63806: 03/12/04: Re: Xilinx Virtex-II: DCM int & ext feedback
63965: 03/12/10: Re: Easypath question (was "Hard-tocopy" rant)
64041: 03/12/13: Re: advantages of ethernet MAC ip core
64436: 04/01/04: Re: please help! state machine
65003: 04/01/18: Re: 802.3 mii
65151: 04/01/21: Re: changing values in a fifo
66907: 04/02/29: Re: difference btw H/W & S/W implementations !!
67336: 04/03/10: Re: A hardware question?
67345: 04/03/10: Re: LVDS
67468: 04/03/12: Re: Issues in Rocket I/O
67528: 04/03/13: Re: XAPP607: Is this just paperwork or based on a real design
67571: 04/03/14: Re: Issues in Rocket I/O
67662: 04/03/16: Re: Difficulties fitting a design into a Xinlinx Virtex-II XC2V6000
67665: 04/03/16: Re: ISE 6.2 (w/ SP#1) is 10+ times slower than 6.1
67667: 04/03/16: Re: ISE 6.2 (w/ SP#1) is 10+ times slower than 6.1
67841: 04/03/20: Re: Xilinx timing analyzer
67855: 04/03/21: Re: Xilinx map -timing through ise gui
68100: 04/03/26: Re: Xilinx map -timing through ise gui
68112: 04/03/26: Re: Switching clocks in FPAG internal clock trees
68800: 04/04/19: Re: Xilinx Rocket IO CRC+Clock Corrections results in CRC error
68984: 04/04/23: Re: Xilinx XST problems packing signals into IOB registers...
69027: 04/04/25: Re: Inferring Dynamic shift registers in XST
69101: 04/04/27: Re: Design PAR in Stratix
69296: 04/05/05: Re: Max7000s: how to use the enable of the dffe flip-flop?
69320: 04/05/06: Re: Max7000s: how to use the enable of the dffe flip-flop?
69391: 04/05/10: Re: Serial Data Capture
69434: 04/05/11: Re: FPGA vs Microprocessor: newbie question
69653: 04/05/17: Re: load on a clock signal in FPGA
70130: 04/06/03: Re: tri-state in altera
70211: 04/06/09: Re: V4 teaser, correction
70212: 04/06/09: Re: xilinx gigabit MAC core full vs half duplex
70986: 04/07/04: Re: crc32 vhdl implementation (4 bit data)
71008: 04/07/05: Re: crc32 vhdl implementation (4 bit data)
71037: 04/07/06: Re: crc32 vhdl implementation (4 bit data)
71065: 04/07/07: Re: crc32 vhdl implementation (4 bit data)
71298: 04/07/13: Re: synchronus reset on bufg? (xilinx)
71985: 04/08/05: Re: xilinx: non LOC pins causing havoc
72026: 04/08/05: Re: xilinx: non LOC pins causing havoc
72188: 04/08/10: Re: Example of network router and # of LUTs utilized - Searching
72458: 04/08/19: Re: A timer with Celoxica RC100
72676: 04/08/28: Re: 16-depth FIFO and 64-depth FIFO use the same Ram
73757: 04/09/29: Re: luts are optimized away
73038: 04/09/11: Re: Need some help with some technical claims...
75142: 04/10/26: Re: Best Place and Route
75282: 04/11/01: Re: XST: suppressing incorrect optimizations in VHDL code
74109: 04/10/04: Re: does ISE 6.3 improve timing vs. ISE 6.2 ?
74420: 04/10/11: Re: Interfacing an 1GS ADC
75321: 04/11/02: Re: XST: suppressing incorrect optimizations in VHDL code
74338: 04/10/08: Re: Interfacing an 1GS ADC
74570: 04/10/14: Re: GLKP and GLKS
75425: 04/11/05: Re: Xilinx Maximum output required time after clock
75457: 04/11/06: Re: IO Timing constraints with internal clocks
75581: 04/11/10: Re: Overshoot/undershoot towards 2V4000
75610: 04/11/10: Re: VirtexII-Pro MGT: 8/10 coding bypass problems
75726: 04/11/13: Re: Spartan3 Block RAM from WebPACK
76223: 04/11/29: Re: XST question
76476: 04/12/03: Re: making an fpga hot
76497: 04/12/04: Re: Virtex-II PRO, DDR2 SDRAM, RocketIO
76609: 04/12/07: Re: Virtex-II PRO, DDR2 SDRAM, RocketIO
76704: 04/12/09: Re: Virtex-II PRO, DDR2 SDRAM, RocketIO
76756: 04/12/10: Re: Floorplanning with only usage estimates. Is it possible?
76832: 04/12/13: Re: Virtex-II PRO, DDR2 SDRAM, RocketIO
76844: 04/12/14: Re: Newbie question: fitting in cpld
76879: 04/12/15: Re: Linking FPGAs with RocketIOs
76962: 04/12/17: Re: Inferring SRLs with INIT value
77016: 04/12/20: Re: Using low-core-voltage devices in industrial applications
77096: 04/12/22: Re: MAP failes after inserting ILA and ICON cores to the design
77114: 04/12/23: Re: MAP failes after inserting ILA and ICON cores to the design
77213: 04/12/30: Re: Rocket I/O Fail modes/problems help
77235: 04/12/31: Re: Newbie looking for multiported-RAM to interface to a Spartan-III
77243: 05/01/01: Re: Altera NIOS II/Stratix II vs Xilinx Products
77304: 05/01/04: Re: code fragment causes error during bitstream generation... ISE 6.2 & Spartan3
77408: 05/01/06: Re: Utilisation of Xilinx FPGAs
77459: 05/01/07: Re: Utilisation of Xilinx FPGAs
77512: 05/01/08: Re: a general question
77897: 05/01/19: Re: LVDS through connectors
77909: 05/01/20: Re: LVDS through connectors
78053: 05/01/23: Re: question regarding the physical dimensions of FPGAs
78068: 05/01/24: Re: question regarding the physical dimensions of FPGAs
78126: 05/01/25: Re: Impact errors programing V4LX25
78490: 05/02/01: Re: Pericom PI6C2404 equivalent
79000: 05/02/10: Re: Local clocking in spartan 3
79001: 05/02/10: Re: theta(jb) for V2-PRO in FG676
79020: 05/02/11: Re: RocketIO in 32-bit Mode
79063: 05/02/12: Re: xilinx MGT compatibility?
79252: 05/02/15: What do future FPGA's need? (was: Updated S2 Power specs)
79266: 05/02/16: Re: Virtex4: On using a LC clock pin for global clock.
79296: 05/02/16: Re: What do future FPGA's need? (was: Updated S2 Power specs)
79297: 05/02/16: Re: What do future FPGA's need? (was: Updated S2 Power specs)
79298: 05/02/16: Re: clock split approach for 270MHz design in Spartan2E
79530: 05/02/20: Re: hdl:lament
79581: 05/02/21: Re: Antti Lukats: all my past live projects to be published...
79671: 05/02/22: Re: FPGA board with best cost/CLB ratio?
79957: 05/02/26: Re: Fast 28x28 multiplier + adder in Virtex4
80057: 05/02/28: Re: virtex4 virtex-4 FX eval board
80137: 05/03/01: Re: RocketIO, where to start?
80176: 05/03/02: Re: Missing Virtex4 Speedfile
80177: 05/03/02: Re: Xilinx ISE7.1
80264: 05/03/02: Re: Virtex4 : speed improvement
80265: 05/03/02: Re: bad synchronous description error
80487: 05/03/07: Re: VoIP & FPGA
80627: 05/03/09: Re: Xilinx vs Altera high-end solutions
80674: 05/03/09: Re: Global Reset paths
80675: 05/03/09: Re: Xilinx vs Altera high-end solutions
80741: 05/03/10: Re: Xilinx vs Altera high-end solutions
80743: 05/03/10: Re: RocketIO and Gigabit Ethernet
80744: 05/03/10: Re: ethernet core on a xc3s200
80745: 05/03/10: Re: 1,5Mhz Clock
80746: 05/03/10: Re: Global Reset paths
80778: 05/03/11: Re: Global Reset paths
80779: 05/03/11: Re: Xilinx vs Altera high-end solutions
80830: 05/03/11: Re: RocketIO and Gigabit Ethernet
80998: 05/03/15: Re: Xilinx ISE and IP cores
81000: 05/03/15: Re: Memory gate count in ASIC and in FPGA
81052: 05/03/16: Re: Memory gate count in ASIC and in FPGA
81148: 05/03/18: Re: Xilinx ISE and IP cores
81209: 05/03/19: Re: Is an XC3S1500 enough to implement a MP@ML MPEG-2 decoder?
81210: 05/03/19: Re: (Stupid/Newbie) Question on UART
81212: 05/03/19: Re: One-hot statemachine design problems
81213: 05/03/19: Re: Stratix II vs Virtex 4
81228: 05/03/19: Re: Spartan 3E vs. Cyclone2
81232: 05/03/19: Re: (Stupid/Newbie) Question on UART
81334: 05/03/21: Re: rocketio
81422: 05/03/23: Re: clock division using DCM, how?
81423: 05/03/23: Re: changing DDR2 pin LOC on UCF generated by MIG for virtex4
81471: 05/03/24: Re: (Stupid/Newbie) Question on UART
81492: 05/03/24: Re: LVPECL, Virtex II and the EP445
81504: 05/03/25: Re: LVPECL, Virtex II and the EP445
81517: 05/03/25: Re: LVPECL, Virtex II and the EP445
81543: 05/03/26: Re: Multi-FPGA PCB data aggregation?
81555: 05/03/27: Re: Multi-FPGA PCB data aggregation?
81557: 05/03/27: Re: some +. for Altera
81584: 05/03/28: Re: Multi-FPGA PCB data aggregation?
81613: 05/03/28: Re: Multi-FPGA PCB data aggregation?
81746: 05/03/30: Re: Achieving required speed in Virtex-II Pro FPGA
81748: 05/03/30: Re: Driving two DCM with same clock input pad.
81768: 05/03/31: Re: Achieving required speed in Virtex-II Pro FPGA
81794: 05/03/31: Re: One or two DLLs for a SDRAM controller?
81809: 05/04/01: Re: Virtex DCM phase alignment and CLK2X registering
81900: 05/04/04: Re: IBUFG and BUFG +xilinx
81901: 05/04/04: Re: Xilinx XPower - Accuracy Information
81964: 05/04/05: Re: One or two DLLs for a SDRAM controller?
82035: 05/04/05: Re: Xilinx V2-Pro + Select Map programming
82131: 05/04/07: Re: Stupid question
82189: 05/04/08: Re: Clock Jitter on Xilinx FPGA
82379: 05/04/11: Re: Timing
82380: 05/04/11: Re: ISE 7.1 for 64 bit Linux ???
82411: 05/04/12: Re: Global buffer feeding non clock pins in VIRTEX II
82453: 05/04/12: Re: Global buffer feeding non clock pins in VIRTEX II
82480: 05/04/13: Re: Simulation and actual FPGA implementation, how different it is?
82540: 05/04/13: Re: virtex4 reconfiguration time
82617: 05/04/14: Re: virtex4 reconfiguration time
82618: 05/04/14: Re: Fitting functionality in an XC2VP30 FPGA.
82622: 05/04/14: Re: clock input over an I/O pin
82673: 05/04/15: Re: clock input over an I/O pin
82738: 05/04/17: Re: Spartan 3E slower that Spartan 3?
82742: 05/04/17: Re: Xilinx tools from the commandline
82801: 05/04/18: Re: Xilinx tools from the commandline
83344: 05/04/27: Re: Sync + FIFO
83493: 05/05/01: Re: current price for (small quantity) XC4VFX12/FF668
83504: 05/05/01: Re: Virtex4 and ISE reality check?
83565: 05/05/03: Re: Max freq. of operation in FPGA?
83567: 05/05/03: Re: Xilinx tools from the commandline
83617: 05/05/03: Re: Max freq. of operation in FPGA?
83737: 05/05/05: Re: System Ace: How many FPGA's in the JTAG chain before require buffers?
83814: 05/05/06: Re: Multiple Virtex 2 Pro's, DCM and CLKIN_DIVIDE_BY_2
83990: 05/05/10: Re: Multiple Virtex 2 Pro's, DCM and CLKIN_DIVIDE_BY_2
84062: 05/05/11: Re: Slice Virtex II = Equivalent gates ??
84369: 05/05/17: Re: Registers replication on Xilinx IOBs
84387: 05/05/18: Re: VHDL array question
84428: 05/05/18: Re: VHDL array question
84435: 05/05/18: Re: How many logic cells are there in one slice
84451: 05/05/19: Re: How many logic cells are there in one slice
84603: 05/05/22: Re: Virtex4 Block Ram : ISE6.3 Problem
84661: 05/05/24: Re: re:FSM stops working
84663: 05/05/24: Re: Nondeterministic ISE Placement
84664: 05/05/24: Re: Xilinx Answer Record 21127
84866: 05/05/31: Re: Timing summary
85148: 05/06/06: Re: Magical Mystery Tour of ISE environment variables
85549: 05/06/10: Re: floorplanning
85555: 05/06/10: Re: computer upgrade time.
85572: 05/06/10: Re: computer upgrade time.
85608: 05/06/11: Re: OrCAD Symbol For Xilinx V2PRO
85909: 05/06/17: Re: Xlinix configuration: DONE pin too early?
85993: 05/06/19: Re: FPGAs: Where will they go?
86000: 05/06/20: Re: ISE 7.1 Service Pack 2 - Ready yet?
86335: 05/06/25: Re: ISE 7.1 Service Pack 2 - Ready yet?
86346: 05/06/25: Re: ISE 7.1 Service Pack 2 - Ready yet?
86506: 05/06/29: Re: V4 and NBTI question, again..
86507: 05/06/29: Re: Good FPGA for an encryptor
86572: 05/06/30: Re: V4 and NBTI question, again..
87236: 05/07/19: Re: July 20th Altera Net Seminar: Stratix II Logic Density
87246: 05/07/20: Re: July 20th Altera Net Seminar: Stratix II Logic Density
87342: 05/07/21: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87344: 05/07/21: Re: Xilinx software update?
87365: 05/07/21: Re: July 20th Altera Net Seminar: Stratix II Logic Density
87671: 05/07/27: Re: Delay Generators in FPGAs
87709: 05/07/28: Re: Delay Generators in FPGAs
87710: 05/07/28: Re: Virtex4 local clock timing
87883: 05/08/03: Re: RocketIO connexion to an optical transceiver
87938: 05/08/03: Re: RocketIO connexion to an optical transceiver
87951: 05/08/04: Re: RocketIO connexion to an optical transceiver
88286: 05/08/14: Re: Clock for serializer with a Spartan3
88516: 05/08/21: Re: Using very large number in VHDL
88574: 05/08/23: Re: Different Synthesis Results on Different Levels of Hierarchy (different amount of occupying slices)
88575: 05/08/23: Re: Using very large number in VHDL
88638: 05/08/24: Re: Send IP packets at the Ethernet level with VIRTEX4
88750: 05/08/27: Re: infering a BRAM block for a dual ported ROM
88752: 05/08/27: Re: ISE 7.1 and DCM clkfx
88753: 05/08/27: Re: SERDES
88850: 05/08/30: Re: infering a BRAM block for a dual ported ROM
88948: 05/08/31: Re: Spartan 3 Serdes
88999: 05/09/02: Re: Spartan 3 Serdes
89490: 05/09/16: Re: DCM question
89743: 05/09/23: Re: 10G serial port with no FEC?
90838: 05/10/22: Re: clock frequency after RTL synthesis vs PAR
90844: 05/10/22: Re: clock frequency after RTL synthesis vs PAR
91777: 05/11/12: Re: Add files to Xilinx ISE Project w/script
93494: 05/12/22: Re: Place and Route Algorithms: where's the fat?
93720: 05/12/28: Re: Xilinx LVDS termination resistor
95666: 06/01/25: Re: encryption
96413: 06/02/03: Re: Back to max thermal and power for XC4VLX200's
96471: 06/02/03: Re: Back to max thermal and power for XC4VLX200's
97689: 06/02/26: Re: ERROR:MapLib:482
98143: 06/03/06: Re: Which CPU and Screen Rez for ISE 6.3i ?
98295: 06/03/08: "toys" = John
100288: 06/04/06: Re: Inferring SRL in Xilinx FPGA
100289: 06/04/06: Re: LVDS in Cyclone-II
100365: 06/04/07: Re: Inferring SRL in Xilinx FPGA
100930: 06/04/21: Re: Bluetooth with FPGA?????
102632: 06/05/18: Re: Reality of V5 as ES
102919: 06/05/23: Re: xilinx pricing discrepancy
103176: 06/05/26: Re: ISE sends sensitive information to Xilinx site!------ Only if you say 'yes'
106274: 06/08/10: Re: ISE software bug???
106584: 06/08/15: Re: Large Spartan3 vs. Small V5
107049: 06/08/23: Re: Global signal conservation
109766: 06/10/05: Re: Generate 16MHz from 75MHz using DCM
110757: 06/10/21: Re: Inferring block ram in Spartan II with non standard bus sizes
116924: 07/03/20: Re: IOSTANDARD default value in Xilinx UCF-Files?
116926: 07/03/20: Re: Athlon X2 or Intel Dual Core for Xilinx ISE tools ?
121059: 07/06/24: Re: What wrong with the DCM of Virtex4 in my project?
121299: 07/07/01: Re: intermitent boot in V4
122174: 07/07/22: Re: FIFO : Synchronous WRITE, Asynchronous READ ?
122181: 07/07/23: Re: Running Virtex5 GTP at lower data rate
122743: 07/08/06: Re: Single Ended signal in sync with V5 GTP
124536: 07/09/26: Re: Logic minimization software with LUT6 support?
124832: 07/10/06: Re: Virtex 13?
125230: 07/10/18: Re: FPGA quiz3, or where Antti did give up and does not know answer or acceptable workaround
126284: 07/11/19: Re: New Laptop for work
126955: 07/12/06: Re: clock lines
127003: 07/12/08: Re: Which FPGA and memory to use? The eternal X vs. A question.
127004: 07/12/08: Re: Which FPGA and memory to use? The eternal X vs. A question.
127031: 07/12/09: Re: Which FPGA and memory to use? The eternal X vs. A question.
127165: 07/12/12: Re: Xilinx RocketIO problems
127289: 07/12/17: Re: global clock (gclk) input at xilinx virtex4 fpga
129990: 08/03/12: Re: its regarding to the Max Frequency in xilinx FPGA
134409: 08/08/09: Re: Coolrunner programming - best way?
134539: 08/08/16: Re: A timing question
Marc Reinert:
20412: 00/02/09: Viterbi Dec. in VHDL (on Xilinx XC4000)
20475: 00/02/11: Re: Viterbi Dec. in VHDL (on Xilinx XC4000)
25606: 00/09/15: PCI-Tip? (for Xilinx Virtex/-E)
26107: 00/10/04: Re: Xilinx Licensing.
26171: 00/10/06: programm Xilinx FPGAs via JTAG
26220: 00/10/09: Re: programm Xilinx FPGAs via JTAG // so far, so good
26222: 00/10/09: Re: programm Xilinx FPGAs via JTAG // so far, so good
26486: 00/10/18: Virtex-E and ADC
26496: 00/10/18: Re: F3.1i, Win2k, LMACs
26502: 00/10/18: Re: Virtex-E and ADC
27582: 00/11/29: Selfmade Cores or something similar (Xilinx)
27825: 00/12/11: Cannot get chip's information from Synopsys
29685: 01/03/05: Parallel Port EPP
29745: 01/03/07: Re: Parallel Port EPP
35720: 01/10/15: JTAG-Programmer Linux
Marc Reinig:
83192: 05/04/25: Help creating a System Ace file
85474: 05/06/09: Re: ISE tools to use SMP?
86419: 05/06/27: Re: USB 2.0 core with 1.1 tranceiver problem
88946: 05/09/01: Re: usb and xc95
89360: 05/09/13: Re: Reading a PAL fusemap with a microscope
100381: 06/04/07: Re: USB Interface to Virtex-4
102462: 06/05/16: Re: Virtex 5 announced and sampling
104876: 06/07/07: Re: Chaos in FF metastability
105204: 06/07/17: Virtex 4, LVDS I/O: Sanity check please
105241: 06/07/18: Re: Virtex 4, LVDS I/O: Sanity check please
105249: 06/07/18: Re: Virtex 4, LVDS I/O: Sanity check please
105845: 06/08/01: Re: Implementing Haar Decomposition on 256 sample input using only sysgen blocks
111483: 06/11/03: Re: Scientific Computing on FPGA
111621: 06/11/07: Re: Scientific Computing on FPGA
125449: 07/10/25: Re: Paper about selecting fixed point bit widths?
128077: 08/01/14: Re: FPGA's as DSP's
129625: 08/02/29: Need info on systolic arrays in actual use
129631: 08/02/29: Re: Need info on systolic arrays in actual use
129647: 08/03/01: Re: Need info on systolic arrays in actual use
Marc Roche:
27645: 00/12/01: Re: jtag for fpga
Marc Van Riet:
50907: 02/12/22: Re: State of the PCB world
52016: 03/01/29: GNU C for custom processor
52075: 03/01/30: Re: GNU C for custom processor
54847: 03/04/20: Re: Is there any information about Xilinx bitstream file format?
56552: 03/06/09: Re: FPGA Development Board
57061: 03/06/23: Re: "Ethernet only" network
58867: 03/08/03: Re: Size does matter
58877: 03/08/04: Re: Size does matter
58992: 03/08/06: Re: Size does matter
63073: 03/11/13: Re: Building the 'uber processor'
Marc Verhoeven:
11783: 98/09/09: Re: DataIO + EPC1 problem
11794: 98/09/10: Re: DataIO + EPC1 problem
Marc Warden:
24759: 00/08/17: Re: Non-disclosures in job interviews
25598: 00/09/14: Re: hardware compatibility and patent infringement
27675: 00/12/02: Re: ANNOUNCE: Checksum and CRC Code/Article
27676: 00/12/02: Re: ANNOUNCE: Checksum and CRC Code/Article
Marc Weber:
121144: 07/06/26: Can FPGAs inputs detect low currents?
121161: 07/06/27: my project / FPGA as USB client ? (Re: Can FPGAs inputs detect low currents?)(
Marc-Eric Uldry:
31401: 01/05/22: inout signals between Viewdraw schematics and VHDL components
marc_ely:
110660: 06/10/19: Re: Using Opencores I2S master
110661: 06/10/19: Fastest ISE Compile PC?
110664: 06/10/19: Fixing Down Parts of Logic in ISE (8.2)
110704: 06/10/20: Re: FAQ: Re: Fastest ISE Compile PC?
111131: 06/10/30: Re: Fastest ISE Compile PC?
113531: 06/12/15: Xilinx ISE 8.2.3 - Re-Creating Projects
113532: 06/12/15: Xilins ISE Re-Creating Projects
113582: 06/12/17: Re: Xilins ISE Re-Creating Projects
Marcel:
43359: 02/05/20: How to generate fractional-N clock ?
43361: 02/05/20: Re: How to generate fractional-N clock ?
44410: 02/06/19: Xilinx .bit file via jtag ?
44421: 02/06/19: Re: Xilinx .bit file via jtag ?
44548: 02/06/23: Xilinx webpack if - else if statement ??
44587: 02/06/24: Re: Xilinx webpack if - else if statement ??
45197: 02/07/15: Which is best method for register with settable and clearable bits
46435: 02/08/29: Re: sensing an oscillator
47271: 02/09/22: Re: Spartan II JTAG reconfiguration bug - workaround
47272: 02/09/22: Re: Cheap development package for beginner?
Marcel Melters:
27873: 00/12/13: Dual-ported RAM instantiation in Virtex-E ?
27879: 00/12/13: Re: Dual-ported RAM instantiation in Virtex-E ?
27910: 00/12/14: Re: Dual-ported RAM instantiation in Virtex-E ?
Marcel van de Burgwal:
123143: 07/08/17: iMPACT command for selecting remote host running CableServer?
Marcel Wattinger:
31205: 01/05/15: Virtex Handbook
Marceli Firlej:
38999: 02/01/29: MapLab:30 Error in ISE 4.1i
Marcello Lajolo:
4959: 97/01/04: Re: Flex 8K boot-up problem
marcelo:
145734: 10/02/21: Re: rocketio TX delay between sata0 and sata1
Marcelo:
145703: 10/02/19: Re: rocketio TX delay between sata0 and sata1
Marcelo Enrique Moisan Naulin:
18144: 99/10/03: A question
Marcelo Moisan:
18168: 99/10/04: I need a Link
18493: 99/10/27: XACT
Marcelo Segura:
145751: 10/02/22: Re: rocketio TX delay between sata0 and sata1
145767: 10/02/22: Re: rocketio TX delay between sata0 and sata1
<marcelo.f.dantas@gmail.com>:
157733: 15/02/25: An Altera CPLD "JTAG Unlocker"
Marcin Czeczko:
6992: 97/07/20: GAL Programmer
Marcin E. Hamerla:
32015: 01/06/11: Re: Pin locking in Maxplus2
38857: 02/01/26: Problem with Altera programmer
38878: 02/01/27: Re: Problem with Altera programmer
38929: 02/01/28: Re: Problem with Altera programmer
39222: 02/02/04: Re: Destroying a CPLD by JTAG
39229: 02/02/04: Re: Destroying a CPLD by JTAG
44498: 02/06/21: Re: Help!I can't use the programmer of Max-plus II on windows XP.
47155: 02/09/19: Re: using CPLD's inverter in oscillator circuit
48832: 02/10/25: Re: maxplus2 on WinXP
48958: 02/10/28: Re: Porting from Xilinx to Altera?
49028: 02/10/30: Re: Altera 1k100 serial EEPROM
49863: 02/11/22: Re: BGA footprints
49868: 02/11/22: Re: BGA footprints
49893: 02/11/24: Re: BGA footprints
51709: 03/01/20: FLEXlm
51752: 03/01/21: Re: FLEXlm
51785: 03/01/21: Re: FLEXlm
51800: 03/01/22: Re: FLEXlm
52132: 03/02/02: Re: How to program Altera EPC1213
52477: 03/02/11: Re: What is wrong with Altera Website?
54408: 03/04/10: Re: Cheap(er) FPGA configuration?
Marcin Michalak:
30154: 01/03/26: Asynchronus Mashine States
30180: 01/03/27: Re: Asynchronus Mashine States
Marcin Olak:
75459: 04/11/06: Problem with Nios Development Board (Cyclone)
75460: 04/11/06: Re: Problem with Nios Development Board (Cyclone)
76133: 04/11/25: 386 IP Core
76142: 04/11/25: Re: 386 IP Core
Marcin Piaskowski:
2898: 96/02/26: FPGA and testing
Marcin Rodzik:
148839: 10/09/01: parsing script arguments in QuestaSim/ModelSim
Marcio A. A. Fialho:
76144: 04/11/25: Searching for rad tolerant, non-volatile (once programmable) FPGA (or CPLD).
76400: 04/12/01: Re: Searching for rad tolerant, non-volatile (once programmable) FPGA (or CPLD).
<marcj@zwallet.com>:
marco:
32572: 01/06/30: free 8 bit cpu core and spartan2
93357: 05/12/20: Place and Route Algorithms
93407: 05/12/21: Re: Place and Route Algorithms
103537: 06/06/05: ProjectMgmt WARNING from ISE 8.1i XST
114167: 07/01/05: data transfer from fast APB clock domain.
114178: 07/01/06: Re: data transfer from fast APB clock domain.
Marco:
8458: 97/12/16: Adaptec SCSI AVA 1505 and DOS
32220: 01/06/20: AHDL & IDE
32692: 01/07/05: Altera ACEX
32825: 01/07/10: Re: Max+2 and multi-cycle timing analysis WAS: Altera ACEX
55864: 03/05/21: Re: Asynchronous State Machines and HDLs
75373: 04/11/03: Re: FPGA for Game and Amusement
78919: 05/02/10: HELP: Graphic LCD + Keypad + printer
78971: 05/02/10: Re: Graphic LCD + Keypad + printer
78982: 05/02/10: Sending text from fpga to printer
79044: 05/02/11: Re: Sending text from fpga to printer
79060: 05/02/12: Re: Sending text from fpga to printer
79203: 05/02/15: OPB IPIF HELP!!!
79450: 05/02/19: Graphic LCD
79477: 05/02/19: Re: Graphic LCD
79493: 05/02/20: Re: Graphic LCD
79526: 05/02/20: Re: Graphic LCD
80342: 05/03/04: VHDL Instantiation
80345: 05/03/04: 1,5Mhz Clock
80349: 05/03/04: RAM Address Calculating
80350: 05/03/04: Re: 1,5Mhz Clock
80382: 05/03/04: Re: 1,5Mhz Clock
80383: 05/03/04: Re: VHDL Instantiation
80417: 05/03/05: Synthesis with EDK 6.3
80431: 05/03/05: reading data from register and writing to ram
80436: 05/03/05: Re: reading data from register and writing to ram
80452: 05/03/06: State Machine Trouble
80458: 05/03/06: Re: State Machine Trouble
80466: 05/03/06: EST Guide
80484: 05/03/07: Re: EST Guide
80773: 05/03/11: How to make a stdout peripheral?
80780: 05/03/11: BFM Simulation Trouble
80782: 05/03/11: Core Generator Troubles
81150: 05/03/18: C Manual for Microblaze Software
82611: 05/04/15: Help OPB <> Wishbone wrapper
82817: 05/04/18: OPB to Wishbone Wrapper
83072: 05/04/22: A PC for make synthesis
83232: 05/04/26: Re: A PC for make synthesis
83240: 05/04/26: Re: A PC for make synthesis
83661: 05/05/04: Help
84154: 05/05/13: Handling Interrupt
84501: 05/05/20: ISE and Linux
84564: 05/05/21: Re: ISE and Linux
84570: 05/05/21: Re: ISE and Linux
84572: 05/05/21: Re: ISE and Linux
84575: 05/05/21: How to make a 1.44MHz clock?
84586: 05/05/22: Re: How to make a 1.44MHz clock?
84587: 05/05/22: Re: How to make a 1.44MHz clock?
84631: 05/05/23: Re: How to make a 1.44MHz clock?
84801: 05/05/27: Accessing BRAM as a SRAM
84804: 05/05/27: Re: Design flow of Spartan3 for my own embedded processor and HW logic?
84806: 05/05/27: Re: Accessing BRAM as a SRAM
84816: 05/05/28: Re: Accessing BRAM as a SRAM
84817: 05/05/28: Re: Accessing BRAM as a SRAM
84825: 05/05/28: Re: Accessing BRAM as a SRAM
84867: 05/05/31: opb bram controller
84868: 05/05/31: Accessing Bram
84932: 05/06/01: Re: Accessing Bram
84951: 05/06/01: Re: Accessing Bram
85366: 05/06/08: Available under the terms of the SignOnce IP License
85415: 05/06/09: Re: Available under the terms of the SignOnce IP License
85433: 05/06/09: Mapping Dual Port Ram into Microblaze address space
85547: 05/06/10: Re: Mapping Dual Port Ram into Microblaze address space
85585: 05/06/11: Re: computer upgrade time.
85647: 05/06/13: RAM State Machine Examples
85974: 05/06/19: Microblaze address space and variables
86001: 05/06/20: Re: Microblaze address space and variables
86051: 05/06/21: Re: Microblaze address space and variables
86061: 05/06/21: Re: Microblaze address space and variables
86141: 05/06/22: Re: Microblaze address space and variables
86165: 05/06/22: Re: Microblaze address space and variables
86317: 05/06/24: Memory Controller and State Machine
86717: 05/07/05: Connecting ADC to Opb_Spi core
86722: 05/07/05: Re: Connecting ADC to Opb_Spi core
86731: 05/07/05: Re: Connecting ADC to Opb_Spi core
86733: 05/07/05: Re: Connecting ADC to Opb_Spi core
87110: 05/07/15: Linux Fedora and Xilinx ISE
87123: 05/07/15: Re: Linux Fedora and Xilinx ISE
87169: 05/07/18: Red Hat Enterprise 64 bit and ISE WebPack
88259: 05/08/13: Troubles when mapping registers into microblaze address space
88261: 05/08/13: Re: Troubles when mapping registers into microblaze address space
88307: 05/08/15: How to disconnect a signal?
88355: 05/08/16: Re: How to disconnect a signal?
88390: 05/08/17: Changing data into mapped register
88414: 05/08/17: Modelsim on a remote display
88431: 05/08/18: Re: Modelsim on a remote display
88441: 05/08/18: Re: Modelsim on a remote display
88443: 05/08/18: State Machine and BUFG
88445: 05/08/18: Re: State Machine and BUFG
88448: 05/08/18: Re: Modelsim on a remote display
88453: 05/08/18: Re: State Machine and BUFG
88470: 05/08/18: Re: State Machine and BUFG
88511: 05/08/20: Verilog translation
88534: 05/08/22: Re: Verilog translation
88569: 05/08/23: Stdin / stdout through RS232
88576: 05/08/23: Re: Stdin / stdout through RS232
88577: 05/08/23: Using bootloader
88582: 05/08/23: Re: Stdin / stdout through RS232
88585: 05/08/23: Re: Using bootloader
88587: 05/08/23: Re: Stdin / stdout through RS232
88603: 05/08/23: Xilinx Xapp482: syncword?
88679: 05/08/25: Microblaze Simple Bootloader
88690: 05/08/25: Re: Stdin / stdout through RS232
88693: 05/08/25: Re: Stdin / stdout through RS232
88724: 05/08/26: Bootloader Linker Script Help
88758: 05/08/27: Mark to initialize BRAM
88774: 05/08/28: How to reduce software size?
88783: 05/08/28: Re: mails from Aman Mediratta
88785: 05/08/28: Question about program and memory location
88908: 05/08/31: Hi-Z input
88916: 05/08/31: Re: Hi-Z input
88917: 05/08/31: Re: LCD Interface
88929: 05/08/31: Re: Hi-Z input
88954: 05/09/01: Re: Hi-Z input
88957: 05/09/01: A strange behavior
88989: 05/09/02: Re: A strange behavior
89000: 05/09/02: Modelsim simulation question
89036: 05/09/03: The best way to sum 8 datas?
89056: 05/09/04: Re: The best way to sum 8 datas?
89175: 05/09/07: Re: spartan 3 starter kit auto configuration at power up
89450: 05/09/15: Re: ISE 7.1 service packs
89491: 05/09/16: Interrupt Handling
89529: 05/09/18: Xilinx Wizard does not create vhdl DMA template?
89749: 05/09/24: "Free" core and license
89774: 05/09/26: Re: "Free" core and license
89814: 05/09/27: Re: How to run ngcbuild in windows xp environment?
89880: 05/09/29: Turion 64 performance
90066: 05/10/04: High Load
90070: 05/10/04: Re: High Load
90072: 05/10/04: Re: High Load
90137: 05/10/05: Re: High Load
90176: 05/10/06: Re: High Load
90178: 05/10/06: Re: High Load
90179: 05/10/06: FSM with High load on clock signal
90241: 05/10/07: Re: FSM with High load on clock signal
90246: 05/10/07: Re: FSM with High load on clock signal
90252: 05/10/07: Re: FSM with High load on clock signal
90259: 05/10/07: Re: FSM with High load on clock signal
90987: 05/10/26: Re: C source for Spartan-3 with microblaze soft core for RS-232 comm
91068: 05/10/28: Sigma-Delta A/D
91119: 05/10/30: Re: Sigma-Delta A/D
91121: 05/10/30: Re: Sigma-Delta A/D
91126: 05/10/30: Re: Sigma-Delta A/D
91127: 05/10/30: Re: Sigma-Delta A/D
91128: 05/10/30: Re: Sigma-Delta A/D
91145: 05/10/31: Re: Sigma-Delta A/D
91148: 05/10/31: Integrator
91192: 05/11/01: Re: Sigma-Delta A/D
91317: 05/11/03: I have received a job offer
91321: 05/11/03: Re: I have received a job offer
91360: 05/11/04: Re: I have received a job offer
91452: 05/11/07: Spartan3 bus for DSP
91531: 05/11/08: Bus for Spartan3
91641: 05/11/10: Re: Looking for tutorials for bootloader writing on xilinx SOC ??
91720: 05/11/11: Clock signal for an external peripheral
91724: 05/11/11: Re: Clock signal for an external peripheral
91726: 05/11/11: Re: Bus for Spartan3
91782: 05/11/13: Re: Clock signal for an external peripheral
92228: 05/11/24: case statement fault
92239: 05/11/24: Re: case statement fault
92537: 05/12/01: Which Phy transceiver for 10/100 ethernet?
92756: 05/12/06: VHDL SPI core
92794: 05/12/07: How to connect 2 FPGA?
92802: 05/12/07: Re: How to connect 2 FPGA?
92867: 05/12/08: Re: How to connect 2 FPGA?
92969: 05/12/10: Re: How to connect 2 FPGA?
93445: 05/12/22: Opencores Can Controller
94260: 06/01/09: spartan3 differential I/O
94282: 06/01/09: Re: spartan3 differential I/O
94757: 06/01/17: Spartan3 initialization with DSP
94841: 06/01/18: Re: Spartan3 initialization with DSP
94910: 06/01/19: Re: Spartan3 initialization with DSP
94917: 06/01/19: Re: Spartan3 initialization with DSP
95412: 06/01/23: SSOs and Vcco on Spartan3
95427: 06/01/23: Re: SSOs and Vcco on Spartan3
95458: 06/01/23: Re: SSOs and Vcco on Spartan3
95648: 06/01/24: Re: Newbie: xilinx vs arm
95692: 06/01/25: Spartan3 DC datasheet
95926: 06/01/27: Xilinx OBUF attributes on Spartan3
95937: 06/01/27: Re: Xilinx OBUF attributes on Spartan3
95941: 06/01/27: Re: Xilinx OBUF attributes on Spartan3
95954: 06/01/27: Re: Xilinx OBUF attributes on Spartan3
95957: 06/01/27: Re: Xilinx OBUF attributes on Spartan3
95960: 06/01/27: Re: Xilinx OBUF attributes on Spartan3
95958: 06/01/27: Re: Xilinx OBUF attributes on Spartan3
96601: 06/02/07: input signals in ISE simulator
96642: 06/02/07: Re: ISE Simulator
97517: 06/02/23: Spartan3 decoupling
98147: 06/03/06: Pullup questions on Spartan3
98150: 06/03/06: Re: Pullup questions on Spartan3
98155: 06/03/06: Vccaux regulator
98170: 06/03/06: Re: Pullup questions on Spartan3
98201: 06/03/06: Re: Vccaux regulator
98202: 06/03/06: Re: Pullup questions on Spartan3
98204: 06/03/07: Re: Power estimates in XC3S1500
98205: 06/03/07: Re: Power estimates in XC3S1500
98211: 06/03/07: Re: Xilinx LVDS
98212: 06/03/07: Re: Xilinx LVDS
98275: 06/03/07: Re: Power estimates in XC3S1500
98276: 06/03/08: DCM question
98285: 06/03/08: Re: DCM question
98334: 06/03/08: Re: DCM question
98375: 06/03/08: Re: DCM question
98572: 06/03/13: Re: using EDK with the gcc -g option...
99861: 06/03/30: need your comments
100082: 06/04/03: Re: need your comments
100203: 06/04/05: Re: need your comments
100637: 06/04/14: PROG_B and JTAG
102327: 06/05/15: pull-ups and jtag questions
102334: 06/05/15: Re: pull-ups and jtag questions
102503: 06/05/16: Re: SPI master
102990: 06/05/24: fpga debug
102993: 06/05/24: Re: fpga debug
102996: 06/05/24: Re: fpga debug
103083: 06/05/25: ISE .ant file
103212: 06/05/28: ISE 8.1 with 7.1
103216: 06/05/29: Re: ISE 8.1 with 7.1
103220: 06/05/29: Re: ISE 8.1 with 7.1
103230: 06/05/29: Re: ISE 8.1 with 7.1
103402: 06/06/01: timings
103509: 06/06/04: Re: timings
103895: 06/06/14: boot mode pins on Spartan3
103899: 06/06/14: Re: boot mode pins on Spartan3
103900: 06/06/14: Re: boot mode pins on Spartan3
103977: 06/06/16: bga routing
104039: 06/06/16: Re: bga routing
104097: 06/06/19: Re: Anyone get a Pictiva OLED to work?
104105: 06/06/19: Re: Anyone get a Pictiva OLED to work?
104300: 06/06/23: is picoblaze worth in my project?
107190: 06/08/25: Error message in ISE7.1
107659: 06/08/30: pull-ups for Spartan3
137751: 09/01/28: Re: Complete optical processors and digital photonics to replace electronics in all form factors for commodity high performance computing at the speed of light for all.
143074: 09/09/18: Re: FPGA for acoustic adaptive beamforming
160477: 18/02/04: Re: Interface on board ADC to Spartan 3E startkit
Marco Albero:
121511: 07/07/06: I need relocate my program outside bram...
121595: 07/07/09: Problem usign xilfatfs...
121627: 07/07/10: Re: Here you have the 'system.hms'
121628: 07/07/10: Re: And here the 'system.mss'
122003: 07/07/17: Sending large amount of data with lwIP...
Marco Castellon:
34479: 01/08/27: DUART core synthesizable in Xilinx FPGA.
Marco Cavadini:
7528: 97/09/19: FPGA/CPLD Overview
Marco Kluge:
58111: 03/07/15: Bus macros and partial reconfiguration
Marco Landert:
29883: 01/03/15: Re: NIOS 16-Bit
29862: 01/03/14: NIOS 16-Bit
29871: 01/03/14: Re: NIOS 16-Bit
marco p.:
70668: 04/06/23: 5V board in a 3.3V PCI slot
70713: 04/06/24: Re: 5V board in a 3.3V PCI slot
Marco Rivero:
583: 95/01/11: Backannotating Xilinx pinouts to ViewLogic symbols... BUT Not by hand!
8803: 98/01/28: Comments about Xilinx Alliance m1.4 w/Novell and other problems
Marco Sanvido:
17925: 99/09/17: Re: Xilinx development board > XVC400
19066: 99/11/26: Re: HDL Editor
Marco Schmidt:
1571: 95/07/19: routing
1620: 95/08/03: Re: 16 bit computer on fpga's
Marco Serafini:
39078: 02/01/31: Setting PCI command register in WinNT OS
39135: 02/02/01: Re: Setting PCI command register in WinNT OS
39139: 02/02/01: Re: Pin assignment on ACEX1K
39309: 02/02/06: Re: Adding internal JTAG chains on FPGA
42268: 02/04/19: Re: fpga limitation
42274: 02/04/19: RAM function in Altera device
49431: 02/11/12: Re: How to instanciate Altera primitive component in VHDL for FPGA Compiler synthesis?
Marco T.:
93513: 05/12/23: Virtex-4FX and ethernet mac
93548: 05/12/24: Re: Virtex-4FX and ethernet mac
93678: 05/12/28: CP2101 <-> Printer?
93723: 05/12/29: USB Printer Interface
93743: 05/12/29: Re: USB Printer Interface
94075: 06/01/05: EDK 8.1i
94444: 06/01/11: Re: best evm for virtex-4 and linux
94827: 06/01/18: Selling Microblaze based Machines
94993: 06/01/20: Loading Data from Prom
95823: 06/01/26: Microblaze data cache question
95922: 06/01/27: Re: Microblaze data cache question
95932: 06/01/27: Multichannel Opb Memory Controller question
95935: 06/01/27: Re: Multichannel Opb Memory Controller question
95938: 06/01/27: Re: Multichannel Opb Memory Controller question
95944: 06/01/27: Re: Multichannel Opb Memory Controller question
95975: 06/01/27: Re: Multichannel Opb Memory Controller question
96022: 06/01/28: Connection between FSL and XCL
96230: 06/02/01: Parallel Cable IV does not work with parallel to usb cable
97350: 06/02/21: SMSC 91c111 and LwIP
97365: 06/02/21: Re: SMSC 91c111 and LwIP
97504: 06/02/23: System with multiple buses
97827: 06/02/28: conv_integer
97831: 06/02/28: Re: conv_integer
97888: 06/03/01: Virtex-4FX Mini Module TEMAC examples
97891: 06/03/01: Re: Virtex-4FX Mini Module TEMAC examples
97944: 06/03/02: Re: Virtex-4FX Mini Module TEMAC examples
97966: 06/03/02: Re: Virtex-4FX Mini Module TEMAC examples
98020: 06/03/03: Virtex-4FX MiniModule Atmel Flash
98078: 06/03/04: Re: Virtex-4FX MiniModule Atmel Flash
98083: 06/03/04: Re: Virtex-4FX MiniModule Atmel Flash
98087: 06/03/04: Re: Virtex-4FX MiniModule Atmel Flash
98111: 06/03/05: Re: Virtex-4FX MiniModule Atmel Flash
98380: 06/03/09: Troubles when upgrading Embedded Virtex-4Fx PowerPc
98435: 06/03/10: Someone need to port LwIP to ll_temac core/wrapper?
98454: 06/03/10: Re: EDK8.1: Is adding IP core parameters stiil possible?
98502: 06/03/11: Re: Plateform FLASH PROM configuration using a Microblaze.
99331: 06/03/23: Re: Problem with LwIP and MicroBlaze
99351: 06/03/23: Re: Problem with LwIP and MicroBlaze
99624: 06/03/27: Opb Spi Controller Trouble
99772: 06/03/29: Storing variables into data ocm memory
99784: 06/03/29: Re: problem with IO in EDK 8.1
99791: 06/03/29: Re: Storing variables into data ocm memory
100346: 06/04/07: Re: Virtex-4 Gigabit Ethernet design
100359: 06/04/07: Re: Someone need to port LwIP to ll_temac core/wrapper?
100730: 06/04/17: Which is the best way to measure low frequencies?
100772: 06/04/18: Re: Which is the best way to measure low frequencies?
100852: 06/04/19: Storing Variables into LMB Memory
101434: 06/05/01: Question about the ip I developed
101436: 06/05/01: Re: Question about the ip I developed
101590: 06/05/03: Re: Someone need to port LwIP to ll_temac core/wrapper?
102716: 06/05/19: Re: Ethernet & ML401
102717: 06/05/19: Re: Use USB ports on ML401
102731: 06/05/19: Re: Ethernet & ML401
102773: 06/05/20: Re: Ethernet & ML401
103179: 06/05/27: DVI connected to Virtex-4
103511: 06/06/05: MIL Qualified RTOS for PowerPc 405
103525: 06/06/05: Re: MIL Qualified RTOS for PowerPc 405
105448: 06/07/23: Delta sigma Modulator Interface
105833: 06/08/01: Re: FPGA LABVIEW programming
105887: 06/08/02: Re: FPGA LABVIEW programming
111112: 06/10/29: Safe Routing
113454: 06/12/14: Re: what are your current SoC design for ?
113775: 06/12/21: Re: MICROBLAZE AND OPB: TOO SLOW FOR VGA
113776: 06/12/21: Re: MICROBLAZE AND OPB: TOO SLOW FOR VGA
113785: 06/12/21: Re: MICROBLAZE AND OPB: TOO SLOW FOR VGA
115613: 07/02/15: ML403 FPGA and CPLD
119049: 07/05/10: Gain and Offset Correction
119056: 07/05/10: Re: Gain and Offset Correction
119150: 07/05/13: Digital gain and offset correction
119161: 07/05/14: Re: Digital gain and offset correction
119196: 07/05/14: Re: Digital gain and offset correction
119216: 07/05/15: Re: Digital gain and offset correction
128365: 08/01/23: Pwm Sine Generation
128375: 08/01/23: Re: Pwm Sine Generation
128386: 08/01/23: Re: Pwm Sine Generation
128714: 08/02/05: Minimum Oscillator Frequency
128765: 08/02/05: Re: Minimum Oscillator Frequency
129100: 08/02/14: Rom Implementation in a CPLD
<marcobuffa@gmail.com>:
98763: 06/03/16: ISE 8.1 linux 64bit license key
98980: 06/03/18: Re: ISE 8.1 linux 64bit license key
100834: 06/04/19: incremental synthesis xst ise 8.1
Marcos:
54669: 03/04/15: Altera PCI Development
Marcos G.:
66950: 04/03/01: Wanted: Insight "Virtual Workbench" for Xilinx XCV300 information
Marcum N. Nance III:
6919: 97/07/09: Re: VHDL to EDIF translater
Marcus:
146323: 10/03/12: Comparing FPGA with ASIC implementations
marcus aurelius:
Marcus Bednara:
43122: 02/05/14: Virtex2 placement problem
Marcus Harnisch:
72560: 04/08/24: Re: DDR SDRAM
72621: 04/08/26: Re: DDR SDRAM
72661: 04/08/27: Re: DDR SDRAM
103719: 06/06/09: Re: Good free or paid merge software that edits two similar files?
115065: 07/01/30: Re: video buffering scheme, nonsequential access (no spatial locality)
123434: 07/08/28: Re: New keyword 'orif' and its implications
146584: 10/03/23: Re: Why hardware designers should switch to Eclipse
147335: 10/04/23: Re: I'd rather switch than fight!
Marcus Lankenau:
10604: 98/06/05: Atmel AT40K
10603: 98/06/05: Re: Example of 8051 codes to configure Xilinx fpga
10640: 98/06/08: Q: FPGA Place and Route Software
10912: 98/06/30: Spartan test-board
10938: 98/07/05: Re: Spartan test-board
10988: 98/07/08: Re: Configure with BIT file
11153: 98/07/21: problems with xilinx foundation
11433: 98/08/13: How to do FFT
Marcus Schaemann:
65394: 04/01/27: Which Environment for Xilinx Design?
Marcus Svensson:
63742: 03/12/02: Modelsim 5.8 corrupt call stack when adding signals to wave window.
63762: 03/12/03: Re: Modelsim 5.8 corrupt call stack when adding signals to wave window.
<marcus.erlandsson@gmail.com>:
138879: 09/03/13: Re: What happens at opencores.org?
138887: 09/03/13: Re: What happens at opencores.org?
<marcus.harnisch@gmx.net>:
83416: 05/04/29: Re: *RANT* Ridiculous EDA software "user license agreements"?
Mardin:
37601: 01/12/17: division 64
37966: 01/12/27: CRC-32 verilog source code
37970: 01/12/27: Re: CRC-32 verilog source code
37993: 01/12/28: Re: CRC-32 verilog source code
Marek Jaskula:
46704: 02/09/06: new in fpga
48423: 02/10/17: Digilab DIO1 rev.B
Marek Kraft:
114954: 07/01/27: Rank order filtering - XAPP953 - what am I doing wrong?
119353: 07/05/17: Re: Avnet Virtex-4 LX Evaluation Kit USB FX2 Issue
120914: 07/06/20: Suggestions for Xilinx based evaluation board for image processing
Marek Ponca:
18370: 99/10/20: Seeking for FPGA/CPLD (Starter) kit
31054: 01/05/10: Waveforms painting
31060: 01/05/10: Re: Waveforms painting
31082: 01/05/11: Re: Waveforms painting
63437: 03/11/21: FC II & Generic
77453: 05/01/07: Synthesis of more FSMs in one file using DC
Marek Skotnica:
1281: 95/05/26: ? FPGA library for ORCAD
4411: 96/10/25: Re: win95 env variables
<marek.kraft@gmail.com>:
126729: 07/11/30: Using DDR RAM on XUP V2Pro board
126759: 07/12/01: Re: Using DDR RAM on XUP V2Pro board
<mares.vit@gmail.com>:
125815: 07/11/06: Re: Linux capable free/GPL SOFT CPU for XC3S500E?
125818: 07/11/06: Re: Linux capable free/GPL SOFT CPU for XC3S500E?
125822: 07/11/06: Re: Linux capable free/GPL SOFT CPU for XC3S500E?
Margaret Dailey:
15728: 99/04/10: Consulting Engineers Wanted
17219: 99/07/09: Designers wanted
17396: 99/07/23: Re: "Contract Outsourcing?!"
17397: 99/07/23: Mixed Signal Design Engineers Wanted
17540: 99/08/08: Designers wanted
18176: 99/10/05: Designers wanted
Margaret Martonosi:
5996: 97/04/03: Configurable Computing Post-Doc at Princeton
6201: 97/04/25: Postdoc Position Available: Configurable Computing, Performance and Synthesis Tools
<margaretatwork@my-deja.com>:
20906: 00/02/26: IC Validation Engineers/Managers Wanted
Margie Way:
13890: 98/12/31: JOB FPGA/CA Startup
14353: 99/01/26: FPGA/Lead job opportunity at Cisco
<mariab52@my-deja.com>:
22872: 00/05/29: Problem with databus for external ROM using 'Z'
22873: 00/05/29: Problem with databus for external RAM using 'Z'
<mariam.makni@gmail.com>:
156653: 14/05/25: Re: Microblaze and MBLite
mariani:
35725: 01/10/15: help request about lattice isp 1032
37059: 01/11/29: palette LUT design(searching ROM)
Marie:
77823: 05/01/18: decrease slew rate - Actel Libero
85487: 05/06/10: programmation with IMPACT with one PROM and two FPGAs
90173: 05/10/06: Actel Libero upgrade - problem with clk pin - Synplify
90197: 05/10/06: Re: Actel Libero upgrade - problem with clk pin - Synplify
90257: 05/10/07: Re: Actel Libero upgrade - problem with clk pin - Synplify
Mariem Makni:
156657: 14/05/27: Re: Microblaze and MBLite
156664: 14/05/28: Re: Microblaze and MBLite
156763: 14/06/22: PLB to AMBA AHB bus bridge
Marija:
68177: 04/03/29: maybe a stupid question
68272: 04/03/31: Re: maybe a stupid question
68482: 04/04/06: number of BRAMs
68512: 04/04/07: timing constraints... again
68519: 04/04/07: Re: Accesing a procedure
68520: 04/04/07: how to use a .ucf file?
68521: 04/04/07: Re: timing constraints... again
Marilyn:
Marinos J. Yannikos:
6718: 97/06/19: APS-X84 - recommended?
19805: 00/01/12: Re: HW resources increased
19824: 00/01/13: Re: HW resources increased
Mario:
32166: 01/06/17: PCI Config Address Space
Mario Ivancic:
65368: 04/01/26: isp Cable for Lattice CPLD
Mario Niebaum:
9637: 98/03/27: Re: VHDL shareware editor?
Mario Prato:
68908: 04/04/21: cpld in plcc84 package
Mario Trams:
54631: 03/04/15: Re: synthesis of a VHDL module in Xilinx
54931: 03/04/22: Re: Initial values for internal RAM
55198: 03/04/30: Re: general: vhdl
55231: 03/05/01: Re: [little OT] SystemC
55441: 03/05/08: Re: Software and hardware monopoly is bad
55468: 03/05/09: Re: [Altera or Xilinx] Questions
55472: 03/05/09: Re: variable clock source for CPLD, PIC
55539: 03/05/12: Re: Register in FPGA
55706: 03/05/16: Re: smallest embedded cpu.
55716: 03/05/16: Re: smallest embedded cpu.
55808: 03/05/20: Re: Xilinx : Tools
55833: 03/05/21: Re: Thermal problems with large FPGA BGA's
55840: 03/05/21: Re: Register in FPGA
55869: 03/05/22: Re: Xilinx : Tools
55873: 03/05/22: Re: Asynchronous State Machines and HDLs
56976: 03/06/20: Re: FPGA device + CPU
56977: 03/06/20: Re: Investment in FPGA
56978: 03/06/20: Re: Port Mode
56979: 03/06/20: Re: Port Mode
57405: 03/06/30: Re: Parallel processing
57771: 03/07/07: Re: division
57913: 03/07/09: Re: how can I use a signal defined in one Architecture to another Architecture
58113: 03/07/15: Re: programming a PLD/CPLD with a PIC?
58217: 03/07/17: Re: Digital Design with just one clock at one edge
58229: 03/07/17: Re: PCI - disabling
58232: 03/07/17: Re: PCI - disabling
58654: 03/07/30: Re: Simulation
59388: 03/08/18: Re: serial communication between pc and altera fpga
59693: 03/08/26: Re: FPGA minimum operating frequencies
59694: 03/08/26: Re: Two near-identicial clocks?
59699: 03/08/26: Re: Two near-identicial clocks?
60044: 03/09/04: Re: New to FPGA, seeking advice
60107: 03/09/05: Re: Suitable FPGA architecture for Robots..
60190: 03/09/07: Re: CMOS camera w/ USB2 -- crazy?
60361: 03/09/11: Xilinx-gdb Sources publicly available?
60408: 03/09/12: Re: Xilinx-gdb Sources publicly available?
60927: 03/09/25: Re: Reading from FPGA Issue
61344: 03/10/02: Re: Good VHDL/Verilog editor?
61345: 03/10/02: Re: Host-PCI Bridge
61506: 03/10/06: Re: Host-PCI Bridge
62655: 03/11/04: Re: Building the 'uber processor'
62785: 03/11/07: Re: Building the 'uber processor'
62986: 03/11/12: Re: Logic implementation in SRAM/OTP FPGAs
63725: 03/12/02: Re: problem with RS485 or RS232
64544: 04/01/07: Re: Virtex and Spartan
64545: 04/01/07: Re: Simulating multi-chip design
64850: 04/01/15: Re: Generating clock delays
65777: 04/02/06: Re: Artificial Intelligence/FPGA
65778: 04/02/06: Re: need desperate help!
69531: 04/05/13: Re: synthesising VHDL for Xilinx FPGAs using ISE 6.1i
69539: 04/05/13: Re: synthesising VHDL for Xilinx FPGAs using ISE 6.1i
70018: 04/05/27: Re: Propogation delays and setup times
70781: 04/06/28: Re: Newbie question -fanout of iopins in fpga
71306: 04/07/14: Re: mcu vs fpga help me to choose !!
71737: 04/07/29: Re: FPGA vs CPLD
71738: 04/07/29: Re: wishbone protocol documentation
71782: 04/07/30: Re: FPGA vs CPLD
Mario Volks:
153867: 12/06/15: Fpga to Asic conversion, firm list and prices.
mariosevr:
135684: 08/10/12: Microblaze Network On Chip
Mariotto:
19043: 99/11/25: CIC Filters in FPGA
19561: 99/12/31: code error in active vhdl
marise:
66830: 04/02/26: Re: Question: size of Stratix??
marius:
19092: 99/11/28: Re: implementing TCP/IP on PLD
Marius Vollmer:
14235: 99/01/21: Re: Can we get back to DSP again? Was Re: Who cares what DSP programmers think?
33950: 01/08/09: Re: Alliance tools going away?
35035: 01/09/18: Mixing VHDL and EDIF in FPGA Compiler II (Xilinx)
35076: 01/09/20: Re: Mixing VHDL and EDIF in FPGA Compiler II (Xilinx)
35078: 01/09/20: Re: Mixing VHDL and EDIF in FPGA Compiler II (Xilinx)
35129: 01/09/22: Re: Mixing VHDL and EDIF in FPGA Compiler II (Xilinx)
55045: 03/04/25: Re: ise4.2i and wine
55742: 03/05/18: Re: Xilinx announces 90nm sampling today!
56520: 03/06/07: Re: Logical analyzer via USB or printer port
57684: 03/07/03: Re: Xilinx ISE drops support for more parts
66169: 04/02/13: Re: Peter's 1Hz-640MHz Synth project
66213: 04/02/14: Re: Peter's 1Hz-640MHz Synth project
66349: 04/02/18: Can FPGA bootstrap itself?
66538: 04/02/21: Re: Can FPGA bootstrap itself?
66583: 04/02/23: Re: Can FPGA bootstrap itself?
66663: 04/02/24: Re: Free PCI-bridge in VHDL for Spartan-IIE
67094: 04/03/05: Re: Need to speed up Stratix compiles.
67411: 04/03/11: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
68448: 04/04/05: Re: FPGA input
69023: 04/04/26: Re: Quartus for linux
69104: 04/04/27: Re: Design PAR in Stratix
76705: 04/12/09: Re: Open source FPGA EDA Tools
76964: 04/12/17: Re: Open source FPGA EDA Tools
77292: 05/01/03: Re: Large open source FPGAs?
77391: 05/01/06: Re: Open source FPGA EDA Tools
77461: 05/01/07: Re: Open source FPGA EDA Tools
79630: 05/02/22: Re: Reconfigure your dreams: fully reconfigurable computer in DIP40
80791: 05/03/11: Xilinx XST 6.3i: Typo in generics, silent failure?
80850: 05/03/12: Re: Xilinx XST 6.3i: Typo in generics, silent failure?
80963: 05/03/15: Re: Xilinx XST 6.3i: Typo in generics, silent failure?
81772: 05/03/31: One or two DLLs for a SDRAM controller?
81904: 05/04/04: Re: One or two DLLs for a SDRAM controller?
81906: 05/04/04: Re: One or two DLLs for a SDRAM controller?
81963: 05/04/05: Re: WebPack_7.1 on Linux ?
MariuszK:
109676: 06/10/03: Re: Looking for HDL code for sin( a ) and x ** y Functions
Mark:
11261: 98/07/31: Symbols, design changes, pin changes
11300: 98/08/03: Re: Symbols, design changes, pin changes
15826: 99/04/16: High speed reconfigurability
20964: 00/03/01: Re: Materials on PCI
20966: 00/03/01: Re: Materials on PCI
23503: 00/06/27: Re: JTAG emulation of TI DSPs
29463: 01/02/22: Virtex II availability
29854: 01/03/13: FPGA : Simple FD latch glitchs
34084: 01/08/13: Re: Use of lpm in Xilinx Foundation 2.1i
34085: 01/08/14: Re: Use of lpm in Xilinx Foundation 2.1i
34328: 01/08/21: FPGA MP3 decoder
34331: 01/08/21: Re: FPGA MP3 decoder
36657: 01/11/14: Re: Synopsys+Xilinx vs Synplicity
36667: 01/11/14: Re: Xilinx s/w upgrade 4.1 problems
37017: 01/11/28: Re: reducing PAR time
37018: 01/11/28: Re: Is there a full open-source synthesis path for any FPGA?
37078: 01/11/29: Re: Is there a full open-source synthesis path for any FPGA?
37079: 01/11/29: Re: reducing PAR time
37081: 01/11/29: Re: reducing PAR time
37123: 01/11/30: Re: Is there a full open-source synthesis path for any FPGA?
37128: 01/11/30: Re: Is there a full open-source synthesis path for any FPGA?
37129: 01/11/30: What do you like/dislike about place and route tools?
40562: 02/03/11: How to Align 7x DDR Data Input to a XC2V6000-5?
40608: 02/03/11: Re: FPGA download fails
40637: 02/03/12: Re: How to Align 7x DDR Data Input to a XC2V6000-5?
40698: 02/03/13: Re: How to Align 7x DDR Data Input to a XC2V6000-5?
40727: 02/03/14: Re: How to Align 7x DDR Data Input to a XC2V6000-5?
44390: 02/06/19: Re: new computer
44442: 02/06/20: Re: new computer
44982: 02/07/08: Re: Getting started with FPGAs
61001: 03/09/26: Re: WARNING do not use your real email address in USENET postings! Swem/Gibe virus will spam you 1000x!
61261: 03/10/01: Interface Between National Semi Channel Link TX AND Virtex-II
71865: 04/08/02: Best tool(s) for filter float->fixed->VHDL flow?
72499: 04/08/20: Virtex II LVDS plus DDR?
88938: 05/08/31: New PCI Express Group
88939: 05/08/31: Re: Spartan 3 Serdes
88945: 05/08/31: Re: Spartan 3 Serdes
92098: 05/11/22: Re: Quartus Problem
92099: 05/11/22: Patient Monitors: Reading RS232 output w/ an FPGA
92226: 05/11/24: Re: Patient Monitors: Reading RS232 output w/ an FPGA
108723: 06/09/15: Re: Problems with NIOS II PIO interrupt
108724: 06/09/15: Re: microblaze lwip
109789: 06/10/05: Re: Nios II interrupt
111240: 06/10/31: Re: Nios 2 application running from external ram
111705: 06/11/08: Re: Nios2 access to EPCS device without using HAL drivers
129600: 08/02/28: Re: Picoblaze enhencement and assembler
131251: 08/04/17: Help, router can't rout all connections (XILINX)
131255: 08/04/17: Re: Help, router can't rout all connections (XILINX)
131257: 08/04/17: Re: Help, router can't rout all connections (XILINX)
131258: 08/04/17: Re: Help, router can't rout all connections (XILINX)
140372: 09/05/11: Re: Dual Port RAM Inference
140377: 09/05/11: Re: Dual Port RAM Inference
140379: 09/05/11: Re: Dual Port RAM Inference
140629: 09/05/20: Re: Online tool that generates parallel CRC and Scrambler
140851: 09/05/27: Re: Online tool that generates parallel CRC and Scrambler
151316: 11/03/22: Via in Hyperlynx linesim
151318: 11/03/22: Re: Via in Hyperlynx linesim
151363: 11/03/28: MAX II CPLD and I2S Clock divider jitter
151371: 11/03/28: Re: MAX II CPLD and I2S Clock divider jitter
157955: 15/05/24: IMX6 Solo - FPGA Module
mark:
14898: 99/02/24: Re: Xilinx Virtex
15069: 99/03/04: Re: Virtex & Xchecker
15148: 99/03/09: Virtex Programming Weirdness
29357: 01/02/15: Design of a divide by 6.5 counter ?
46901: 02/09/11: XC2V Embedded Multipliers and Chipscope Usage
47098: 02/09/17: Re: XC2V Embedded Multipliers and Chipscope Usage
Mark Linn:
80257: 05/03/02: newbie ABEL questions
80331: 05/03/03: Re: newbie ABEL questions
Mark (UK):
70666: 04/06/23: Re: Asteroids Deluxe in an FPGA
70717: 04/06/24: Re: Asteroids Deluxe in an FPGA
Mark A. Odell:
21929: 00/04/07: Re: Any free design of 8051 in the net?
40681: 02/03/12: Re: Mystery two wire interface, or am I being dense?
72484: 04/08/20: Re: GAL,PAL,PLD, CPLD,FPGA
Mark Aaldering:
61: 94/08/06: Re: Intel iFX questions
4811: 96/12/17: Re: Fpga, Epld, cpld....
4924: 96/12/31: Re: I2C Bus Interface in FPGAs
4960: 97/01/04: Re: EPX880 & 8160 to Become Obsolete
5496: 97/02/20: Re: Xilinx or Altera?
6206: 97/04/26: Re: prep benchmarks for FPGAs
6219: 97/04/29: Re: Low power PLD?
7219: 97/08/15: Re: Low-cost programming FPGAs (was: Re: free FPGA software from actel)
9020: 98/02/14: Re: Philips P5Z22V10 wanted
9021: 98/02/14: Re: Altera Classic Devices 1810, 910, 5128 Problems
10831: 98/06/24: Re: Q: I squared C on an FPGA
13785: 98/12/28: Re: 22V10 Metastability - help please
17130: 99/07/01: Re: FW: Xilinx Acquisition of CoolRunners
23233: 00/06/18: Re: Reed Solomon in Xilinx FPGA?
23583: 00/07/01: Re: Free PCI core
32180: 01/06/18: Re: Timing results Xilinx Core Multiplier in FPGA Compiler 2
35818: 01/10/18: Re: Xilinx PCI core and XST
42293: 02/04/19: Re: Source code for a NIOS instruction set simulator?
42314: 02/04/19: was: NIOS ISS, MicroBlaze Cycle Accurate ISS
42390: 02/04/22: Re: NIOS ISS, MicroBlaze Cycle Accurate ISS
Mark Adams:
5077: 97/01/21: Re: Meta Assembler wanted
5526: 97/02/22: Re: Xilinx or Altera?
6893: 97/07/07: Re: Altera archiving
7916: 97/10/29: Re: Modeling using Altera devices
14190: 99/01/18: Re: Ratings for Synplicity Synplify
mark andrew:
81004: 05/03/15: Re: Which HDL?
92283: 05/11/25: How to tell which synthesis tool I am using
Mark Anstice:
29865: 01/03/14: Xilinx webpack supported pachages
Mark Aren:
75590: 04/11/10: Advice on Contemporary Low cost, Medium Density CPLDs
Mark Baert:
32181: 01/06/18: data compression IP for FPGA's
Mark Barr:
38788: 02/01/25: Get error that part is invalid or not supported when Run from synthesis
45119: 02/07/12: Foundation 2.1i --- does it support vertexII?
Mark Borgerson:
33771: 01/08/03: Newbie Question: LPT245 in CoolRunner?
34029: 01/08/12: Xilinx WebPack .UCF file
34222: 01/08/16: Re: Xilinx WebPack .UCF file
Mark Bowlby:
23516: 00/06/28: Re: Virtex Demo Board
Mark Brehob:
154210: 12/09/09: Re: Looking for an extremely cheap FPGA board (in quantity, academic use)
154211: 12/09/09: Re: Looking for an extremely cheap FPGA board (in quantity, academic use)
154249: 12/09/16: Re: Looking for an extremely cheap FPGA board (in quantity, academic use)
154250: 12/09/16: Re: Looking for an extremely cheap FPGA board (in quantity, academic use)
154251: 12/09/16: Re: Looking for an extremely cheap FPGA board (in quantity, academic use)
Mark Byers:
2456: 95/12/07: Re: (no subject)
Mark Cartlidge:
2470: 95/12/11: Re: Help on boards using FPGA devices for hareware realisation
Mark Champion:
6313: 97/05/14: Re: VHDL or Verilog?
6342: 97/05/16: Re: VHDL or Verilog?
Mark Christensen:
3725: 96/07/22: Re: FPGA vs CPLD
3794: 96/08/02: Re: US-NH FPGA Design Engineer, Avionics
3817: 96/08/06: "Xilinx nixes its antifuse arrays"
Mark Christiaens:
89707: 05/09/23: Announcement Free Symposium on the Future of Configurable Hardware
Mark Coles:
25550: 00/09/13: emma/dy ssn
Mark Condit:
17315: 99/07/20: Re: Xilinx/Synopsys License Problem
Mark Curry:
28920: 01/01/29: Re: looping and ranges
31393: 01/05/21: Re: LFSR Taps for 64 bit registers?
144926: 10/01/15: Re: SystemVerilog Verification Example using Quartus and ModelSim
147360: 10/04/23: Re: I'd rather switch than fight!
148248: 10/07/02: Re: Xilinx xapp175, empty + full flag really synchronous?
150964: 11/02/24: Re: Simulating mutiplication of 'X' with '0'
151111: 11/03/08: Re: IP Core Delivery Format Info
151294: 11/03/21: Re: RAM - DIMM vs SO-DIMM: price vs. (hardware & software) ease of use
151296: 11/03/21: Re: RAM - DIMM vs SO-DIMM: price vs. (hardware & software) ease of use
152435: 11/08/22: Re: MAXDELAY constraint
152463: 11/08/26: Re: ISE and detecting flowthrus
152677: 11/09/26: Re: Implementation Issue
153001: 11/11/10: Re: ASIC design job vs FPGA design job
153004: 11/11/10: Re: ASIC design job vs FPGA design job
153006: 11/11/10: Re: ASIC design job vs FPGA design job
153183: 12/01/04: Re: Beginner question on FIFO in "FPGA prototyping by VHDL examples"
153330: 12/02/01: Re: Design Notation VHDL or Verilog?
153336: 12/02/02: Re: Design Notation VHDL or Verilog?
154008: 12/07/10: Re: Possibility to use MGTREFCLK1P/MGTREFCLK1N as clock for user logic in
154276: 12/09/20: Re: Global Reset using Global Buffer (long!)
154374: 12/10/17: Re: .do files... why?
154911: 13/02/12: Re: Vivado - Pack I/O Registers?
155398: 13/06/25: Re: Pure HDL Xilinx Zynq Arm Instantiation
155569: 13/07/22: Re: Verilog: "don't care" in
155664: 13/08/01: Re: seperate high speed rules for HDL?
155720: 13/08/21: Re: Cascaded floating-point reduction?
155724: 13/08/22: Re: Cascaded floating-point reduction?
155729: 13/08/23: Re: Cascaded floating-point reduction?
155794: 13/09/05: Re: Lattice Announces EOL for XP and EC/P Product Lines
155866: 13/10/08: Re: Granularity of components for FPGA synthesis?
155883: 13/10/11: Re: reset strategy FPGA Igloo
155889: 13/10/11: Re: reset strategy FPGA Igloo
155932: 13/10/16: Re: reset strategy FPGA Igloo
155996: 13/11/04: Re: Verilog module not working,binary division,shifting problem!!
156044: 13/11/12: Re: legacy Xilinx software
156045: 13/11/12: Re: Qsys and clock crossings
156170: 14/01/06: Re: register naming
156173: 14/01/06: Re: register naming
156273: 14/02/03: Re: Verilog (Xilinx): Virtual tristate or muxes?
156285: 14/02/05: Re: Xilinx Xpower Issues - Help from xilinx team please
156289: 14/02/06: Re: pipelined algorithm, flow control
156295: 14/02/10: Re: How to synchronize register bank used in the IP Core
156390: 14/03/27: Re: [cross-post][long] svn workflow for fpga development
156648: 14/05/22: Re: Microblaze and MBLite
156983: 14/08/11: Re: Has anyone forked any Xilinx IP?
156994: 14/08/14: Re: Has anyone forked any Xilinx IP?
157015: 14/08/26: Re: Bidirectional Pin FPGA (Parallel ADC)
157172: 14/10/24: Re: [cross-post] verification vs design
157175: 14/10/27: Re: XILINX PCIe read of slow device
157193: 14/10/29: Re: XILINX PCIe read of slow device
157684: 15/01/27: Re: Artix-7 tools, ISE vs Vivado
157995: 15/06/22: Re: Conditional Interpretation of VHDL
158310: 15/10/09: Re: recovery/removal timing
158336: 15/10/22: Re: DC Blocker
158342: 15/10/22: Re: DC Blocker
158343: 15/10/22: Re: DC Blocker
158355: 15/10/23: Re: recovery/removal timing
158356: 15/10/23: Re: recovery/removal timing
158361: 15/10/23: Re: recovery/removal timing
158400: 15/10/29: Re: recovery/removal timing
158406: 15/10/29: Re: recovery/removal timing
158416: 15/10/30: Re: recovery/removal timing
158420: 15/10/30: Re: recovery/removal timing
158444: 15/11/30: Re: Simulation vs Synthesis
158481: 15/12/02: Re: Simulation vs Synthesis
158485: 15/12/03: Re: Simulation vs Synthesis
158498: 15/12/03: Re: Simulation vs Synthesis
158626: 16/02/08: Re: Source control and ip cores
158645: 16/02/25: Re: Source control and ip cores
158668: 16/03/04: Re: How to define a counter whose width is big enough to hold integer
158927: 16/05/25: Re: Explicitly setting a variable to undefined
158929: 16/05/25: Re: Explicitly setting a variable to undefined
158987: 16/05/31: Re: Explicitly setting a variable to undefined
158989: 16/05/31: Re: Explicitly setting a variable to undefined
158994: 16/06/01: Re: Explicitly setting a variable to undefined
159079: 16/07/26: Re: Mod-24: The State of High-Level Synthesis in 2016
159355: 16/10/14: Re: CORDIC in a land of built-in multipliers
159475: 16/11/21: Re: Phrasing!
159479: 16/11/22: Re: Phrasing!
159516: 16/11/29: Re: Phrasing!
159826: 17/03/24: Re: Simulation of PCIe at TLP level
159831: 17/04/04: Re: handshacking between modules, best practices ?
159957: 17/05/02: Re: RISC-V Support in FPGA
159969: 17/05/03: Re: RISC-V Support in FPGA
159971: 17/05/03: Re: RISC-V Support in FPGA
159974: 17/05/03: Re: RISC-V Support in FPGA
159976: 17/05/03: Re: RISC-V Support in FPGA
159981: 17/05/04: Re: creating a seed on a FPGA.
160200: 17/08/04: Re: minimal HDMI pins to send video ?
160258: 17/09/18: Re: logic scope coding
160447: 18/01/23: Re: My invention: Coding wave-pipelined circuits with buffering function
Mark D'Sylva:
39183: 02/02/03: Re: JTAG Boundary Scan with the XDS510
39203: 02/02/04: Re: JTAG Boundary Scan with the XDS510
Mark de Wit:
8069: 97/11/13: Looking for dynamically reprogrammable FPGA's
Mark Dixon:
55266: 03/05/02: SPI-4.2 dynamic alignment - how'd they do that?
Mark Enwright:
20368: 00/02/07: Cool website... Engineering Salary Survey
Mark Fanara:
3459: 96/06/03: Re: RS422 Connections and Pin-outs
3481: 96/06/06: Re: RS422 Connections and Pin-outs
Mark Ferguson:
33793: 01/08/05: Re: Why did Zephram spool outside all the users? We can't post procedures unless Brion will grudgingly dig afterwards.
Mark Fleming:
85955: 05/06/19: Re: Upgrading the EDK from 6.3
Mark Freeman:
67478: 04/03/12: Re: PWM, PLD programming ,(up/down ramp frequency)
Mark Garaway:
3821: 96/08/06: Problem With Xilinx/Viewlogic PROwave
3908: 96/08/18: Re: XACT6.0:prosim and routed design
5523: 97/02/21: Re: Q: Anyone bought APS-X84 FPGA board?
Mark Goldberg:
3552: 96/06/20: Agencies Avaliable
Mark Gonzales:
2716: 96/01/29: Re: Chosing VHDL or Verilog Does Have An Impact For U.S. Engineers
Mark Goodson:
8599: 98/01/12: Re: SDRAM model
9672: 98/03/30: Re: VHDL shareware editor?
Mark Grindell:
17178: 99/07/07: Re: ALTERA GDF to VHDL QUESTION
17179: 99/07/07: Re: 100 Billion operations per sec.!
17180: 99/07/07: Re: 100 Billion operations per sec.!
17286: 99/07/17: Re: fpga 10k50 and up prototype with a/d d/a
17347: 99/07/22: Re: fpga 10k50 and up prototype with a/d d/a
17348: 99/07/22: Re: Chemical FPGAs
17470: 99/07/30: Semi-deterministic behaviour in FPGA's
Mark Haase:
92645: 05/12/02: Re: Quick question, how do I supply +-5V?
Mark Harrison:
30479: 01/04/10: CONTRACTORS
Mark Harvey:
10829: 98/06/24: vhdl model for duart
17877: 99/09/15: R: PROBLEMS WITH ORCA
18000: 99/09/22: No Subject
18351: 99/10/18: R: Reading a Lattice ispLSI 1016
18695: 99/11/08: R: StateCAD versus Viewdraw
19042: 99/11/25: R: How to use multiple resets?
19309: 99/12/13: R: Command line for FPGA Express
20178: 00/01/30: Re: ARM core?
20179: 00/01/30: Re: Testbenches
20433: 00/02/10: Re: Xilinx vs Altera
20434: 00/02/10: Re: Spartan and timing analyzer: clock nets using non-dedicated resources
20471: 00/02/11: Re: MP3 & Wavelet on FPGA
20750: 00/02/20: Re: Viewlogic 4 and XACT6.1 - any good for XC4k ??
20783: 00/02/22: Re: Generating a Higher Frequency Clock from a Lower One in FPGA
21664: 00/03/28: Xilinx DLL properties
22201: 00/05/01: Re: Xilinx CPLD Make file
22389: 00/05/07: Re: edif
22508: 00/05/10: SpartanXL driving 5V CMOS input
22741: 00/05/22: Re: Spartan 2 Industrial temp range versions
23053: 00/06/11: Re: using DDL in virtex FPGA
25390: 00/09/09: Re: VirtexE availability?
25506: 00/09/13: Re: VirtexE availability?
25507: 00/09/13: Re: VirtexE availability?
25508: 00/09/13: Re: VirtexE availability?
25689: 00/09/17: Re: VirtexE availability?
26350: 00/10/12: Re: Xilinx FDN Express vs. Base Express ??
26418: 00/10/15: Re: DLL's Spread Spectrum Compatible ??
26605: 00/10/22: Re: Cheapy FPGA sw
27131: 00/11/12: Re: ChipScope
27318: 00/11/17: Re: 5v parallel cable with 2.5/3.3v spartan II?
27333: 00/11/18: Re: Altera MAX+PlusII v.s. Xilinx Foundation
30660: 01/04/22: Re: Who make Xilinx Proto PCBs ? Spartan II on PCI bus.
Mark Hillers:
19386: 99/12/17: Simulation of Virtex-XDW
20595: 00/02/15: coregen-bug produces bad blockram > 16 bit
20613: 00/02/16: Re: coregen-bug produces bad blockram > 16 bit
20682: 00/02/17: Re: coregen-bug produces bad blockram > 16 bit
20709: 00/02/18: Re: coregen-bug produces bad blockram > 16 bit
23897: 00/07/14: synopsys 2000.05 loses control of virtexBlockRam
26805: 00/10/30: ChipScope, MultiLINX and NT
Mark Holland:
70079: 04/06/01: Problems with PLAmap (part of RASP package) from UCLA
Mark Humphries:
160420: 18/01/18: Re: HDL simple survey - what do you actually use
Mark Indovina:
2307: 95/11/18: Re: [q][Reverse Engineering Protection]
MARK INDOVINA Xxxxx Ppppp:
32: 94/08/01: Re: How pricey is FPGA development?
91: 94/08/12: John Cooley is looking for FPGA/Synth Benchmarks
483: 94/12/01: Re: Bit Serial ?
885: 95/03/21: Re: Free Viewlogic design kits?
932: 95/03/31: Re: Opinions on IBM PowerPC for Electronics CAD lab
973: 95/04/05: Re: Neocad merges with Xilinx
1027: 95/04/18: Re: $40 Million For NeoCAD & A New FPGA Synthesis Tool
Mark Johnson:
562: 95/01/04: Re: What's Up At ViewLogic?
6583: 97/06/04: Re: Memory workshop, San Jose
7887: 97/10/27: Re: All Digital DLL or PLL with less than 20ps resolution
8130: 97/11/20: Study guide for metastability
8268: 97/12/04: Fun real-world problem re: metastability, can YOU work it?
8441: 97/12/15: Re: MTBF Calculation. Looking for articles on the subject
8453: 97/12/16: metastability: full citation of Hohl, extracting TAU and T0
10666: 98/06/09: Re: papers wanted on DRAM
Mark Jones:
77753: 05/01/16: Re: What is the difference between ASIC and FPGA?.
82489: 05/04/13: Re: Regarding driving of SCL and SDA pins of I2C
82544: 05/04/13: Re: Regarding driving of SCL and SDA pins of I2C
Mark Kahrs:
1020: 95/04/17: Re: Need "fusemap" information from vendor, likely?
Mark Kinsley:
17314: 99/07/20: Solaris vs. NT
17319: 99/07/21: Re: Solaris vs. NT
38753: 02/01/24: Intel vs. AMD
38807: 02/01/25: Re: Intel vs. AMD
38997: 02/01/29: Re: Synthsis Tools for Xilinx
Mark Korsloot:
14536: 99/02/03: Re: Q:EEPROM for Xilinx XC4k
24273: 00/08/02: Re: QuickLogic PCI/FPGA chip (QL5064)...experiences?
25594: 00/09/14: Re: CPLD: Basic informations
29528: 01/02/25: Re: Second Source For ALTERA EPC1 ?
30248: 01/03/29: Re: PCI-X core
30251: 01/03/29: Re: VHDL question
47106: 02/09/17: Re: Question on Fast CPLDs
Mark L. Hampton:
2558: 96/01/02: Re: Need help: Actel "bibuf" working with Quicksim II (Men 8.4)
Mark Lancaster:
13539: 98/12/08: Re: Verilog/FPGA Express Synth Problem
17694: 99/08/24: Re: Parallel in Serial out
17709: 99/08/25: Re: Parallel in Serial out
Mark Levis:
15607: 99/04/02: Re: New Book: Programming Embedded Systems in C and C++
Mark Levitski:
75283: 04/11/01: Question on Xilinx VirtexProII PCMCIA support (FPGA boards).... please
75318: 04/11/02: Re: Question on Xilinx VirtexProII PCMCIA support (FPGA boards).... please
75319: 04/11/02: Re: Question on Xilinx VirtexProII PCMCIA support (FPGA boards).... please
74622: 04/10/15: Question on Xilinx VirtexPro II FPGA chip... please
74717: 04/10/17: Re: Xilinx VirtexE internal oscillator
74718: 04/10/17: Re: Xilinx VirtexE internal oscillator
74832: 04/10/20: Re: Question on Xilinx VirtexPro II FPGA chip... please
Mark Lew:
Mark Luscombe:
15704: 99/04/09: Re: ZBT to Virtex Interface at +100M
20452: 00/02/10: Xilinx Virtex Reset
20551: 00/02/14: Re: Xilinx Virtex Reset
20636: 00/02/16: Re: Xilinx Virtex Reset
20681: 00/02/17: Re: Xilinx Virtex Reset
Mark Mahoney:
27188: 00/11/14: Job posting info
Mark Markham:
9479: 98/03/16: Re: Xilinx could gaurd its secrets better (Re: Strange Xilinx question?)
Mark McDougall:
72963: 04/09/09: Re: Need assistance with an FPGA based project.
73052: 04/09/13: Re: Need some help with some technical claims...
73629: 04/09/27: Re: embedded linux on FPGA?
72921: 04/09/08: Re: Need assistance with an FPGA based project.
73098: 04/09/14: Re: Need some help with some technical claims...
73148: 04/09/15: Re: EDK OPB Uart 16550
75157: 04/10/28: Re: Programmable I/O Card for the PC - does it exist ?
75179: 04/10/28: Re: Viewing/Controling C-Build Outputs
76728: 04/12/10: Re: Getting Started With Simple Sound Synthesis
77938: 05/01/21: Re: C programmer, what does this syntax mean?
77940: 05/01/21: Re: Xilinx Sum in VHDL
80893: 05/03/14: Re: Which HDL?
81010: 05/03/17: Re: Need recommendation on an FPGA board with a USB socket.
81335: 05/03/22: OCIDEC3 testbench failure
81337: 05/03/22: Re: OCIDEC3 testbench failure
81342: 05/03/22: Re: OCIDEC3 testbench failure
81615: 05/03/29: newbie verilog question
81688: 05/03/30: Re: newbie verilog question
82323: 05/04/11: Re: Shared bus on FPGA
83207: 05/04/26: Re: Space Invaders!
88080: 05/08/09: Re: how to reduce vga memory????????
88081: 05/08/09: Re: how to reduce vga memory????????
88474: 05/08/19: Re: how to reduce vga memory????????
88557: 05/08/23: Re: how to reduce vga memory????????
88558: 05/08/23: Re: uDMA Hard drive interface - putting together multiple programs.
89244: 05/09/09: Re: Cyclone conf flash - 25p10 !
89245: 05/09/09: Re: Quartus II - Timing Analyzer
89252: 05/09/09: Re: Cyclone conf flash - 25p10 !
89292: 05/09/12: Re: Has anyone successfully used opencores PCI in FPGA desings?
89326: 05/09/13: Re: SDRAM quality
89378: 05/09/14: Re: SDRAM quality
89385: 05/09/14: Re: fan out capability of FPGA
89386: 05/09/14: Re: fan out capability of FPGA
89580: 05/09/20: Re: Reprogramming FPGA over PCI???
89902: 05/09/30: Re: There is a way to instantiate 'N' VHDL components using a repetitive
90305: 05/10/10: Re: 16550 VHDL code
90429: 05/10/13: Re: [OT]Re: converting 12v signal to 3.3v
91061: 05/10/28: Re: hex rep. in VHDL
91178: 05/11/01: Re: hex rep. in VHDL
91186: 05/11/01: Re: hex rep. in VHDL
91191: 05/11/01: Simulating Cyclone II PLL
91229: 05/11/02: Re: hex rep. in VHDL
91801: 05/11/14: Re: PCI test bench
91927: 05/11/17: Re: UART CORE FOR NIOS
92219: 05/11/24: Re: Unconnected Ports
92780: 05/12/07: Re: VHDL SPI core
93102: 05/12/14: Re: Frequency dependent SOPC builder components
93159: 05/12/15: Re: Frequency dependent SOPC builder components
95907: 06/01/27: Re: ATA controller in fpga
96217: 06/02/01: Re: ERROR message when programming FPGA with Altium Designer 2004
96219: 06/02/01: Re: scrambling
96934: 06/02/14: Re: SCHEMATICS ... Is anybody as frustrated as I am with the software?
97868: 06/03/01: Re: FPGA communication, I2C and DAC
98002: 06/03/03: Re: DMA and PCI in SoPC Builder
98633: 06/03/14: Re: Why does Xilinx hate version control?
100771: 06/04/18: Re: Quartus SignalTap and bus turn around
100774: 06/04/18: Re: How to connect FPGA and =?ISO-8859-1?Q?=B5C?=
101953: 06/05/09: Re: PCI Express and DMA
102041: 06/05/10: Re: PCI Express and DMA
102042: 06/05/10: Re: PCI Express and DMA
102052: 06/05/10: Re: simulation works fine but the actual chip doesnt work
102130: 06/05/11: Re: PCI Express and DMA
102145: 06/05/11: XCFxxP Plaform Flash Device Questions
102147: 06/05/11: Re: XCFxxP Plaform Flash Device Questions
102202: 06/05/12: Re: simulation works fine but the actual chip doesnt work
103678: 06/06/08: Re: Incrmental Compilation in Quartus 5.1
104085: 06/06/19: Re: Floppy to FPGA?
104138: 06/06/20: Re: Floppy to FPGA?
104298: 06/06/23: Re: stimulus for FPGA
104406: 06/06/27: Re: Space invaders on Spartan3e starter board
104411: 06/06/27: Re: Space invaders on Spartan3e starter board
104570: 06/06/30: Re: Altium Designer LiveDesign Evaluation Kits (once again)
104575: 06/06/30: Re: Spartan3e starter kit vga mod
104781: 06/07/06: Re: How much time does it need to sort 1 million random 64-bit/32-bit
105251: 06/07/19: Re: Which PCI core for Cyclone II board?
105307: 06/07/20: Re: Which PCI core for Cyclone II board?
105505: 06/07/25: Re: Which PCI core for Cyclone II board?
105506: 06/07/25: Re: Which PCI core for Cyclone II board?
105556: 06/07/26: Re: Virtex4 Rocket I/O. Power filtering.
105600: 06/07/27: Re: Which PCI core for Cyclone II board?
105605: 06/07/27: Re: Which PCI core for Cyclone II board?
106302: 06/08/11: NgdBuild:604 error
106303: 06/08/11: Re: NgdBuild:604 error
106468: 06/08/14: Re: NgdBuild:604 error
106534: 06/08/15: Re: NgdBuild:604 error
106582: 06/08/16: Re: NgdBuild:604 error
106663: 06/08/17: Re: Quartus and source control (continued)
106664: 06/08/17: Re: xilinx or altera?
106665: 06/08/17: Re: xilinx or altera?
106676: 06/08/17: Re: Quartus and source control (continued)
106677: 06/08/17: Re: Quartus and source control (continued)
107756: 06/09/01: Re: Performance Appraisals
109377: 06/09/26: Re: Help required regarding PCI Master core
109448: 06/09/27: Re: Help required regarding PCI Master core
109527: 06/09/28: Re: Is it worth learning SOPC Builder, DSP Builder & Nios Processor?
109543: 06/09/28: Re: Help required regarding PCI Master core
109544: 06/09/28: Re: Is it worth learning SOPC Builder, DSP Builder & Nios Processor?
109745: 06/10/05: Re: Help required regarding PCI Master core
110038: 06/10/10: Re: Quartus II 6.0
110087: 06/10/11: Re: Nios software IDE
110088: 06/10/11: Re: Nios software IDE
110100: 06/10/11: Re: Nios software IDE
110172: 06/10/12: Re: a clueless bloke tells Xilinx to get a move on
110178: 06/10/12: Re: Cyclone PLL
110627: 06/10/19: Re: Cheapest FPGA board to study VHDL on
110815: 06/10/24: Re: Survey on Quartus SOPC/Nios-II
111191: 06/10/31: Re: FPGA's for Ethernet?
111270: 06/11/01: Re: FPGA's for Ethernet?
111435: 06/11/03: Re: regardign signal assinment statement............................
111438: 06/11/03: Re: Help required regarding PCI Master core
111548: 06/11/06: Re: Help required regarding PCI Master core
111623: 06/11/07: Modelsim problem - mixed VHDL,Verilog & VHO
111669: 06/11/08: Re: Modelsim problem - mixed VHDL,Verilog & VHO
111670: 06/11/08: Re: Modelsim problem - mixed VHDL,Verilog & VHO
111716: 06/11/09: Re: Graphics-2-FPGA
111718: 06/11/09: Re: floating point arithemetic on fpga
111719: 06/11/09: Re: Non deterministic behaviour in quartus II ?
111720: 06/11/09: Re: Modelsim problem - mixed VHDL,Verilog & VHO
111779: 06/11/10: Re: Non deterministic behaviour in quartus II ?
111780: 06/11/10: Re: Non deterministic behaviour in quartus II ?
111899: 06/11/13: Re: SPI module in FPGA
111967: 06/11/14: Re: NTSC/VGA / Ethernet Advice for S3EBOARD from Digilent
111972: 06/11/14: Re: Nested Generate Statement in VHDL
112099: 06/11/16: Re: Problems with Opencores' I2C "READ" function
113304: 06/12/11: Re: JTAG programming of Altera Cyclone and CONF_DONE
113370: 06/12/12: Re: JTAG programming of Altera Cyclone and CONF_DONE
113593: 06/12/18: Re: JTAG programming of Altera Cyclone and CONF_DONE
114264: 07/01/10: Re: Accessing SATA hard disk for read/write IO through FPGA in an
115179: 07/02/02: Re: Graphics demo using FPGA?
115244: 07/02/05: Re: query in P&R of FPGA
116667: 07/03/15: Re: .bit file to VHDL/verilog source code
117217: 07/03/27: Re: how to read a sequence of video
117812: 07/04/11: Re: Newbie with bus width mismatch problem. Quartus II
118217: 07/04/20: Re: Regarding drivers for FPGA based PCI cards
118398: 07/04/26: Re: I make a usb blaster for altera by myself!
119467: 07/05/21: Re: Signal Assignment bugs in Quartus-II ... AGAIN!
119713: 07/05/25: Re: 6502 and CPU licences in general
119714: 07/05/25: Re: VGA signal through breadboard?
120087: 07/06/01: Re: After PAR simulation, should I assume that it will work on FPGA
120219: 07/06/04: Re: Regarding multiple write problem in opencores pci bridge
120220: 07/06/04: Re: Altera Serial Flash Loader (SFL) question
120221: 07/06/04: Re: Altera Serial Flash Loader (SFL) question
120227: 07/06/04: Re: Altera Serial Flash Loader (SFL) question
120486: 07/06/08: Re: A first FPGA project
120503: 07/06/08: Re: A first FPGA project
120560: 07/06/10: Re: A first FPGA project
120674: 07/06/14: Re: Frogger and Scramble released
120947: 07/06/21: Re: Can anyone identify the manufacturer of this Chip ?
120950: 07/06/21: Re: Can anyone identify the manufacturer of this Chip ?
121012: 07/06/22: Re: Can anyone identify the manufacturer of this Chip ?
121068: 07/06/25: Re: Can anyone identify the manufacturer of this Chip ?
121111: 07/06/26: Re: Can Cyclone II PLL_out be driven by the pll output c0 and c1?
121112: 07/06/26: Re: Can Cyclone II PLL_out be driven by the pll output c0 and c1?
121152: 07/06/27: Re: Can Cyclone II PLL_out be driven by the pll output c0 and c1?
121238: 07/06/29: Re: d-link router?
121428: 07/07/04: Re: Hobbyist trying to decide which device to start with...
121621: 07/07/10: Re: LiveDesign, Altium [opinion]
121773: 07/07/13: Re: Xilinx PCIe endpoint core minimalistic design
122039: 07/07/18: Re: Generating video noise.
123383: 07/08/27: Re: Annoying
123488: 07/08/29: Re: VGA controller in the EDK ?
123718: 07/09/03: Re: [Nios II] How Can I define the pio inputs as a interrupt?
123849: 07/09/06: Re: =?ISO-8859-1?Q?=A1=BENios_II=A1=BFHow_Can_I_Find_O?=
123978: 07/09/10: Re: Anyway to stop Altera Stratix II SignalTap data acquisition
124014: 07/09/11: Re: How to simple convert a hex or mif file from Altera to Xilinx
124082: 07/09/12: Re: PCI byte enalbes in read cycles
124083: 07/09/12: Re: PCI byte enalbes in read cycles
124098: 07/09/12: Re: PCI byte enalbes in read cycles
124189: 07/09/14: Re: overloading ' operators in VHDL
124531: 07/09/26: Re: Never buy Altera!!!!
124603: 07/09/28: Re: Never buy Altera!!!!
124604: 07/09/28: Re: Never buy Altera!!!!
124933: 07/10/11: Xiinx ERROR:PhysDesignRules:10
125213: 07/10/18: Re: FPGA quiz3, or where Antti did give up and does not know answer
125214: 07/10/18: Re: FPGA quiz3, or where Antti did give up and does not know answer
125410: 07/10/25: Re: builing a SPI interface in vhdl
125463: 07/10/26: Re: is Quartus 7.1 really that S*** !?
125464: 07/10/26: Re: fgpa beginner
126630: 07/11/29: Quartus memory init file
126637: 07/11/29: Re: Quartus memory init file
126644: 07/11/29: ISE WARNING Xst:647
126645: 07/11/29: Re: Quartus memory init file
126706: 07/11/30: Re: ISE WARNING Xst:647
126713: 07/11/30: Re: ISE WARNING Xst:647
126799: 07/12/03: Re: ISE WARNING Xst:647
126803: 07/12/03: Re: ISE WARNING Xst:647
128522: 08/01/30: Re: regarding DMA memory to memory copy in NIOS II
128566: 08/01/31: Re: ROM/LUT
128706: 08/02/05: Re: 4-bit table look-up
128866: 08/02/08: Re: I/O mode to use for USB ..?
128924: 08/02/11: Re: Strange "Style guide" requirements...
129756: 08/03/05: Re: [Altera] How to infer some code into ROM-blocks (in automatic
130994: 08/04/08: Re: Avalon Bus <-> Wishbone Bus
133262: 08/06/23: Re: is lwIP absolutely necessary for tcp-ip?
133329: 08/06/25: Re: Configuration Management Best Practices
133504: 08/07/02: Re: Nintendo DS Screenshots / Video Capture
133536: 08/07/03: Re: Nintendo DS Screenshots / Video Capture
133786: 08/07/15: Re: Reading FPGA internal memory data
133789: 08/07/15: Re: Reading FPGA internal memory data
134628: 08/08/22: Re: Apple II on FPGA
134944: 08/09/08: Re: need sme help on data encryption based on fpga
135151: 08/09/18: Re: Moving to Altera from Xilinx
135167: 08/09/19: Re: Moving to Altera from Xilinx
135316: 08/09/26: Re: Please recommend good textbook or technical report about FPGA
136041: 08/10/29: ISE 9.2.03i problem
136042: 08/10/29: Re: ISE 9.2.03i problem - work-around
136069: 08/10/30: Re: ISE 9.2.03i problem
136070: 08/10/30: Re: ISE 9.2.03i problem
136087: 08/10/31: Re: ISE 9.2.03i problem
136088: 08/10/31: Re: ISE 9.2.03i problem
136089: 08/10/31: Re: ISE 9.2.03i problem
136142: 08/11/04: Re: ISE 9.2.03i problem
136143: 08/11/04: Re: Why does Nios cannot pass make?
136150: 08/11/04: Re: Why does Nios cannot pass make?
136362: 08/11/13: Re: ISE 9.2.03i problem
136365: 08/11/13: Re: ISE 9.2.03i problem
136460: 08/11/18: Re: Aligned PLL clocks in RTL simulation
136481: 08/11/19: Re: vga interfacing for image display
136533: 08/11/21: Re: Altera DE3 - USB Bulk Transfer
136584: 08/11/24: Re: Altera DE3 - USB Bulk Transfer
136585: 08/11/24: Re: Altera DE3 - USB Bulk Transfer
137168: 08/12/30: Re: How do I xor two signals in VHDL?
137202: 09/01/02: Re: Altera - Create sof file with software inside.
137508: 09/01/21: Re: Image enhancement on FPGA
138277: 09/02/12: Re: Read a PS2 Keyboard input
138644: 09/03/03: Re: Character generator ROM and VGA controller for Spartan 3E
139196: 09/03/24: Globals in mixed-language projects
139552: 09/04/03: Re: clock multipliers, dividers, and more clocks...
139584: 09/04/06: Re: clock multipliers, dividers, and more clocks...
139598: 09/04/07: Re: Modulo-10 counter
139599: 09/04/07: Re: Modulo-10 counter
139605: 09/04/07: Re: pll
139634: 09/04/08: Re: Modulo-10 counter
139817: 09/04/15: Re: Ethernet on Altera FPGA: Help required
139838: 09/04/16: Re: Synchronous clocking between Cyclone III and SDRAM
141987: 09/07/21: Re: How do you handle build variants in VHDL?
141989: 09/07/21: Re: Using OPEN in port map
142040: 09/07/23: Re: How do you handle build variants in VHDL?
142041: 09/07/23: Re: How do you handle build variants in VHDL?
142081: 09/07/24: Re: How do you handle build variants in VHDL?
142148: 09/07/27: Re: How do you handle build variants in VHDL?
142663: 09/08/25: Re: Yet Another Graphics Controller
142664: 09/08/25: Re: Yet Another Graphics Controller
142795: 09/09/02: Re: Wants an update on FPGA development IDE/toolchains
142857: 09/09/04: Re: Wants an update on FPGA development IDE/toolchains
142858: 09/09/04: Re: Choice of Language for FPGA programming
142897: 09/09/07: Re: Choice of Language for FPGA programming
143828: 09/10/28: Re: HI.. Help Needed Its Urgent
143985: 09/11/06: OK Xilinx users, it's time I was let in on the joke...
144243: 09/11/23: Re: NIOS and ftoa()
148669: 10/08/17: Re: VDHL initializing
Mark McMahon:
42754: 02/05/02: Xilinx Download Cable III
49951: 02/11/26: Re: Fast Digital Synthesis Generator
50175: 02/12/04: Re: PROM for XC2S300
Mark Momcilovich:
29350: 01/02/15: Re: Configuration of FPGA using SPROM
40528: 02/03/08: Re: Synopsys Design Compiler
46185: 02/08/21: Re: INOUT port
46405: 02/08/28: Re: My SpartanII thinks it's a Virtex??
Mark Moyer:
56962: 03/06/19: Re: Stapl Player vs. SVF Player
57014: 03/06/20: Re: PALs, GALs and ABEL
59811: 03/08/28: Re: Convert Jedec to logical equations
Mark Murray:
102808: 06/05/21: Quartus ByteBlaster in Active Serial Programming mode not working
102817: 06/05/21: Re: Quartus ByteBlaster in Active Serial Programming mode not working
Mark Nass:
981: 95/04/06: Re: Need 100 MHz, relatively low power FPGAs
Mark Nelson:
41553: 02/04/02: Re: Data Compression in FPGAs
Mark Ng:
31295: 01/05/17: Re: Xilinx Coolrunner 100% routable - but the tools aren't
32799: 01/07/09: Re: XC9500 drive capability
32802: 01/07/09: Re: Xilink WebPACK keeps removing a pin I want to keep.
42081: 02/04/15: Re: Xilinx FPGA load - XAPP 502
42640: 02/04/29: Re: Xilinx XC9500XL family - disabling the bus-hold circuits
44922: 02/07/05: Re: Setting individual slewrate on Xilinx Coolrunner II
46829: 02/09/09: Re: Are Xilinx CoolRunners / Atmel ATF15xx CPLD's flash-based?
48890: 02/10/25: Re: cpld I/O modes
55635: 03/05/14: Re: CollRunner-II EVB problems
66024: 04/02/11: Re: NAND flash interface?
70480: 04/06/17: Re: SPARTAN-IIE -> LVCMOS18
70956: 04/07/02: Re: Xilinx VS. Lattice ABEL code a standard?
72228: 04/08/11: Re: new XILINX 9500XL datasheets
72835: 04/09/03: Re: [XC96xxXL] Maximum Value for the external Pull-Up resistor ...
73561: 04/09/23: Re: High speed counters on Xilinx CoolRunner-II
75875: 04/11/17: Re: 5V inputs with series resistor on Spartan-3
Mark Norton:
4832: 96/12/18: Proper target for design
Mark Osterud:
5683: 97/03/07: FPGA Reliability
Mark Pettigrew:
34716: 01/09/05: Re: FPGA : USB in an FPGA, has anyone done it before?
Mark Proctor:
22365: 00/05/05: Re: [BitGen] - pb option UserClk
Mark Purcell:
11221: 98/07/27: Re: How to write a VHDL counter of up & down
11299: 98/08/03: Re: [****] VHDL Compile Error ( +, & Operator )
11302: 98/08/03: VHDL std_logic_vector to integer
11314: 98/08/04: Re: VHDL std_logic_vector to integer
11334: 98/08/05: Re: VHDL std_logic_vector to integer
11336: 98/08/05: Re: VHDL std_logic_vector to integer
11428: 98/08/12: Re: Gray code counter in ABEL HDL?
11477: 98/08/18: Re: Help on Xilinx !
11489: 98/08/19: Re: Where are the multiple drivers?
11535: 98/08/21: Re: half full flag in a xilinx async fifo?
11629: 98/08/27: Re: half full flag in a xilinx async fifo?
11650: 98/08/28: Re: half full flag in a xilinx async fifo?
11923: 98/09/18: Re: ASIC -> FPGA async issues
11971: 98/09/22: Re: ASIC -> FPGA async issues
Mark Raviola:
30229: 01/03/28: Recommended Oscillators for DLL's at 25 MHz
Mark Rawlings:
26270: 00/10/10: Computer Architecture emulator on a Xilinx chip
Mark Rogers:
15521: 99/03/28: Re: Free Xilinx Vendor Tools ... NOT :-(
15527: 99/03/29: IP cores and software industry
15535: 99/03/29: Re: Free Xilinx Vendor Tools ... NOT :-(
15558: 99/03/30: Re: Free Xilinx Vendor Tools ... NOT :-(
Mark Russell:
27870: 00/12/13: Hold time constraints in virtex?
28005: 00/12/19: Re: Hold time constraints in virtex?
Mark Sandford:
1033: 95/04/18: Re: Free Hardware
50432: 02/12/10: Re: Tiny Forth Processors
56359: 03/06/03: Re: size of SRAM, antifuses and EPROM elements
56381: 03/06/03: Re: Spartan-3 questions?
56818: 03/06/16: Re: Downloading bit-stream with a microprocessor.
57673: 03/07/03: Re: ARM+FPGA
58556: 03/07/25: Re: device selection for game system
67956: 04/03/23: Re: How many times can I burn an FPGA?
Mark Sandstrom:
4640: 96/11/25: How to utilize XC4000e IOB FFs in Synopsys?
6383: 97/05/20: Problem in Leonardo synthesis targetting Altera
6395: 97/05/21: Re: Problem in Leonardo synthesis targetting Altera
6871: 97/07/04: How to describe XC4000EX/XL FIFOs/RAMs in VHDL?
6970: 97/07/17: Problem with unexpanded logic in xnf synhesized by Leonardo
6978: 97/07/18: Re: Problem with unexpanded logic in xnf synhesized by Leonardo
6997: 97/07/21: Re: Problem with unexpanded logic in xnf synhesized by Leonardo
Mark Sasten:
14093: 99/01/12: Foundation v1.5i Spartin Problems
27020: 00/11/07: Re: Architecture/environment suggestions
71947: 04/08/04: Re: adding real UART to xilinx ultracontroller design.
83740: 05/05/05: Re: including components, i.e. SRL16
Mark Schellhorn:
55705: 03/05/16: Eng. samples -- differences from production?
56283: 03/06/02: Re: Parallel_case Synthesis directive
56331: 03/06/03: Re: Parallel_case Synthesis directive
64158: 03/12/18: Re: Xilinx IOSTANDARD for PCI-X 100MHz interface
64266: 03/12/23: Re: pcix core in XC2VP7
64360: 03/12/30: Re: virtex-II problems
64473: 04/01/05: Re: Xilinx Logicore PCI64 Problem
64716: 04/01/12: Re: pci-x core
64776: 04/01/13: logicore PCIX issue/question
64800: 04/01/14: Re: logicore PCIX issue/question
64879: 04/01/15: Re: DMA w/ Xilinx PCIX core: speed results and question
64884: 04/01/15: Re: logicore PCIX issue/question
64926: 04/01/16: Re: DMA w/ Xilinx PCIX core: speed results and question
67257: 04/03/09: Re: a way to use netlists from C
67802: 04/03/19: Re: Why It Is not Recommended to Infer latches in VLSI Design...
69400: 04/05/10: Re: PCIX DMA Serverworks chipset
70851: 04/06/30: PCI-X DMA problem w/ Xeon?
72124: 04/08/09: Re: PCI express FPGA board
Mark Shand:
934: 95/03/31: Re: meta-systems, who are they ?
3517: 96/06/13: External SRAM, XC4000 and clock hackery
4154: 96/09/19: Re: 256K EEPROM
4429: 96/10/28: Re: Has anyone ever used a C -> Xilinx netlister?
5479: 97/02/19: Re: [Q] Xilinx FPGA Resources
5480: 97/02/19: Re: PCI Prototyping board with a XC4013E or XC4013EX
15228: 99/03/15: Re: Questions on Pamette.
Mark Sitkowski:
3650: 96/07/09: Re: ANNOUNCE: New Model of the Month - 16 bit ADC
3659: 96/07/10: Re: ANNOUNCE: New Model of the Month - 16 bit ADC
Mark Smith:
48943: 02/10/28: Re: VHDL v. Verilog, Xilinx v. Altera.
76581: 04/12/06: Re: making an fpga hot
76582: 04/12/06: Re: How to subscribe to the newsgroup comp.arch.fpga
77908: 05/01/20: Re: LVDS through connectors
Mark Smotherman:
4008: 96/09/02: query: C to FPGA?
Mark Snook:
643: 95/01/26: Exemplar vs. NeoCAD
925: 95/03/30: FPGA synthesis
1050: 95/04/21: VHDL -> Xilinx synthesis
1138: 95/05/04: Re: IOLOC or Other Xilinx Tools
1215: 95/05/16: PLDShell Plus
1250: 95/05/22: global clocks in ASYL
1332: 95/06/02: Re: AT&T serial EEPROMS
1745: 95/08/24: Quicklogic/Cypress/Warp3
2239: 95/11/08: Wanted Xilinx XC3090LTQ176-8PC
7977: 97/11/05: Re: Vital files generated by maxplus2
13101: 98/11/16: Re: Xilinx COREgen and Leonardo troubles...
mark spencer:
59674: 03/08/25: Dini DN3000K10S board for sell
Mark Stephens:
2672: 96/01/22: Re: Virtual Computer Corp. still in business?
2714: 96/01/29: GAL programming for hobby use...Is there no hope?
2734: 96/01/31: Re: GAL programming for hobby use...Is there no hope?
2746: 96/02/01: Re: GAL programming for hobby use...Is there no hope?
2872: 96/02/21: Giga Operations ... Comments from customers?
Mark Sterk:
30384: 01/04/05: Re: DSP Volume-control in FPGA
Mark Summerfield:
14941: 99/02/26: Re: Xilinx ABEL?
16273: 99/05/13: Re: Synchronizer design?
16291: 99/05/14: Re: Synchronizer design?
17895: 99/09/16: Re: simple VHDL?
17917: 99/09/17: Re: simple VHDL?
17967: 99/09/20: Re: simple VHDL?
19026: 99/11/25: Re: implementing TCP/IP on PLD
19036: 99/11/25: Re: implementing TCP/IP on PLD
19057: 99/11/26: Re: Analog
19145: 99/12/02: Re: data serializer/decoder FPGA solution
19971: 00/01/21: Re: Indexing functions
19972: 00/01/21: Re: Patent licences for circuits in FPGA
19973: 00/01/21: Re: looping FIFO?
20757: 00/02/21: Re: multiplier
21269: 00/03/15: Re: Programming FPGAs via backplane (Xilinx)
Mark Taylor:
34301: 01/08/20: Some questions about Spartan2 (& a bug report for XST sp8)
34305: 01/08/20: Re: Some questions about Spartan2 (& a bug report for XST sp8)
34334: 01/08/21: Re: Some questions about Spartan2 (& a bug report for XST sp8)
34448: 01/08/25: Re: Some questions about Spartan2 (& a bug report for XST sp8)
34449: 01/08/25: Re: Xilinx FPGA Editor - how to route to an internal macro net?
34466: 01/08/26: Re: Some questions about Spartan2 (& a bug report for XST sp8)
34467: 01/08/26: Some questions about Spartan2 (& a bug report for XST sp8)
34510: 01/08/28: Re: Xilinx FPGA Editor - how to route to an internal macro net?
34608: 01/08/30: Re: Xilinx FPGA Editor - how to route to an internal macro net?
34624: 01/08/31: Re: Xilinx FPGA Editor - how to route to an internal macro net?
Mark Thorson:
21198: 00/03/10: Re: Extremely fault tolerant strategies
152566: 11/09/14: Re: The Manifest Destiny of Computer Architectures
152567: 11/09/14: Re: The Manifest Destiny of Computer Architectures
152568: 11/09/14: Re: The Manifest Destiny of Computer Architectures
Mark van de Belt:
19147: 99/12/02: Command line for FPGA Express
19172: 99/12/03: Re: Command line for FPGA Express
19405: 99/12/20: Re: How to include SpartanXL code in C souce code?
19470: 99/12/23: Re: Bi-directional 3-State Buffer
39062: 02/01/30: Re: MapLab:30 Error in ISE 4.1i
39894: 02/02/21: Re: Problem While Downloading to Spartan 2 FPGA using JTAG
39896: 02/02/21: INIT on XC2S30
39928: 02/02/22: Re: INIT on XC2S30
39995: 02/02/23: Re: Replacing expensive configuration SPROM
63068: 03/11/13: Re: unknown devices in JTAG chain
63069: 03/11/13: Writing Blockrams in VHDL
63103: 03/11/14: Re: Writing Blockrams in VHDL
63104: 03/11/14: Re: Inferring Dual Port Block RAM
63397: 03/11/20: Re: avoiding GCLK
63665: 03/11/27: Re: Dual port RAM for Xilinx
63666: 03/11/27: Re: PCI LogiCORE with ISE 5.2
63815: 03/12/04: Re: Dual port RAM for Xilinx
Mark van Wyk:
110938: 06/10/25: Re: Xilinx documentation typos
Mark Vorenkamp:
1396: 95/06/14: Re: Any one working on Cypress PLD's ?
Mark W Brehob:
20989: 00/03/02: Re: Extremely fault tolerant strategies
24435: 00/08/08: Re: Memory specification
28279: 01/01/05: Re: Nondeterministic FSMs in hardware?
Mark W.:
21076: 00/03/06: Re: An optical allusion that will astound you, works on all spec pc's:) 9523
Mark Walter:
30354: 01/04/04: Xilinx Foundation 2.1i License
30868: 01/05/02: Serial UART
30910: 01/05/03: Re: Serial UART
31528: 01/05/29: Re: My80-- i8080A instruction compatible processor core
32193: 01/06/19: Xilinx Student 2.1i FPGA Supported Chips
34035: 01/08/12: Use of lpm in Xilinx Foundation 2.1i
Mark Webster:
1023: 95/04/18: Viewlogic 4.1 & Windows '95
2639: 96/01/17: ProSeries + Actel & Xilinx
3777: 96/07/30: Re: BIDIR Buses
Mark Willey:
8619: 98/01/14: VLSI Design of an FPGA
9291: 98/03/05: Re: The case for free operating systems and EDA
9289: 98/03/05: Re: The case for free operating systems and EDA
9308: 98/03/06: Re: The case for free operating systems and EDA
9309: 98/03/06: Re: The case for free operating systems and EDA
9373: 98/03/07: Re: The case for free operating systems and EDA
Mark Williams:
54550: 03/04/14: Re: Hardware acceleration for raytracing purposes
Mark Wills:
152798: 11/10/24: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE
155072: 13/04/05: Re: MISC - Stack Based vs. Register Based
155073: 13/04/05: Re: MISC - Stack Based vs. Register Based
155076: 13/04/05: Re: MISC - Stack Based vs. Register Based
Mark Woods:
5948: 97/03/28: Re: viewoffice <--> viewoffice compatibility
8778: 98/01/26: Re: Looking for someone to help......
17115: 99/07/01: Re: How to build a NetBridge use FPGA
17116: 99/07/01: Re: FPGAs v/s DSPs in Cell phones
17837: 99/09/10: Re: FreeDES and Free6502 Comments
Mark Wyman:
21212: 00/03/10: Re: **NEW VERSION** MindBender v1.2 814
Mark Zenier:
60: 94/08/06: Re: This (new) froup
2659: 96/01/20: Re: PLD JDEC Files
2717: 96/01/29: Re: GAL programming for hobby use...Is there no hope?
5940: 97/03/27: Re: *** SUMMIT Microelectronics - new semiconductor manufacturer website ***
8291: 97/12/05: Re: what is metastability time of a flip_flop
11674: 98/08/31: Re: New Evolutionary Electronics Book
11808: 98/09/10: Re: New Evolutionary Electronics Book
23210: 00/06/17: Re: Designing a narrowband bandpass filter to pass a tone (analog domain)
<mark.jarvin@gmail.com>:
112961: 06/12/02: Re: Firmware for Xilinx USB cable
112997: 06/12/04: Re: Firmware for Xilinx USB cable
113215: 06/12/08: Re: Firmware for Xilinx USB cable
<mark.snook@arm.com>:
8683: 98/01/20: Altera serial PROMs and Xilinx FPGAs
mark2112:
154400: 12/10/25: RE: Xilinx Xact software for XC2018 Logic Cell Array
<mark4415@my-deja.com>:
27869: 00/12/13: Hold time constraint in Xilinx?
<mark_harvey@my-deja.com>:
18281: 99/10/12: Re: Lattice 1016 replacement
21256: 00/03/14: JTAG by parallel port
MarkAren:
134443: 08/08/11: Altera question - MAX3000 vs MAX7000
134446: 08/08/11: Re: Altera question - MAX3000 vs MAX7000
134514: 08/08/15: Q: Demo Altera NIOS II SOPC limitations
134525: 08/08/16: Re: Q: Demo Altera NIOS II SOPC limitations
134553: 08/08/17: MJL Cyclone Development kit and Quartus II
137211: 09/01/02: MAX7000 power and slew rate control
137234: 09/01/05: Re: MAX7000 power and slew rate control
137235: 09/01/05: Re: MAX7000 power and slew rate control
137283: 09/01/07: Re: MAX7000 power and slew rate control
markc:
153864: 12/06/14: FPGA FIFO MAX data speed
MarkCondit:
4005: 96/09/02: Re: Looking for s/w to generate test vectors
4006: 96/09/02: Re: FPGA vs. Custom design
Marketer:
17492: 99/07/31: Aesthetic software
Markku Vähätaini:
6368: 97/05/19: Re: suggestion about a pcmcia in a fpga
markman:
142269: 09/07/31: Re: Xilinx USB CABLE SCHEMATIC NOW OFFICIALLY PUBLISED !!!! ::) yippii ?yee
<markmcmahon@hotmail.com>:
122386: 07/07/26: Is my microblaze cache functioning?
122818: 07/08/07: Microblaze GPIO interrupt
128733: 08/02/05: GCLK overmapped
129970: 08/03/11: Re: Making changes to custom IP in EDK
130216: 08/03/18: FSL or DMA w/ FIFO?
130226: 08/03/18: Re: FSL or DMA w/ FIFO?
130232: 08/03/18: Re: FSL or DMA w/ FIFO?
136210: 08/11/05: Re: Reading files from CF (microblaze 7 and plb)
markn:
5943: 97/03/28: HELP! - peel programming?
Marko:
30238: 01/03/29: Re: Problems with NIC and FlexLM / W2K
30788: 01/04/29: Re: Virtex-II: Clock-to-PAD Issue
31355: 01/05/20: Re: Can anyone comment on the difference between modelsim PE and XE
35690: 01/10/13: Instantiating Virtex II library macros.
35691: 01/10/13: How to instantiate I/O port with both registered input and output?
70942: 04/07/02: Re: *RANT* Ridiculous EDA software "user license agreements"?
81149: 05/03/18: FIFO i Handel-C
85687: 05/06/13: Re: Searching FPGA board for private use
86882: 05/07/07: Re: Verilog exponential operator issues in simulation (ISE 7.1 SP3 w/ ModelSim 6.0a)
86883: 05/07/07: Re: about fast adder
86897: 05/07/08: Re: Possible bug in Vertex-4 Rocket-IO?
86919: 05/07/08: Re: Possible bug in Vertex-4 Rocket-IO?
86920: 05/07/08: Re: Rocket IO failure after power cycle.
86929: 05/07/09: Re: Possible bug in Vertex-4 Rocket-IO?
86943: 05/07/10: Re: Possible bug in Vertex-4 Rocket-IO?
88561: 05/08/22: Re: ISE7.1i SP3, Dual port block ram, coregen issue
89107: 05/09/05: Re: Modelsim XE and multi-file Verilog projects
89265: 05/09/09: Re: Signed addition
97291: 06/02/20: Is FPGA code called firmware?
97298: 06/02/20: Re: Is FPGA code called firmware?
97340: 06/02/20: Re: arctangent again
97883: 06/03/01: Re: Serious problem with XST
Marko S:
102148: 06/05/11: sqrt(a^2 + b^2) in synthesizable VHDL?
102166: 06/05/11: Re: sqrt(a^2 + b^2) in synthesizable VHDL?
102167: 06/05/11: ISE 8.1 error, help. Or where is the path?
102170: 06/05/11: Re: ISE 8.1 error, help. Or where is the path?
Marko Zec:
142436: 09/08/11: Re: Spartan-6 Boards - Your Wish List
152545: 11/09/12: Re: Lattice XP2 getting hot and/or reading 0's as JTAG ID
152547: 11/09/12: Re: Lattice XP2 getting hot and/or reading 0's as JTAG ID
152548: 11/09/12: Re: Lattice XP2 getting hot and/or reading 0's as JTAG ID
153013: 11/11/14: Re: Enterpoint New Boards
154986: 13/03/18: Re: full tcp offload solution with tcp session setup/teardown support
156644: 14/05/22: Re: How to reduce "Core static thermal dissipation" from fpga design in Quartus
159005: 16/06/04: Re: Advice to a newbie
159902: 17/04/24: Re: glitching AND gate
<marko.udvanc@trilus-spe.si>:
22024: 00/04/13: Re: jtag/jtagprog and fpga-demo-board
markp:
28090: 00/12/20: Re: 3V -> 5V clock signal level conversion
28098: 00/12/21: Re: 3V -> 5V clock signal level conversion
28107: 00/12/21: Re: Help with encoder/decoder
28118: 00/12/21: Re: Help with encoder/decoder
28168: 00/12/23: Re: really fast counter in SpartanXL?
28199: 00/12/28: Re: really fast counter in SpartanXL?
47762: 02/10/03: Re: Need advice wiring up a CPLD
47773: 02/10/03: Re: Need advice wiring up a CPLD
75738: 04/11/13: Digital LP filter in multiplier free FPGA
75741: 04/11/13: Re: Digital LP filter in multiplier free FPGA
75771: 04/11/14: Re: Digital LP filter in multiplier free FPGA
75772: 04/11/14: Re: Digital LP filter in multiplier free FPGA
75773: 04/11/14: Re: Digital LP filter in multiplier free FPGA
75774: 04/11/14: Re: Digital LP filter in multiplier free FPGA
75857: 04/11/17: Re: Digital LP filter in multiplier free FPGA
98337: 06/03/08: Parallel readback on Spartan IIE
98347: 06/03/08: Re: Parallel readback on Spartan IIE
Markus:
67100: 04/03/05: Re: How do I fix this type of errors?
86232: 05/06/23: Xilinx Impact-Tool: Error when downloading partial bitstream
101489: 06/05/02: Re: XDL router info needed
110584: 06/10/18: Re: from LUT contents to boolean equation
113202: 06/12/08: Re: Xilinx PAR crashing with 'make'
116854: 07/03/20: ModelSim PE exit code 211
116915: 07/03/21: Re: ModelSim PE exit code 211
116938: 07/03/21: Re: Using xilkernel with C++
122415: 07/07/27: Re: Xilinx, converting ncd back to edif
123243: 07/08/21: Re: Amount of wire and logic
125327: 07/10/22: Re: Protecting slices from GLOBAL_LOGIC0/GLOBAL_LOGIC1 usage?
125348: 07/10/23: Re: Protecting slices from GLOBAL_LOGIC0/GLOBAL_LOGIC1 usage?
128361: 08/01/23: Re: Problem with UART EDK 9.2.02i
128766: 08/02/06: Re: Problems with GDB in EDK 9.2
129127: 08/02/15: Re: Microblaze 7.0 on V2pro?
131942: 08/05/08: Re: EDK for spartan2?
132503: 08/05/29: Re: Virtex 2 with PLB_v34 and EDK 10.1
135440: 08/10/02: Re: reasonable timing analysis without mapping design to IO
135735: 08/10/14: Microblaze and PowerPC405/440
136287: 08/11/10: Re: Tilera multicore replaces FPGA?
136790: 08/12/05: Re: Preventing PAR from routing signals in closed area groups
136829: 08/12/08: Re: Preventing PAR from routing signals in closed area groups
136859: 08/12/09: Re: Inverting bus connection order in Verilog
136907: 08/12/12: Re: How to insert ChipScope
137230: 09/01/05: Re: Classifying different kinds of FPGA optimizations
138380: 09/02/18: Re: ERROR: overlaps section...
138405: 09/02/20: Re: VHDL long elsif state machine
138555: 09/02/27: Re: mb-gcc producing incorrect code ???
141277: 09/06/15: Re: About Altera patent application "Logic Cell Supporting Addition
markus:
108861: 06/09/18: Xilinx XAPP775: 10GbE PCS
109070: 06/09/20: Re: i2c,ahb,apb
109262: 06/09/22: Re: i2c,ahb,apb
109362: 06/09/25: Re: i2c,ahb,apb
110559: 06/10/17: OpenCores.org's I2C: Clock Stretching Support
112079: 06/11/15: Problems with Opencores' I2C "READ" function
112125: 06/11/16: Re: Problems with Opencores' I2C "READ" function
112408: 06/11/21: I2C "READ" Setup/Hold Requirement
112468: 06/11/22: Re: I2C "READ" Setup/Hold Requirement
113070: 06/12/05: Re: Usage of BUFIO in Virtex 4?
113119: 06/12/06: Re: Usage of BUFIO in Virtex 4?
113124: 06/12/06: Re: Clock phase shift
Markus Blank:
81971: 05/04/05: Protection measurements
Markus Dobschall:
28353: 01/01/09: Error in Logic Simulator
31477: 01/05/27: dual channel NCO in Xilinx VirtexE
Markus Fras:
36551: 01/11/12: PLL in Altera's Apex20K
49274: 02/11/07: Programming Altera EPC16
114875: 07/01/25: Xilinx USB download cable
114877: 07/01/25: Re: Xilinx USB download cable
116410: 07/03/08: Xilinx CoreGen fifo - ngdbuild error
116446: 07/03/09: Re: Xilinx CoreGen fifo - ngdbuild error
121447: 07/07/04: Change PicoBlaze ROM Code on Spartan 3E Development Board
122391: 07/07/26: DCM with Xilinx Spartan 3E and Precision
122416: 07/07/27: Re: DCM with Xilinx Spartan 3E and Precision
139859: 09/04/17: EDIF generation with Synopsys Design Compiler version B-2008.09
Markus Freund:
152506: 11/08/29: Re: Very cheap Spartan3 board that can be configured by simple USB
152507: 11/08/29: Re: Very cheap Spartan3 board that can be configured by simple USB
153299: 12/01/29: Re: TCP/IP
Markus Fuchs:
74335: 04/10/08: Flex10K10A, I2C, MultiVolt IO, pull-ups
74487: 04/10/12: Re: Flex10K10A, I2C, MultiVolt IO, pull-ups
108562: 06/09/13: SoC Development Board
108907: 06/09/19: Re: SoC Development Board
108908: 06/09/19: Re: SoC Development Board
Markus Knauss:
83544: 05/05/02: JTAG communication Problems in Quartus using Signal Tap
83557: 05/05/03: Re: JTAG communication Problems in Quartus using Signal Tap
83582: 05/05/03: Re: JTAG communication Problems in Quartus using Signal Tap
83583: 05/05/03: Re: JTAG communication Problems in Quartus using Signal Tap
83691: 05/05/05: Re: JTAG communication Problems in Quartus using Signal Tap
87029: 05/07/13: Re: QII simulation annoyance
93267: 05/12/17: Altera based Video development board
93277: 05/12/18: Re: Altera based Video development board
117455: 07/03/31: Config PROM for Spartan II
117675: 07/04/06: Re: Config PROM for Spartan II
Markus Koechy:
70825: 04/06/29: File format *.eqn in Altera IDE
74285: 04/10/07: Re: spartan 3 starter kit
Markus Kuhn:
97105: 06/02/16: Implementing a two-modulus PLL divider in Altera Stratix II
97147: 06/02/17: Re: Communication between FPGA and PC with ethernet
97762: 06/02/27: Re: VGA specification
99632: 06/03/27: Re: Altera web site inaccessible
99780: 06/03/29: Re: Please recomend textbook with AES encryption.
99886: 06/03/30: Re: USB phy in dev board
101265: 06/04/28: Re: ISE 8.1i for Linux ?
101906: 06/05/08: Re: Quartus and source control
118411: 07/04/26: Altera Quartus II v7.0 under openSUSE 10.2
119658: 07/05/24: Quartus 7.1 segv on recent Linux distributions
119659: 07/05/24: Re: Altera Cyclone II - used in 100USD Laptop
119701: 07/05/24: Re: Quartus 7.1 segv on recent Linux distributions
129865: 08/03/07: Altera Quartus II v7.2 SP2 under openSUSE 10.3 (i686)
Markus Lavin:
148416: 10/07/21: Announcing AjarDSP - an open source VLIW DSP
148425: 10/07/21: Re: Announcing AjarDSP - an open source VLIW DSP
148503: 10/07/28: Re: Announcing AjarDSP - an open source VLIW DSP
Markus Leberecht:
8074: 97/11/14: Register Intensive Designs and Dynamically Reconfigurable FPGAs
8107: 97/11/18: Re: Register Intensive Designs and Dynamically Reconfigurable FPGAs
8109: 97/11/18: Re: Register Intensive Designs and Dynamically Reconfigurable FPGAs
Markus Meng:
30872: 01/05/02: [Q] PC104 Slave Board Minimum Signal Requirements ...
31096: 01/05/11: Re: [Q]CardBus PC Card with PCI device
31953: 01/06/09: [Xilinx] Spartan II Devices ..internal tristate busses ...
33635: 01/08/01: [ALTERA] EPC1 devices in DIP8 package for sell
33969: 01/08/09: Spartan-II serial configuration problem from ATMEL device
34283: 01/08/18: [Spartan-II] JTAG configuration problem ...
35600: 01/10/11: [Spartan-XL] Driving a BUFGS from a std. IO ...
37359: 01/12/08: [Spartan-II] Global Timing Constraints valid for Block RAM's ?
37367: 01/12/08: Re: [Spartan-II] Global Timing Constraints valid for Block RAM's ?
37384: 01/12/09: Re: [Spartan-II] Global Timing Constraints valid for Block RAM's ?
37453: 01/12/11: Re: [Spartan-II] Global Timing Constraints valid for Block RAM's ? Update ...
38073: 02/01/03: ACTEL SX-A serie and ROM implementation ...
38225: 02/01/09: Triscend ARM+FPGA chips Experience
38755: 02/01/24: UCF Parsing Error for Pin2Pin Constraints 3.1i
38795: 02/01/25: [Spartan-II] Fastest Possibel Output Enable Time for -5 Devices ??
38806: 02/01/25: Re: [Spartan-II] Fastest Possibel Output Enable Time for -5 Devices ??
39759: 02/02/19: I/O Type of the Xilinx CCLK pin ??
40729: 02/03/13: Spartan-XL, SpartanII and Spartan-IIE bitstream format question ...
40827: 02/03/16: Why do I want to do this ??
40829: 02/03/16: Re: Spartan-XL, SpartanII and Spartan-IIE bitstream format question ...
41937: 02/04/11: HDLC Controller Design
47307: 02/09/23: Fast serial interconnect bus using spartan-II
50180: 02/12/04: HowTo 'freeze' a placement
50346: 02/12/09: [Spartan-IIE] Additional DLL input pins
51194: 03/01/06: SPI programming through the pc parallel port
52087: 03/01/31: More than four clocks within a spartan-ii device?
52150: 03/02/03: Spartan-II OBUF Driver Impedance
52831: 03/02/24: Program a Serial Data Flash - SPI - Interface through a CPLD via JTAG
52842: 03/02/24: Re: Program a Serial Data Flash - SPI - Interface through a CPLD via JTAG
52896: 03/02/25: Unprogrammed XC9536XL is driving the databus high
52905: 03/02/25: Re: Unprogrammed XC9536XL is driving the databus high
52946: 03/02/26: Re: Unprogrammed XC9536XL is driving the databus high
52949: 03/02/26: Re: Unprogrammed XC9536XL ... the end ...
53057: 03/03/02: Re: Design Manager in ISE 5.x
53418: 03/03/13: [Xilinx] Looking for Parallel Cable III ...
53627: 03/03/18: Re: Cheapest Spartan II/IIE configuration flash EEPROM!
55538: 03/05/12: CRC Generator for 6Byte serial Transmission
55661: 03/05/15: [Q] HowTo Speed Constraint Multiple Clock Constraints for Spartan-II
55912: 03/05/23: Using Desigin Constraints in VHDL for Xilinx Spartan-II
55947: 03/05/24: Re: CLKDLL: Dividing
56229: 03/05/31: Re: FPGA's an Flash
56245: 03/06/01: Re: FPGA's an Flash
56348: 03/06/03: Re: FPGA's an Flash
56444: 03/06/05: Re: FPGA's an Flash
57200: 03/06/25: Max Allowable Clock Skew on local Clocks - Spartan-II -5
57209: 03/06/25: Re: Max Allowable Clock Skew on local Clocks - Spartan-II -5
57625: 03/07/03: [DLL Virtex/Spartan-II] Which is the right feedback in x1 and x2 Appl
57628: 03/07/03: [DLL usage Virtex/Spartan-II] HowTo drive CLKDV Div 2 off Chip
58027: 03/07/12: Re: CLKDLLE CLK2X180 Outpu doesn't work
61875: 03/10/14: DCM driving multiple OBUF's ... skew in between ...
63138: 03/11/16: Re: More basic questions about Spartan 2 IOB
64155: 03/12/18: www.micron.com VHDL models gone ??
64312: 03/12/27: [Spartan-IIE] Exeeding max. input rise/fall time of signals ??
67475: 04/03/12: Which Clock Source for TI's TLK1501, TLK2501 SERDES Chips
67522: 04/03/13: XAPP607: Is this just paperwork or based on a real design
67578: 04/03/15: Re: XAPP607: Is this just paperwork or based on a real design
67840: 04/03/20: Re: LVDS
72451: 04/08/19: [Synthesis][VHDL] HowTo prevent Removal of Registers ...
73784: 04/09/29: [NIOS-II SOPC] SDRAM Read Burst Cycle Length ...
73957: 04/10/01: Re: Altera SDRAM controller - Only 2 words burst???
72828: 04/09/03: [XC96xxXL] Maximum Value for the external Pull-Up resistor ...
73498: 04/09/22: [ALTERA] NIOS-II + MMU + FPU
75528: 04/11/08: Re: SpartanII + ARM7 Question
75529: 04/11/08: Re: SRAM to be able to read/write Micron SDRAM
75596: 04/11/10: Re: SpartanII + ARM7 Question
77166: 04/12/27: [Xilinx ISE6.3 SP3] WebUpdate dies at 84% ...
83161: 05/04/25: [Sparan-II] Internal Power-On Reset Block?
83176: 05/04/25: Re: [Sparan-II] Internal Power-On Reset Block?
83685: 05/05/05: Re: [Sparan-II] Internal Power-On Reset Block?
83881: 05/05/09: Re: 8051 IP core
88194: 05/08/11: [Q] Virtex-IV with RLDRAM-II any experience with it?
88429: 05/08/18: [Q] Synthesis : HowTo Preserve FSM encodings
95881: 06/01/26: Re: DDR2 SDRAM controller
95831: 06/01/26: Re: DDR2 SDRAM controller
97009: 06/02/14: Re: Altera RoHS Irony
106512: 06/08/14: [Xilinx] MIG V1.6 Reduced max Speed for DDR2 controllers ??
109615: 06/10/01: Re: ddr2 sodimm controller
109616: 06/10/01: Re: Anyone had success with MIG, DDR2 and V2Pro?
111515: 06/11/04: Re: JTAG connection for chipscope
111516: 06/11/04: Re: PCI
111518: 06/11/04: Re: chipscope
Markus Michel:
14545: 99/02/04: Re: Need Help! clock multiplier!
14556: 99/02/04: Re: VHDL problem (Xilinx-problem)
15436: 99/03/24: Synplify -> MaxPlus II
15957: 99/04/23: Re: on using EAB of FLEX10k
16228: 99/05/11: Re: Synchronizer design?
16818: 99/06/11: Re: Configuring AlteraFlex10k with maxII
16865: 99/06/15: Re: Configuring AlteraFlex10k with maxII
20859: 00/02/24: PCI 64 bit / 66 MHz
25064: 00/08/25: DLL Properties on Xilinx Virtex/VirtexE
26671: 00/10/24: IOBUF's replaced by IBUF's
27438: 00/11/22: Re: Resetting Flip-Flops in Virtex
30948: 01/05/04: Re: Use of record type in a hierarchical architecture
Markus Pfaff:
989: 95/04/08: Xilinx XC3000a/4000 as LCD-driver
Markus Rettinger:
3248: 96/05/03: SILAGE
Markus Rossmann:
10375: 98/05/15: Re: Neural Network implementation
Markus Sponsel:
30986: 01/05/08: Re: Licensing PB in Synplify_pro 6.2
46900: 02/09/11: Re: Saving results with modelsim
50125: 02/12/03: Re: register OR latch ?
58378: 03/07/22: Re: Is QuickSwitch devices a good method to interface fpga 3.3v(spartan IIE) and 5v logic divices?
Markus Svilans:
103707: 06/06/08: Re: Good free or paid merge software that edits two similar files?
Markus Walter:
51134: 03/01/03: Alternative to theXilinx XC4005E
Markus Wannemacher:
1555: 95/07/14: Q: New XILINX XC6200-FPGA
1594: 95/07/24: Re: PREP data
1635: 95/08/09: Re: Looking for info on ACM FPGA'96 workshop
1727: 95/08/21: Re: List of FPGA Based Computing Machines
2126: 95/10/18: Re: Library of Parametrized Modules info
3176: 96/04/18: Re: Crosspoint Solutions
4584: 96/11/18: GEC Plessey, Toshiba, PlusLogic FPGAs?
6069: 97/04/09: comp.arch.fpga archiv dead?
6077: 97/04/10: Crosspoint Solutions FPGA???
9850: 98/04/09: German only: Neues FPGA-Kochbuch
10445: 98/05/19: German only: Neues FPGA-Kochbuch
10468: 98/05/20: Re: Archives for comp.arch.fpga?
12120: 98/09/30: Re: Free FPGA/HDL Newsletter Announcement
12486: 98/10/13: Re: books
12607: 98/10/20: Re: Where to find comp.arch.fpga newsgroup archive
14754: 99/02/15: Re: comp.arch.fpga Archives
15703: 99/04/09: Re: FPGA testing board
16922: 99/06/17: Re: FPGA board for ISA bus wanted
18771: 99/11/13: Re: looking for Xilinx/Actel Board
22036: 00/04/14: Re: Demo - board
38794: 02/01/25: XC2V10000 still on the Xilinx roadmap?
Markus Wolfgart:
44580: 02/06/24: Old Synario SW, how to adapt for MACH211 and MACH4-64/32 programming?
49030: 02/10/30: Data sheet for an Altera EPS464LC wanted!
49062: 02/10/31: Which PCI-IO-Chip manufacturer to prefer?
49365: 02/11/11: Re: Which PCI-IO-Chip manufacturer to prefer?
49780: 02/11/21: XCS-05-3PC84 and XCS10-3PC84 Question
49845: 02/11/22: Re: XCS-05-3PC84 and XCS10-3PC84 Question
49907: 02/11/25: Re: XCS-05-3PC84 and XCS10-3PC84 Question
Markus Zingg:
62413: 03/10/29: How to protect fpga based design against cloning?
62418: 03/10/29: Re: How to protect fpga based design against cloning?
62462: 03/10/30: Re: How to protect fpga based design against cloning?
63974: 03/12/10: Re: Soldering of FPGAs
64094: 03/12/16: Re: Soldering of FPGAs
98590: 06/03/13: Re: Soldering SMT/BGA
106018: 06/08/05: verilog versus vhdl
109424: 06/09/26: Newbee question - how to upgrade to Xilinx ISE/EDK 8.2 from 8.1
109430: 06/09/26: Re: Newbee question - how to upgrade to Xilinx ISE/EDK 8.2 from 8.1
109685: 06/10/03: JTAG cable @ 2.5 V - where?
109710: 06/10/04: Re: Xilinx PowerPC & MicroBlaze Development Kit
116460: 07/03/09: Virtex 4 FX12 - where are the EMACs and PPC core located?
116529: 07/03/12: Re: Virtex 4 FX12 - where are the EMACs and PPC core located?
116546: 07/03/12: Re: Virtex 4 FX12 - where are the EMACs and PPC core located?
142977: 09/09/11: How to get two PLB slave burst interfaces into custom core with Xilinx EDK?
143288: 09/09/30: PLB bursts and adress alignement
<markus.jank@de.bosch.com>:
123500: 07/08/29: Strange behaviour of a design
123553: 07/08/29: Re: Strange behaviour of a design
<markus.jank@gmx.de>:
123598: 07/08/30: Re: Strange behaviour of a design
123802: 07/09/04: Re: Strange behaviour of a design
<markx.gregory@intel.com>:
15779: 99/04/14: Intel Opportunity
marlboro:
54069: 03/04/01: Re: parity checking trick for PCI core
57196: 03/06/25: Re: Interfacing IDE
58272: 03/07/18: Re: How fast coregen FIR?
58280: 03/07/18: 4.2i sp3 map error xc2v3000-ff1152
59078: 03/08/07: Re: Need help: getting 3.1i Coregen working on P4-system
60121: 03/09/05: Re: Schematic simulation and then FPGA programming?
61434: 03/10/03: Re: Graphics rendering revisited
61435: 03/10/03: Re: Graphics rendering revisited
Marlboro:
48013: 02/10/09: Re: Why can Xilinx sw be as good as Altera's sw?
50843: 02/12/20: Vitex DLL and external PLL
51279: 03/01/09: Re: External RAM...
51461: 03/01/14: Re: Help for Generating Video Clock synchronous to Hsync of the Video..........
51519: 03/01/15: Re: SChematic design approach compared to VHDL entry approach
53029: 03/02/28: SCSI SPI-4 interface
57443: 03/06/30: 48bit adder won't fit
57446: 03/06/30: Re: 48bit adder won't fit
58340: 03/07/21: virtex2 map error?
59539: 03/08/21: Re: DCM vs state machine
59552: 03/08/21: Re: DCM vs state machine
59581: 03/08/22: LVPECL I/O and Fndtn4.2
64483: 04/01/05: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
66312: 04/02/16: Re: FIR filter coefficient (with COE file)
70654: 04/06/22: Re: Is the Xilinix XC3020 atill supported?
72388: 04/08/17: Re: let me have logic design for traffic light
72754: 04/08/31: Re: The Effect of Pin Assginment
74314: 04/10/07: Xilinx lead free parts hidden fact
74648: 04/10/15: Re: direct calculation of the modulus ?
76047: 04/11/23: Re: Help! What is this card?
96798: 06/02/10: Re: Spartan3 embedded synchronous multipliers
101936: 06/05/08: Re: flashing a led
103091: 06/05/25: Re: Virtex 5 announced
106295: 06/08/10: Re: Who is your favourite FPGA guru?
107122: 06/08/24: Re: Xilinx BRAMs question - help needed ..
107885: 06/09/01: Re: Interface of 8051 microcontroller with FPGA Block RAM
108581: 06/09/13: Re: X4000 bad configuration
108591: 06/09/13: Re: X4000 bad configuration
108968: 06/09/19: Re: VHDL oddity
108971: 06/09/19: Re: Buffering the critical path.
109087: 06/09/20: Re: MicroFpga = program an FPGA as it would be a MCU !
109813: 06/10/05: Re: nicer code => slower code??
110079: 06/10/10: Re: FPGA to SRAM port interface
110121: 06/10/11: Re: FPGA to SRAM port interface
110219: 06/10/12: Re: VGA timing
110930: 06/10/25: Am I seeing meta-stable or what?
112853: 06/11/29: Re: DVI clock generation
113897: 06/12/28: Re: better ways for debugging?
113898: 06/12/28: Re: remove logic redundancy
113929: 06/12/29: Re: remove logic redundancy
114967: 07/01/28: Re: how do you code this?
114969: 07/01/28: Re: how do you code this?
114972: 07/01/28: Re: video buffering scheme, nonsequential access (no spatial locality)
115375: 07/02/08: Re: question abt DPRAM
115495: 07/02/12: Re: substracting a whole array of values at once
115496: 07/02/12: Re: substracting a whole array of values at once
115501: 07/02/12: Re: ModelSim - Do Files
116042: 07/02/28: Xilinx USB flatform cable length mistery ?
116048: 07/02/28: Re: Xilinx USB flatform cable length mistery ?
116348: 07/03/07: DFF with clock and async-preset tied together
119754: 07/05/25: IOSTANDARD user constrain
119771: 07/05/25: Re: IOSTANDARD user constrain
120156: 07/06/01: Weekend pop quiz
120167: 07/06/02: Re: Weekend pop quiz
120194: 07/06/02: Re: Weekend pop quiz
120204: 07/06/03: Re: FIFO : Synchronous WRITE, Asynchronous READ ?
120466: 07/06/07: What's wrong with CoreGen 7.0: dynamic coef multiplier (port B = constant /w reloadable)
120470: 07/06/07: Re: What's wrong with CoreGen 7.0: dynamic coef multiplier (port B = constant /w reloadable)
120474: 07/06/07: Re: What's wrong with CoreGen 7.0: dynamic coef multiplier (port B = constant /w reloadable)
120563: 07/06/10: Re: adaptive filter FPGA
120647: 07/06/12: Re: adaptive filter FPGA
120690: 07/06/13: Re: adaptive filter FPGA
120719: 07/06/14: Re: adaptive filter FPGA
120760: 07/06/15: Re: Stolen Spartan 3E-1600 Development Board
124469: 07/09/23: Re: Gated Clock Problems
125034: 07/10/15: Re: FIFO depth
125147: 07/10/16: Re: Unrouted nets (Xilinx FPGA Editor)
125972: 07/11/10: Re: FIFO interface design
126791: 07/12/02: Re: Traffic Light with counter
128596: 08/01/31: Design security for pre-Virtex2 parts ?
128656: 08/02/01: Re: Design security for pre-Virtex2 parts ?
131121: 08/04/11: Re: Xilinx tech Xclusive
134666: 08/08/25: Re: Analog Imager interface to FPGA
134668: 08/08/25: Re: Analog Imager interface to FPGA
134692: 08/08/26: Re: Analog Imager interface to FPGA
135190: 08/09/19: Is it hard to detect an ucf sytax error?
136898: 08/12/11: How to insert ChipScope
138110: 09/02/06: ISE10.1 not support guide mode Map & PAR ?
138273: 09/02/11: Re: ISE10.1 not support guide mode Map & PAR ?
Marloboro:
58242: 03/07/17: How fast coregen FIR?
Maroc:
103923: 06/06/15: XPLA3 bidirectional bus
125167: 07/10/17: High level FPGA work flow: available tool?
125175: 07/10/17: Re: High level FPGA work flow: available tool?
maroni:
118231: 07/04/20: Clock signal FPGA XC95288xl144
Maroof H. Choudhury:
5567: 97/02/25: Re: Q: Search Engines for Electronic Parts?
<marouen.arfaoui.42@gmail.com>:
156353: 14/03/16: how add an IP on vivado for Nexys4
Marra:
120565: 07/06/10: Re: Mobile DDR vs DDR2
marsala.miz@gmail.com:
137214: 09/01/03: DE2 Board DDR Controller Problem
marta:
103145: 06/05/26: ADV7321 interlaced mode
103234: 06/05/29: Re: ADV7321 interlaced mode
Marten:
59795: 03/08/28: Re: Selecting between two clock signals
Marten van Essen:
46926: 02/09/12: Re: Saving results with modelsim
Marteno Rodia:
140385: 09/05/12: [newbie asking] I don't like Xilinx
140411: 09/05/13: Re: I don't like Xilinx
140420: 09/05/13: Re: I don't like Xilinx
140506: 09/05/15: Re: I don't like Xilinx
140903: 09/05/28: I don't like xilinx (again)
140999: 09/06/01: Re: I don't like xilinx (again)
141113: 09/06/06: Re: Xilinx ISE doesn't recognize a signal added in Xilinx Platform
<marthajonese@gmail.com>:
157206: 14/11/04: practical experience with GPL IP core in commercial product
157208: 14/11/04: Re: practical experience with GPL IP core in commercial product
157210: 14/11/04: Re: practical experience with GPL IP core in commercial product
Martijn:
106680: 06/08/17: Using XMD for memory dumps (speed)
106738: 06/08/18: Re: Using XMD for memory dumps (speed)
107187: 06/08/25: Xilinx IPIF DMA done interrupt ?
107407: 06/08/28: Re: Xilinx IPIF DMA done interrupt ?
Martin:
23962: 00/07/18: Re: Altera fitter woes
30564: 01/04/17: Re: XCV1000BG560: onchip ram
31403: 01/05/22: Counter problem
31414: 01/05/22: Re: Counter problem
31428: 01/05/23: Re: Counter problem
31647: 01/06/01: Re: Help requested in choosing a career
37111: 01/11/30: Ballynuey 2 Hostsoftware
41796: 02/04/08: Re: A learner of Modelsim
42929: 02/05/07: Re: Virtex 2: Partial Bitstream Generation
43275: 02/05/17: Re: Virtex2 placement problem
43610: 02/05/27: Re: FPGA, VHDL : RAM initialization
44823: 02/07/02: Re: Power consumtion simulation for FPGA?
45514: 02/07/25: Re: XST vs FPGA Express???
46864: 02/09/10: Re: Xilinx Parallell Cable IV and Wine
52829: 03/02/24: Looking for Virtex2Pro and Linux (PPC)
64036: 03/12/12: advantages of ethernet MAC ip core
67396: 04/03/11: Clock and data synchronization
69147: 04/04/28: Clock frequency converter from 1.544MHz to 2.048MHz (or multiples)
77172: 04/12/28: PicoBlaze implementation
77777: 05/01/17: USB Host
77811: 05/01/17: Re: USB Host
77815: 05/01/18: Re: USB Host
78158: 05/01/25: Linux on V2P
78193: 05/01/26: Re: Linux on V2P
78358: 05/01/31: OT: Design security
78409: 05/01/31: Re: Design security
78489: 05/02/02: Re: Design security
81460: 05/03/24: OT: EDA tools
81511: 05/03/26: Re: OT: EDA tools
81512: 05/03/26: Re: OT: EDA tools
87338: 05/07/21: Xilinx software update?
87350: 05/07/22: Re: Xilinx software update?
87463: 05/07/24: Re: Xilinx software update?
88960: 05/09/01: "Perform Timing-Driven Packing and Placement" error?
88994: 05/09/02: Re: "Perform Timing-Driven Packing and Placement" error?
88996: 05/09/02: Re: "Perform Timing-Driven Packing and Placement" error?
91776: 05/11/13: Bitstream compression
91798: 05/11/13: Re: Bitstream compression
91843: 05/11/15: Re: Bitstream compression
91844: 05/11/15: RoHS
91881: 05/11/15: Re: RoHS
91892: 05/11/16: Re: RoHS
91909: 05/11/16: Re: RoHS
93923: 06/01/03: Re: FPGA DVI output with CH7301
94505: 06/01/12: OT: RoHS and Lead?
94533: 06/01/13: Re: OT: RoHS and Lead?
97985: 06/03/02: DMA and PCI in SoPC Builder
98030: 06/03/03: Re: DMA and PCI in SoPC Builder
98168: 06/03/06: Re: DMA and PCI in SoPC Builder
98377: 06/03/09: Re: DMA and PCI in SoPC Builder
113438: 06/12/13: GUI Based vs. Manual Instantiation of Components
137337: 09/01/09: Software Debugging on Power PC
137338: 09/01/09: Re: Software Debugging on Power PC
138331: 09/02/16: PowerPC 405 Problem on Xilinx Virtex II FPGA
149446: 10/10/26: Ncvhdl Problem with simple logical operators
149450: 10/10/26: Re: Ncvhdl Problem with simple logical operators
martin:
49602: 02/11/17: mcu and fpga interface question
Martin Bosma:
97583: 06/02/24: USB 2.0 OTG in FPGA
97591: 06/02/24: Re: USB 2.0 OTG in FPGA
Martin =?ISO-8859-1?Q?Br=FCckner?=:
147470: 10/04/28: Re: Booting Linux from my own bootloader
147528: 10/04/30: Re: Booting Linux from my own bootloader
Martin =?UTF-8?B?QnLDvGNrbmVy?=:
147413: 10/04/26: Booting Linux from my own bootloader
147424: 10/04/27: Re: Booting Linux from my own bootloader
147456: 10/04/28: Re: Booting Linux from my own bootloader
147457: 10/04/28: Re: Booting Linux from my own bootloader
Martin Anding:
6104: 97/04/12: Re: Cadence dfII Layout Plotter: which type are the best solution ?
Martin Brown:
50010: 02/11/28: Re: hardware image processing - log computation
85866: 05/06/17: Re: Idea exploration - Image stabilization by means of software.
150565: 11/01/26: Re: Xilinx news
martin capitanio:
31102: 01/05/11: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
31119: 01/05/12: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
Martin Charlwood:
127058: 07/12/10: GAL16V8
Martin Curran-Gray:
201: 94/09/20: Re: PLD for async state machine?
215: 94/09/26: Xilinx 4000
1681: 95/08/15: Re: Timespecs in XNF format
Martin Czamai:
41941: 02/04/11: Insight service and PCI demo board question
41984: 02/04/12: Re: Insight service and PCI demo board question
Martin d'Anjou:
4336: 96/10/17: Re: xc4000 and 2 clocks
4346: 96/10/18: Re: xc4000 and 2 clocks
4671: 96/11/27: Re: How to use Xilinx ?
4746: 96/12/10: Re: ASICs Vs. FPGA in Safety Critical Apps.
6042: 97/04/07: Chip Temperature (was:Re: Sole source)
6050: 97/04/08: Re: Chip Temperature (was:Re: Sole source)
Martin dAnjou:
5370: 97/02/11: Re: Random Number Generators with Xilinx FPGA xc4000 series
Martin DAnjou:
3854: 96/08/09: Re: ANNOUNCE : HDL Editor
Martin Darwin:
28635: 01/01/18: Re: revision control tools ??
38266: 02/01/10: Re: asic vs. fpga
38310: 02/01/11: Re: asic vs. fpga
131865: 08/05/05: Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
Martin Duffy:
13322: 98/11/25: DynaChip
13939: 99/01/04: Re: PLL in FPGAs?
15118: 99/03/08: Re: Current State of FPGA-based PCI Interfaces?
15501: 99/03/26: Re: IBM 600MHz FPGA
16015: 99/04/28: Re: High speed PLL inside FPGA
16040: 99/04/29: martin_duffy@compuserve.com
16041: 99/04/29: Re: martin_duffy@compuserve.com
16933: 99/06/17: Actel's proASIC
Martin E.:
42177: 02/04/17: Re: just bought Cohen's book...Real Chip Design and Verification using Verilog and VHDL
42840: 02/05/04: SelectRAM and DCM
42869: 02/05/05: Re: SelectRAM and DCM
42870: 02/05/05: Re: SelectRAM and DCM
42921: 02/05/07: Re: Frequency synthesiser
46340: 02/08/26: VirtexII: HSWAP_EN
46347: 02/08/26: Re: VirtexII: HSWAP_EN
46348: 02/08/27: Re: VirtexII: HSWAP_EN
46351: 02/08/27: Re: VirtexII: HSWAP_EN
46373: 02/08/27: Re: VirtexII: HSWAP_EN
47470: 02/09/26: Choosing Virtex II Speed grade
47484: 02/09/26: Re: Choosing Virtex II Speed grade
107239: 06/08/25: FPGA -> SATA?
107258: 06/08/25: Re: FPGA -> SATA?
108235: 06/09/07: Re: TI TFP410 DVI transmitter help?
Martin Eisenberg:
87899: 05/08/03: Re: System Engineering in the R/D World
Martin Ellis:
80902: 05/03/14: Re: editing waveforms under Linux
82753: 05/04/17: Re: Xilinx tools on Linux
82892: 05/04/19: Re: Xilinx tools on Linux
88925: 05/08/31: Re: Fine grain vs. Coarse Grain Architectures
91314: 05/11/03: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91319: 05/11/03: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91339: 05/11/03: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91344: 05/11/03: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
96625: 06/02/07: Re: FPGA ogg Vorbis/Theora player
96908: 06/02/13: Re: Async Processors
Martin Ericson:
62050: 03/10/17: How to get Synplify 7,0 Pro and Xilinx EDK 3,2 work together.
Martin Euredjian:
35328: 01/09/29: Re: comparison of performance and advantages for fpga's versus microcontroller+dsp
35415: 01/10/03: [OT] Prototyping with BGA's
47761: 02/10/03: Re: USB2 in FPGA?
47934: 02/10/08: Re: USB2 in FPGA?
47957: 02/10/08: Re: USB2 in FPGA?
50427: 02/12/10: VirtexII pin assignments/signal flow
50509: 02/12/11: Re: VirtexII pin assignments/signal flow
50559: 02/12/12: Re: VirtexII pin assignments/signal flow
53804: 03/03/24: Re: synthesizability question
53812: 03/03/24: Re: synthesizability question
54024: 03/03/31: uP interface question
54081: 03/04/02: Re: uP interface question
54082: 03/04/02: Excel and FPGA's
54102: 03/04/02: Re: uP interface question
54104: 03/04/02: Re: Excel and FPGA's
54125: 03/04/03: Re: Excel and FPGA's
54126: 03/04/03: Re: Excel and FPGA's
54137: 03/04/03: Re: uP interface question
55925: 03/05/23: DCM Trouble
55935: 03/05/23: Re: DCM Trouble
55943: 03/05/24: Re: FPGA design: firmware or hardware?
56288: 03/06/02: Re: Virtex 2 evaluation board
56361: 03/06/04: Re: Online courses for FPGA
56566: 03/06/09: Shift registers
56589: 03/06/10: Re: Shift registers
56624: 03/06/10: Re: DVI with a Virtex-II
56626: 03/06/10: Re: Shift registers
56653: 03/06/11: Re: Shift registers
56683: 03/06/11: Re: DVI with a Virtex-II - summary
56692: 03/06/11: Re: DVI with a Virtex-II - summary
56693: 03/06/11: Re: DVI with a Virtex-II
56725: 03/06/12: Re: DVI with a Virtex-II
56858: 03/06/17: Logic removal
57067: 03/06/23: Re: vga controller
57077: 03/06/23: Re: vga controller
57099: 03/06/23: Re: vga controller
57101: 03/06/23: Re: vga controller
57215: 03/06/25: Re: Xilinx Webpack bugs bugs bugs
57293: 03/06/27: Re: why so many problems Xilinx ?
57339: 03/06/27: STARTUP_WAIT
57438: 03/06/30: Re: Asynchronous RESET?
57801: 03/07/07: Pulse stretching
57816: 03/07/07: Re: Pulse stretching
57888: 03/07/09: Re: Pulse stretching
57938: 03/07/10: Re: okay what am I missing??? Please
58031: 03/07/12: Parallel processing (synthesis and simulation)
58290: 03/07/19: Re: Initialize Block RAM
58322: 03/07/21: Re: Instantiating pins on Virtex-II Pro
58373: 03/07/22: Re: asynchronous FIFO
58404: 03/07/22: Re: FPGA Editor
58405: 03/07/22: Re: Instantiating pins on Virtex-II Pro
58406: 03/07/22: Re: FPGA Editor
58423: 03/07/23: Floorplanner "features"
58424: 03/07/23: Re: FPGA Editor
58426: 03/07/23: Re: Floorplanner "features"
58444: 03/07/23: Re: FPGA Editor
58461: 03/07/24: Re: FPGA Editor
58462: 03/07/24: Re: FPGA Editor
58463: 03/07/24: Re: Active Probe
58465: 03/07/24: Multi Pass Place & Route
58485: 03/07/24: Re: FPGA Editor
58491: 03/07/24: Re: FPGA Editor
58493: 03/07/24: Re: FPGA Editor
58517: 03/07/25: Re: FPGA Editor
58518: 03/07/25: Re: Reseting the whole thing
58520: 03/07/25: Re: Pricing question....
58521: 03/07/25: Re: Reseting the whole thing
58523: 03/07/25: Re: Multi Pass Place & Route
58555: 03/07/26: Re: Multi Pass Place & Route
58570: 03/07/27: Re: FPGA Editor
58578: 03/07/27: Re: FPGA Editor
59036: 03/08/06: Re: Patent granted for "system on a chip" framework?
59049: 03/08/07: OT: Offshore engineering
59065: 03/08/07: Re: Patent granted for "system on a chip" framework?
59067: 03/08/07: Re: Offshore engineering
59143: 03/08/10: Re: Xilinx virtex II DCM CLKFX output not working
59153: 03/08/10: Re: Offshore engineering
59173: 03/08/11: Re: FPGA for a Newcomer
59175: 03/08/11: Re: a quick searching problem
59200: 03/08/12: Re: Win2k service packs for running Xilinx tools
59271: 03/08/13: Re: Xilinx DLL driving multiple off chip clocks
59377: 03/08/18: Re: custom memory array implementaion
59415: 03/08/19: Re: "sniffing" signals
59472: 03/08/20: Re: Synchronous FSM
59498: 03/08/20: Re: performance tweaking FPGA designs
59615: 03/08/25: TIG Constraint
59626: 03/08/25: Re: TIG Constraint
59653: 03/08/25: Re: TIG Constraint
59666: 03/08/25: Re: TIG Constraint
59759: 03/08/27: Re: WebPack ISE and Norton Anti-virus
59823: 03/08/29: Re: Max finding
59877: 03/08/30: Re: Shift register
60033: 03/09/04: Re: ISE 5.2 constraint file problem
60212: 03/09/08: Impact error
60228: 03/09/08: Re: Impact error
60246: 03/09/09: Re: Impact error
60938: 03/09/25: Graphics rendering
60985: 03/09/26: Re: Graphics rendering
61016: 03/09/26: Re: Graphics rendering
61019: 03/09/26: Re: Graphics rendering
61041: 03/09/26: Re: Graphics rendering
61042: 03/09/26: Re: Graphics rendering
61049: 03/09/26: Re: Graphics rendering
61065: 03/09/27: Re: Graphics rendering
61066: 03/09/27: Re: Graphics rendering
61071: 03/09/27: Re: Graphics rendering
61072: 03/09/27: Re: Graphics rendering
61083: 03/09/27: Re: Graphics rendering
61107: 03/09/28: ISE: Parallel Processing
61334: 03/10/02: Re: Digesting runs of ones or zeros "well"
61374: 03/10/02: Re: Graphics rendering -- use a BRAM line buffer
61395: 03/10/03: Re: Apology to Martin Erudjian
61396: 03/10/03: Re: Graphics rendering revisited
61401: 03/10/03: Re: Safe state machine design problem
61406: 03/10/03: Re: Safe state machine design problem
61407: 03/10/03: Xilinx courses
61449: 03/10/04: Re: Xilinx courses
61455: 03/10/04: Re: Graphics rendering revisited
61457: 03/10/04: Re: Graphics rendering revisited
61460: 03/10/04: Re: Xilinx courses
61461: 03/10/04: Re: Xilinx courses
61462: 03/10/04: Re: Interesting article about FPGAs
61465: 03/10/04: Re: newbie to FPGA
61470: 03/10/05: Re: Interesting article about FPGAs
61472: 03/10/05: Re: Interesting article about FPGAs
61480: 03/10/05: Re: Interesting article about FPGAs
61487: 03/10/05: Re: Interesting article about FPGAs
61489: 03/10/06: Re: Interesting article about FPGAs
61548: 03/10/06: Re: Xilinx courses
61555: 03/10/06: Re: Xilinx courses
61560: 03/10/07: Re: Xilinx courses
61562: 03/10/07: RLOC specification
61570: 03/10/07: Re: RLOC specification
61573: 03/10/07: More RPM / RLOC fun
61577: 03/10/07: Re: Xilinx courses
61611: 03/10/07: Re: More RPM / RLOC fun
61613: 03/10/07: Re: More RPM / RLOC fun
61617: 03/10/07: Re: More RPM / RLOC fun
61619: 03/10/07: Re: Avnet Xilinx Virtex II Development Board - getting started
61631: 03/10/08: Re: Avnet Xilinx Virtex II Development Board - getting started
61634: 03/10/08: Re: Visualizing VHDL
61646: 03/10/08: Re: More RPM / RLOC fun
61675: 03/10/08: Re: Visualizing VHDL
61687: 03/10/09: Re: Visualizing VHDL
61689: 03/10/09: Floorplanning, Routing, FPGA Editor
61690: 03/10/09: Re: Floorplanning, Routing, FPGA Editor
61704: 03/10/09: Where is the logic?
61730: 03/10/09: Re: Floorplanning, Routing, FPGA Editor
61731: 03/10/09: Re: Where is the logic?
61732: 03/10/09: Re: Where is the logic?
61744: 03/10/09: Re: Where is the logic?
61746: 03/10/09: Re: Where is the logic?
61749: 03/10/10: Re: Where is the logic?
61764: 03/10/10: Re: Floorplanning, Routing, FPGA Editor
61789: 03/10/10: Re: Graphics rendering revisited
61798: 03/10/11: Re: FPGA Editor: Macro(Xilinx)
61812: 03/10/13: ISE6.1i Floorplanner
61813: 03/10/13: ISE6.1i RPM's, Multipliers and grids
61840: 03/10/14: Re: ISE6.1i RPM's, Multipliers and grids
61880: 03/10/14: Re: ISE6.1i RPM's, Multipliers and grids
62008: 03/10/16: Re: explain the vhdl code
62076: 03/10/17: Re: LUT and latch in the FPGA
62187: 03/10/21: Job postings
62188: 03/10/21: Re: please help, modelsim does not simulate
62236: 03/10/22: Re: Beginners advice for selecting an environment for FPGA design
62386: 03/10/28: Re: How can I lock design with ISE 5.2?
62440: 03/10/29: Re: How to protect fpga based design against cloning?
62441: 03/10/29: Re: Virtex-II DCM frequency synthesizer
62452: 03/10/30: Re: Questions that question????
62456: 03/10/30: Re: Xilinx Spartan3: Price
62457: 03/10/30: Re: Some FPGA questions
62565: 03/11/01: Re: Some FPGA questions
62589: 03/11/02: Re: Power-On-Reset from a xilinx
62594: 03/11/03: Re: Vendor supplied symbol/part models?
62684: 03/11/04: Re: DCM recover after interruption of input clock
62722: 03/11/05: Re: Virtex II DCM & ZBT SRAM
62770: 03/11/07: Re: Virtex II DCM & ZBT SRAM
62846: 03/11/10: Re: FPGAs and DRAM bandwidth
63028: 03/11/13: Re: Layout examples
63029: 03/11/13: Re: Transforming vector position to binary value
63036: 03/11/13: Re: Layout examples
63037: 03/11/13: Re: Transforming vector position to binary value
63061: 03/11/13: Re: Transforming vector position to binary value
63066: 03/11/13: Re: Transforming vector position to binary value
63092: 03/11/14: Re: Layout examples
63267: 03/11/19: Re: Transforming vector position to binary value
63346: 03/11/20: Re: Transforming vector position to binary value
63347: 03/11/20: Re: SDRAM-Controller XAPP134
63348: 03/11/20: Re: Xilinx UCF file conditional includes ?
63561: 03/11/25: Re: area constraints
63599: 03/11/26: Re: area constraints
63658: 03/11/27: Re: area constraints
63659: 03/11/27: Re: [VirtexII + DCM + newbie] problems with the clocksignals from DCM
63663: 03/11/27: Re: [VirtexII + DCM + newbie] problems with the clocksignals from DCM
63681: 03/11/28: Re: [VirtexII + DCM + newbie] problems with the clocksignals from DCM
63687: 03/11/29: Re: [VirtexII + DCM + newbie] problems with the clocksignals from DCM
63750: 03/12/03: Re: Exact Timing Constraints vs. Over-Constraining
63854: 03/12/05: Block RAM simulation VII
63866: 03/12/06: Re: Block RAM simulation VII
63867: 03/12/06: Re: Floorplanning techniques
63874: 03/12/06: Re: Block RAM simulation VII
63876: 03/12/07: Re: Block RAM simulation VII
63887: 03/12/07: Re: Block RAM simulation VII
63890: 03/12/08: Re: Block RAM simulation VII
64030: 03/12/12: Re: Latches inferred ?
64042: 03/12/13: Re: Question about filters and verilog etc..
64218: 03/12/21: Re: WHAT APPLICATION WE CAN IMPLEMENT ON VERTEX II PRO
64231: 03/12/21: Re: WHAT APPLICATION WE CAN IMPLEMENT ON VERTEX II PRO
64240: 03/12/22: Re: FIR Filter cores for Virtex-][
64241: 03/12/22: Hyperthreading vs. Dual proc
64267: 03/12/23: Re: Hyperthreading vs. Dual proc
64268: 03/12/23: Re: Net name convention for Xilinx UCF files.
64276: 03/12/23: Re: Problems with Xilinx ISE6.1i P&Rs for Virtex II
64296: 03/12/25: Re: How to get first bit '0' position in certain register?
64599: 04/01/08: Large/Fast static RAM
64604: 04/01/08: Re: Large/Fast static RAM
64638: 04/01/09: Re: Large/Fast static RAM
64650: 04/01/10: Re: Large/Fast static RAM
64687: 04/01/11: Re: PCB for FG456: layers
64746: 04/01/13: Re: Power plane assignments in a Xilinx PCI card
64824: 04/01/14: Faster than a speeding bullet...
64826: 04/01/14: XC2V1000-5FG456C
64827: 04/01/14: Re: XC2V1000-5FG456C
64835: 04/01/15: Re: Faster than a speeding bullet...
64883: 04/01/15: Re: yo, Mr. FPGA Engineer
64886: 04/01/15: Re: Faster than a speeding bullet...
65004: 04/01/18: Anisotropic filter
65112: 04/01/20: Re: SDRAM Controller timing problem
65206: 04/01/22: Re: OT: liability insurance
65427: 04/01/29: Re: Flip-Chip Package Substrate Solder Issue
65990: 04/02/11: Re: Do Xilinx Fix Their Prices?
66212: 04/02/14: Re: Pricing, 101
66236: 04/02/15: Re: DCM Jitter?
66268: 04/02/16: Polyphase filter
66290: 04/02/16: Re: Manual Partitioning to Multiple FPGAs
66304: 04/02/17: Re: DCM Jitter?
66431: 04/02/19: Re: Can FPGA bootstrap itself?
66436: 04/02/19: Re: Dual-stack (Forth) processors
66454: 04/02/20: Re: Dual-stack (Forth) processors
66456: 04/02/20: Re: Dual-stack (Forth) processors
66463: 04/02/20: Re: Dual-stack (Forth) processors
66464: 04/02/20: Re: Dual-stack (Forth) processors
66479: 04/02/20: Re: Dual-stack (Forth) processors
66523: 04/02/21: Re: Dual-stack (Forth) processors
66539: 04/02/21: Re: Dual-stack (Forth) processors
66545: 04/02/22: Re: Dual-stack (Forth) processors
66546: 04/02/22: Re: Can FPGA bootstrap itself?
66564: 04/02/23: Re: Dual-stack (Forth) processors
66676: 04/02/25: Re: Dual-stack (Forth) processors
66677: 04/02/25: Re: Why warnings: "Input <xyz> never used???"
66710: 04/02/25: Re: Dual-stack (Forth) processors
66831: 04/02/27: Re: Dual-stack (Forth) processors
66901: 04/02/29: Re: Xilinx iMPACT error: "Done did not go high"
66902: 04/02/29: Re: Polyphase filter
67163: 04/03/07: Re: Polyphase filter
67990: 04/03/24: Re: How many times can I burn an FPGA?
68041: 04/03/25: Re: How many times can I burn an FPGA?
72041: 04/08/06: Acceleration
72062: 04/08/06: Re: Acceleration
72121: 04/08/09: Carbon nanotubes
72151: 04/08/10: Re: Carbon nanotubes
72711: 04/08/30: Re: The Effect of Pin Assginment
72804: 04/09/02: Re: The Effect of Pin Assginment
Martin Filteau:
16536: 99/05/26: Re: floating points to fixed points on a FPGA
24560: 00/08/14: Re: CLKDLL for Virtex PCI?
27507: 00/11/25: Re: Virtex-PCI-Boards
Martin Fischer:
35383: 01/10/02: Which Cable for the Xilinx 3064XL ?
35420: 01/10/04: Re: Which Cable for the Xilinx 3064XL ?
35629: 01/10/12: PWM Signal in VHDL ?
37703: 01/12/19: How can I check my PLD program ?
37712: 01/12/19: Boundary Scn, Bist
38411: 02/01/14: Falling edge in PLD
38459: 02/01/15: Re: Falling edge in PLD
38838: 02/01/26: Peaks in smaller PLDs
38906: 02/01/28: Re: Peaks in smaller PLDs
Martin Forest:
32123: 01/06/14: Xilinx Virtex 2: Configurations problems
Martin Forsberg Lie:
52849: 03/02/24: Re: FPGA's at High Temperatures
52853: 03/02/24: Re: LVDS LCD
Martin Freeman:
25: 94/07/29: HOT CHIPS SYMPOSIUM VI, AUGUST 14-16, STANFORD UNIVERSITY
Martin Gagnon:
107205: 06/08/25: Re: Style of coding complex logic (particularly state machines)
Martin Geisse:
108691: 06/09/15: problems with IOSTANDARD
108808: 06/09/17: Re: problems with IOSTANDARD
108815: 06/09/17: Re: problems with IOSTANDARD
martin griffith:
18720: 99/11/09: Re: Sample Rate Conversion.
18798: 99/11/17: Re: Q: implementing TCP/IP on PLD
107537: 06/08/30: Re: September training?
107648: 06/08/30: Re: Performance Appraisals
107649: 06/08/30: Re: Performance Appraisals
107745: 06/09/01: Re: Performance Appraisals
107980: 06/09/03: Re: Please help me with (insert task here)
108056: 06/09/04: Re: Please help me with (insert task here)
108063: 06/09/05: Re: Please help me with (insert task here)
Martin Guibert:
17265: 99/07/15: Re: Dongle problems.
45322: 02/07/18: How's the FPGA design job market near you??
45331: 02/07/19: Re: How's the FPGA design job market near you??
45361: 02/07/20: Re: spiral / waterfall /watersluice : Which are your methods?
46627: 02/09/04: Re: Virtex-2 BRAM
49914: 02/11/25: Q about operating temperatures
Martin Hansel:
95963: 06/01/27: LogiBlox on Foundation 4.1 Error
Martin Heimlicher:
23167: 00/06/16: Re: PCI for a fpga board
27891: 00/12/13: How do I specify clock skew in the Altera Quartus tool ?
27892: 00/12/13: Multicycle timing requirements in Altera Quartus
27893: 00/12/13: Is it necessary to synchronize the reset signal in an FPGA ?
27970: 00/12/18: Re: async interface
Martin Herrmann:
151375: 11/03/29: Xilinx DDR3 controller: rewrite mode registers
151379: 11/03/30: Re: Xilinx DDR3 controller: rewrite mode registers
Martin Hoffensetz:
7827: 97/10/20: Importing FLEX10k into Cadence
MARTIN jm:
63677: 03/11/28: Re: problem with RS485 or RS232
Martin Kellermann:
48059: 02/10/10: Re: how do initialised signals really get set in Xilinx slices?
54396: 03/04/10: Re: Modular Design: XAPP404
55378: 03/05/06: Re: Xilinx VirtexII Pro Rocket-IO
55437: 03/05/08: Re: Xilinx VirtexII Pro Rocket-IO--Power
58381: 03/07/22: Re: help needed..... ERROR:MapLib:30 - Bad format for LOC constraint AB12 on rx.
59432: 03/08/19: Re: Xilinx Parallel Cable III Schematic
63369: 03/11/20: Re: avoiding GCLK
64066: 03/12/15: Re: Extracting timing from a demo board (V2MB1000)
64753: 04/01/13: Re: V2Pro Rocket IO Primitive- Parameter and Port Settings
66682: 04/02/25: Re: Experience with Simulating RocketIO in Modelsim
66923: 04/03/01: Re: Xilinx iMPACT error: "Done did not go high"
67255: 04/03/09: Re: Reg..How to use BUFGMUX in Spartan 2 family
76033: 04/11/23: Re: Help! What is this card?
77689: 05/01/14: Re: Xilinx FPGA editor
martin lytz:
15910: 99/04/20: Re: What's the best way to learn about fpga's?
17263: 99/07/15: Re: Easy money !!! and it's REAL
Martin Maierhofer:
7188: 97/08/12: Job announcement?
Martin Mason:
1354: 95/06/06: AT17C128 and AT17C65 E2PROM PARTS
1394: 95/06/13: Re: 17C256 EEPROMs from Atmel.
1948: 95/09/22: Reprogrammable 17CXXX devices.
4108: 96/09/11: Re: 256K EEPROM
4473: 96/11/02: Re: Altera Configuration EPROM Equivalents
5263: 97/02/02: Re: Altera BitBlaster
6408: 97/05/22: logicores and parameterized macros
6584: 97/06/03: Re: In circuit programming of flash with Xilinx devices??
6585: 97/06/03: Re: New Reconfigurable Computing newsgroup?
6666: 97/06/10: Re: ATMEL 17Cxxx ISP function
7216: 97/08/15: Re: Price of Serial EEPROM is Outrageous
7524: 97/09/18: Re: Atmel 17256 serial config EEPROMs
7589: 97/09/24: Re: ISP Serial EEPROM for Altera FLEX10k
7767: 97/10/13: Atmel's NEW FPGA.
7765: 97/10/13: New AT40K FPGA Arch.
7945: 97/11/01: Re: Complex Multiplier
8429: 97/12/14: Re: combinational multipliers
8605: 98/01/12: Re: Xilinx Configuration Problem
8606: 98/01/12: Re: serial conf. PROMS
9022: 98/02/14: Re: altera max7000s and JTAG ISP
9135: 98/02/23: Re: Atmel SPROMs for Xilinx
9395: 98/03/09: Re: Problems with Atmel IDS 5.0 installation
9665: 98/03/29: Re: Dual port
10006: 98/04/21: Re: Could you help me save CLB's?
martin mason:
744: 95/02/22: Re: PLA? PAL? PLD? GAL?
839: 95/03/10: Re:FPGA bit serial multipliers
1204: 95/05/13: Re: Overheating (was Re: Compression algo's for FPGA's)
1676: 95/08/15: Fwd: Re: Xilinx PROMs
Martin Mason 408 436 4178:
214: 94/09/23: Reconfigurable FPGAs
447: 94/11/18: Encryption and reconfigurable FPGAs
Martin Maurer:
16864: 99/06/15: 3 Questions with XILINX CPLD
17127: 99/07/01: ABL-Problem (XILINX CPLD)
34710: 01/09/04: Searching a few pieces of Lattice ispLSI 1016E
67857: 04/03/21: XC95108: Problem with state machine reset in ABEL
67859: 04/03/21: XC95108: Problem with state machine reset in ABEL -> now full posting...
68782: 04/04/18: UART with FIFO -> CPLD / FPGA / ?
69031: 04/04/26: Xilinx CPLD - FSM - one hot - lost token...
69377: 04/05/09: VHDL Beginner: Reset a counter (instead of "000000000....000000") - better way ?
69623: 04/05/16: Internal Signals and other questions with ModelSim XE/II Starter 5.7g VHDL Testbench
69854: 04/05/22: Re: FPGA Board with Flash Memory
70264: 04/06/11: Avoid action on very short peak on input signal (Xilinx Spartan 2)
72311: 04/08/14: Re: Free Spartan3 download program for GNU/Linux
Martin Melzer:
32786: 01/07/09: Metastability constants for Altera FPGAs?
Martin Meserve:
12205: 98/10/05: Re: Verilog Simulators
Martin Muggli:
48593: 02/10/21: Re: Using MXE II starter as a restricted user
Martin Neilan:
9692: 98/03/31: Digital PLL's or Manual Synching?
Martin Radetzki:
1556: 95/07/14: Re: Synopsys timing simulation of two XC3000 chips
1994: 95/09/29: Altera Sim. with Leapfrog
3354: 96/05/18: Re: is high input number mutliplxer inferrable?
3429: 96/05/29: Re: more about optimal synthesis of FSM
Martin Rice:
33084: 01/07/17: Coolrunner: availability
33893: 01/08/07: Re: Newbie Question: LPT245 in CoolRunner?
34165: 01/08/15: Re: Building a clock out of a PLD
34202: 01/08/16: Re: Xilinx WebPack .UCF file
35414: 01/10/03: What's a process?
37995: 01/12/29: Re: Look for FPGA Starterkit
38337: 02/01/11: Re: latch vs. register
Martin Riddle:
77817: 05/01/18: Re: Quartus II Command Line and Project Files
78109: 05/01/25: Re: Scripted Xilinx flow with free Webpack tools?
79548: 05/02/21: Re: does anyone have a c compiler for the picoblaze
81681: 05/03/30: Re: Custom compilation step in Quartus
83341: 05/04/28: Re: *RANT* Ridiculous EDA software "user license agreements"?
142969: 09/09/10: Re: An email from Altera
152468: 11/08/27: Re: cheating Arria FPGA i/o count
152752: 11/10/18: Re: Altera FPGA weirdness
157969: 15/06/08: Re: PCIe card with FPGA and DAC
157970: 15/06/08: Re: PCIe card with FPGA and DAC
Martin Roenne:
34428: 01/08/24: Re: SmartMedia
Martin Rosner:
12344: 98/10/09: Re: FCCM 99?
Martin Ryba:
66208: 04/02/14: Re: Sine Wave Generation
Martin Sauer:
40726: 02/03/14: Difference between Virtex-II(E) und Virtex-E
40732: 02/03/14: Xilinix FPGA width 5V IO
40908: 02/03/18: Xilinx Virtex II in comparsion with Altera Apex 20KC
44743: 02/06/28: Programming a Xilinx CPDL with a Microcontroller
52610: 03/02/16: VITAL_primitives Library in Xilinx WebPack
56655: 03/06/11: Xilinx CPLD programming with microcontroller
56664: 03/06/11: Re: Xilinx CPLD programming with microcontroller
56882: 03/06/18: Fuse Map for Xilinx XPLA3
56886: 03/06/18: User Electronic Signature in Xilinx XPLA3
63450: 03/11/21: Xilinx WebPack and Linux/WINE
124259: 07/09/17: ECP2/M und Serdes
136647: 08/11/28: Dithering video signals
136662: 08/11/29: Re: Dithering video signals
Martin Schoeberl:
26082: 00/10/03: JVM processor
31452: 01/05/25: Re: FPGA
31453: 01/05/25: Re: Need A little prog?
31532: 01/05/29: Re: what cables and softwares do you need to use "Xilinx FPGA Demonstration Evaluation Board"?
33039: 01/07/16: Re: Byteblasting an ACEX in running system?
33088: 01/07/17: Re: processor core
33144: 01/07/18: Xilinx WebPACK - ROM
33164: 01/07/18: Re: Xilinx WebPACK - ROM
33165: 01/07/18: Re: Xilinx WebPACK - ROM
33314: 01/07/23: Re: free VHDL and/or Verilog tools?
33411: 01/07/25: Re: FPGA Express or Spectrum?
33586: 01/07/31: RAM - VHDL - Altera,...
33591: 01/07/31: Re: RAM... got it
33628: 01/08/01: Re: RAM - VHDL - Altera,...
33674: 01/08/02: Re: RAM - VHDL - Altera,...
33746: 01/08/03: Re: Spartan II and asynchronous memory interface
38835: 02/01/26: Re: Pin assignment on ACEX1K
41180: 02/03/22: Re: Clock termination affecting JTAG interface
45574: 02/07/27: Re: can 555 be used as clock input to cplds
45575: 02/07/27: Re: Making my own software
48896: 02/10/26: Re: Crystal oscillator question
48897: 02/10/26: Re: slow slew rate signal...
49034: 02/10/30: Ann: Altera Prototyping Board
49382: 02/11/11: Re: How to instanciate Altera primitive component in VHDL for FPGA Compiler synthesis?
49489: 02/11/13: Re: Tristate buffers + leonardo Spectrum
49491: 02/11/13: Re: EPP slave interface
50068: 02/11/30: Re: picoJava & the other of Eclipse Sun
50335: 02/12/09: Ann.: Ethernet, IO expansion for protoyping board
50384: 02/12/10: Re: Tiny Forth Processors
50403: 02/12/10: Re: Tiny Forth Processors
50404: 02/12/10: Re: Tiny Forth Processors
50405: 02/12/10: Re: State of the PCB world
50435: 02/12/10: Re: Tiny Forth Processors
50436: 02/12/10: Re: Tiny Forth Processors
50462: 02/12/11: Re: Tiny Forth Processors
50463: 02/12/11: Re: Tiny Forth Processors
50510: 02/12/11: Re: Tiny Forth Processors
50511: 02/12/11: Re: Tiny Forth Processors
50632: 02/12/14: Quartus does not start on Windows ME
50723: 02/12/18: Re: A/D converter in FPGA
50897: 02/12/22: Re: Programming ACEX1K from FlashEprom
50921: 02/12/23: Pin definition in Quartus
52694: 03/02/19: Cyclone EP1C6/EP1C12 pinout
52798: 03/02/22: Re: Should I choose Xilink or Altera for a small project
52928: 03/02/26: Re: configuring xilinx fpga with nand flash
52943: 03/02/26: Re: configuring xilinx fpga with nand flash
52955: 03/02/27: Re: configuring xilinx fpga with nand flash
53237: 03/03/07: Cyclone power up problem
53239: 03/03/07: Re: Cyclone power up problem
53336: 03/03/11: Re: Cyclone power up problem
53383: 03/03/12: Re: Cyclone power up problem
53398: 03/03/12: Re: Cyclone power up problem
53399: 03/03/12: Re: Cyclone power up problem
53403: 03/03/12: Re: Buying memory for FPGA...
53468: 03/03/13: Re: Cyclone power up problem
53469: 03/03/14: Re: Cyclone power up problem
53512: 03/03/14: Cyclone power up problem - Summery
53549: 03/03/16: Re: Cyclone power up problem - Summery
53550: 03/03/16: Re: Cyclone power up problem - Summery
53553: 03/03/16: Re: Cyclone power up problem - Summery
53567: 03/03/16: Re: FPGA dev boards
53574: 03/03/17: Re: FPGA dev boards
53703: 03/03/20: Re: Altera ACEX 1K
54149: 03/04/03: Re: Cyclone power up problem - Summery
54163: 03/04/03: Re: Altera Cyclone
54182: 03/04/04: Re: Cyclone power up problem - Summery
54186: 03/04/04: Re: Altera Cyclone
54234: 03/04/05: Re: Cyclone power up problem - 'Engineerus Emptor'
54400: 03/04/10: Re: Cheap(er) FPGA configuration?
54401: 03/04/10: Re: Cheap(er) FPGA configuration?
54460: 03/04/11: Re: Cheap(er) FPGA configuration?
54462: 03/04/11: Re: Ethernet MAC (was Re: Cheap(er) FPGA configuration?)
54465: 03/04/11: Re: Altera not supplying Leonardo any more
55018: 03/04/24: [ANN] Cyclone FPGA board
55142: 03/04/28: Re: Use of bidir ports on Flex 10k.
55326: 03/05/04: Output switching time
55350: 03/05/05: Re: Output switching time
55356: 03/05/05: Re: Output switching time
55370: 03/05/06: Re: Output switching time
55371: 03/05/06: Re: Output switching time
55374: 03/05/06: Re: Ibis for Cyclone?
55388: 03/05/06: Re: Ibis for Cyclone?
55477: 03/05/09: Re: Info about development kit
55728: 03/05/17: Re: Output switching time
55729: 03/05/17: Re: Output switching time
55770: 03/05/19: Re: Output switching time
56999: 03/06/20: Quartus bug or wrong VHDL?
57010: 03/06/20: Re: Quartus bug or wrong VHDL?
57035: 03/06/21: Re: Quartus bug or wrong VHDL?
57037: 03/06/21: Quartus / Leonardo frustration
58255: 03/07/18: Re: Altera ByteBlaster Standalone Programming Utility
58256: 03/07/18: Re: Graduation Day: My first 4-layer PCB
58775: 03/08/01: Re: Size does matter
58846: 03/08/02: Re: Size does matter
58897: 03/08/04: Re: opencores.org - Question on project licensing?
58908: 03/08/04: Re: opencores.org - Question on project licensing?
59253: 03/08/13: Re: Size does matter
59384: 03/08/18: Re: Never used FPGA board for sale
59396: 03/08/18: Re: Never used FPGA board for sale
59425: 03/08/19: Re: Never used FPGA board for sale
59447: 03/08/19: Re: serial communication between pc and altera fpga
59838: 03/08/29: Re: pricing, cyclone or spartan
59852: 03/08/29: Re: pricing, cyclone or spartan
59857: 03/08/29: Re: pricing, cyclone or spartan
60231: 03/09/08: Re: Sending and receiving Ethernet traffic
60245: 03/09/09: Re: Sending and receiving Ethernet traffic
62103: 03/10/19: Re: Picojava FPGA and Development board
62480: 03/10/30: Re: Some FPGA questions
63773: 03/12/03: Re: getting started in FPGA
66298: 04/02/16: Re: Dual-stack (Forth) processors
66391: 04/02/18: Re: Dual-stack (Forth) processors
66426: 04/02/19: Re: Dual-stack (Forth) processors
68228: 04/03/30: Re: Quartus removes Tristate Buffer
68546: 04/04/07: Re: Cyclone and ByteBlasterMV?
68594: 04/04/08: Re: Min. Reqmts For Altera Nios -- i.e Will it work on Parallax Cyclone FastPack?
68715: 04/04/15: Re: what is a better approach to synthezise synchronous reset on FPGA?
68720: 04/04/15: Re: what is a better approach to synthezise synchronous reset on FPGA?
68721: 04/04/15: Re: what is a better approach to synthezise synchronous reset on FPGA?
69248: 04/05/03: [ANN] Altera Cyclone EP1C12 FPGA Board
69370: 04/05/08: Re: Which board to buy? Status of open source tools?
71780: 04/07/30: Re: Suggestions for programming flash RAM for SoC via FPGA
72069: 04/08/07: LEGO mindstorms and FPGA
72086: 04/08/08: Re: LEGO mindstorms and FPGA
72092: 04/08/08: Re: LEGO mindstorms and FPGA
72162: 04/08/10: Re: LEGO mindstorms and FPGA
72166: 04/08/10: Re: LEGO mindstorms and FPGA
72334: 04/08/15: Re: LEGO mindstroms and FPGA
72410: 04/08/18: Re: nand flash memory chips
73946: 04/10/01: JOP on Spartan-3 Starter Kit
73976: 04/10/01: Re: JOP on Spartan-3 Starter Kit
73981: 04/10/01: Re: Capabilities of Spartan-3 Starter Kit (XC3S200).
74007: 04/10/02: Re: JOP on Spartan-3 Starter Kit
74018: 04/10/02: Re: JOP on Spartan-3 Starter Kit
74023: 04/10/02: Re: JOP on Spartan-3 Starter Kit
74024: 04/10/02: Re: JOP on Spartan-3 Starter Kit
74025: 04/10/02: Re: JOP on Spartan-3 Starter Kit
74027: 04/10/02: Re: Open-Source MicroBlaze IP-Core working in FPGA :)
74030: 04/10/02: Re: Capabilities of Spartan-3 Starter Kit (XC3S200).
74032: 04/10/02: Re: Open-Source MicroBlaze IP-Core working in FPGA :)
74036: 04/10/02: Re: JOP on Spartan-3 Starter Kit
74039: 04/10/02: Re: NV on-chip memory?
72987: 04/09/09: AD: ACEX 1K50 FPGA board clearance sale
72989: 04/09/09: Re: ACEX 1K50 FPGA board clearance sale
72990: 04/09/09: Re: AD: ACEX 1K50 FPGA board clearance sale
73569: 04/09/24: Re: spartan-3 sram
74956: 04/10/22: Re: interfacing a PC based program with a FPGA
74958: 04/10/22: Re: Introducing MANIK - a 32 bit Soft-Core RISC Processor
74965: 04/10/22: Re: Spartan 3 - Internal busses & tristate ?
74060: 04/10/03: Re: Open-Source MicroBlaze IP-Core working in FPGA :)
74061: 04/10/03: Re: NV on-chip memory?
74100: 04/10/04: Re: NV on-chip memory?
74102: 04/10/04: Re: Differences between Xilinx ISE Foundation and WebPACK.
74108: 04/10/04: Re: Open-Source MicroBlaze IP-Core working in FPGA :)
74164: 04/10/05: Re: Features of Xilinx ISE WebPACK & Altera's Quartus II.
74165: 04/10/05: Re: JOP on Spartan-3 Starter Kit
74217: 04/10/06: Re: JOP on Spartan-3 Starter Kit
74264: 04/10/06: Re: JOP on Spartan-3 Starter Kit
74311: 04/10/07: add/sub 2:1 mux and ena in a single LE (Cyclone)
74331: 04/10/08: Re: add/sub 2:1 mux and ena in a single LE (Cyclone)
74332: 04/10/08: Re: PLL lock usage into Altera Stratix devices
74370: 04/10/08: Re: PLL lock usage into Altera Stratix devices
74373: 04/10/09: Re: PLL lock usage into Altera Stratix devices
74374: 04/10/09: Re: PLL lock usage into Altera Stratix devices
74378: 04/10/09: Re: add/sub 2:1 mux and ena in a single LE (Cyclone)
74401: 04/10/10: Re: JOP on Spartan-3 Starter Kit
74403: 04/10/10: Re: JOP on Spartan-3 Starter Kit
74444: 04/10/11: Re: CAche memory
74529: 04/10/13: Re: EP1C12 or XC3S400?
74714: 04/10/17: Re: JOP on Spartan-3 Starter Kit
74719: 04/10/17: Re: add/sub 2:1 mux and ena in a single LE (Cyclone)
75829: 04/11/16: Re: Hello anyone! Does someone works with CS8900 under NIOSII? It's really works? Please, write works it with HAL? Thx.
75953: 04/11/20: Re: FPGA development board
76007: 04/11/22: JOP on Trenz Retrocomputiong Board
78729: 05/02/07: Quartus project files
78734: 05/02/07: Cyclone configuration device
78743: 05/02/07: Re: Cyclone configuration device
78747: 05/02/07: Re: Cyclone configuration device
78750: 05/02/07: Re: Cyclone configuration device
78751: 05/02/07: Re: Cyclone configuration device
78794: 05/02/08: Re: Quartus project files
78795: 05/02/08: SimmStick FPGA module
78801: 05/02/08: Re: SimmStick FPGA module
78825: 05/02/08: Re: SimmStick FPGA module
78827: 05/02/08: Re: SimmStick FPGA module
78829: 05/02/08: Re: SimmStick FPGA module
78862: 05/02/09: Re: SimmStick FPGA module
78864: 05/02/09: Re: quartus "make clean" ?
78921: 05/02/10: Re: SimmStick FPGA module
78965: 05/02/10: Re: Writing IP-Cores while sleeping ;)
79128: 05/02/14: Re: SimmStick FPGA module
79149: 05/02/15: Re: SimmStick FPGA module
79151: 05/02/15: Re: SimmStick FPGA module
79533: 05/02/20: JOP VHDL simulation
79575: 05/02/21: Re: Reconfigure your dreams: fully reconfigurable computer in DIP40 !
79606: 05/02/21: Re: JOP VHDL simulation
79609: 05/02/21: Re: Reconfigure your dreams: fully reconfigurable computer in DIP40 !
79639: 05/02/22: SD Card and FPGA
79641: 05/02/22: Re: Tristate Discussion
79665: 05/02/22: Re: SD Card and FPGA
79667: 05/02/22: Re: FPGA board with best cost/CLB ratio?
79707: 05/02/23: Re: Tristate Discussion
80093: 05/03/01: Re: block adder for Altera!
83457: 05/04/30: Re: Flexray ip core
84796: 05/05/27: Re: ISE 7.1 small advice about project files (.ISE extension)
85426: 05/06/09: Re: Spartan 3 Starter kit group formed
85518: 05/06/10: Re: Microblaze 4.0 with uClinux is ok or not?
86494: 05/06/29: Re: Chess & FPGAs
86612: 05/06/30: Direct audio output from FPGA pins
86628: 05/07/01: Re: Direct audio output from FPGA pins
87525: 05/07/25: Re: OnChip Oscillator for Xlinx FPGA's (Spartan-3 available now)
88816: 05/08/29: Re: digilent spartan 3 kit example project
88820: 05/08/29: JTAG conifguration via USB
91899: 05/11/16: Quartus crash
92066: 05/11/21: Re: Quartus crash
92202: 05/11/23: Wishbone comments
92204: 05/11/24: Re: Design Implementation in Xilinx XST
92230: 05/11/24: Memory in VHDL
92233: 05/11/24: Re: Memory in VHDL
92243: 05/11/24: Re: Memory in VHDL
92244: 05/11/24: Re: Memory in VHDL
92249: 05/11/24: Re: Memory in VHDL
92257: 05/11/24: Re: Wishbone comments
92326: 05/11/28: Re: Wishbone comments
92327: 05/11/28: Re: Memory in VHDL
92354: 05/11/28: Re: instruction counts and cache hits/misses on FPGA
92540: 05/12/01: Quartus db issue
92549: 05/12/01: Re: Quartus db issue
93018: 05/12/12: Re: MMC(MultiMedia Card) interfacing with FPGA
93022: 05/12/12: Re: MMC(MultiMedia Card) interfacing with FPGA
93639: 05/12/27: Re: Download to board with RS232
93644: 05/12/27: Re: Download to board with RS232
93738: 05/12/29: Re: Power Optimization: can the routing and placement really save power?
93744: 05/12/29: Re: Power Optimization: can the routing and placement really save power?
93747: 05/12/29: Actel Fusion
93756: 05/12/29: Re: Power Optimization: can the routing and placement really save power?
96095: 06/01/30: Floating-Point Unit (for JOP)
96343: 06/02/02: Re: AC97 Controller
96426: 06/02/03: Quartus programmer problem
97727: 06/02/27: Re: miniuart
98529: 06/03/12: LEON processor core
98575: 06/03/13: Re: LEON processor core
105952: 06/08/03: Cyclone I & II memory fmax
105984: 06/08/04: Re: Cyclone I & II memory fmax
106007: 06/08/04: Re: Cyclone I & II memory fmax
106013: 06/08/05: Re: How to implement large ROM's from binary sources?
106033: 06/08/06: Re: Cyclone I & II memory fmax
106053: 06/08/07: Re: How do I treat "default" case which is useless?
106288: 06/08/10: Altera SOPC ModelSim question
106334: 06/08/12: JOP as SOPC component
106350: 06/08/12: Re: JOP as SOPC component
106355: 06/08/12: Re: JOP as SOPC component
106382: 06/08/12: Re: JOP as SOPC component
106389: 06/08/12: Re: JOP as SOPC component
106391: 06/08/12: Re: JOP as SOPC component
106397: 06/08/12: Re: JOP as SOPC component
106400: 06/08/12: Re: JOP as SOPC component
106452: 06/08/13: Re: JOP as SOPC component
106454: 06/08/13: Re: JOP as SOPC component
106458: 06/08/13: Re: JOP as SOPC component
106460: 06/08/13: Re: JOP as SOPC component
106462: 06/08/14: Re: JOP as SOPC component
106466: 06/08/14: Re: JOP as SOPC component
106467: 06/08/14: Re: JOP as SOPC component
106503: 06/08/14: Re: JOP as SOPC component
106506: 06/08/14: Re: JOP as SOPC component
106528: 06/08/15: Re: JOP as SOPC component
106619: 06/08/16: Re: Alternative for Mentor''s HDL Designer
106630: 06/08/16: Re: Alternative for Mentor''s HDL Designer
106672: 06/08/17: Re: Quartus and source control (continued)
106743: 06/08/18: Re: JOP as SOPC component
106891: 06/08/22: Re: JOP as SOPC component
106892: 06/08/22: Re: CPU design
106894: 06/08/22: Re: CPU design
106994: 06/08/23: Re: CPU design
106997: 06/08/23: Re: JOP as SOPC component
107002: 06/08/23: Re: JOP as SOPC component
107124: 06/08/24: Re: JOP as SOPC component
107128: 06/08/24: Re: JOP as SOPC component
107175: 06/08/25: Re: JOP as SOPC component
107366: 06/08/27: Re: JOP as SOPC component
107398: 06/08/28: Re: JOP as SOPC component
107550: 06/08/30: Re: JOP as SOPC component
119358: 07/05/17: FPGA and LEGO Mindstroms
129457: 08/02/25: The Java processor JOP is now GPL
138798: 09/03/11: What happens at opencores.org?
138895: 09/03/14: Re: What happens at opencores.org?
138896: 09/03/14: Re: What happens at opencores.org?
142093: 09/07/24: AD: Used Cyclone EP1C6 boards
142199: 09/07/29: Re: Used Cyclone EP1C6 boards
154719: 12/12/29: Chisel as alternative HDL
154723: 12/12/29: Re: Chisel as alternative HDL
154729: 12/12/30: Re: Chisel as alternative HDL
154738: 13/01/03: Re: Chisel as alternative HDL
154746: 13/01/03: Re: Chisel as alternative HDL
154764: 13/01/04: Re: Chisel as alternative HDL
154768: 13/01/05: Re: Chisel as alternative HDL
154774: 13/01/07: Re: Chisel as alternative HDL
154781: 13/01/08: Re: Chisel as alternative HDL
154913: 13/02/13: Re: Chisel as alternative HDL
Martin Strubel:
153041: 11/11/20: Re: Production Programming of Flash for FPGAs and MCUs
Martin Studach:
27285: 00/11/17: Re: FPGA Pin Nunber
Martin Thompson:
26918: 00/11/03: ACEX1K vs FLEX10K
34750: 01/09/06: Re: LPM_FIFO_DC
34751: 01/09/06: Re: strange behaviour of LPM_FIFO_DC in altera 10k130e
34966: 01/09/17: Re: Altera 10K shortage
35214: 01/09/26: Re: Handle C
35216: 01/09/26: Re: WANTED source code of CPLD on TI 5402 DSK
35224: 01/09/26: Pentium 3 vs Pentium 4 benchmarks
35253: 01/09/27: Re: Pentium 3 vs Pentium 4 benchmarks
35511: 01/10/09: Re: ROM based FSMs
35536: 01/10/10: Re: anyone know of SDRDRAM controller for free?
35639: 01/10/12: Re: High level synthesis will never work well :)
35646: 01/10/12: Re: Use of Global in Altera FLEX 10KA
35740: 01/10/16: Re: open-drain bidirs in xilinx or altera
35805: 01/10/18: Re: open-drain bidirs in xilinx or altera
35806: 01/10/18: Re: SDRAM Controller for Xilinx Virtex
35900: 01/10/23: Re: Problems with writing into text file
36088: 01/10/29: Re: Digital image input for simulation on Altera FPGA
36548: 01/11/12: Re: Decoupling capacitors on Virtex II
36671: 01/11/15: Re: Incrementing counter from state-machine
36681: 01/11/15: Re: Decoupling capacitors on Virtex II
36864: 01/11/22: Re: Decoupling capacitors on Virtex II
36889: 01/11/23: Re: Decoupling capacitors on Virtex II
36921: 01/11/26: Re: Decoupling capacitors on Virtex II
38792: 02/01/25: Re: Intel vs. AMD
39025: 02/01/30: Re: Flex10KA vs MAX7000S
39318: 02/02/06: Re: FPGA --> SDRAM & Groundbounce: Latchup Possible?
39319: 02/02/06: Re: Making Altera development quicker
39353: 02/02/07: Re: Altera MAX7000 PLD's
39736: 02/02/18: Re: Making Altera development quicker
40019: 02/02/25: Re: How can I disable clock buffer (BUFG) insertion in Xilinx Foundation F3.1i?
40062: 02/02/26: Re: RAM question
40129: 02/02/28: Re: Beginner Altera Questions
40130: 02/02/28: Re: Simulation Question
40169: 02/03/01: Re: Beginner Altera Questions
40382: 02/03/06: V-II DCM options
40401: 02/03/06: Re: V-II DCM options
41124: 02/03/21: Re: more questions
41284: 02/03/25: Re: High speed clock routing
41333: 02/03/26: Re: High speed clock routing
41797: 02/04/08: Variable phase-shift
41882: 02/04/10: Re: differences betw. EPF10K30E and EP1K30?
41940: 02/04/11: Attributes *and* generics!?
41983: 02/04/12: Re: Attributes *and* generics!?
42068: 02/04/15: Re: Attributes *and* generics!?
42069: 02/04/15: Re: Attributes *and* generics!?
42920: 02/05/07: Re: Availability of XC2S150E-6FG456I
43640: 02/05/28: Re: Strange error message from MaxPlus II !
44224: 02/06/14: Re: Power supply caps on PCB
44904: 02/07/05: Re: Type conversion - adding integer to logic_vector
44906: 02/07/05: Re: How to improve this VHDL code ?
44948: 02/07/08: Re: Type conversion - adding integer to logic_vector
46664: 02/09/05: Re: Hardware Code Morphing?
47625: 02/10/01: Re: design multiplier
47738: 02/10/03: Re: C\C++ to VHDL Converter
47791: 02/10/04: Re: C\C++ to VHDL Converter
47792: 02/10/04: Re: C\C++ to VHDL Converter
48116: 02/10/11: Re: Verilog vs VHDL discussion on comp.arch.verilog group
48205: 02/10/14: Re: Verilog vs VHDL discussion on comp.arch.verilog group
48330: 02/10/16: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
48414: 02/10/17: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
49373: 02/11/11: Re: Altera MAX7000E (EPM7128ELC84) - programmer?
49428: 02/11/12: Re: Altera MAX7000E (EPM7128ELC84) - programmer?
50330: 02/12/09: Re: Warnings in FPGA express
50386: 02/12/10: Re: Warnings in FPGA express
50387: 02/12/10: Re: How to assign pins in VHDL?
51833: 03/01/23: Re: Virtex II: noise on Vcco causing loss of DCM lock
51941: 03/01/27: Somewhat OT - TECO, was Re: VHDL or Verilog?
52289: 03/02/06: Re: JTAG from CAN
52879: 03/02/25: Re: LVDS LCD
53879: 03/03/26: Re: Problems with Altera Max Plus II software
53951: 03/03/28: Re: DSP-FPGA interface
54469: 03/04/11: Re: Really long vectors in VHDL
56132: 03/05/29: Re: JTAG madness
56611: 03/06/10: DVI with a Virtex-II
56662: 03/06/11: Re: DVI with a Virtex-II - summary
56716: 03/06/12: Re: DVI with a Virtex-II - summary
56717: 03/06/12: Re: DVI with a Virtex-II
56745: 03/06/13: Re: DVI with a Virtex-II
56793: 03/06/16: Re: DVI with a Virtex-II
56794: 03/06/16: Re: Problem with tristate-inout-pins of PS/2-Host
56844: 03/06/17: Re: Problem with tristate-inout-pins of PS/2-Host
57178: 03/06/25: Re: scaling fixed point fft
57233: 03/06/26: Re: Xilinx Webpack bugs bugs bugs
57301: 03/06/27: Re: Xilinx Webpack bugs bugs bugs
57304: 03/06/27: Re: Eighty layers of metal!
57317: 03/06/27: Re: why so many problems Xilinx ?
58215: 03/07/17: Re: device selection for game system
58338: 03/07/21: Re: Graduation Day: My first 4-layer PCB
58699: 03/07/31: Re: VHDL Book Recommendations Please
59243: 03/08/13: News server for posting [was Re: Q: async flip-flop reset by a signal from a different clock domain]
59429: 03/08/19: Re: Async logic in FPGAs
59474: 03/08/20: Re: Parallel interface to an FPGA
59696: 03/08/26: Re: Altera ACEX 1K IOE
59937: 03/09/02: Re: Altera Devices
59983: 03/09/03: Re: Altera Devices
59984: 03/09/03: Re: altera latch synthesis
60104: 03/09/05: Re: Flex6K configuration PROM
60208: 03/09/08: Re: Flex6K configuration PROM
60209: 03/09/08: Re: Flex6K configuration PROM
60413: 03/09/12: Re: Reading and processing input from graphics cards (DVI)?
61574: 03/10/07: Re: beginner - exisit some free schematics programmer for fpga ?
61636: 03/10/08: Instantiating LUTs and INIT strings [was Re: Digesting runs of ones or zeros "well"]
61924: 03/10/15: Re: Xilinx Logic Handbook
62122: 03/10/20: Re: ISE5.2 to ISE6.1
62330: 03/10/27: Re: SDRAM Controller
62332: 03/10/27: Re: Altera ACEX1K configuration and initialisation
62371: 03/10/28: Re: Beginners advice for selecting an environment for FPGA design
62372: 03/10/28: Re: Memory for FPGA based LCD Driver/Controller
62472: 03/10/30: Re: PicoBlaze for Altera (ACEX1K)?
62618: 03/11/03: Re: Vendor supplied symbol/part models?
62649: 03/11/04: Re: Vendor supplied symbol/part models?
62929: 03/11/11: Re: Layout examples
62991: 03/11/12: Re: Layout examples
63030: 03/11/13: Re: Layout examples
63148: 03/11/17: Re: Layout examples
63922: 03/12/09: Re: Block RAM simulation VII
64100: 03/12/16: Re: VHDL-Testbench-Simulation in QuartusII
64451: 04/01/05: Re: Hyperthreading vs. Dual proc
64503: 04/01/06: Re: Hyperthreading vs. Dual proc
64711: 04/01/12: Re: image file reading in vhdl
65473: 04/01/30: Re: Where to get FPGA devices for testing?
66679: 04/02/25: Re: Altera ACEX chip wide reset
66748: 04/02/26: Re: Altera ACEX chip wide reset
68266: 04/03/31: Re: speed vs. temperature
68268: 04/03/31: Re: rs232 interface on nios
69428: 04/05/11: Re: Which board to buy? Status of open source tools?
69429: 04/05/11: Re: VHDL Beginner: Reset a counter (instead of "000000000....000000") - better way ?
69489: 04/05/12: Re: One issue about free hardware
69529: 04/05/13: Re: One issue about free hardware
69568: 04/05/14: Re: One issue about free hardware
69647: 04/05/17: Re: std_logic_vector vs unsigned
69685: 04/05/18: Re: std_logic_vector vs unsigned
69742: 04/05/19: Re: Malfunctioning dual port block ram.
69799: 04/05/20: Re: Malfunctioning dual port block ram.
69989: 04/05/26: Re: VHDL simple question: is 2-D array synthesizable
69990: 04/05/26: Re: Xilinx training
70349: 04/06/14: Re: SDRAM
70350: 04/06/14: Re: Costs of IPs
70623: 04/06/22: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
70671: 04/06/23: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
70708: 04/06/24: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
70709: 04/06/24: Re: Suse 9.1 Linux and Xilinx ISE 6.2i
71112: 04/07/08: Re: Puzzled Simulating with 'X' input Quartus II v4.0 sp1
71207: 04/07/12: Re: Puzzled Simulating with 'X' input Quartus II v4.0 sp1
71494: 04/07/20: Re: Using Verilog to embed the synthesis date and time
72740: 04/08/31: Re: Channel Link signals into Xilinx
73768: 04/09/29: Re: suggestions for Xilinx tool enhancements
73865: 04/09/30: Re: suggestions for Xilinx tool enhancements
75549: 04/11/09: Re: SDRAM sustained bursts
75828: 04/11/16: Re: Basic DVI example?
75885: 04/11/18: Re: video camera interface to FPGA
75886: 04/11/18: Re: Xilinx, VHDL, Verilog, ModelSim, BMP
77606: 05/01/12: Re: (d)ram interface
78950: 05/02/10: Re: Plea for help with MAX7000S
82045: 05/04/06: Re: Stupid question
82046: 05/04/06: Re: Structural vs Behavioral
82416: 05/04/12: Re: xapp134 on sdram controllers: @ bits reordering?
83882: 05/05/09: Re: DVI implementation
83936: 05/05/10: Re: DVI implementation
83998: 05/05/11: Re: DVI implementation
85143: 05/06/06: Re: Magical Mystery Tour of ISE environment variables
86682: 05/07/04: Re: vhdl source code cross reference tool
86759: 05/07/06: Re: Xilinx: XST synchronous FIFO using BRAMs
86814: 05/07/07: Re: fastest FPGA speed grade? Not the only measure, but ...
86894: 05/07/08: Re: aurora reliability
87106: 05/07/15: Re: ise 7.1 Input clk is never used.
87504: 05/07/25: Re: Problems installing windrvr.o in Red Hat EL3...
87646: 05/07/27: Re: how to measure number of cycles in ISE6.3
87718: 05/07/29: Re: Using unregistered inputs in FSM
87943: 05/08/04: Re: RocketIO connexion to an optical transceiver
88215: 05/08/12: Re: memory in verilog(its urgent plz help)
89480: 05/09/16: Re: IP Protection of code block in Xilinx FPGA?
89558: 05/09/19: Re: Xilinx ML403
89848: 05/09/28: Re: Image Processing Algorithm based on FPGA?
89849: 05/09/28: Re: Sythesis software for Virtex-4
89919: 05/09/30: Re: ... failed to route using a CLK template
90414: 05/10/12: [Going OT] Automotive Re: converting 12v signal to 3.3v
90443: 05/10/13: Re: [Going OT] Automotive Re: converting 12v signal to 3.3v
90706: 05/10/19: Re: Rosetta Results
90747: 05/10/20: Re: Rosetta Results
90864: 05/10/24: Re: Implementing five stage pipeline
90913: 05/10/25: Re: Implementing five stage pipeline
91630: 05/11/10: Re: Spartan 3e is slower than Virtex 2p
91727: 05/11/11: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91728: 05/11/11: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
91862: 05/11/15: Re: ISE, JTAG and ChipScopePro.
92284: 05/11/25: Re: Memory in VHDL
92285: 05/11/25: Re: Memory in VHDL
92811: 05/12/07: Re: I2C controller chipset to interface with FPGA
94928: 06/01/19: Re: FPGA Journal Article
94822: 06/01/18: Re: FPGA Journal Article
94930: 06/01/19: Re: FPGA Journal Article
94995: 06/01/20: Re: FPGA Journal Article
95807: 06/01/26: Re: So what happened to JHDLBits?
95806: 06/01/26: Re: open source fpga programmer programs
100074: 06/04/03: Re: deglitching a clock
100842: 06/04/19: Re: INFO: *.XDL file
100888: 06/04/20: Re: INFO: *.XDL file
100918: 06/04/21: Re: How to trsiate o/p pins?
101987: 06/05/09: Re: Can an FPGA be operated reliably in a car wheel?
102162: 06/05/11: Re: CoolRunner XPLA3 getting axed?
102238: 06/05/12: Re: CoolRunner XPLA3 getting axed?
102511: 06/05/17: Re: Power for Spartan 3
102730: 06/05/19: Re: Processing DVI signals with an FPGA
103146: 06/05/26: Re: setting max fanout with xps flow
103564: 06/06/06: Re: Verilog vs VHDL
103568: 06/06/06: Re: Quartus and source control
104694: 06/07/04: Re: Inferring multiple-DSP48 pipelined multiplier in VHDL
104718: 06/07/05: Re: Inferring multiple-DSP48 pipelined multiplier in VHDL
105178: 06/07/17: Re: Development Boards -Your chance to suggest features
105179: 06/07/17: Re: Need for reset in FPGAs
105213: 06/07/18: Re: Development Boards -Your chance to suggest features
105465: 06/07/24: Re: Why 8 clock trees in Xilinx Spartan-3 device?
105568: 06/07/26: Re: Designing a matrix multpier block using existing xilinx toolbox
106057: 06/08/07: Re: verilog versus vhdl
107060: 06/08/24: Re: DCM vs. PLL
107181: 06/08/25: Re: Digilent USB support from Xilinx Impact (Programmer cable SDK for Impact)
107182: 06/08/25: Re: ISERDES strange simulation behaviour
107481: 06/08/29: Re: high level languages for synthesis
107482: 06/08/29: Re: high level languages for synthesis
107566: 06/08/30: Re: high level languages for synthesis
107567: 06/08/30: Re: high level languages for synthesis
107571: 06/08/30: Re: Style of coding complex logic (particularly state machines)
107608: 06/08/30: Re: Style of coding complex logic (particularly state machines)
107609: 06/08/30: Re: Style of coding complex logic (particularly state machines)
107680: 06/08/31: Re: Style of coding complex logic (particularly state machines)
107681: 06/08/31: Re: placing addiional caps across existing caps to reduce noise
107792: 06/09/01: Re: placing addiional caps across existing caps to reduce noise
108017: 06/09/04: Re: Spartan-3 Starter Kit newbie question
108328: 06/09/08: Re: TI TFP410 DVI transmitter help?
108330: 06/09/08: Re: Managing small IP library
108850: 06/09/18: Re: What resources do the Xilinx tools require on a PC?`
109455: 06/09/27: Re: Now on 8.2.03i Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
109849: 06/10/06: Re: An implementation of a clean reset signal
109852: 06/10/06: Re: Instantiating Altera M4K block without MegaWizard
109968: 06/10/09: Re: An implementation of a clean reset signal
109971: 06/10/09: Re: Instantiating Altera M4K block without MegaWizard
109972: 06/10/09: Re: Instantiating Altera M4K block without MegaWizard
109976: 06/10/09: Flancters (was Re: An implementation of a clean reset signal)
110044: 06/10/10: Re: ISE/EDK computer selection
110138: 06/10/11: Re: EDK Bug
110224: 06/10/12: Re: Functional Languages in Hardware
110226: 06/10/12: Re: VGA timing
111298: 06/11/01: Re: Dual Port RAM
111374: 06/11/02: Re: Dual Port RAM
111568: 06/11/06: Re: Interface standards (was Re: Dual Port RAM)
111587: 06/11/06: Re: reset
111635: 06/11/07: Re: Interface standards (was Re: Dual Port RAM)
111688: 06/11/08: Re: Interface standards (was Re: Dual Port RAM)
111742: 06/11/09: Re: Interface standards (was Re: Dual Port RAM)
112793: 06/11/29: Re: So who has used Lattice FPGAs recently?
112794: 06/11/29: Re: DVI clock generation
113604: 06/12/18: Re: DSP or FPGA for high-speed image processing?
113677: 06/12/19: Re: Announce: XDLAnalyze v1.1 and colorized_signals (for ModelSim) v1.1
114101: 07/01/04: Re: SUNDANCE FPGA CONFIGURATION
114133: 07/01/05: Re: SUNDANCE FPGA CONFIGURATION
114309: 07/01/11: Re: inserting text into a video stream (from a pre-existing video source)
114567: 07/01/19: Re: Beginner VHDL questions
114707: 07/01/23: Re: Xilinx ISE 8.2
114777: 07/01/24: Re: Xilinx ISE 8.2
114778: 07/01/24: Re: Xilinx ISE 8.2
114779: 07/01/24: Re: Xilinx ISE 8.2
114809: 07/01/24: Re: system generator from Xilinx
114847: 07/01/25: Re: Xilinx ISE 8.2
114867: 07/01/25: Re: video buffering scheme, nonsequential access (no spatial locality)
114918: 07/01/26: Re: Xilinx ISE 8.2
114998: 07/01/29: Re: Xilinx ISE 8.2
114999: 07/01/29: Re: video buffering scheme, nonsequential access (no spatial locality)
115003: 07/01/29: Re: Forcing a LUT to not be optimized
115056: 07/01/30: Re: bram can't store elf
115103: 07/01/31: Re: bram can't store elf
115152: 07/02/01: Re: Graphics demo using FPGA?
115323: 07/02/07: Re: generating VHDL code from Matlab code for DSP - wavelet image compression
115352: 07/02/08: Re: generating VHDL code from Matlab code for DSP - wavelet image compression
115459: 07/02/12: Re: generating VHDL code from Matlab code for DSP - wavelet image compression
115771: 07/02/20: Re: How to get the area/time results without IO mapping
116031: 07/02/28: Re: How to implement pipeline in this case?
116081: 07/03/01: Potential problem in batch files for Xilinx [was SCons build tool as an alternative to makefiles]
116146: 07/03/02: Re: Potential problem in batch files for Xilinx
116218: 07/03/05: Re: Potential problem in batch files for Xilinx
116219: 07/03/05: Re: Potential problem in batch files for Xilinx
116286: 07/03/06: Re: SCons build tool as an alternative to makefiles
116316: 07/03/07: Re: Potential problem in batch files for Xilinx
116317: 07/03/07: Re: SCons build tool as an alternative to makefiles
116318: 07/03/07: Re: Large power planes vs. power islands vs. slits for decoupling
116389: 07/03/08: Re: SCons build tool as an alternative to makefiles
116408: 07/03/08: Re: using XIlinx impact in batch mode to generate EEPROM files
116577: 07/03/13: Re: odd warning in Xilinx ISE webpack
116685: 07/03/15: Re: Does anybody work with Sundance Module (smt338vp30-> Virtex II Pro 30)
116806: 07/03/19: Re: chipscope
117049: 07/03/22: Re: Virtex-II block RAM problem
117123: 07/03/23: Re: Virtex-II block RAM problem
117310: 07/03/28: Re: Where is Open Source for FPGA development?
117357: 07/03/29: Re: Where is Open Source for FPGA development?
117402: 07/03/30: Re: Where is Open Source for FPGA development?
117486: 07/04/02: Re: Where is Open Source for FPGA development?
117565: 07/04/04: Re: RFC: VHDL testbench enhancements
118096: 07/04/17: Re: vpw/pwm controller
118183: 07/04/19: Re: 64 bit matrix multplication
118372: 07/04/25: Re: VHDL editing with UltraEdit
118376: 07/04/25: Re: Incorrect response from MAC FIR Low Pass Filter
118377: 07/04/25: Re: Problem with PowerPC PIT interrupt
118408: 07/04/26: Re: VHDL editing with UltraEdit
118563: 07/04/30: Re: VHDL editing with UltraEdit
118564: 07/04/30: Re: VHDL editing with UltraEdit
118581: 07/04/30: Re: Xilinx software quality - how low can it go ?!
118829: 07/05/04: Re: Unused Pin setting on per-pin basis
118830: 07/05/04: Re: Wait-for / until won't work ? Xilinx Spartan 3
119416: 07/05/18: Re: VHDL newbie: building sequential circuits with basic gates
119417: 07/05/18: Re: video soltion provider
121159: 07/06/27: Re: Xilinx ISE 9.1 - Version Control - VSS
121175: 07/06/27: Re: CameraLink to Hotlink-II video converter
121252: 07/06/29: Re: Execute from SPI flash
121348: 07/07/03: Re: Xilinx ISE + Multi CPU setup?
121376: 07/07/03: Re: Xilinx ISE + Multi CPU setup?
121731: 07/07/12: Re: Chipscope 9.1: Any easy way to rename and regroup signals?
122002: 07/07/17: Re: Xilinx System generator vs Simulink HDL Coder
122417: 07/07/27: Re: Xilinx VHDL multidimensional array synthesis
122755: 07/08/06: Re: SDR SDRAM controller for Xilinx Spartan-3E
123097: 07/08/16: Re: Multiplication Problem on Microblaze Software
123559: 07/08/30: Re: Xilinx FPGA Based Board Problem
124029: 07/09/11: Re: Free downloadable PDF graph paper.
124107: 07/09/12: Re: FPGA Archives
124166: 07/09/13: Re: FPGA Archives
124303: 07/09/18: Re: Camera Link i/f spec - signal requirements on FVAl/LVAL/DVAL
124311: 07/09/18: Re: Camera Link i/f spec - signal requirements on FVAl/LVAL/DVAL
124478: 07/09/24: [ANN] FPGAOptim - Do you know where your slices are going...?
124498: 07/09/25: Re: [ANN] FPGAOptim - Do you know where your slices are going...?
124499: 07/09/25: Re: Automotive Electronic Control
124504: 07/09/25: Re: Automotive Electronic Control
124614: 07/09/28: Re: Never buy Altera!!!!
124850: 07/10/08: Re: [ANN] FPGAOptim - Do you know where your slices are going...?
124853: 07/10/08: Re: [ANN] FPGAOptim - Do you know where your slices are going...?
126807: 07/12/03: Re: What's the difference for VHDL code between simulation and synthesis?
126842: 07/12/04: Re: What's the difference for VHDL code between simulation and synthesis?
127117: 07/12/12: Re: sobel in vhdl
127784: 08/01/08: Re: Core Generators...
128035: 08/01/14: Re: Resource utilization broken down by hierarchy?
128122: 08/01/16: Re: Real examples of metastability causing bugs
128538: 08/01/30: Re: Active-HDL 7.3 vs Modelsim 6.3d-PE (for Verilog/Systemverilog)
128551: 08/01/30: Re: Grisoft AVG false positve virus detection in Xilinx software.
128581: 08/01/31: Re: ROM/LUT
128582: 08/01/31: Re: About 10-bit pixel datum from CMOS image sensor
128828: 08/02/07: Re: Simple Memory Read problem, help appreciated
129028: 08/02/13: Re: Newbie looking for guidance
129099: 08/02/14: Re: Is a FPGA the solution ?
129727: 08/03/04: Re: Is there any way to disable JTAG for Sptantan3AN
130227: 08/03/18: Re: FSL or DMA w/ FIFO?
130267: 08/03/19: Re: FSL or DMA w/ FIFO?
130270: 08/03/19: Re: Optimizing an inferred counter
130314: 08/03/20: Re: Optimizing an inferred counter
130323: 08/03/20: Re: Optimizing an inferred counter
130362: 08/03/21: Re: Is there a means to conditional synthesis in VHDL?
131234: 08/04/16: Re: Virtex 4 DCM problem
131250: 08/04/17: Re: Virtex 4 DCM problem
132355: 08/05/23: Re: timing constraint is impossible to meet
132755: 08/06/06: Re: Your favourite DSP textbooks/websites?
132895: 08/06/10: Re: SDRAM controller
133381: 08/06/26: Re: FPGA area use by module?
134566: 08/08/19: Re: why does inferred RAM cause synthesis times to explode?
134615: 08/08/21: Re: Image input
134976: 08/09/09: Re: IEEE 1394 interface for FPGA??
135320: 08/09/26: Re: wishbone interface
135513: 08/10/06: Re: Video processing in FPGA
135514: 08/10/06: Re: Spartan 3E overmapping problem
136018: 08/10/28: Re: Question on timing constraints
136019: 08/10/28: Re: Design security
136733: 08/12/03: Re: CameraLink Deserilization and Module Constraint Files
137502: 09/01/21: Re: Image enhancement on FPGA
137557: 09/01/22: Re: Image enhancement on FPGA
137558: 09/01/22: Re: How to add some SDRAM to a FPGA board ?
137717: 09/01/28: Re: Got UART Working!!! need syntax help with using ascii/buffer scheduling.
137729: 09/01/28: Re: Got UART Working!!! need syntax help with using ascii/buffer scheduling.
137732: 09/01/28: Re: What software do you use for PCB with FPGA ?
138693: 09/03/05: Spartan 6 3.3V (was Re: Virtex6 Virtex4 FPGA compatibility)
138694: 09/03/05: Re: writing current date to a register
138729: 09/03/06: Re: Spartan 6 3.3V
138731: 09/03/06: Re: DDR access on Spartan 3E 500 Starter Kit
139193: 09/03/23: Re: How big is my vhdl and am I approaching some size limitation on the chip.
139244: 09/03/24: FPGAs in automotive apps (was Re: Silicon Blue last datesheet correct URL)
139289: 09/03/25: Re: FPGAs in automotive apps
139316: 09/03/26: Re: FPGAs in automotive apps
139342: 09/03/27: Re: FPGAs in automotive apps
139343: 09/03/27: Re: Best way to export Xilinx EDK project in ISE and how to initialize Brams ?
140144: 09/04/30: Re: a basics question: using input pins, pullup, short to ground vs driven signal.
140145: 09/04/30: Re: FPGA simulator for face recognition
140415: 09/05/13: Re: how i can use the external SRAM of FPGA
140604: 09/05/20: Re: XILINX license model restricts longtime availability
140697: 09/05/22: Re: please recommend a soft processor for small image processing tasks
140698: 09/05/22: Re: Are all these claims in VHDL correct?
141134: 09/06/08: Re: digital RGB Video to Analog VGA triple DAC question
141470: 09/06/25: Re: True dual-port RAM in VHDL: XST question
141843: 09/07/13: Re: Xilinx Spartan 3 DCM no output!
141857: 09/07/14: Re: Xilinx Spartan 3 DCM no output!
141903: 09/07/16: Re: HELP required floating point multiplier on FPGA
141961: 09/07/20: Re: HELP required floating point multiplier on FPGA
142017: 09/07/22: Re: Spartan 3 and DDR2
142019: 09/07/22: Re: building a card reader into a virtex 2 or 5 based FPGA device.
142048: 09/07/23: Re: Why do both Xilinx and Altera DPS use 18*18?
142152: 09/07/27: Re: Xilinx ISE 11.x lossage
142865: 09/09/04: Re: Multiple Microblaze on FSL link
143239: 09/09/28: Re: ChipScope Pro, storing stimuli in ILA core
143386: 09/10/08: Re: Implement ARM cores on a FPGA chip?
143460: 09/10/12: Re: Implement ARM cores on a FPGA chip?
143488: 09/10/13: Re: integrating chipscope pro in EDK
143489: 09/10/13: Re: A simple rs232 CLI
143652: 09/10/20: Re: problem while receiving negative integer in microblaze
143653: 09/10/20: Re: xilinx edge trigger interrupt
143960: 09/11/05: Re: problem fpga aera optimization
144042: 09/11/09: Re: Interconnection of MicroBlaze processors
144193: 09/11/19: Re: ML 403 hardware implementation
144244: 09/11/23: Re: Error:Place:645 on a non-clock pin.
144279: 09/11/24: Re: Microblaze interconnection
144463: 09/12/09: Re: Xilinx's version of Quartus' Signaltap?
145045: 10/01/22: Re: State Machine Initialization in Synplify Pro
145074: 10/01/25: Re: State Machine Initialization in Synplify Pro
145304: 10/02/05: Re: Board layout for FPGA
145427: 10/02/09: Re: Xilinx ISE 11.1 crash - Visual Studio error
145596: 10/02/15: Re: VHDL vs Verilog
145738: 10/02/22: Re: System design in FPGA
145742: 10/02/22: Re: how to read bmp file in vhdl
146083: 10/03/05: Re: Modelsim PE vs. Aldec Active-HDL (PE)
146195: 10/03/08: Re: Modelsim PE vs. Aldec Active-HDL (PE)
146196: 10/03/08: Re: Modelsim PE vs. Aldec Active-HDL (PE)
146220: 10/03/09: Re: Modelsim PE vs. Aldec Active-HDL (PE)
146302: 10/03/11: Re: Why doesn't this situation generate a latch?
147079: 10/04/13: Re: How to find latches in Xilinx ISE 10.1
147138: 10/04/15: Re: MPEG Reading material
147208: 10/04/19: Re: MPEG Reading material
147209: 10/04/19: Re: Which 32 bit cores support full Linux?
147309: 10/04/22: Can Altera generate EDIF
147339: 10/04/23: Re: How to over clock for DSP48
147398: 10/04/26: Re: I'd rather switch than fight!
147603: 10/05/06: Re: Floating point unit in microblaze
147674: 10/05/14: Re: Expecting sequential output, but RTL shows concurrent implementation.
147695: 10/05/17: Re: Expecting sequential output, but RTL shows concurrent implementation.
147711: 10/05/18: Re: Expecting sequential output, but RTL shows concurrent implementation.
147995: 10/06/11: Re: Is it possible to get consistent implementation results?
148241: 10/07/01: Re: altshift_taps for Xilinx?
148291: 10/07/05: Re: SPI Flash configuration and data access rate
148319: 10/07/07: Re: FPGA Video processing board (HDMI).. who makes one?
148326: 10/07/07: Re: How to declare a port with a new type
148442: 10/07/23: Re: Using std_ulogic at synthesis level
148478: 10/07/27: Re: Connecting "signed" to "std_logic_vector" ports.
149076: 10/09/29: Re: FPGA For Image Processing[Economical]
149126: 10/10/04: Re: FPGA design not working!
149214: 10/10/08: Re: help with bad synchronous description error
149270: 10/10/13: [ANN] FPGAOptim0208r available
149288: 10/10/14: Re: FPGAOptim0208r available
149563: 10/11/05: Re: combinatorial process not simulating correctly
149582: 10/11/08: Re: Statemachine debugging with Chipscope
149591: 10/11/09: Re: Statemachine debugging with Chipscope
149592: 10/11/09: Re: Statemachine debugging with Chipscope
149819: 10/11/25: Re: Brain Cramps...
149856: 10/11/29: Re: Brain Cramps...
149857: 10/11/29: Re: 1653 - At least one timing constraint is impossible to meet
149869: 10/11/30: Re: Brain Cramps...
149894: 10/12/01: Re: Brain Cramps...
149919: 10/12/02: Re: Brain Cramps...
149920: 10/12/02: Re: Brain Cramps...
149921: 10/12/02: Re: Brain Cramps...
150080: 10/12/10: Re: Interfacing DS92LV1021 with FPGA serdes
150099: 10/12/13: Re: Interfacing DS92LV1021 with FPGA serdes
150133: 10/12/16: Re: microblaze spi core problem
150540: 11/01/26: Re: how to read an image from the PC and store it in FPGA ROM
150583: 11/01/27: Re: how to read an image from the PC and store it in FPGA ROM
150696: 11/02/04: Re: Trivia: Where are you on the HDL Map?
150728: 11/02/07: Re: Trivia: Where are you on the HDL Map?
150743: 11/02/08: Re: Trivia: Where are you on the HDL Map?
151080: 11/03/04: Re: Count bits in VHDL, with loop and unrolled loop produces different results
151227: 11/03/16: Re: Regfile access
151380: 11/03/30: Re: MCode Block Problem
151457: 11/04/11: Re: Do people do this by hand?
151894: 11/06/02: Re: FFT using logic gates only
151910: 11/06/03: Re: Microblaze and PowerPC
151911: 11/06/03: Re: How could I get LUT-level netlist in Xilinx ISE?
151946: 11/06/13: Re: Area Optimization
152039: 11/06/24: Re: Sporadic simulation result with modelsim
152043: 11/06/27: Re: Sporadic simulation result with modelsim
152081: 11/07/01: Re: XST 13.1 explodes with generic of enum type with only one member
152228: 11/07/25: Re: FSL Problem:Data Return and Use
152284: 11/08/03: Re: Regarding process time calculation
152292: 11/08/04: Re: Regarding process time calculation
152293: 11/08/04: Re: Regarding process time calculation
152301: 11/08/05: Re: Regarding process time calculation
152302: 11/08/05: Re: Regarding process time calculation
152304: 11/08/05: Re: image storing into BRAM
152670: 11/09/26: Re: comparing Xilinx XC3S500E-4CPG132C vs Altera Cyclone IV FPGA (EP4CE22F17C6N) apples to apples.
152727: 11/10/12: Re: Microblaze Resources such as BRAMS, LUTS
153097: 11/11/29: Re: Classic Disk Drive simulation and binary file IO.
153100: 11/11/30: Re: Classic Disk Drive simulation and binary file IO.
153104: 11/12/01: Re: Classic Disk Drive simulation and binary file IO.
153305: 12/01/30: Re: Design Notation VHDL or Verilog?
153381: 12/02/13: Re: Life after XDL
153386: 12/02/15: Re: LUT6 FPGAs and Carry Logic
153398: 12/02/16: Re: LUT6 FPGAs and Carry Logic
153457: 12/03/02: Re: JTAG to obsolete Lattice MACH131?
153503: 12/03/19: Re: ways to find frequency of operation in early phase of the design without syntheis
153736: 12/05/03: Re: Smallest GPL UART
153750: 12/05/10: Re: Comparing virtex2 to spartan6
153889: 12/06/22: Re: Data transfers between MicroBlaze and VHDL
153894: 12/06/25: Re: Data transfers between MicroBlaze and VHDL
154089: 12/08/02: Re: how much costs the Artix 7 devices?
154465: 12/11/06: Re: Real Time Protocol - RTP using FPGA
154899: 13/02/04: Re: Using CAN on Zynq
156944: 14/08/01: Re: Professional VHDL Examples?
Martin Usher:
25269: 00/09/03: Re: Non-disclosures in job interviews, Round Two
25509: 00/09/13: Re: hardware compatibility and patent infringement
Martin v. Weymarn:
34039: 01/08/12: Keep Xilinx Webpack from removing unused NETs?
Martin van Eersel:
3359: 96/05/20: PCI fpga
14547: 99/02/04: PCI based development board?
Martin Vorbach:
6846: 97/07/02: Verilog Simulation and Synthesis for FPGA Devices
6845: 97/07/02: Verilog Simulation and Synthesis for FPGA Devices (VeriBests Bug
6912: 97/07/08: Verilog Simulation and Synthesis for FPGA Devices
6972: 97/07/17: Exists a special measurement newgroup?
6973: 97/07/17: How is the ALTERA 10K100 IO-Pin state before (!) configuration (I
6993: 97/07/20: Re: FPGA design tools
7076: 97/07/29: ASIC NRE costs, how are they calculated, which values are typical
7077: 97/07/29: Re: FPGA die photograph
7078: 97/07/29: Re: Problem simulating 3-state output with M1 and Synopsys
7252: 97/08/19: 10K100 socket?
7253: 97/08/19: MaxPlusII from Altera.
7251: 97/08/19: FPGA Express...
7284: 97/08/21: ISP Stories
7303: 97/08/23: MaxPlusII from Altera.
7385: 97/09/05: fpga configuration over PCI
7436: 97/09/10: Large FPGA
7506: 97/09/18: Choosing a good pin assignment for multiple-xilinx prototype.
7507: 97/09/18: Altera Internal PLL
7637: 97/09/30: How to instantiate LPMs in Verilog (is there an equivalent for th
7620: 97/09/29: ALTERA´s promises are not real! Buy XILINX.
9493: 98/03/18: Open IP
9490: 98/03/18: Synthesizable SDRAM-Controller wanted!
Martin Whitaker:
16181: 99/05/07: Re: BGA Prototyping ?
martin+x@y.z:
118672: 07/05/01: Xilinx tools concern
118742: 07/05/02: Re: Xilinx tools concern
Martin, Charles:
39474: 02/02/11: Xilinx m1map vs map
39613: 02/02/14: Re: Xilinx m1map vs map
Martin.J Thompson:
25793: 00/09/20: Re: Virtex 'shutdown' phenomenon
25939: 00/09/27: Re: Simon , decoupling caps
25940: 00/09/27: Re: Synthesiser comparisons (was: FPGA Express strikes again)
26133: 00/10/05: Re: Simon , decoupling caps
27927: 00/12/15: Re: Altera free development tools
28431: 01/01/12: Re: Altera free software
28910: 01/01/29: Re: UK parts
<martin.j.thompson@trw.com>:
30692: 01/04/24: Altera Mercury comments
32695: 01/07/05: Re: Altera ACEX
33685: 01/08/02: Re: May I connect two pins to the same net?
33686: 01/08/02: Re: Altera EPM7064.............HELP
33741: 01/08/03: Re: May I connect two pins to the same net?
33742: 01/08/03: Re: Spartan II and asynchronous memory interface
33819: 01/08/06: Re: May I connect two pins to the same net?
34720: 01/09/05: Re: LPM_FIFO_DC
34723: 01/09/05: Re: LPM_FIFO_DC
<martin.leibetseder@ge.com>:
122596: 07/08/01: Fatal Error ISE 9.1
<martin@atmel.com>:
8564: 98/01/08: Re: serial conf. PROMS
<martin@gubbins.demon.co.uk>:
23947: 00/07/17: Altera fitter woes
<martin@nospam.the-thompsons.freeserve.co.uk>:
18074: 99/09/27: Re: Flex 10k: power-on initialisation of FSM. How to do?
<martin@the-thompsons.freeserve.co.uk>:
18553: 99/10/30: Re: Comparison between Altera and Xilinx
18558: 99/10/31: Re: Comparison between Altera and Xilinx
18578: 99/11/01: Re: Comparison between Altera and Xilinx
18579: 99/11/01: Re: Comparison between Altera and Xilinx
18580: 99/11/01: Re: Comparison between Altera and Xilinx
18581: 99/11/01: Re: Altera Reset Strategy?
19075: 99/11/27: Re: Configuration of ALTERA EPC2LC20 Please help!
martin_05:
148111: 10/06/21: Re: Why is Google so F****** dense about SPAM?
148125: 10/06/22: Re: Why is Google so F****** dense about SPAM?
148184: 10/06/25: Re: Why is Google so F****** dense about SPAM?
<martin_at_deja@my-deja.com>:
18118: 99/10/01: Slice (or CLB) count
18162: 99/10/04: Re: Slice (or CLB) count
<martin_pager@yahoo.com>:
125447: 07/10/25: Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!
Martine Schlag:
5824: 97/03/18: Re: Development board with multiple FPGAs
<martinh@qualcomm.com>:
95060: 06/01/20: Stratix-II <==> Virtex4 interconnect; 10 GB Ethernet cores
martinjpearson:
158153: 15/08/22: Re: Handel-C to VHDL
158155: 15/08/24: Re: Handel-C to VHDL
<martinthompson@my-deja.com>:
23955: 00/07/18: Re: Altera fitter woes
23954: 00/07/18: Re: Altera fitter woes
<martstev@gmail.com>:
111408: 06/11/02: reset
129561: 08/02/27: Quicksim/modelsim
132421: 08/05/26: signal value at power up
132423: 08/05/26: Re: signal value at power up
137406: 09/01/14: VHDL data sampling question
Marty:
36380: 01/11/07: Question about pipelining a design
43590: 02/05/24: Re: Frequency synthesiser
47429: 02/09/25: Re: virtex II pro development board
Marty D:
110778: 06/10/22: Re: Cheapest FPGA board to study VHDL on
Marty Hoffensetz:
7576: 97/09/24: ISP Serial EEPROM for Altera FLEX10k
Marty Pietruszka:
49544: 02/11/14: Re: why systemc?
Marty Ryba:
117172: 07/03/26: Re: shift register with distributed ram
117226: 07/03/27: Variable delay line (was Re: shift register with distributed ram)
117651: 07/04/06: Re: Digital Receiver chip suggestion
118991: 07/05/09: Re: An Open-Source suggestion for Xilinx
128196: 08/01/18: Two's complement Coregen gone?
128249: 08/01/19: Re: Source of accurate frequency
130253: 08/03/19: Optimizing an inferred counter
131081: 08/04/10: Re: Xilinx FFT C-sim model
131192: 08/04/15: Re: Intel plans to tackle cosmic ray threat (actually they have been working on it for at least five years...austin)
132034: 08/05/11: Re: how to set trigger in ChipScopePro for this
135732: 08/10/14: Re: converting MATLAB to VHDL
137546: 09/01/22: Re: FPGA granularity
137592: 09/01/23: Re: FPGA granularity
137878: 09/02/01: Re: Heavily pipelined design
138417: 09/02/21: Very fast counter in VirtexII
138461: 09/02/24: Re: Very fast counter in VirtexII
139487: 09/04/01: Re: Fiber optics protocols for mid range speed
139489: 09/04/01: Re: clock distribution on VITA 57 (FMC)
139731: 09/04/11: Re: NCO'S
140401: 09/05/13: Re: which low cost fpga for space?
141193: 09/06/11: Re: IF board for fpga?
142579: 09/08/18: Re: VHDL code for finding standard deviation for a chunk of numbers
Marty Stan:
14529: 99/02/03: Contract Job: Boston; Xilinx, FPGA; ATM
14876: 99/02/22: Houston - Need FPGA Work
Marvin:
131971: 08/05/08: Re: Spartan 3 Mapping Problem
134849: 08/09/03: Re: Is it possible to do incremental synthesis and placement?
Marvin L:
158884: 16/05/14: Recoding openCV C++ project in pure verilog
159008: 16/06/05: comparing hardware architecture
159009: 16/06/05: comparing hardware architecture
159143: 16/08/25: Four_Bit_Counter in VHDL
159144: 16/08/25: Four_Bit_Counter in VHDL
159149: 16/08/25: Re: Four_Bit_Counter in VHDL
159150: 16/08/25: Re: Four_Bit_Counter in VHDL
159152: 16/08/25: Re: Four_Bit_Counter in VHDL
159153: 16/08/26: Re: Four_Bit_Counter in VHDL
159302: 16/09/27: Sharing a single Lookup Table
159333: 16/10/06: Help with multiplier code
159389: 16/10/23: entity component binding issue with configurations
159391: 16/10/23: Re: entity component binding issue with configurations
159392: 16/10/23: Re: entity component binding issue with configurations
MarvL:
21103: 00/03/07: Newbie asks: prototype done, now what?
marwen brikcha:
156534: 14/04/16: Nexys 4 FPGA Board
mary:
151619: 11/04/26: about slices in xilinx
Mary Fisher:
130729: 08/03/31: Re: thread problem?
Mary Frantz:
20440: 00/02/10: Altera vs Cypress?
mary helen aka lisa lee:
151064: 11/03/02: Re: Does anyone have current contact details for Jerry D. Harthcock?
Masaaki:
23854: 00/07/12: Re: Xilinx vs Altera
Masahiko Imahashi:
2056: 95/10/07: [Q] Looking for VHDL models for FPGA
Masca:
135583: 08/10/08: Re: Newbie question
Masononyx:
11225: 98/07/28: Get Rich now
Masood Makkar:
1628: 95/08/08: Xilinx xc4013 routing problems ??
41953: 02/04/11: Re: equivalence checking with FPGA
Masoud Naderi:
46485: 02/08/31: Thermoelectric Controller by FPGAs
46758: 02/09/07: Fault tolerant FPGA design
46768: 02/09/08: Re: Fault tolerant FPGA design
46769: 02/09/08: Re: Fault tolerant FPGA design
46770: 02/09/08: Re: Fault tolerant FPGA design
46915: 02/09/11: Re: Fault tolerant FPGA design
50712: 02/12/18: FPGA instead of HDMP-1022/24
50993: 02/12/25: Parallel Automatic Synchronization System in HDMP-1034
51162: 03/01/04: HDMP-1032/34 Design experinces, hints and so
56066: 03/05/28: IL711 with LVDS
56252: 03/06/01: Re: IL711 with LVDS
56253: 03/06/01: IDT TDM Switch
56254: 03/06/01: SONET/SDH chipset on FPGA
58498: 03/07/24: temux
58548: 03/07/25: Re: temux
58550: 03/07/25: Re: temux
58563: 03/07/26: Re: temux
58586: 03/07/27: Re: FPGA research
58909: 03/08/04: Clock recovery chip for electirical interfacing of LXT6155 to SPECTRA chip
64057: 03/12/15: How LVDS Drivers kills?
64089: 03/12/15: Re: How LVDS Drivers kills?
64224: 03/12/21: Re: How LVDS Drivers kills?
67121: 04/03/05: FPGA hangs
67146: 04/03/06: Re: FPGA hangs
Massi:
65480: 04/01/30: Phase detector for DLL
137130: 08/12/24: PCI newbie problems
137139: 08/12/27: Re: PCI newbie problems
137815: 09/01/30: Pci Express on Virtex 5: PC doesn't reboot
Massimo Baleani:
7980: 97/11/05: Digital reverberator on FPGA
Massimo Gaggero:
91808: 05/11/14: ISE, JTAG and ChipScopePro.
91873: 05/11/15: Re: ISE, JTAG and ChipScopePro.
MassiveProng:
115483: 07/02/12: Re: Building Coaxial transmission line on PCB?
115659: 07/02/16: Re: Building Coaxial transmission line on PCB?
115699: 07/02/16: Re: Building Coaxial transmission line on PCB?
115700: 07/02/16: Re: Building Coaxial transmission line on PCB?
115701: 07/02/16: Re: Building Coaxial transmission line on PCB?
115704: 07/02/16: Re: Building Coaxial transmission line on PCB?
115705: 07/02/16: Re: Building Coaxial transmission line on PCB?
115706: 07/02/16: Re: Building Coaxial transmission line on PCB?
115707: 07/02/16: Re: Building Coaxial transmission line on PCB?
115708: 07/02/16: Re: Building Coaxial transmission line on PCB?
115713: 07/02/16: Re: Building Coaxial transmission line on PCB?
115714: 07/02/16: Re: Building Coaxial transmission line on PCB?
115715: 07/02/16: Re: Building Coaxial transmission line on PCB?
115716: 07/02/16: Re: Building Coaxial transmission line on PCB?
115725: 07/02/17: Re: Building Coaxial transmission line on PCB?
115733: 07/02/18: Re: Building Coaxial transmission line on PCB?
<massmail@aol.com>:
11737: 98/09/05: WE MASS E-MAIL YOUR EXCLUSIVE AD TO 900k - $99
Massoud:
115571: 07/02/14: Is there any version of Aurora protocol which works with LVDS instead of MGTs?
massoud shakeri:
76212: 04/11/29: Running EDK 6.2i with ISE6.3i
76375: 04/12/01: Re: Running EDK 6.2i with ISE6.3i
master:
60073: 03/09/04: Disable Pull up
Master:
60118: 03/09/05: Re: Disable Pull up
60178: 03/09/07: Re: Disable Pull up
Masterbot:
18110: 99/09/30: Lattice ISP-cable
18296: 99/10/12: ISP-Cable again
Mastupristi:
63364: 03/11/20: avoiding GCLK
63381: 03/11/20: Re: avoiding GCLK
63416: 03/11/21: ERROR:Pack:1107 - ISE 6.1
76544: 04/12/06: JTAG recognise xcv50e instead of xc2s50e
76553: 04/12/06: how to use Spastan2e's dll in vhdl
76604: 04/12/07: adding signals to chipscope pro debugging
76608: 04/12/07: Re: adding signals to chipscope pro debugging
mat:
52846: 03/02/24: LVDS LCD
Mat Nieuwenhoven:
85311: 05/06/07: Re: Sch & Layout Free Program
<matadouros.home@gmail.com>:
126950: 07/12/06: For God's sake !! It did not work at all !!!
Mateen:
105748: 06/07/31: Re: EDK : *.bit and *.elf Files
<mathai@ecf.toronto.edu>:
14702: 99/02/12: asyncronous finite state machines on FPGAs?
15223: 99/03/15: multiport register file--Altera Flex10k20 ?
mathedman:
48494: 02/10/18: Re: log calculation
Mathew J. Lamb:
1970: 95/09/26: Alliance, FPGA's, VHDL code......
Mathew Orman:
50467: 02/12/11: ispDesignEXPERT installation
50485: 02/12/11: Re: Power consumption question
51072: 02/12/30: Re: BP programmer questions, prices, alternatives
51077: 02/12/30: Re: BP programmer questions, prices, alternatives
51091: 02/12/31: Re: BP programmer questions, prices, alternatives
52502: 03/02/12: Einstein era>>the ultimate killer experiment! (do it your self instantaneous signal propagation above 40 x c speed )***************************
Mathew Wojko:
18104: 99/09/30: Re: Fine grain vs. Coarse grain
20542: 00/02/14: Multiple GND & VCC Instances
20691: 00/02/18: Re: multiplier
20699: 00/02/18: Re: multiplier
23710: 00/07/06: PamDC question.
23885: 00/07/14: Re: PamDC question.
Mathias Schmalisch:
13202: 98/11/19: Re: DES in VHDL?
29300: 01/02/13: ROM initialization in VHDL for Virtex
79694: 05/02/23: XST: How to select the architecture for synthesis?
Mathias Weierganz:
144404: 09/12/04: Problem with Xilinx ISE and Spartan3
144429: 09/12/07: Re: Problem with Xilinx ISE and Spartan3
Matija:
68009: 04/03/24: PULL-UPs on Xilinx-FPGA
69745: 04/05/19: I2C Slave
69858: 04/05/22: Re: I2C Slave
Matjaz Finc:
41982: 02/04/12: problems with Nios 2.0
42106: 02/04/16: Re: problems with Nios 2.0
42204: 02/04/18: Re: problems with Nios 2.0
42613: 02/04/29: Altera Nios - ptf documentation
42614: 02/04/29: Altera Nios - master/slave peripheral
43201: 02/05/16: Nios 32bit - simulation problem
46015: 02/08/14: Re: Altera APEX clock problem
46924: 02/09/12: Re: Quartus 2 flow
47634: 02/10/01: Re: Nios interrupt latency?
50129: 02/12/03: Re: register OR latch ? (source code)
50183: 02/12/04: Altera Nios pipeline
50540: 02/12/12: Re: NIOS C Programming: Accesing the Status Register?
51185: 03/01/06: Re: Altera SOPC Builder 2.61 problems ...
51409: 03/01/13: Re: Bug in Quartus2 Web 2.2
matrix:
9674: 98/03/30: ISSS'98 FINAL CALL FOR PAPERS
153024: 11/11/16: Migrating to Actel Libero
153029: 11/11/18: Re: Migrating to Actel Libero
MatrixGear:
42315: 02/04/20: Re: Xilinx Programmable World 2002 - Review
Matrox Imaging:
140169: 09/05/01: Re: FPGA/DSP/Video Board
Mats Brorsson:
42107: 02/04/16: Source code for a NIOS instruction set simulator?
42317: 02/04/20: Re: Source code for a NIOS instruction set simulator?
Mats Olsson:
2152: 95/10/20: Problem using Xilinx XC4025
Matt:
43833: 02/06/04: Re: FPGAs used to crack Xbox security
43834: 02/06/04: Re: FPGAs used to crack Xbox security
43835: 02/06/04: Re: chipscope
51538: 03/01/16: quality of software tools in general
51582: 03/01/16: Re: quality of software tools in general
51627: 03/01/17: Re: quality of software tools in general
51646: 03/01/17: Re: quality of software tools in general
51667: 03/01/18: Re: XST vs Synplify observations
51790: 03/01/22: Re: quality of software tools in general
51819: 03/01/22: Re: quality of software tools in general
52542: 03/02/13: Re: Setting CPLD options (Webpac)
52543: 03/02/13: Re: Setting CPLD options (Webpac)
52768: 03/02/21: Re: Synthesis Tools
52866: 03/02/25: Re: VHDL & FPGA Design tools
54953: 03/04/23: Re: Webpack 5.2 Install problems?
55154: 03/04/29: Re: ISE 5.2i evaluation and problem with Windows ME
57032: 03/06/21: Re: FPGA GPU (Spartan IIe 300K)
57519: 03/07/01: VHDL variable setup and propogations
57577: 03/07/02: Process variable setup times and propogations
57599: 03/07/02: Re: UART -- Process variable setup times and propogations
57784: 03/07/07: Re UART troubles solved - THANKS Mike, Peter, and Philip!!
60195: 03/09/07: Re: PIC Programming Help
60446: 03/09/13: Re: Webpack Vs. ISE
60726: 03/09/20: Re: ISE 6.1 and Redhat 9
60864: 03/09/24: Re: ISE 6.1 and Redhat 9
60922: 03/09/25: Re: ISE 6.1 and Redhat 9
61902: 03/10/15: Re: FPGA/CPLD With Analog Functions?
63140: 03/11/16: Re: standalone IMPACT
63269: 03/11/19: Re: Anyone use HDL as design tool for PCBs?
63350: 03/11/20: Re: Anyone use HDL as design tool for PCBs?
63494: 03/11/24: Re: Laptop without serial/parallel port
63596: 03/11/26: Re: Laptop without serial/parallel port
63852: 03/12/05: Xilinx 5.2 and EDK 3.2: Simulation given 'Z' ouput form tutorial design
63904: 03/12/08: Re: Xilinx 5.2 and EDK 3.2: Simulation given 'Z' ouput form tutorial design
64034: 03/12/12: Question about EDK and C functions
64742: 04/01/12: System Generator and Microblaze
64748: 04/01/13: Re: Power plane assignments in a Xilinx PCI card
65467: 04/01/30: Re: Where to get FPGA devices for testing?
66919: 04/03/01: Re: netlist tricks
68154: 04/03/28: Re: AHDL, VERILOG or VHDL??
68244: 04/03/31: Re: AHDL, VERILOG or VHDL??
68657: 04/04/13: Re: Is Xilinx Parallel Cable III OK For Memec V2Pro / Xilinx EDK?
79461: 05/02/19: EMC and Shared SRAM/FLASH Bus
79466: 05/02/19: Re: EMC and Shared SRAM/FLASH Bus
79539: 05/02/20: SRAM & Flash Address Bus w/EMC
133680: 08/07/09: logical net 'NET' has no load
133684: 08/07/09: Re: logical net 'NET' has no load
133722: 08/07/11: Re: logical net 'NET' has no load
matt:
96881: 06/02/13: Xilinx + I2C + PPC -> crash
Matt Fornero:
100492: 06/04/10: NTSC video capture
100552: 06/04/11: ISE 7.1 Map Error
Matt Aubury:
10511: 98/05/26: Re: [++] Fast Life code (Was:Re: FPGA-based CPUs (was Re: Minimal ALU instruction set))
10515: 98/05/26: Re: [++] Fast Life code (Was:Re: FPGA-based CPUs (was Re: Minimal ALU instruction set))
10568: 98/05/31: Re: [++] Fast Life code (Was:Re: FPGA-based CPUs (was Re: Minimal ALU instruction set))
10579: 98/06/02: Re: [++] Fast Life code (Was:Re: FPGA-based CPUs (was Re: Minimal ALU instruction set))
Matt B:
115631: 07/02/15: Re: Xilinx Platform Studio adding Xilinx coreGen IP
Matt Bielstein:
14604: 99/02/06: Re: Synplify/Xilinx4085XLA question
15153: 99/03/10: Re: Xilinx Foundation Timing
36078: 01/10/27: Re: Virtex 2 or E Evaluation Board
38859: 02/01/26: Re: Synthsis Tools for Xilinx
Matt Billenstein:
19342: 99/12/15: Re: State machine ok with binary encoding but unstable with one hot encoding
19501: 99/12/28: Re: xilinx help *desperately* needed
19502: 99/12/28: Specifying Virtex CLKDLL CLKDV_DIVIDE property in VHDL
19558: 99/12/30: Foundation 2.1i Synthesis->Options One-Hot/Zero-Hot state machine encoding
19651: 00/01/06: Virtex 5V io
19516: 99/12/28: Re: xilinx help *desperately* needed
19652: 00/01/07: Virtex real time debugging
19732: 00/01/10: Virtex Temperature Sensing diode pins DXP, DXN
19935: 00/01/19: Virtex Fine Pitch BGA pcb layout
20093: 00/01/27: Re: Pin to pin
20094: 00/01/27: Re: Virtex Fine Pitch BGA pcb layout
20264: 00/02/03: Re: part time
20597: 00/02/15: Simulating Virtex
20605: 00/02/16: Simulating Virtex
20670: 00/02/17: Suggested prototyping boards < $200
20798: 00/02/22: Xilinx Logic Simulator Foundation 2.1i help
21014: 00/03/03: Virtex decoupling cap considerations...
22069: 00/04/18: Re: PULL-UPs on Xilinx-FPGA pads
29262: 01/02/11: Re: double precision floating point arithmetic
29286: 01/02/12: Re: double precision floating point arithmetic
30292: 01/04/01: adding std_logic_vectors
30512: 01/04/11: ngdbuild:432 primitives unexpanded in Foundation?
30668: 01/04/23: Virtex-E HDL -- Possible to clock register directly from ibuf?
Matt Blanton:
101601: 06/05/03: xst segmentation fault
101615: 06/05/03: Re: xst segmentation fault
103008: 06/05/24: setting max fanout with xps flow
103078: 06/05/25: Re: setting max fanout with xps flow
103081: 06/05/25: Re: setting max fanout with xps flow
103100: 06/05/25: Re: setting max fanout with xps flow
103103: 06/05/25: Re: setting max fanout with xps flow
103106: 06/05/25: Re: setting max fanout with xps flow
104435: 06/06/27: dcm clkin_divide_by_2
Matt Boytim:
41259: 02/03/23: Re: All Digital PLL for locking DDS to input clock
Matt Clement:
96603: 06/02/07: why does speed grade effect VHDL program??
96609: 06/02/07: Re: why does speed grade effect VHDL program??
96617: 06/02/07: Re: why does speed grade effect VHDL program??
96619: 06/02/07: Re: why does speed grade effect VHDL program??
96622: 06/02/07: Re: why does speed grade effect VHDL program??
96624: 06/02/07: Re: why does speed grade effect VHDL program??
96652: 06/02/08: Re: why does speed grade effect VHDL program??
96721: 06/02/09: Re: why does speed grade effect VHDL program??
96973: 06/02/14: is there a way to initialize signals to a value
96974: 06/02/14: Re: is there a way to tri-state outputs
97006: 06/02/14: Re: is there a way to initialize signals to a value
98047: 06/03/03: why use an FPGA when a CPLD will do ??
98232: 06/03/07: recommendation for JTAG Boundary Scan software??
98248: 06/03/07: Re: recommendation for JTAG Boundary Scan software??
102326: 06/05/15: Re: JTAG tutorial
Matt Cohen:
69957: 04/05/25: CPLD Board design newbie questions
70097: 04/06/02: 5 V inputs to 3.3 V CPLD
70117: 04/06/03: Re: 5 V inputs to 3.3 V CPLD
Matt Cossoul:
32127: 01/06/14: Re: Xilinx PCI core location constraints
Matt Cross:
3762: 96/07/26: Clearing security fuse on Lattice ispLSI2032?
3795: 96/08/02: Re: Clearing security fuse on Lattice ispLSI2032?
Matt D.:
159470: 16/11/21: Re: Tools on Linux
Matt Dykes:
70483: 04/06/17: Xilinx XST synthesis removes input pin even though it's LOCed
70576: 04/06/21: Re: Xilinx XST synthesis removes input pin even though it's LOCed
Matt Ettus:
53971: 03/03/28: Spartan vs. Cyclone for arithmetic functions
54169: 03/04/03: Re: Spartan vs. Cyclone for arithmetic functions
54520: 03/04/12: Help installing Altera web tools
54537: 03/04/13: Re: Help installing Altera web tools
54538: 03/04/13: Re: Help installing Altera web tools
55021: 03/04/24: bidirectional bus
56495: 03/06/06: Zero for replication multiplier --Quartus Bug?
57016: 03/06/20: Cyclone Migration EP1C6 to EP1C12
59617: 03/08/24: Problem configuring Cyclone
59757: 03/08/27: Re: Problem configuring Cyclone
136980: 08/12/16: Gigabit Ethernet PHY without NDA?
137000: 08/12/18: Re: Gigabit Ethernet PHY without NDA?
Matt Fornero:
97988: 06/03/02: Assign FPGA pins to submodule
98033: 06/03/03: Re: Assign FPGA pins to submodule
Matt Gavin:
19385: 99/12/17: Global buffer insertion (Synplify/Flex10K)
20584: 00/02/15: 100% slice utilization in Virtex FPGA
22364: 00/05/05: Virtex clock buffers
22401: 00/05/08: Re: Virtex clock buffers
23464: 00/06/26: inferring global buffers in Leonardo?
23841: 00/07/12: hold time errors in FPGA's ?
23844: 00/07/12: Re: hold time errors in FPGA's ?
23918: 00/07/14: Re: hold time errors in FPGA's ?
Matt Giwer:
54552: 03/04/14: Re: Hardware acceleration for raytracing purposes
54602: 03/04/14: Re: Hardware acceleration for raytracing purposes
54603: 03/04/14: Re: Hardware acceleration for raytracing purposes
54675: 03/04/15: Re: Hardware acceleration for raytracing purposes
Matt Gosline:
11480: 98/08/18: Re: Where are the multiple drivers?
Matt Grandison:
72595: 04/08/26: Nios IRQ lockup
Matt H:
43269: 02/05/17: Re: SDRAM pricing
Matt Hardy:
62328: 03/10/26: Initializing inferred components with Xilinx ISE Foundation 6
Matt Hayes:
30337: 01/04/03: RC4/ARC4 on an FPGA.
Matt Hosler:
6975: 97/07/17: request for Xilinx 6200 FPGA mappings
Matt Klein:
81513: 05/03/25: Re: Altera's power consumption net seminar
Matt Koepnick:
36640: 01/11/13: Displaying Verilog variables when simulating in Max+Plus II
Matt L:
155057: 13/04/04: Re: FPGA for large HDMI switch
Matt North:
62035: 03/10/17: VFDs
62121: 03/10/20: Re: VFDs
62127: 03/10/20: Re: Lattice Mach CPLD - Leonardo Spectrum vs. Synplify
62287: 03/10/24: Re: Are clock and divided clock synchronous?
62415: 03/10/29: Re: How to protect fpga based design against cloning?
62459: 03/10/30: Re: Some FPGA questions
64022: 03/12/12: Initialising LPM_ROM
65670: 04/02/04: Re: Reconfiguring at runtime internally?
67998: 04/03/24: Re: Bus width between registers in IIR
71735: 04/07/29: Re: FPGA vs CPLD
71873: 04/08/03: VGA Signals
84752: 05/05/26: Re: Lattice ROM file tool....
86436: 05/06/28: Re: Good FPGA for an encryptor
Matt Owens:
22884: 00/05/30: FPGA Jobs in Germany
Matt Parks:
65803: 04/02/06: Connecting FPU core on Virtex II Pro
Matt Sorrensen:
118241: 07/04/21: FPGA Newbie
118268: 07/04/21: Re: FPGA Newbie
118269: 07/04/21: Re: FPGA Newbie
Matt Timmermans:
87414: 05/07/22: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87430: 05/07/23: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87470: 05/07/24: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87471: 05/07/24: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87552: 05/07/25: Re: Best Practices to Manage Complexity in Hardward/Software Design?
Matt van de Werken:
43325: 02/05/19: Re: Circuit design for Altera ACEX development board
43326: 02/05/19: Re: Freeware EDIF viewer
<matt.lettau@gmail.com>:
155110: 13/04/19: Re: FPGA for large HDMI switch
156098: 13/11/22: Re: legacy Xilinx software
156380: 14/03/21: Re: Xilinx ISERDESE2 deserializer primitive behaviour
156428: 14/04/04: Re: Simulation deltas
matt.oppenheim@gmail.com:
114477: 07/01/17: Re: Surface mount ic's
<matt@esquire>:
4379: 96/10/22: Re: Multipliers on Xilinx FPGAs
<matt_hocker@yahoo.com>:
23900: 00/07/14: ARC ARChitect
mattdykes:
96983: 06/02/14: Xilinx HDLParsers:810 or HDLParsers:3329
97011: 06/02/14: Re: Xilinx HDLParsers:810 or HDLParsers:3329
matteo:
107132: 06/08/24: no luck instantiating system.xmp (EDK project file) within ISE
107139: 06/08/24: Re: no luck instantiating system.xmp (EDK project file) within ISE
114150: 07/01/05: dynamically created blockRAM contents?
114199: 07/01/07: Re: dynamically created blockRAM contents?
114543: 07/01/18: Re: dynamically created blockRAM contents?
115132: 07/01/31: virtex4 configuration via XCF32P Prom
115144: 07/01/31: Re: virtex4 configuration via XCF32P Prom
Matteo:
74216: 04/10/06: Constant instantiation
Matteo Mascagni:
9428: 98/03/13: Re: Byteblaster
Matteo Ricchetti:
14088: 99/01/12: cypress isp cable?
Matthew Alan Kendall:
9121: 98/02/22: Re: PROBS W/ ALTERA MAX+PLUS II 8.2 S/W
Matthew Campbell:
50986: 02/12/24: Newbie Question
51039: 02/12/27: Re: Newbie Question
Matthew Carlson:
2087: 95/10/12: Re: * WARNING * $1,000,000 in 90 Days!
Matthew Donadio:
24768: 00/08/17: Re: Implementing an All Digital PLL in FPGA
29117: 01/02/06: Re: MPEG1 video encoder availability?
Matthew E Rosenthal:
47350: 02/09/24: fpga comparisons???
47578: 02/09/29: xilinx size historical information
47581: 02/09/29: altera size historical information
49676: 02/11/19: xilinx device inception dates
67449: 04/03/11: Virtex 2 P -> PPC write to block RAM
67774: 04/03/18: V2p, plb VS opb
67916: 04/03/22: opb, plb routing resources?
67923: 04/03/22: Re: opb, plb routing resources? (fwd)
67926: 04/03/22: quick opb bus questions
67960: 04/03/23: xilinx PPC map file
67970: 04/03/23: RE: IBUFDS -> BUFG
68196: 04/03/29: problem programming V2pro w/gmac logicore
68296: 04/03/31: does V2p support tristate
68378: 04/04/02: Re: ML300 and GigE Experiences
68513: 04/04/07: how to get XST to infer 8:1 mux or just hard code it?
68558: 04/04/08: Re: how to get XST to infer 8:1 mux or just hard code it?
68611: 04/04/09: Re: Virtex2PV20 programming failed, DONE pin doesn't go HIGH
68619: 04/04/09: rocket IO MGT location constraint?
68682: 04/04/14: Re: Problem downloading with parallel converter
69190: 04/04/29: best machine setup for ISE ??
69191: 04/04/29: Re: best machine setup for ISE ??
69265: 04/05/03: Re: XILINX System Generator "fatal error"
69291: 04/05/04: chipscope nuance question?
69301: 04/05/05: Re: chipscope nuance question?
69309: 04/05/05: V2p block ram clock -> Q delay help
69312: 04/05/05: Re: V2p block ram clock -> Q delay help
69558: 04/05/13: Re: V2p block ram clock -> Q delay help
70007: 04/05/26: Re: What can I do if my chip can't meet timing?
70074: 04/06/01: converting design from ise 6.1 to 6.2 problems
70205: 04/06/09: xilinx gigabit MAC core full vs half duplex
70410: 04/06/15: length of parallel cable attached to P IV xilinx jtag cable
70412: 04/06/15: Re: length of parallel cable attached to P IV xilinx jtag cable
71245: 04/07/12: dots during P&R, ISE
71291: 04/07/13: synchronus reset on bufg? (xilinx)
71855: 04/08/02: adding real UART to xilinx ultracontroller design.
71980: 04/08/04: xilinx: non LOC pins causing havoc
72002: 04/08/05: Re: xilinx: non LOC pins causing havoc
72009: 04/08/05: EDK tutorial?????
72020: 04/08/05: Re: EDK tutorial?????
72231: 04/08/11: get net name after place and route, ISE
72435: 04/08/18: xilinx ultracontroller reseting in simulation
72561: 04/08/24: Re: Edk BMM file problem in ISE
72567: 04/08/24: XST 5 input mux synthesis question
72568: 04/08/24: Re: XST 5 input mux synthesis question(s)
72658: 04/08/27: using GNU to compile for PPC405?
72687: 04/08/28: Re: using GNU to compile for PPC405?
Matthew Fettke:
26820: 00/10/31: Virtex Hardware Verification
Matthew Fowle:
52008: 03/01/28: Re: VHDL or Verilog?
52504: 03/02/11: Newbie Starting Places + Books?
52529: 03/02/12: Re: Newbie Starting Places + Books?
52530: 03/02/12: Re: Newbie Starting Places + Books?
52602: 03/02/15: Star Bridge
Matthew Harding:
3910: 96/08/19: Interesting Xilinx XACT observation.
4497: 96/11/06: Re: What is the fastest fpga for ...
Matthew Hicks:
108254: 06/09/07: Re: how can I decrease the time cost when synthesis and implement
109288: 06/09/22: PCI Express
109316: 06/09/23: Re: PCI Express
109502: 06/09/27: Re: Balanced inputs on Spartan3E
109504: 06/09/27: Re: I2C slaves needed
109526: 06/09/27: Re: Anyone had success with MIG, DDR2 and V2Pro?
110155: 06/10/11: Re: nicer code => slower code??
110165: 06/10/11: Re: nicer code => slower code??
110346: 06/10/13: Re: Xilinx documentation typos
110347: 06/10/13: Re: [ISE8.2] DIFF_TERM and unused pin
110566: 06/10/18: Re: 8B/10B vs. Start/Stop for SERDES
110605: 06/10/18: PCB Design Houses
110628: 06/10/18: Re: FIR filter fpga help
110672: 06/10/19: Re: how to implement integrator?
111170: 06/10/30: Re: Programming Virtex II Pro Eval Board
111239: 06/10/31: Re: filter design for low-pass
111311: 06/11/01: Re: Xilinx ISE, where do the pins go?
111356: 06/11/01: Re: Need flash adc with plcc format?
111388: 06/11/02: Re: Need flash adc with plcc format?
111609: 06/11/06: XUP USB
111660: 06/11/07: Re: How to send data/program to the memory of a Spartan 3 starter kit board
111665: 06/11/07: Re: XUP USB
111830: 06/11/10: Re: Area Constraints in Xilinx
111867: 06/11/11: Re: Area Constraints in Xilinx
112024: 06/11/14: Re: xupv2p
112266: 06/11/18: Re: Static Timing Analysis vs Dinamic Timing Analysis
112267: 06/11/18: Re: pulse jitter due to clock
112839: 06/11/29: Re: Spartan-3E or Generic FPGA -> PC133 interface details??
113237: 06/12/08: Re: FFT on Virtex-II Pro (how to download .dat file?)
113622: 06/12/18: Re: Frequency divider?
113623: 06/12/18: Re: Frequency divider?
114285: 07/01/10: Re: crossing clock domain ??
114324: 07/01/11: Re: crossing clock domain ??
114508: 07/01/18: Re: Process on both edges
114607: 07/01/20: Re: How can I make xst to infer BlockRAM instead of Distributed RAM
114808: 07/01/24: Re: book recommendation for self study in digital logic design
114900: 07/01/26: Re: book recommendation for self study in digital logic design
115073: 07/01/30: Re: USB 2.0 Streaming using FPGAs
115786: 07/02/20: Re: configuring in slave serial mode with serial platform PROM
115998: 07/02/27: Re: spartan 3E USB port... use for i/o instead of programming
116197: 07/03/04: Re: Multiplication operation
116209: 07/03/05: Re: Multiplication operation
116210: 07/03/05: Re: Multiplication operation
116243: 07/03/05: Re: Multiplication operation
116349: 07/03/07: Re: Spartan3AN - Roadmap
116469: 07/03/09: Re: Spartan3AN - Roadmap
117449: 07/03/31: Re: Help with a face recognition system
117505: 07/04/02: Re: Help with a face recognition system
117740: 07/04/09: MGT Clocking
118359: 07/04/24: Problem with PowerPC PIT interrupt
118394: 07/04/25: Re: Problem with PowerPC PIT interrupt
118402: 07/04/26: Re: Problem with PowerPC PIT interrupt
118404: 07/04/26: Re: Problem with PowerPC PIT interrupt
118610: 07/05/01: Re: debounce state diagram FSM
119304: 07/05/16: Re: Mutiple MAC on OPB Bus
119563: 07/05/22: Re: JTAG FPGA Debugging
119767: 07/05/25: PC to JTAG
119776: 07/05/25: Re: PC to JTAG
119780: 07/05/25: Re: PC to JTAG
119784: 07/05/25: Re: PC to JTAG
119927: 07/05/29: Re: JTAG FPGA Debugging
120008: 07/05/31: Re: Building Gradually Expertise on VHDL/Verilog Design
120157: 07/06/02: Re: 180 differential inputs each 800Mbps using V5
120161: 07/06/02: Re: 180 differential inputs each 800Mbps using V5
121101: 07/06/25: Re: Xilinx FPGA: "after 10ns" constraint
121143: 07/06/26: Re: Xilinx ISE 9.1 - Version Control - VSS
121291: 07/06/30: Re: Xilinx programmer, many unknown devices...
121294: 07/06/30: Re: Xilinx programmer, many unknown devices...
121303: 07/07/01: Re: Question about xilinx programmer
121337: 07/07/03: Re: How to choose FPGA for a huge computation?
121424: 07/07/03: Re: How to choose FPGA for a huge computation?
121457: 07/07/04: Re: read/write in bram block
121611: 07/07/09: Synplify Problem
121616: 07/07/09: Re: Synplify Problem
121622: 07/07/10: Re: Synplify Problem
121623: 07/07/10: Re: Synplify Problem
121634: 07/07/10: Re: configuring vertex4 FPGA
121662: 07/07/11: Re: Virtex-II Pro Flip-Flop Setup time
121664: 07/07/11: Re: Type Conversion in VHDL
121691: 07/07/11: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
121734: 07/07/12: Re: ASM within C code in a PPC405 of VIRTEX II Pro
121767: 07/07/12: Re: Convert Schematic Files (.sch) to Verilog Files (.v) for simulation in ModelSim
121769: 07/07/12: Re: Synplify Problem
121898: 07/07/14: Re: ASM within C code in a PPC405 of VIRTEX II Pro
121957: 07/07/16: Re: Timing in Modelsim
121961: 07/07/16: Re: 1ms delay in V5 FPGA
122224: 07/07/24: Re: Corgen Adder Vs DSP48 Adder in Virtex4
122225: 07/07/24: Re: Arming the Chipscope Pro ILA
122229: 07/07/24: Re: 3 input adder in Spartan 3E
122234: 07/07/24: Re: 3 input adder in Spartan 3E
122254: 07/07/24: Re: Xint64 ?
122258: 07/07/24: Re: 3 input adder in Spartan 3E
122259: 07/07/24: Re: Altera or Xilinx
122662: 07/08/02: Re: Corgen Adder Vs DSP48 Adder in Virtex4
122706: 07/08/03: Re: V4FX PPC suspend/resume
122726: 07/08/05: Re: Confused about my behavioral simulation under ISE 9.1
122739: 07/08/05: Re: OpenSPARC
122740: 07/08/05: Re: bidirectional pin
122756: 07/08/06: Re: bidirectional pin
122769: 07/08/06: Re: Download the contents of the FPGA's RAM block
122772: 07/08/06: AREA_GROUP Map Error
122780: 07/08/06: Re: AREA_GROUP Map Error
122947: 07/08/12: Re: Amount of wire and logic
123323: 07/08/23: Re: Xilinx / ISE multi-cycle path constraint pitfall
123330: 07/08/23: Re: ROUTING=CLOSED in Xilinx 9.1 PR tools
124605: 07/09/28: Re: Never buy Altera!!!!
124641: 07/09/28: Re: Never buy Altera!!!!
124792: 07/10/04: Re: Companies that Manufacture Multi-FPGA Hardware
125049: 07/10/16: Re: FPGA quiz: what can be wrong
125052: 07/10/16: Re: FPGA quiz: what can be wrong
125708: 07/11/01: Re: can i use dual edge or two clocks?
126034: 07/11/13: Re: bidirectional in fpga
126146: 07/11/15: EDK 9.1 Issues
126151: 07/11/15: Re: EDK 9.1 Issues
126160: 07/11/15: Re: EDK 9.1 Issues
126161: 07/11/15: Re: EDK 9.1 Issues
126341: 07/11/20: 33+ Regs in PLB IPIF
126380: 07/11/20: Re: problem with adding custom logic to an IP core (xilinx edk)
126381: 07/11/20: Re: 33+ Regs in PLB IPIF
126528: 07/11/27: Re: scanf and printf in EDK's BSP
126531: 07/11/27: Re: scanf and printf in EDK's BSP
126584: 07/11/28: Re: 33+ Regs in PLB IPIF
126585: 07/11/28: Re: area group constraint problem
126921: 07/12/06: Re: converting verilog to vhdl
126993: 07/12/07: Re: virtex II pro - own core on plb with 2 interrupts
126994: 07/12/07: Re: usb cable driver
127106: 07/12/12: Re: Poor quality Xilinx boards ? Your experience ?
128971: 08/02/12: Re: ModelSim versus Active-HDL....redux
129013: 08/02/13: Re: Does PC-FPGA communication requires a driver?
131464: 08/04/22: Re: How to independently program the embedded PowerPC in a Virtex?
132064: 08/05/12: Re: Getting started with VHDL and Verilog
132746: 08/06/06: Re: Xilinx cuts 250 jobs.
132758: 08/06/06: Re: Xilinx cuts 250 jobs.
132805: 08/06/07: Re: Xilinx cuts 250 jobs.
132806: 08/06/07: Re: Xilinx cuts 250 jobs.
132810: 08/06/07: Re: Xilinx cuts 250 jobs.
133324: 08/06/24: Re: Configuration Management Best Practices
133363: 08/06/26: Re: PPC440 hangs after first interrupt
133364: 08/06/26: Re: Configuration Management Best Practices
133488: 08/07/01: Re: Type Casting in verilog
133489: 08/07/01: Re: EDK question
133490: 08/07/01: VHDL libraries
133495: 08/07/01: Re: VHDL libraries
133499: 08/07/01: Re: VHDL libraries
133534: 08/07/03: Re: EDK question
135201: 08/09/19: Re: WebPack on CentOS 5 ?
135236: 08/09/23: Re: duty cycle significance
135563: 08/10/08: MUX Inference
135572: 08/10/08: Re: MUX Inference
135675: 08/10/12: Re: Newbie attempt with ALU
135922: 08/10/22: Re: Entry Level FPGA Jobs and Outsourcing
137852: 09/02/01: Re: Heavily pipelined design
138061: 09/02/05: Re: dual processor PC for PPR - are they worth the extra cost?
138076: 09/02/05: Re: dual processor PC for PPR - are they worth the extra cost?
138390: 09/02/19: Re: VHDL long elsif state machine
138400: 09/02/19: Re: VHDL long elsif state machine
138402: 09/02/19: Re: generic parameterised coding:passing of parameters
139572: 09/04/04: Re: Maximum frequency
140597: 09/05/19: Re: Sigasi Public Beta: future of VHDL design
140640: 09/05/21: Re: Can we expect ISE Gui and makefile to produce identical bit files?
140984: 09/06/01: Re: Open Source FPGA circuit design.
141125: 09/06/07: Re: clock skew as an asset
141164: 09/06/10: Re: Xilinx Block RAM Sim
142597: 09/08/20: Re: Emulation of highly complex superscaler processor using FPGAs
143827: 09/10/28: Re: synplify question for FPGA
147133: 10/04/15: Re: I'd rather switch than fight!
Matthew J Myers:
4277: 96/10/09: 16x16 multiplier needer (Altera or VHDL)
Matthew John Duane:
57422: 03/06/30: Creating interface with NAND flash
Matthew Mahr:
42289: 02/04/19: Re: Source code for a NIOS instruction set simulator?
Matthew Marks:
377: 94/11/02: Re: about downloading FPGAs
1096: 95/04/27: Re: Need help about conference chip
1199: 95/05/12: Re: Overheating (was Re: Compression algo's for FPGA's)
2652: 96/01/19: GRRR!!! Xilinx Makebits defaults changing
Matthew Miller:
1949: 95/09/23: Re: Anyone using Altera 8820A ?
Matthew Morris:
8838: 98/01/31: Re: MAX+II Version 8.2
10462: 98/05/19: Re: Turbo bit in Altera 7000
10635: 98/06/08: Re: FPGA Conversion
10826: 98/06/23: Re: How to Double Clk Freq in the FPGA design
10834: 98/06/24: Re: How to Double Clk Freq in the FPGA design
10849: 98/06/25: Re: How to Double Clk Freq in the FPGA design
10850: 98/06/25: Re: How to Double Clk Freq in the FPGA design
11747: 98/09/07: Re: Altera 10K20 Register File Implementation??
13636: 98/12/15: Re: [Altera]Unrecognized Devices..
13637: 98/12/15: Re: Dedicated pin in ALTERA 10K familly
15210: 99/03/13: Re: Power Estimiation
Matthew Murphy:
13673: 98/12/17: Re: xilink Parallel cable III
14935: 99/02/25: Re: JTAG HANG UP......
Matthew Ouellette:
68917: 04/04/21: Re: OPB bus burst transfer support?
69208: 04/04/29: Re: EDK 3.2
69629: 04/05/16: Re: EDK6.1 MBlaze : problems with INTC IPIF and external interrupts
69667: 04/05/17: Re: EDK6.1 MBlaze : problems with INTC IPIF and external interrupts
70344: 04/06/13: Re: Microblaze asm and C shared variables
70525: 04/06/18: Re: TCP/IP in Virtex II Pro
73660: 04/09/27: Re: MicroBlaze & SRAM
76016: 04/11/22: Re: Xilinx OPB custom interface
76923: 04/12/15: Re: Xilinx Christmas present: EDK 6.3 !
77037: 04/12/20: Re: edk-chipscope 6.2 to 6.3 update
77202: 04/12/29: Re: (Q) interconnections between microblazes
Matthew P. Ouellette:
44605: 02/06/24: Re: Microblaze uart communication pb!!
Matthew Plante:
41768: 02/04/07: signal delay in altera 20KE
41772: 02/04/07: Re: signal delay in altera 20KE
76337: 04/11/30: block ram and bmm files
76383: 04/12/01: Re: clocks switch
76384: 04/12/01: Re: block ram and bmm files
87632: 05/07/27: bmm file and ramb16
87636: 05/07/27: Re: bmm file and ramb16
87660: 05/07/27: dual port ram
88742: 05/08/26: ISE 7.1 and DCM clkfx
88973: 05/09/01: FIFO PhysDesignRules:993
89182: 05/09/07: ISE 64bit question
89962: 05/09/30: Xilinx ISE 7.1i Portability Error
90143: 05/10/05: Re: Xilinx ISE 7.1i Portability Error
91038: 05/10/27: locking hdl to a particular fpga
Matthew R Henry,2274,4-2630:
657: 95/01/30: Seeking Info on LPM
Matthew Robinson:
11811: 98/09/10: Xilinx Spartan vs. 4K series
11884: 98/09/16: Xilinx Spartan and 4K speed grades
11998: 98/09/23: Viewlogic's EXPT1076 utility: problems
11999: 98/09/23: Re: Viewlogic's EXPT1076 utility: problems
12893: 98/11/03: Re: Xilinx bit file format question
Matthew S. Smith:
6521: 97/05/30: Re: NMEA and HW connection
Matthew S. Staben:
25109: 00/08/25: Re: Non-disclosures in job interviews, Round One
25191: 00/08/29: Re: Non-disclosures in job interviews, Round One
25243: 00/08/31: Re: Non-disclosures in job interviews, Round One
Matthew Warren:
52581: 03/02/14: Xilinx BRAM enable or wrote
<matthewlawrencecohen@yahoo.com>:
79105: 05/02/14: clock division / multiplication in xilinx cpld
Matthias:
36218: 01/11/02: Re: Implementing Filter
Matthias =?iso-8859-1?Q?M=FCller?=:
60818: 03/09/23: Location constraint
64265: 03/12/23: pcix core in XC2VP7
64338: 03/12/29: Re: pcix core in XC2VP7
64715: 04/01/12: pci-x core
65434: 04/01/29: pci-x core/ XC2VP/ pin capacitance
65781: 04/02/06: Rocket I/O receiver
67048: 04/03/04: DMA PCI-X core
67686: 04/03/17: pcix-core target memory write
67752: 04/03/18: Re: pcix-core target memory write
68315: 04/04/01: XC18V master parallel configuration
69055: 04/04/26: pcix core master dma
69396: 04/05/10: PCIX DMA Serverworks chipset
70015: 04/05/27: ise 6.2 lvdci_33
71005: 04/07/05: Re: PCI-X DMA problem w/ Xeon?
Matthias Alles:
78164: 05/01/25: Generic External Memory Controller for OPB
78652: 05/02/04: Multi-Master problem with OPB
78679: 05/02/05: OPB ZBT
79303: 05/02/17: Re: VGA core
81395: 05/03/22: OPB component for serial Flash?
81672: 05/03/29: Re: hook up SRAM to Spartan3
81723: 05/03/30: Re: hook up SRAM to Spartan3
81724: 05/03/30: Re: hook up SRAM to Spartan3
81728: 05/03/30: Re: Read Data from BlockRAM
97745: 06/02/27: Serious problem with XST
97835: 06/02/28: Re: Serious problem with XST
111787: 06/11/10: add-compare-select
115104: 07/01/31: Re: Graphics demo using FPGA?
123008: 07/08/14: xst fails...
123013: 07/08/14: Re: xst fails...
123014: 07/08/14: Re: xst fails...
123047: 07/08/15: Re: xst fails...
131938: 08/05/08: Re: ps2 mouse protocol
133316: 08/06/24: PPC440 hangs after first interrupt
133333: 08/06/25: Re: PPC440 hangs after first interrupt
133335: 08/06/25: Re: PPC440 hangs after first interrupt
133372: 08/06/26: Re: PPC440 hangs after first interrupt
133765: 08/07/14: Re: ps2 mouse initialization fails
133859: 08/07/17: Re: ps2 mouse initialization fails
133873: 08/07/18: Re: free of bugs
134096: 08/07/25: floating point alignment issues with xilkernel
134098: 08/07/25: Re: double precision floating point alignment issues with xilkernel
134214: 08/07/31: Re: double precision floating point alignment issues with xilkernel
134709: 08/08/27: Genode FPGA graphics project launched
134924: 08/09/07: Re: Genode FX on PPC
136195: 08/11/05: Re: Xilinx TFT controller
136605: 08/11/25: Re: timer interrupt problem: microblaze
136888: 08/12/11: Re: Xilinx ISE 10.1 SP3 MPMC NPI VHDL simple sample needed
137304: 09/01/08: Re: interrupt cannot return
137431: 09/01/16: Re: Actel IGLOO FPGA has lower power consumption then Xilinx Coolrunner-II
137554: 09/01/22: Re: ML505 - How to read/write SRAM?
137812: 09/01/30: Re: XPS PS2 INTERFACE - ML505 and EDK 10.1
140409: 09/05/13: Achronix' asynchronous FPGAs
140410: 09/05/13: Re: Achronix' asynchronous FPGAs
141962: 09/07/20: Re: How do you handle build variants in VHDL?
142665: 09/08/25: Re: Why there is multi-source error in these VHDL code?
153080: 11/11/28: Re: XC7V2000T, the perfect Thanksgiving gift
Matthias Braeunig:
76154: 04/11/26: Quartus Debian Install
Matthias Brucke:
12142: 98/10/01: Re: Fastest Add
14522: 99/02/03: Re: FPGA Express Evaluation...
14667: 99/02/10: Re: Board for XC4085XL
14946: 99/02/26: pipelined multipliers for behavioral synthesis (->XC4062XL)
20609: 00/02/16: Re: coregen-bug produces bad blockram > 16 bit
20708: 00/02/18: Re: coregen-bug produces bad blockram > 16 bit
Matthias Colsman:
17835: 99/09/09: Re: xilinx software
Matthias D. Kistler:
14555: 99/02/04: DES in VHDL for FPGAs
Matthias Dyer:
38270: 02/01/10: Avoid routing through a certain area (Xilinx)
43485: 02/05/22: Re: fpga cpu
48217: 02/10/14: low power embedded FPGA
50336: 02/12/09: virtex output pin voltage
56995: 03/06/20: User Core OPB Problem (EDK3.2)
57073: 03/06/23: Re: ModelSim 5.7 and xilinx libraries
Matthias Einwag:
117544: 07/04/03: Looking for Memory Recommendation for Spartan 3E 1200
117607: 07/04/04: Re: Looking for Memory Recommendation for Spartan 3E 1200
117608: 07/04/04: Re: Looking for Memory Recommendation for Spartan 3E 1200
119315: 07/05/16: Re: downto usage in EDK
Matthias Fuchs:
17098: 99/06/30: Re: More help with Foundation
17100: 99/06/30: xilinx Foundation map-warning
17101: 99/06/30: foundation F1.5i warning:
18396: 99/10/22: xilinx foundation: bit_gen warning becasue of pullUps
18471: 99/10/26: Re: Announcing Free VHDL Simulator for Windows
18862: 99/11/19: who to reset one-hot-fsm ?
24877: 00/08/21: power consumption for spartan xcs05(XL)
29324: 01/02/14: Duplicate definitions for timing specs (xilinx fnd)
29618: 01/03/01: throughput of SDRAM controller - xilinx appnote 134
30179: 01/03/27: Xilinx Core generator with WebPack ISE
30213: 01/03/28: problem when printing from Xilinx FPGA editor
31093: 01/05/11: SpartanII: non clock pad drives clock net ?
31797: 01/06/06: problem: bahavior simulation of xilinx's coregen cores
31810: 01/06/06: Re: problem: bahavior simulation of xilinx's coregen cores
31876: 01/06/07: Force tristate enable register into IOB
32017: 01/06/11: Re: Force tristate enable register into IOB
32026: 01/06/11: Re: Force tristate enable register into IOB
32053: 01/06/12: Re: Force tristate enable register into IOB
32059: 01/06/12: Re: Force tristate enable register into IOB
32106: 01/06/14: Floppy-Disc-Controller core ?
32289: 01/06/22: Re: Xilinx Software free
34095: 01/08/14: constaining dll stuff problem
34248: 01/08/17: Re: Internal clock skew when using DLL
34901: 01/09/13: configuration latency for PCI bridge in FPGA
35255: 01/09/27: Programming flash connected to CPLD via JTAG
35306: 01/09/28: Re: Programming flash connected to CPLD via JTAG
35446: 01/10/05: Re: CoreGenerator and WebPack ISE
Matthias Koch:
159039: 16/06/22: Re: J1 forth processor in FPGA - possibility of interactive work?
Matthias Monhart:
15815: 99/04/15: flex10K with USB
16013: 99/04/28: Re: Double Port ram for Altera EPF10K20
16336: 99/05/17: Re: Fancy Dram problem
Matthias Neuroth:
44790: 02/07/01: Re: Xpower accuracy (is there anybody from Xilinx out there ?)
Matthias Sauer:
6334: 97/05/16: Re: Scientific American article on FPGAs
8014: 97/11/07: Re: I'm interested in FPGAs. How do I start ?
10011: 98/04/22: Re: C++, C, Java to hardware compiler
12998: 98/11/10: Re: FPGA VGA interface
14502: 99/02/02: Re: C to Hardware translators [was: The development of a free FPGA synthesis tool]
Matthias Scheerer:
38264: 02/01/10: XST in ISE Alliance 4.1 for Solaris
38267: 02/01/10: Re: XST in ISE Alliance 4.1 for Solaris
40017: 02/02/25: Re: PCI/FPGA evaluation board
40139: 02/02/28: PCI book ... still confused
40166: 02/03/01: Re: PCI book ... still confused
40395: 02/03/06: Re: Block Ram
Matthias Weber:
38036: 02/01/02: asic vs. fpga
38109: 02/01/05: full custom design
38178: 02/01/08: latch vs. register
38179: 02/01/08: Xilinx XC2000, XC3000, XC4000 families
38216: 02/01/09: distributed ram bits in XCVxxxx series
38217: 02/01/09: function generators of Xilinx XCVxxxxE series
Matthias Weingart:
7413: 97/09/08: Re: Binary to Intel Hex
31094: 01/05/11: How to program a mach 4? How to get a chain file?
31208: 01/05/15: Re: Quad Decoder
41332: 02/03/26: Re: I2C Slave sampling edge
Matthias Wenzel:
40317: 02/03/05: Array case expression must have a static subtype (VHDL)
matthias werner:
11435: 98/08/13: ADPCM G.726 encoder/decoder
<matthias.meurer@corrsys-datron.com>:
138493: 09/02/24: Re: XST hangs on HDL Analysis
<matthias.ruemmele@googlemail.com>:
138538: 09/02/26: Re: Frame ECC and Virtex-4
Matthieu:
121334: 07/07/03: Re: Xilinx ISE + Multi CPU setup?
122509: 07/07/30: Re: Best CPU platform(s) for FPGA synthesis
125032: 07/10/16: Re: FPGA quiz: what can be wrong
125058: 07/10/16: Re: FPGA quiz: what can be wrong
125065: 07/10/16: Re: FPGA quiz: what can be wrong
125092: 07/10/16: Re: FPGA quiz: what can be wrong
126131: 07/11/15: Re: Xilinx Encrypted bit file
142939: 09/09/09: Re: ANN: Coding style guidance for FPGA memory
Matthieu Benoit:
69134: 04/04/28: Altera EP320 to PAL16V8
69379: 04/05/09: Altera EPM7032LC44 programming w/ ALL-03A Hilo
Matthieu Cattin:
105950: 06/08/03: Xilinx ISE 8.2 implementation problem
114271: 07/01/10: crossing clock domain ??
114272: 07/01/10: P160 analog module ?
114276: 07/01/10: Re: crossing clock domain ??
114357: 07/01/12: FIFO LogiCore with ISE 8.2 ??
Matthieu Cossoul:
32045: 01/06/11: Re: Xilinx PCI core location constraints
Matthieu LIGER:
18327: 99/10/15: Re: compiling vhdl code(help please)
Matthieu Liger:
19263: 99/12/09: Passing attributes from VHDL with FPGA Express for Xilinx
Matthieu Michon:
86255: 05/06/23: Re: ISE 7.1 - block memory init value issue during simulation
89268: 05/09/09: Re: Disconnect the FPGA I/O pads from the outside world
91357: 05/11/04: Re: use ppc405 on virtex-II pro
144668: 09/12/22: Re: Please help, Xilinx FIFO problem!
Matthieu MICHON:
84693: 05/05/24: Re: more and more and more issues with Xilinx tools
85711: 05/06/14: Re: never seen XST error
85842: 05/06/16: Re: LUT, how to?
Matti Dun:
149549: 10/11/04: SVGA Controller on FPGA
149565: 10/11/05: Re: SVGA Controller on FPGA
Matti Ruusunen:
30405: 01/04/06: Why FPGA/CPLDs draw a lot current?
30425: 01/04/07: Re: Why FPGA/CPLDs draw a lot current?
38856: 02/01/26: Re: MSP430 + Xilinx via JTAG
38881: 02/01/27: Re: MSP430 + Xilinx via JTAG
Mattias Onils:
2447: 95/12/06: Problems with Autologic using Altera FPGA...
Matz:
41059: 02/03/20: Re: FPGA or Micro-controller in Lowpower designs?
Maurice:
22255: 00/05/03: Bidirectional bus
22424: 00/05/09: Re: Programming FPGA
Maurice Branson:
121744: 07/07/12: highly-parallel highspeed connection between two FPGA boards
121785: 07/07/13: Re: highly-parallel highspeed connection between two FPGA boards
146090: 10/03/05: Display Control Application Using Spartan FPGA
146656: 10/03/25: USB 3.0 implementation on FPGA
146658: 10/03/25: Re: USB 3.0 implementation on FPGA
146696: 10/03/26: Re: USB 3.0 implementation on FPGA
Maurice Moore:
2413: 95/12/02: Re: PC VHDL synth for FPGA?
Mauricio Lange:
43172: 02/05/15: PCI Board Project
43205: 02/05/16: Re: PCI Board Project
43232: 02/05/16: PCI target with FPGA question
44074: 02/06/11: Asynchronous Perhiperal Mode
44126: 02/06/12: Re: Asynchronous Perhiperal Mode
46030: 02/08/14: XC4010 losses configuration
46907: 02/09/11: Clocking an FPGA with the PCI clock
47035: 02/09/15: Re: Clocking an FPGA with the PCI clock
51936: 03/01/26: Re: New to FPGA world...need guidline/help
51992: 03/01/28: PCI protocol - assigning an address to my device
52023: 03/01/28: Re: PCI protocol - assigning an address to my device
52035: 03/01/29: Re: PCI protocol - assigning an address to my device
52107: 03/01/31: LogiBLOX behavior
52187: 03/02/03: Re: PCI protocol - assigning an address to my device
52320: 03/02/06: Re: difference between pci2.1 and pci2.2
69088: 04/04/26: Looking for XC4010XL-09
Maurizio Lippi:
1899: 95/09/18: palce16v8hd obsolescence
Maurizio Stefani:
45768: 02/08/05: ATMEL GAL
<maurizio.gencarelli@dsto.defence.gov.au>:
116656: 07/03/14: SEC:U Problem getting rid of bit latch errors
maurizio.tranchero:
144152: 09/11/14: Re: An incomplete Mux and Latch?
144707: 09/12/26: Re: More details: VHDL: assignment to two different fields of the
145095: 10/01/27: Re: Achronix FPGA
145112: 10/01/28: Re: Achronix FPGA
146989: 10/04/08: Re: VHDL coding
149560: 10/11/05: Re: combinatorial process not simulating correctly
149562: 10/11/05: Re: combinatorial process not simulating correctly
150176: 10/12/26: Re: some VHDL error
150190: 10/12/30: Re: some VHDL error
Mauro Cerisola:
293: 94/10/13: Re: PALASM versions?
937: 95/03/31: Re: Excuse me while I vent about Data I/O & Abel...
Mauro Fiorini:
5876: 97/03/21: problem: my xc4003 don't work !!!!
53710: 03/03/20: programmer adapter for Xilinx XC9572
53883: 03/03/26: Virtex board schematics
Mauro Olivieri:
7059: 97/07/28: information on RIPP10
Mauro Pintus:
48616: 02/10/22: FPGA XC4005E
48761: 02/10/24: Re: FPGA XC4005E
mav1101:
108927: 06/09/19: Using a global clock as a flip-flop enable?
Maverick:
120536: 07/06/08: Re: LVPECL output skew
120845: 07/06/18: .xco file and vcs verilog compiler
maverick:
118378: 07/04/25: Using OPB PCI In EDK 8.1
119854: 07/05/28: accesing JTAG ports on GPIOs
119905: 07/05/29: Re: accesing JTAG ports on GPIOs
119974: 07/05/30: Re: accesing JTAG ports on GPIOs
120083: 07/05/31: Re: accesing JTAG ports on GPIOs
120096: 07/05/31: Re: accesing JTAG ports on GPIOs
120098: 07/05/31: Re: accesing JTAG ports on GPIOs
127444: 07/12/26: Spartan 3 FPGA verification via readback
127903: 08/01/10: Multiple UCF support in Xilinx ISE
128683: 08/02/03: Bitstream verification through readback
128831: 08/02/07: Marking Flase paths for Timing Ignore + Virtex 2 Pro support
129425: 08/02/23: FPGA Editor Tutorial based on examples
129772: 08/03/05: PCI Timing Contraints ignored
129815: 08/03/05: Re: PCI Timing Contraints ignored
130603: 08/03/27: FPGA board with an ADC
130836: 08/04/03: Protecting design from being downloaded on other (similar) FPGA
130880: 08/04/04: Re: Protecting design from being downloaded on other (similar) FPGA
131978: 08/05/09: 5 V oscillator output to GCLK
135541: 08/10/06: Looking for an FPGA board with large memory and high speed interfaces
135545: 08/10/07: Re: Looking for an FPGA board with large memory and high speed
137485: 09/01/20: Digilent USB Cable supported Devices
141966: 09/07/20: Strange FPGA behavior
142018: 09/07/22: Re: Strange FPGA behavior
147464: 10/04/27: Re: Fpga Board detection on INTEL motherboard S5000XVN and S3210SHLC
148772: 10/08/20: Analog Video Processing module
153014: 11/11/14: Looking for a decent FPGA board with multiple Xilinx Virtex 5 FPGAs
153028: 11/11/17: Re: Looking for a decent FPGA board with multiple Xilinx Virtex 5 FPGAs
154094: 12/08/03: 64-bit kernel mode driver for Avnet Virtex 5 LX110T PCIe development board
156882: 14/07/15: vmWare supporting Avnet Virtex-5 PCIe board
<Mavin>:
6891: 97/07/06: Metrics
Mavrick:
120452: 07/06/07: Lattce SC Purspeed I/O
120453: 07/06/07: Re: How many OSERDES per bufio
120481: 07/06/07: LVPECL output skew
120487: 07/06/07: Re: LVPECL output skew
120493: 07/06/07: Re: LVPECL output skew
120514: 07/06/08: Re: LVPECL output skew
120622: 07/06/12: Re: LVPECL output skew
Mawa_fugo:
140155: 09/04/30: Xilinx ground pin
143751: 09/10/23: ISe 10.1 nightmare bug
143763: 09/10/24: Re: ISe 10.1 nightmare bug
143796: 09/10/26: Re: ISe 10.1 nightmare bug
143798: 09/10/26: Re: ISe 10.1 nightmare bug
144144: 09/11/13: Re: OK Xilinx users, it's time I was let in on the joke...
146477: 10/03/19: Update init data in dualport BRAM without re-run anything?
146479: 10/03/19: Re: Update init data in dualport BRAM without re-run anything?
146489: 10/03/19: Re: Update init data in dualport BRAM without re-run anything?
146499: 10/03/20: Re: Update init data in dualport BRAM without re-run anything?
146505: 10/03/21: Re: Finally, selling my old Xilinx/Viewlogic software package
146592: 10/03/23: Re: Update init data in dualport BRAM without re-run anything?
146600: 10/03/23: Re: Update init data in dualport BRAM without re-run anything?
147004: 10/04/09: Spartan-3 dsp FG676 Vccint decoupling caps
147007: 10/04/09: Re: Spartan-3 dsp FG676 Vccint decoupling caps
147015: 10/04/09: Re: Spartan-3 dsp FG676 Vccint decoupling caps
147181: 10/04/16: Changing output pins slew&drive strength without re-run ISE
147680: 10/05/14: Altra mega core SDI vs. Gennum devices
149493: 10/10/29: Re: Designing for Xilinx Spartan in 2010?
149494: 10/10/29: Re: JTAG stops working!
150369: 11/01/12: Re: Transfer data from one clock domain to another clock created by
150370: 11/01/12: Re: Xilinx support makes me want to scream
150371: 11/01/12: Re: Xilinx support makes me want to scream
150372: 11/01/12: Re: spartan 3 xc3s1000 not getting programmed
151665: 11/05/03: Re: about slices in xilinx
151851: 11/05/24: Re: Why feedback clock in SDRAM controllers?
152100: 11/07/06: Spartan3DSP TphDCM spec question
152108: 11/07/07: Re: Spartan3DSP TphDCM spec question
152113: 11/07/08: Re: Spartan3DSP TphDCM spec question
152114: 11/07/08: Re: Spartan3DSP TphDCM spec question
152215: 11/07/21: Re: source synchronous DDR bus with non-continuous clock
152265: 11/07/29: DVI-decoder clock question
152388: 11/08/17: Re: DVI-decoder clock question
152461: 11/08/26: Re: What is the advantage of source-syncronization (in SDRAMs)?
152519: 11/08/30: Re: What is the advantage of source-syncronization (in SDRAMs)?
152525: 11/09/02: Re: What is the advantage of source-syncronization (in SDRAMs)?
152783: 11/10/21: Re: Peter Alfke has passed away
152817: 11/10/25: Re: Peter Alfke has passed away
153169: 11/12/27: This comp.arch.fpga group is suck - I'm leaving now
153170: 11/12/28: Re: This comp.arch.fpga group is suck - I'm leaving now
153250: 12/01/18: Re: balancing IIR filter (after adding extra registers)
153583: 12/04/02: Re: Could you explain these speed spec to me?
153623: 12/04/05: Re: Very poor Xilinx experience
153668: 12/04/11: Re: strange letter from Xilinx
153869: 12/06/15: Re: FPGA FIFO MAX data speed
155948: 13/10/19: Re: draw lines, circles, squares on FPGA by mouse and display on VGA
155968: 13/10/30: Re: draw lines, circles, squares on FPGA by mouse and display on VGA
Mawafugo:
139116: 09/03/21: DVI in FPGA
<mawais2011@namal.edu.pk>:
157600: 14/12/26: Prime number in verilog
MAx:
129282: 08/02/20: scanf problem in EDk 9.1i (Microbaze)
129328: 08/02/20: Re: scanf problem in EDk 9.1i (Microbaze)
129448: 08/02/24: Re: scanf problem in EDk 9.1i (Microbaze)
max:
52306: 03/02/06: Max+PlusII: Design Doctor: synchronized by another clock
52445: 03/02/10: Re: Max+PlusII: Design Doctor: synchronized by another clock:Counter
59050: 03/08/07: Xilinx ISE WebPack 5.2 & VHDL : wait synthesis
143429: 09/10/11: floating point operation in interrupt handler on ML403
143457: 09/10/12: Re: floating point operation in interrupt handler on ML403
147237: 10/04/20: Developin tool for Xilinx XC2018
Max:
21356: 00/03/18: Actel fpgas
60535: 03/09/16: back-annotate pin location with xilinx webpack 5.2
60988: 03/09/26: pullup on inputs
61203: 03/09/30: Re: pullup on inputs
64730: 04/01/12: IOB costraints
64731: 04/01/12: to generate steps in phase
66881: 04/02/28: Re: Dual-stack (Forth) processors
66884: 04/02/28: Re: Dual-stack (Forth) processors
66894: 04/02/29: Re: OT Re: Dual-stack (Forth) processors
66895: 04/02/29: Re: Dual-stack (Forth) processors
66904: 04/02/29: Re: difference btw H/W & S/W implementations !!
66965: 04/03/02: Re: OT Re: Dual-stack (Forth) processors
66976: 04/03/02: Re: Need to speed up Stratix compiles.
67005: 04/03/03: Re: Need to speed up Stratix compiles.
67006: 04/03/03: Re: Need to speed up Stratix compiles.
67011: 04/03/03: Re: Need to speed up Stratix compiles.
67013: 04/03/03: Re: Need to speed up Stratix compiles.
67020: 04/03/03: Re: Need to speed up Stratix compiles.
67054: 04/03/04: Re: Need to speed up Stratix compiles.
67057: 04/03/04: Re: Dongle compatibility
67060: 04/03/04: Re: mersenne twister
67081: 04/03/05: Re: Need to speed up Stratix compiles.
67082: 04/03/05: Re: mersenne twister
67088: 04/03/05: Re: mersenne twister
67093: 04/03/05: Re: mersenne twister
67125: 04/03/06: Re: mersenne twister
67144: 04/03/06: Re: mersenne twister
67171: 04/03/08: Re: Delay on Virtex-II IOB input FF
67403: 04/03/11: Re: Oftenly used hardware algorithm for RC4 encryption?
67445: 04/03/12: Re: Oftenly used hardware algorithm for RC4 encryption?
86992: 05/07/12: Xilinx Conversion 3.1 --> 6.1
87008: 05/07/12: Re: Xilinx Conversion 3.1 --> 6.1
136299: 08/11/10: Silicon used for realising FPGA logic
Max Baker:
109176: 06/09/21: Re: Xilinx - no secret, you are not to use the PMV primitive
124081: 07/09/11: Re: V5 Configuration via SPI
Max Edmand:
41484: 02/03/29: pipelined correlation block on Virtex2000?
41582: 02/04/02: Simulator for xilinx Cores?
41699: 02/04/04: Re: Simulator for xilinx Cores?
41920: 02/04/10: Built in multipliers in Virtex 2000E?
42005: 02/04/12: "Creat RPM" in Core Generator?
Max K.:
49306: 02/11/08: functional test for Xilinx virtex II Pro
49308: 02/11/08: Re: functional test for Xilinx virtex II Pro
Max Khusid:
52284: 03/02/05: Re: top colleges in VLSI Design education
Max L.:
29403: 01/02/19: Infering DPRAM with both outputs
"Max Larine":
1399: 95/06/15: AT&T serial eproms
<max.giacometti@libero.it>:
102687: 06/05/19: Ethernet & ML401
102691: 06/05/19: Re: Ethernet & ML401
102702: 06/05/19: Use USB ports on ML401
102728: 06/05/19: Re: Ethernet & ML401
102737: 06/05/19: Re: Ethernet & ML401
<max@maxpages.com>:
7843: 97/10/22: FREE Web Site
max_mont:
101654: 06/05/04: EPLD Lattice Prog Problem
maxascent:
94403: 06/01/11: Samples
96829: 06/02/11: LVDS
96844: 06/02/11: Re: LVDS
97167: 06/02/17: equivalent time sampling
97187: 06/02/18: Re: equivalent time sampling
97207: 06/02/18: Re: equivalent time sampling
97239: 06/02/19: Re: equivalent time sampling
97615: 06/02/24: FPGA Selection Question
97682: 06/02/26: Re: FPGA Selection Question
97821: 06/02/28: Xilinx MIG
98035: 06/03/03: Xilinx Coregen
98385: 06/03/09: DDR for Spartan 3
98623: 06/03/13: Re: Xilinx DDR SDRAM Controller
98662: 06/03/14: Spartan 3 DCM
98675: 06/03/14: Re: Spartan 3 DCM
98721: 06/03/15: Re: Spartan 3 DCM
98761: 06/03/16: ADC Interleaving
98768: 06/03/16: Re: ADC Interleaving
99098: 06/03/20: DDS
99112: 06/03/20: Re: DDS
99127: 06/03/20: Re: DDS
99275: 06/03/22: Lattice FPGA
99847: 06/03/30: PCB Bypass Caps
99970: 06/03/31: Virtex II Pro
100008: 06/04/01: Re: PCB Bypass Caps
100409: 06/04/08: DDR Termination
100604: 06/04/13: PCB Stack
100607: 06/04/13: Re: PCB Stack
100640: 06/04/14: Re: PCB Stack
100719: 06/04/17: Virtex II Pro Config
101382: 06/04/30: Xilinx PROM
105747: 06/07/31: Core Generator
105878: 06/08/02: Chipscope
105996: 06/08/04: Re: Chipscope
105997: 06/08/04: Synplify
106964: 06/08/23: Modelsim
106971: 06/08/23: Re: Modelsim
106990: 06/08/23: Timing
108685: 06/09/15: net skew
109759: 06/10/05: EDIF
110854: 06/10/24: Memory
111134: 06/10/30: Dual Port RAM
111336: 06/11/01: Re: Interface standards (was Re: Dual Port RAM)
111746: 06/11/09: ZBT Bus
112499: 06/11/23: Xilinx EDK Problem
114328: 07/01/11: arbitrator
120255: 07/06/04: MGT Clock
120301: 07/06/05: Choosing a clock
120670: 07/06/13: Virtex 4 Config
120740: 07/06/15: Re: Virtex 4 Config
120779: 07/06/16: Re: Virtex 4 Config
121207: 07/06/28: ISE 9.1 Problem
121914: 07/07/15: QDR II SRAM Interface
123027: 07/08/14: SDRAM Controller
123110: 07/08/16: MGT Link
123146: 07/08/17: Re: MGT Link
123318: 07/08/23: ML365
123443: 07/08/28: PCB Layers
123457: 07/08/28: Re: PCB Layers
123569: 07/08/30: PCB Impedance Control
123681: 07/09/01: Re: PCB Layers
124778: 07/10/04: Re: Companies that Manufacture Multi-FPGA Hardware
125101: 07/10/16: FPGA to FPGA Bus
125776: 07/11/04: DDR2 Interface
125898: 07/11/08: Spartan 3E config
127525: 08/01/01: Split Plane
128537: 08/01/30: Xilinx PAR problem when using chipscope
128541: 08/01/30: Re: Xilinx PAR problem when using chipscope
129129: 08/02/15: Virtex 4 package layout
129190: 08/02/18: Re: Virtex 4 package layout
129193: 08/02/18: Re: Virtex 4 package layout
129250: 08/02/19: Re: Virtex 4 package layout
135174: 08/09/19: usb on a spartan
135259: 08/09/23: Xilinx Mode Select Pins
136031: 08/10/28: system verilog state machine
136118: 08/11/02: Re: system verilog state machine
138761: 09/03/09: FPGA IO Routing
138770: 09/03/09: Re: FPGA IO Routing
138909: 09/03/14: Virtex 5 LVDS
138922: 09/03/14: Re: Virtex 5 LVDS
138932: 09/03/15: Re: Virtex 5 LVDS
138935: 09/03/15: Re: Virtex 5 LVDS
139628: 09/04/07: Re: Xilinx user constraints with respect to output clock from the design
139657: 09/04/08: Re: Xilinx user constraints with respect to output clock from the design
139660: 09/04/08: Re: xilinx edk issues
139699: 09/04/09: Re: How to insert Chipscope blocks directly in Xilinx Project Navigator
140505: 09/05/15: Virtex 5 clocking
140513: 09/05/15: Re: Virtex 5 clocking
140535: 09/05/16: Re: Virtex 5 clocking
141048: 09/06/03: Secure netlist
141056: 09/06/04: Re: Secure netlist
141135: 09/06/08: ISE 11.1
141136: 09/06/08: Xilinx Block RAM Sim
141141: 09/06/08: Re: Xilinx Block RAM Sim
141143: 09/06/08: Re: Xilinx Block RAM Sim
141158: 09/06/09: Re: ISE 11.1
141159: 09/06/09: Re: Xilinx Block RAM Sim
141170: 09/06/10: Re: Xilinx Block RAM Sim
141566: 09/06/28: Re: Virtex 5 Block Ram usage with Coregen FIFO
141567: 09/06/28: Re: Xilinx USB CABLE SCHEMATIC NOW OFFICIALLY PUBLISED !!!! ::) yippii ?yee
141677: 09/07/03: OVM compilation problem
141679: 09/07/03: Re: OVM compilation problem
141861: 09/07/14: Re: How to initialize a Rom with a list of coefficients
141887: 09/07/15: Re: How to initialize a Rom with a list of coefficients
142288: 09/08/02: Re: [newbie] Verilog test bench with automatic verification
142301: 09/08/03: Re: [newbie] Verilog test bench with automatic verification
142308: 09/08/03: Re: ucf and clock pin placement on Spartan 3E?
142434: 09/08/11: Re: DDR2 Controllers: Bursting to Odd Addresses
142545: 09/08/16: Virtex 4 package code
142627: 09/08/22: Virtex 5 config Virtex 4
142755: 09/08/30: Virtex 5 HDMI
142766: 09/08/31: Re: Virtex 5 HDMI
143021: 09/09/15: Re: To Xilinx: Regarding the download manager
143024: 09/09/15: Re: To Xilinx: Regarding the download manager
143105: 09/09/21: Re: Memory Interface Generator
143635: 09/10/19: Re: How to inspect values in a Xilinx core FIFO with Modelsim?
143662: 09/10/20: Re: Spartan-3A DSP and include a Digital Clock Manager (DCM_SP) - How to do it?
143769: 09/10/24: Virtex 5 I/O
143832: 09/10/28: Chipscope with Verilog
143876: 09/10/31: Re: Chipscope with Verilog
143880: 09/10/31: Re: Chipscope with Verilog
144175: 09/11/17: Re: Error:Place:645 on a non-clock pin.
144246: 09/11/23: Virtex 5 ISERDES
144247: 09/11/23: Re: Virtex 5 ISERDES
144274: 09/11/24: Re: Virtex 5 ISERDES
144395: 09/12/03: Re: Does Xilinx sync FIFO use dual port memory? Does this affect resource?
144417: 09/12/05: Re: BRAM usage in synplify pro
144615: 09/12/21: Re: Please help, Xilinx FIFO problem!
144617: 09/12/21: Re: Please help, Xilinx FIFO problem!
144622: 09/12/21: Re: Please help, Xilinx FIFO problem!
144626: 09/12/21: Re: Please help, Xilinx FIFO problem!
144627: 09/12/21: Re: Please help, Xilinx FIFO problem!
144768: 10/01/01: verilog multiplexer
144770: 10/01/01: Re: verilog multiplexer
144779: 10/01/02: Re: verilog multiplexer
144924: 10/01/15: Re: SystemVerilog Verification Example using Quartus and ModelSim
145603: 10/02/15: Re: Repost on 10 layer stack for 1152 pin BGA.
145628: 10/02/16: Re: EDK 11,1 on Windows 7, 32 Bit
145669: 10/02/18: Re: Derived clock violation in Virtex4
145688: 10/02/18: Re: Derived clock violation in Virtex4
145694: 10/02/19: Re: Derived clock violation in Virtex4
145899: 10/02/27: Re: Place and Route
146010: 10/03/03: Re: Xilinx IOBUF - operation Q (virtex4 chip)
146507: 10/03/21: Virtex 5 GTP
146508: 10/03/21: Virtex 5 GTP
146933: 10/04/02: Microblaze and DDR2
147042: 10/04/11: Microblaze Reset
147080: 10/04/13: EDK BFM Simulation
147095: 10/04/14: Re: EDK BFM Simulation
147190: 10/04/17: Microblaze and DDR2
147198: 10/04/17: Re: Microblaze and DDR2
147402: 10/04/26: data2mem
147534: 10/04/30: Synplify constraint problem
147544: 10/05/01: Re: Synplify constraint problem
147551: 10/05/01: Re: Synplify constraint problem
147640: 10/05/11: Re: Two PCIe Endpoints in one Virtex-6?
147697: 10/05/17: Re: using ChipScope to debug external design
147757: 10/05/22: Re: Debugging SDRAM interfaces
147933: 10/06/03: Re: Spartan-6 hold time problems (multipost to Xilinx forums)
147985: 10/06/10: Re: Design passes synthesis and routing but fails on FPGA
147987: 10/06/10: Re: Design passes synthesis and routing but fails on FPGA
147999: 10/06/11: Re: how to interface a ddr2 memory controller to a processor
148004: 10/06/11: Re: Is it possible to get consistent implementation results?
148008: 10/06/12: Re: Is it possible to get consistent implementation results?
148173: 10/06/25: Re: fooling the compiler
148217: 10/06/30: Testbench
148244: 10/07/01: Re: DMA operation to 64-bits PC platform
148251: 10/07/02: Re: Xilinx xapp175, empty + full flag really synchronous?
148256: 10/07/02: Re: PN crashing (64 bit)
148288: 10/07/05: Re: Difference between DDR and DDR2
148289: 10/07/05: Re: xilinx leadtimes
148359: 10/07/15: Re: Another Xilinx webpack download rant
148433: 10/07/22: Re: Xilinx Plan Ahead question
148518: 10/07/29: Re: SDRAM AutoPrecharge and Refresh
148649: 10/08/12: Re: Spartan3a: improving DCM performance and
148835: 10/09/01: Re: Xilinx Series 7 device availability
148851: 10/09/03: Re: Xilinx Series 7 device availability
149112: 10/10/02: Re: External Circuit to FPGA.
149114: 10/10/02: Re: External Circuit to FPGA.
149295: 10/10/14: LVDS simulation in Hyperlynx
149332: 10/10/17: Re: Project including MIG core problems with Chipscope
149357: 10/10/18: Re: IO pin question
149364: 10/10/19: Re: IO pin question
149374: 10/10/20: Re: IO pin question
149433: 10/10/25: Virtex 5 GTP Clocking
149434: 10/10/25: Re: Using LVPECL_25 inputs in Spartan3e problem
149437: 10/10/25: Re: Virtex 5 GTP Clocking
149443: 10/10/25: Re: Using LVPECL_25 inputs in Spartan3e problem
149485: 10/10/29: Virtex 5 GTP Simulation
149487: 10/10/29: Re: Virtex 5 GTP Simulation
149504: 10/11/01: Re: Timing error for EDK project using a DCM?
149520: 10/11/02: Re: Timing error for EDK project using a DCM?
149663: 10/11/15: Re: Cypres PSoC devices - hdl entry for digital sections?
149689: 10/11/17: Re: Signal is connected to multiple drivers
149747: 10/11/22: Re: minimum clock period of a combinational circuit
149849: 10/11/28: Re: 1653 - At least one timing constraint is impossible to meet
149872: 10/11/30: Re: PCI Architecture Question for Data Acquisition Board
150007: 10/12/06: Linux on Microblaze
150018: 10/12/06: Re: Interconnection of multiple cores
150067: 10/12/09: Re: LPDDR on spartan-3e
150144: 10/12/19: Re: FPGA modules/cards with peripheral functions
150159: 10/12/21: Re: Simple ISE Microblaze with GPIO and custom logic example?
150178: 10/12/28: Re: Verilog inout, I2C
150181: 10/12/28: Re: Verilog inout, I2C
150195: 10/12/30: Re: XST Fails 2D array wild card sensitivity list
150201: 10/12/31: Re: Verilog inout, I2C
150206: 10/12/31: Re: Verilog inout, I2C
150384: 11/01/14: Re: Verilog Book for VHDL Users
150504: 11/01/25: Re: FPGA changes behaviour when the resource's usage percentage changes
150621: 11/01/28: Re: V6 SerDes simulation
150662: 11/02/01: Re: PCI Express Transfer
150674: 11/02/02: Re: PCI Express Transfer
150681: 11/02/03: Re: Dynamic Voltage switching for FPGA IO
150694: 11/02/04: Re: FPGA pin re-configuration
150783: 11/02/10: Re: Designing in Altium
150795: 11/02/11: Virtex 6 FIFO18E1
150810: 11/02/14: Re: Xilinx USB programming cable.
150845: 11/02/16: Re: Regarding passing a control signal from fast to slow cloak domain
150910: 11/02/21: Re: timing issues at high speed
151000: 11/02/28: Re: Question regarding bitstream generation
151094: 11/03/05: Re: IP Core Delivery Format Info
151119: 11/03/08: Re: IP Core Delivery Format Info
151214: 11/03/15: Re: HiTech Global Virtex5 PCIe Board
151221: 11/03/16: Re: ping pong buffer overflow issue
151268: 11/03/19: Re: RAM - DIMM vs SO-DIMM: price vs. (hardware & software) ease of use
151289: 11/03/21: Re: RAM - DIMM vs SO-DIMM: price vs. (hardware & software) ease of use
151292: 11/03/21: Re: RAM - DIMM vs SO-DIMM: price vs. (hardware & software) ease of use
151397: 11/04/02: Virtex 5 PCIe Debug
151437: 11/04/08: Re: Reference book on Pci-express (Hardware and software point of view)
151507: 11/04/15: Re: ML505 NOT RECOGNIZED BY THE PC THROUGH PCI EXPRESS
151516: 11/04/16: Re: XST - timing constraints of the combinatorial logic
151538: 11/04/18: Re: Oscilloscope recommendations Ghz range?
151539: 11/04/18: Re: Help with Verilog Code
151729: 11/05/11: Re: Why feedback clock in SDRAM controllers?
151736: 11/05/13: Re: Best syntheses
151738: 11/05/13: Re: Best syntheses
151745: 11/05/14: Re: Best syntheses
151786: 11/05/18: Modelsim
151789: 11/05/18: Re: Modelsim
151792: 11/05/18: Re: Modelsim
151877: 11/05/27: Re: Instantiation of an EDF netlist within a Verilog top RTL
151919: 11/06/03: Re: Looking for bitgen Virtex7 and Kintex7 support
151964: 11/06/15: Re: What is the advantage of source-syncronization (in SDRAMs)?
152026: 11/06/23: Re: Verilog Custom Core To Read and Write From RAM
152064: 11/06/29: Re: Virtex 5 Rocket IO design for reading in ADC data.
152068: 11/06/30: Re: Virtex 5 Rocket IO design for reading in ADC data.
152070: 11/06/30: Re: Virtex 5 Rocket IO design for reading in ADC data.
152073: 11/06/30: Re: Virtex 5 Rocket IO design for reading in ADC data.
152076: 11/06/30: Re: Virtex 5 Rocket IO design for reading in ADC data.
152098: 11/07/06: Re: Verilog Custom Core To Read and Write From RAM
152104: 11/07/07: Re: Verilog Custom Core To Read and Write From RAM
152149: 11/07/13: Re: Looking for a FPGA board
152258: 11/07/29: Re: Bitstream compression
152262: 11/07/29: Re: Bitstream compression
152320: 11/08/08: Re: Newbie PCB
152351: 11/08/11: Re: Newbie PCB
152413: 11/08/20: VHDL Basic Question
152415: 11/08/20: Re: VHDL Basic Question
152418: 11/08/20: Re: VHDL Basic Question
152419: 11/08/20: Re: VHDL Basic Question
152421: 11/08/21: Re: VHDL Basic Question
152423: 11/08/21: Re: VHDL Basic Question
152425: 11/08/21: Re: VHDL Basic Question
152683: 11/09/30: VHDL problem
152685: 11/09/30: Re: VHDL problem
152695: 11/10/03: Re: most stable version of ISE ?
152696: 11/10/03: Re: VHDL problem
152701: 11/10/04: Testbench
152712: 11/10/05: VHDL connection problem
152718: 11/10/06: Re: VHDL connection problem
153039: 11/11/19: Re: Xilinx PCI Express - Am I starting too low?
153301: 12/01/29: Re: =?ISO-8859-1?Q?Post=2Dsynth=E8se_simulation?=
153624: 12/04/05: Re: Very poor Xilinx experience
153820: 12/05/28: EDK problems
153877: 12/06/19: Re: Data transfers between MicroBlaze and VHDL
153884: 12/06/20: Re: Data transfers between MicroBlaze and VHDL
154092: 12/08/02: Re: how much costs the Artix 7 devices?
154107: 12/08/08: Re: spartan 6 ddr2 pinout
154198: 12/09/07: Verilog file operations
154203: 12/09/07: Re: Verilog file operations
155154: 13/05/11: Xilinx SDK 14.5 debug
155155: 13/05/11: Re: Inferring Xilinx BlockRAM FIFO
157752: 15/03/02: DDS
maxbatley:
125905: 07/11/08: Spartan 3E Starter Kit DDR RAM
maxfoo:
57831: 03/07/08: Re: Altera licenses
57927: 03/07/10: Re: phase noise in NCO
72357: 04/08/16: JTAG Vcc pin on coolrunner
72508: 04/08/21: Re: JTAG Vcc pin on coolrunner
73608: 04/09/25: Re: Looking for a Design for a Small FPGA Board
maxi:
130296: 08/03/19: Altera EPM7032S reading checksum
Maxim Golov:
12885: 98/11/03: Re: New free FPGA CPU
12911: 98/11/04: Re: New free FPGA CPU
Maxim S. Shatskih:
63359: 03/11/20: Re: 400 Mb/s ADC
63390: 03/11/20: Re: 400 Mb/s ADC
80845: 05/03/12: Re: (Stupid/Newbie) Question on UART
80855: 05/03/12: Re: (Stupid/Newbie) Question on UART
80856: 05/03/12: Re: (Stupid/Newbie) Question on UART
80870: 05/03/13: Re: (Stupid/Newbie) Question on UART
80940: 05/03/15: Re: (Stupid/Newbie) Question on UART
Maximilian Epple:
39111: 02/01/31: metastability: failsafe solution???
39137: 02/02/01: Re: metastability: failsafe solution???
Maximo H. Salinas:
18234: 99/10/08: GSR on ORCA FPGAs
18272: 99/10/11: Re: GSR on ORCA FPGAs
18291: 99/10/12: Re: GSR on ORCA FPGAs
Maxlim:
59016: 03/08/06: Memory map for Nios
59211: 03/08/12: Nios Clock Frequency
59241: 03/08/13: Re: Nios Clock Frequency
61417: 03/10/03: large integer support in GNUPro for Altera Nios software development
61452: 03/10/03: Re: large integer support in GNUPro for Altera Nios software development
64443: 04/01/04: Floating point in Nios SDK
64794: 04/01/14: nios-build debug option
67787: 04/03/19: Altera Quartus Compilation Report
Maxx:
53657: 03/03/19: spartan-2 clocking problem
53696: 03/03/20: Re: spartan-2 clocking problem
Maya:
27014: 00/11/07: Re: ISO C -> VHDL translator, prefer open source
Maya Gokhale:
3029: 96/03/17: pointers and fpgas
4182: 96/09/23: Re: query: C to FPGA
Maya Reuveni:
1792: 95/09/03: timing constraints in xilinx
1814: 95/09/06: pci board design guide
2200: 95/10/31: xilinx flor planner
2493: 95/12/18: Floor Planning for Xilinx
2550: 96/01/01: xilinx xxx.cst files
3926: 96/08/21: xilinx programing
<mayan@sandbridgetech.com>:
57313: 03/06/27: Re: Eighty layers of metal!
MAYFLOWERCOM@DELPHI.COM:
3317: 96/05/13: GPS job offerings
mayichao:
117475: 07/04/01: how to use and calculate prom checksum in prm file.
Mayil:
83611: 05/05/03: ERROR: NgdBuild:604 - logical block
83662: 05/05/04: Re: ERROR: NgdBuild:604 - logical block
Maynard Handley:
4812: 96/12/17: Re: ASICs Vs. FPGA in Safety Critical Apps.
14075: 99/01/11: Re: smallest DCT algorithm?
14157: 99/01/15: Re: smallest DCT algorithm?
28445: 01/01/12: Re: Nondeterministic FSMs in hardware?
Mayur Joshi:
72953: 04/09/08: Initializing on-board memory on V2MB100 development board
Mazlaini Yahya:
6260: 97/05/06: Advantages/disadvantages between CMOS/BiCMOS
mb:
83163: 05/04/25: what is microblaze ?
83319: 05/04/27: Re: what is microblaze ?
83352: 05/04/27: XPS vs. Project navigator
110374: 06/10/14: Re: PLB/OPB Bus Access from ISE
110425: 06/10/15: Re: System Generator implement to FPGA problem
mbaxter:
9486: 98/03/17: POSITION IN RECONFIGURABLE COMPUTING
9758: 98/04/03: RECONFIGURABLE COMPUTING JOB POSITION
mBird:
96757: 06/02/09: ModelSim # Error loading design
96780: 06/02/10: Re: ModelSim # Error loading design
96790: 06/02/10: Re: ModelSim # Error loading design
96792: 06/02/10: Re: ModelSim # Error loading design
<mbitzko@my-dejanews.com>:
11155: 98/07/21: Symbol Generation from FPGA Compiler Reports
11156: 98/07/21: Schematic Symbol Generation
<mbmsv@my-deja.com>:
25805: 00/09/21: Re: Freelance Designer Needed: Protel & FPGA
MBodnar:
133819: 08/07/16: Re: xilinx v5 ddr2 controller
149263: 10/10/12: Re: Xilinx SDK Debugger Problem
151135: 11/03/09: Re: Problems with Xilinx SDK and LwIP
151328: 11/03/23: Re: Xilinx EDK - max array size
152691: 11/10/02: Re: VHDL problem
153652: 12/04/10: Re: Best FPGA for algorithmic acceleration
mbonnici:
36156: 01/10/31: Hard macro in xilinx
<mbzbcm@aol.com>:
26376: 00/10/13: AOL - TIME WARNER MERGER! Tell the F.C.C. what you think! 7734
mc:
108060: 06/09/04: Re: Please help me with (insert task here)
108091: 06/09/05: Re: Please help me with (insert task here)
108092: 06/09/05: Re: Please help me with (insert task here)
MC:
76877: 04/12/15: XILINX slice structure detaild description
Mc Canzee:
61208: 03/09/30: nallatech ballynuey board
<mc4519@mclink.it>:
2499: 95/12/19: CYPRESS WARP 2+ VHDL DEVELOPMENT SYSTEM
mcb:
24015: 00/07/21: AM85C30 SCC probs
<mcbride@rosharon.wireline.slb.com>:
6522: 97/05/30: Re: Need Address/Phone/Fax List of Semiconductor Companies
mccarley:
28970: 01/01/31: 64b/66b gearbox in an FPGA
mccask:
1920: 95/09/20: Re: QuickLogic SpDE 5.0
1921: 95/09/20: Re: Fast FPGA's?
2761: 96/02/03: Re: Synplify from SYNPLICITY
mcholbi:
150758: 11/02/09: Designing in Altium
151867: 11/05/26: Records as ports in Synplify
<mcintosh@vima.austin.tx.us>:
12983: 98/11/09: TE16 ENV1
12970: 98/11/09: TE16 ENV1
<mcjy@my-deja.com>:
19523: 99/12/29: Re: USB2 core call for Volunteers
19524: 99/12/29: Re: USB2 core call for Volunteers
19551: 99/12/30: Re: USB2 core call for Volunteers
19552: 99/12/30: Re: USB2 core call for Volunteers
19560: 99/12/31: Re: Using internal RAM in Altera Flex 10KE
19718: 00/01/09: Re: Optimizing VHDL for Altera
19773: 00/01/11: Re: PCI/USB project started
McMeikan:
36511: 01/11/10: ZX81 production run, is there any interest?
36566: 01/11/13: Re: ZX81 production run, is there any interest?
36610: 01/11/13: Re: ZX81 production run, is there any interest?
36653: 01/11/14: Re: ZX81 production run, is there any interest?
<mcoyle5605@my-deja.com>:
23003: 00/06/08: data communication
<mctuva4004@gmail.com>:
160553: 18/04/01: Re: Very low pin count FPGA
MD:
10237: 98/05/06: Re: Arbiter help !!!
md:
21481: 00/03/23: IC Designers, validation engineers--Portland, OR
23842: 00/07/12: DESIGNERS WANTED
<mdini@dinigroup.com>:
60658: 03/09/18: Re: High Bandwidth Virtex II boards
68033: 04/03/24: Re: study verilog or vhdl?
mdisman:
10503: 98/05/25: Programmable Logic News update
11078: 98/07/17: PLD Design Center
11481: 98/08/18: PLD Design Center
11563: 98/08/24: Programmable logic News
11784: 98/09/09: New Tech Note
13460: 98/12/03: EDTN Tech Notes
13605: 98/12/11: Tech Note Article
14102: 99/01/13: EDTN Tech Note
14214: 99/01/20: EDTN Tech Note
15345: 99/03/19: Tech Note
15817: 99/04/15: New Tech Note
<mdschulte@gmail.com>:
130859: 08/04/03: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
<mduane@umich.edu>:
57487: 03/07/01: NAND flash file
Me:
28981: 01/02/01: Re: Can Virtex-II be programmed with MultiLINX?
28982: 01/02/01: Re: lvds and lvpecl differential I/O input termination on Virtex II -
29036: 01/02/03: Re: Can Virtex-II be programmed with MultiLINX?
29451: 01/02/22: Re: Infering DPRAM with both outputs
39614: 02/02/14: Re: Power estimation for Virtex-2 device
148801: 10/08/26: about (low-level) jtag
me:
8147: 97/11/21: Re: FPGA basics please ?
24498: 00/08/11: what does 0.35 micron mean
43418: 02/05/21: Configuration Blues
<me@here.com>:
16274: 99/05/13: Re: Help me: What is FPGA?
<me@youwishyouknew.com>:
<me_2003@walla.co.il>:
96418: 06/02/03: question for the EDK users out there...
96505: 06/02/05: Re: question for the EDK users out there...
96531: 06/02/06: Re: question for the EDK users out there...
96557: 06/02/06: microblaze xmd question..
96565: 06/02/06: Re: microblaze xmd question..
96567: 06/02/06: Re: microblaze xmd question..
96573: 06/02/06: Re: microblaze xmd question..
96604: 06/02/07: Microblaze Virtual platform problem
96716: 06/02/09: EDK - PLB/OPB Bus questions.
96776: 06/02/10: Re: EDK - PLB/OPB Bus questions.
96778: 06/02/10: Re: Simulation of MicroBlaze embedded system
96784: 06/02/10: Re: EDK - PLB/OPB Bus questions.
96990: 06/02/14: Re: EDK - PLB/OPB Bus questions.
97012: 06/02/14: EDK: OPB Question
97313: 06/02/20: EDK -running from external sram
97685: 06/02/26: VGA specification
98112: 06/03/05: Question for the EDK ppc users ...
98160: 06/03/06: Simulating a ppc working with external memory
98308: 06/03/08: Re: FPGA imple. of aes
98395: 06/03/09: Re: FPGA imple. of aes
98556: 06/03/12: using EDK with the gcc -g option...
98558: 06/03/12: Re: EDK - PLB/OPB Bus questions.
98570: 06/03/13: Re: using EDK with the gcc -g option...
98576: 06/03/13: Re: using EDK with the gcc -g option...
98579: 06/03/13: Re: using EDK with the gcc -g option...
98584: 06/03/13: Re: using EDK with the gcc -g option...
98628: 06/03/13: debuging power_pc + microblaze
98857: 06/03/17: EDK : PPC405 Interrupt question
104741: 06/07/05: EDK question - debugging PPC405 and MB..
107084: 06/08/24: Xilinx BRAMs question - help needed ..
107106: 06/08/24: Re: Xilinx BRAMs question - help needed ..
107107: 06/08/24: Re: Xilinx BRAMs question - help needed ..
107356: 06/08/27: Re: Xilinx BRAMs question - help needed ..
109921: 06/10/08: Two instances of Microblaze ...
110054: 06/10/10: Re: Two instances of Microblaze ...
111564: 06/11/06: To Xilinx guys out there - microblaze mapping problem
111591: 06/11/06: Re: To Xilinx guys out there - microblaze mapping problem
111640: 06/11/07: Re: To Xilinx guys out there - microblaze mapping problem
111643: 06/11/07: Re: How to generate a PROM file and then burn it on FPGA
111650: 06/11/07: Re: To Xilinx guys out there - microblaze mapping problem
111694: 06/11/08: Re: How to generate a PROM file and then burn it on FPGA
115366: 07/02/08: Radar pulse detection
115437: 07/02/11: chipscope + mdm with microblaze ..
115458: 07/02/12: Re: chipscope + mdm with microblaze ..
125636: 07/10/30: debugging ppc + mb
125727: 07/11/01: To Xilinx users - PLB bus features (for PPC)
125728: 07/11/01: Re: debugging ppc + mb
125772: 07/11/04: APU (xilinx PPC) is it a soft core ?
Mechanic Mike:
38622: 02/01/19: Dev tools needed
Med440:
591: 95/01/12: ViewLogic simulation without master reset
<mediacan@supernet.ab.ca>:
1326: 95/06/01: VIRTUAL REALITY
mediatronix:
81321: 05/03/21: Re: FIR choice
Medical Electronics Lab:
11199: 98/07/24: Re: High-radix division
Meelis Kuris:
30399: 01/04/06: Re: High Speed PLA/FPGA
30401: 01/04/06: Re: High Speed PLA/FPGA
30744: 01/04/27: Modelsim license
31086: 01/05/11: Re: Virtex-2 - experiences ?
31135: 01/05/12: Fine phase shift in Virtex2
31168: 01/05/14: Re: Fine phase shift in Virtex2
31173: 01/05/14: free simulator
31204: 01/05/15: Re: Fine phase shift in Virtex2
31214: 01/05/15: CLKFX of DCM stops working.
31216: 01/05/15: Re: BUFG in Virtex_E
31289: 01/05/17: Re: Digital PLL (DPLL) design help
31408: 01/05/22: Re: Counter problem
31456: 01/05/25: who needs clk180
Mees:
71188: 04/07/11: RC100 Video DAC
meg:
78388: 05/01/31: Xilinx Virtex2p configuration
Meg:
48469: 02/10/17: Size of configuration bitstream for xcv50 (xilinx)
MegaBolt:
21373: 00/03/20: Beginner's Guide
MegaPowerStar:
40439: 02/03/07: DPRAM implementation in altera
40499: 02/03/07: Re: Webpack/SpartanII maplib:93 error
43074: 02/05/12: reconfigurable FPGAs
MegaPoweSstar:
39126: 02/01/31: JTAG Emulator Tutorial
megha:
133721: 08/07/11: VHDL code for DDFS
133754: 08/07/13: mean of ddfs
133755: 08/07/13: Re: VHDL code for DDFS
mehdi bousfiha:
154441: 12/11/03: help
154443: 12/11/03: Re: help
154446: 12/11/04: Re: help
154448: 12/11/04: Re: help
154451: 12/11/04: Re: help
154463: 12/11/05: Re: help
mehdiru:
150309: 11/01/09: Xilinx ML561 Schematics
mehmeto:
36647: 01/11/14: interleaver delay question
36670: 01/11/15: Re: interleaver delay question
49496: 02/11/13: question about booth multipliers
<mehmeto@my-deja.com>:
19905: 00/01/17: Viterbi decoder in FPGA
<mehta.nupur@gmail.com>:
139285: 09/03/25: Re: Fm digital baseband demodulation
139286: 09/03/25: Re: Fm digital baseband demodulation
mehtavishal:
153994: 12/07/09: RE: now what is this? iMPACT:2356 - Platform Cable USB firmware must be updated.
mehul:
89115: 05/09/06: Carry saver adder
Meindert Sprang:
92454: 05/11/30: Re: Why does two channels of ADC give different outputs?
92461: 05/11/30: Re: Why does two channels of ADC give different outputs?
92486: 05/11/30: Re: Why does two channels of ADC give different outputs?
92533: 05/12/01: Re: Why does two channels of ADC give different outputs?
92747: 05/12/06: Re: Quick question, how do I supply +-5V?
95020: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95021: 06/01/20: Re: OT:Shooting Ourselves in the Foot
108146: 06/09/06: Re: Please help me with (insert task here)
115473: 07/02/12: Re: Building Coaxial transmission line on PCB?
135795: 08/10/16: Re: free cpu 8051 verilog code
mel:
17175: 99/07/07: Programming Xilinx without Foundation
17199: 99/07/08: Re: Programming Xilinx without Foundation
17200: 99/07/08: Re: Programming Xilinx without Foundation
98667: 06/03/14: Altera FIR compiler
Mel:
56415: 03/06/04: Re: Xilinx Virtex development board for cPCI
56775: 03/06/14: Re: Power consumed in a non configured FPGA?
57916: 03/07/09: Re: Xilinx price question
136659: 08/11/28: Re: Gizmo invent Gizmo. The State of the Art in 1999, today and the future. submitted by Mr Ian Martin Ajzenszmidt
147555: 10/05/01: Re: Cheap FPGAs for tutorial
149187: 10/10/06: Re: Driving a design via TCP/IP
Melanie Nasic:
93194: 05/12/15: Xilinx' encrypted HPICE models in PSPICE
93332: 05/12/20: Virtex-4 clocking
93335: 05/12/20: real-time compression algorithms on fpga
93341: 05/12/20: Re: real-time compression algorithms on fpga
93345: 05/12/20: Re: Virtex-4 clocking
93498: 05/12/23: Re: real-time compression algorithms on fpga
melbadri:
89668: 05/09/21: opb ip master/slave...arbiter problems
89669: 05/09/21: Re: OPB bus communication
89861: 05/09/28: Re: chipscope pro
melinda:
143921: 09/11/03: ModelSim view internal signals in instantiated verilog modules
143924: 09/11/03: Re: ModelSim view internal signals in instantiated verilog modules
143937: 09/11/04: Re: ModelSim view internal signals in instantiated verilog modules
Melissa Abato:
1175: 95/05/11: Re: VITAL Support Survey
3538: 96/06/17: Re: FPGA Conversions
Melissa Vetromille:
90104: 05/10/04: I'm desperate... EDK project simulation
90156: 05/10/05: Re: I'm desperate... EDK project simulation
90157: 05/10/05: Re: I'm desperate... EDK project simulation
90201: 05/10/06: Re: I'm desperate... EDK project simulation
<MelissaGilbert@Nude.Here>:
10492: 98/05/23: -SEE SNEAK LOCKER ROOM PIX OF GYMNASTS FREE 95695
Mellby:
102844: 06/05/22: Urgent help programming SPI-flash trough JTAG (Spartan3E)
102847: 06/05/22: Re: Urgent help programming SPI-flash trough JTAG (Spartan3E)
Melle Jonker:
54385: 03/04/09: Re: Really long vectors in VHDL
Meloun:
30285: 01/03/31: Re: Reed/Solomon ENcoder
melvin:
138322: 09/02/16: cpld 9572 xilinx
//members.home.nl/stoelie:
19377: 99/12/17: Http://members.home.nl/stoelie
<mench@mench.com>:
12440: 98/10/12: Re: Schematic entry?
12644: 98/10/21: Re: State machines in VHDL/Verilog
12661: 98/10/22: Re: State machines in VHDL/Verilog
12808: 98/10/30: Re: Schematic entry?
14198: 99/01/19: Re: constant and signal for fuction parameter
14564: 99/02/04: Re: VHDL problem (Xilinx-problem)
14992: 99/03/02: Re: LCD driver
15441: 99/03/24: Re: HDL-307 error
15442: 99/03/24: Re: big/little endian mishap
15452: 99/03/24: Re: big/little endian mishap
15949: 99/04/22: Re: Job Advert Netiquette?
16601: 99/05/29: Re: Modelsim, VHDL & mem core
17132: 99/07/01: Re: OrCAD (was "Re: ALTERA GDF to VHDL QUESTION")
17442: 99/07/28: Re: Problem with Max+PlusII / Flex10k
17769: 99/09/01: VHDL 200x Survey Participation Request
17814: 99/09/07: Re: VHDL 200x Survey Participation Request
19349: 99/12/15: Re: State machine ok with binary encoding but unstable with one hot encoding
20358: 00/02/07: Re: Conditional compilation in VHDL?
22116: 00/04/25: Re: xilinx --> altera vhdl
Meng Soo:
8129: 97/11/19: Reprogrammable Config Memories
68650: 04/04/12: Re: 66B mode of VirtexII-ProX Rocket I/O
<mengsoo@gmail.com>:
91766: 05/11/11: Re: Rocket IO reset problem
Mensanator:
145421: 10/02/08: Re: using an FPGA to emulate a vintage computer
mentari:
136222: 08/11/07: Tilera multicore replaces FPGA?
136241: 08/11/07: Re: Tilera multicore replaces FPGA?
136265: 08/11/07: Re: Tilera multicore replaces FPGA?
136535: 08/11/20: Picochip Wimax designs available to public?
<meo2662@gmail.com>:
118240: 07/04/20: FPGA MAC for Point to Point Connection
mep:
72683: 04/08/28: Re: Counter counting on both clock edges.
<meralonurlu@gmail.com>:
133196: 08/06/20: beginner
133338: 08/06/25: Beginner : Rotary switch (quad sw)
133427: 08/06/28: Still a Beginner: Accumulator has no reset
133434: 08/06/28: Re: Still a Beginner: Accumulator has no reset
133597: 08/07/05: ISE Simulator
merche:
122045: 07/07/18: Actel. Libero. Synplify: "unbound component..."
122088: 07/07/19: libero.actel
122090: 07/07/19: modelsim Warning "VIOLATION ON D WITH RESPECT TO CLK"
122108: 07/07/19: Re: Actel. Libero. Synplify
122137: 07/07/20: libero.actel. i need a clock in a non global pin.
124359: 07/09/19: help! ACTEL PROASIC PLUS clock buffer
124382: 07/09/20: Re: help! ACTEL PROASIC PLUS clock buffer
124383: 07/09/20: proasic plus. actel
124427: 07/09/21: Re: help! ACTEL PROASIC PLUS clock buffer
128578: 08/01/31: I need a SDRAM controller
128583: 08/01/31: Re: I need a SDRAM controller
128584: 08/01/31: Re: I need a SDRAM controller
128585: 08/01/31: Re: I need a SDRAM controller
Meres Five:
103643: 06/06/07: ICAP Virtex4 32 bits
103805: 06/06/12: Re: ICAP Virtex4 32 bits
<merlin_jiang@hotmail.com>:
90312: 05/10/10: Yet another NGDBUILD 455 problem
<mertserimer@gmail.com>:
156160: 13/12/30: Simple Telephone Conversation on Fpga board and SSD
Meryem Marzouki:
1074: 95/04/25: Re: Sunrise ???
<meserve@my-dejanews.com>:
10702: 98/06/11: Re: Are you looking for a good VHDL/Verilog Editor?
Meshenger:
158288: 15/10/03: Re: System On Chip From Microsemi
158297: 15/10/05: Re: System On Chip From Microsemi
meshoshow:
113523: 06/12/15: Lcd Block Diagram - Vhdl - On Fpga.. help!
116220: 07/03/05: LCD code
Mesner:
30083: 01/03/22: XS40 and XS95: Recommend books?
Mess at Cabot:
9558: 98/03/24: Re: Cypress ISR
messa:
137831: 09/01/30: transmission gate
meta:
46967: 02/09/13: Re: 2-D resistor array
46968: 02/09/13: Re: 2-D resistor array
46988: 02/09/13: Re: 2-D resistor array
46989: 02/09/13: Re: 2-D resistor array
46990: 02/09/13: Re: re:2-D resistor array
46997: 02/09/13: Re: 2-D resistor array
46998: 02/09/13: Re: 2-D resistor array
Meta Fernando:
28430: 01/01/12: APEX20K multi-device configuration
metal:
97265: 06/02/20: Re: equivalent time sampling
97301: 06/02/20: Re: WebPACK license (and Quartus Web Edition too).
97328: 06/02/20: Re: SCHEMATICS ... Is anybody as frustrated as I am with the software?
97468: 06/02/22: Re: SCHEMATICS ... Is anybody as frustrated as I am with the software?
98520: 06/03/12: Re: fpga to 5v ttl logic
98523: 06/03/12: Re: Combinatorial Division?
98702: 06/03/14: Re: Combinatorial Division?
98703: 06/03/14: Re: Soldering SMT/BGA
98704: 06/03/14: Spread Spectrum Cores ??
98747: 06/03/15: Re: Spread Spectrum Cores ??
98748: 06/03/15: Re: fpga to 5v ttl logic
98749: 06/03/15: Re: fpga to 5v ttl logic
98821: 06/03/16: Re: Where are FPGA heading?
98822: 06/03/16: Re: Where are FPGA heading?
98823: 06/03/16: Re: Where are FPGA heading?
98824: 06/03/16: Re: for all those who believe in ASICs....
98825: 06/03/16: Re: Where are FPGA heading?
<metamazster@gmail.com>:
101685: 06/05/04: Re: Xilinx 3s8000?
Metastabl:
41919: 02/04/10: Re: Low-cost FPGA + processor board?
41965: 02/04/11: Re: Low-cost FPGA + processor board?
42020: 02/04/12: Re: Low-cost FPGA + processor board?
mete:
73940: 04/10/01: Re: spartan-3 sram
73485: 04/09/22: spartan-3 sram
73540: 04/09/23: Re: spartan-3 sram
74474: 04/10/12: direct calculation of the modulus ?
74713: 04/10/17: Re: direct calculation of the modulus ?
2.1 Meter Observer:
20796: 00/02/22: Re: VHDL Examples for Xilinx Foundation 2.1 (Synopsys lite) needed !
20797: 00/02/22: Re: VHDL Examples for Xilinx Foundation 2.1 (Synopsys lite) needed !
methi:
84643: 05/05/23: Mapping problem due to invalid pins in UCF file
84673: 05/05/24: Re: Mapping problem due to invalid pins in UCF file
84682: 05/05/24: Re: Mapping problem due to invalid pins in UCF file
84689: 05/05/24: Re: Mapping problem due to invalid pins in UCF file
84696: 05/05/24: Re: Mapping problem due to invalid pins in UCF file
85183: 05/06/06: Clock doubler to double an input 13.5 Mhz
85195: 05/06/06: Re: Clock doubler to double an input 13.5 Mhz
85196: 05/06/06: Re: Clock doubler to double an input 13.5 Mhz
85209: 05/06/06: Re: Clock doubler to double an input 13.5 Mhz
85215: 05/06/06: Re: Clock doubler to double an input 13.5 Mhz
86143: 05/06/22: Need help with AHDL
86148: 05/06/22: Need help understanding this AHDL code
86181: 05/06/22: Re: Need help understanding this AHDL code
87259: 05/07/20: Design is too large for the device! xc3s400
87263: 05/07/20: Re: Design is too large for the device! xc3s400
87272: 05/07/20: Re: Design is too large for the device! xc3s400
87273: 05/07/20: Re: Design is too large for the device! xc3s400
87274: 05/07/20: Re: Design is too large for the device! xc3s400
87278: 05/07/20: Re: Design is too large for the device! xc3s400
87291: 05/07/20: Re: Design is too large for the device! xc3s400
87576: 05/07/26: Re: Design is too large for the device! xc3s400
87656: 05/07/27: Re: Design is too large for the device! xc3s400
87703: 05/07/28: Re: Design is too large for the device! xc3s400
96724: 06/02/09: Need help with generating video patterns using VHDL
96999: 06/02/14: Re: Need help with generating video patterns using VHDL
97446: 06/02/22: Re: Need help with generating video patterns using VHDL
Metin:
113407: 06/12/13: BLVDS_25 @ SPARTAN3
115657: 07/02/16: Lattice / M-LVDS
121588: 07/07/09: Spartan3A : timing Constraints / DCM Outputs
121592: 07/07/09: Re: Spartan3A : timing Constraints / DCM Outputs
121635: 07/07/10: Re: Spartan3A : timing Constraints / DCM Outputs
Metin Yerlikaya:
32390: 01/06/25: black box instantiation in Spartan II Design
<metinnn@gmx.de>:
140125: 09/04/29: offset out
140163: 09/05/01: Re: offset out
140177: 09/05/01: Re: offset out
140199: 09/05/02: Re: offset out
metiu:
122185: 07/07/23: help: buggy IDE driver on Intel IXP425 GPIO(EXPB)
metry:
103245: 06/05/29: How to add a peripheral IP generated by Coregen to EDK?
mexas:
152354: 11/08/11: to sell: Nallatech H101-PCIXM PCI-X FPGA Accelerator Card (used)
mfgunes:
122149: 07/07/20: Writing to bram and reading from bram with microblazer
122209: 07/07/24: Re: Writing to bram and reading from bram with microblazer
122210: 07/07/24: Connecting Bram LMB Controller to Microblaze
122215: 07/07/24: Re: Connecting Bram LMB Controller to Microblaze
122222: 07/07/24: Re: Connecting Bram LMB Controller to Microblaze
122274: 07/07/25: Re: Connecting Bram LMB Controller to Microblaze
122284: 07/07/25: ERROR:NgdBuild:927 - Failed to process BMM file edkBmmFile.bmm
122286: 07/07/25: ERROR:NgdBuild:927 - Failed to process BMM file edkBmmFile.bmm
122513: 07/07/30: Re: ERROR:NgdBuild:927 - Failed to process BMM file edkBmmFile.bmm
122514: 07/07/30: Re: ERROR:NgdBuild:927 - Failed to process BMM file edkBmmFile.bmm
122647: 07/08/02: Writing data to bram with microblaze
123050: 07/08/15: Multiplication Problem on Microblaze Software
123056: 07/08/15: Re: Multiplication Problem on Microblaze Software
123094: 07/08/16: Re: Multiplication Problem on Microblaze Software
123100: 07/08/16: Re: Multiplication Problem on Microblaze Software
123106: 07/08/16: Re: Multiplication Problem on Microblaze Software
123204: 07/08/20: Re: Multiplication Problem on Microblaze Software
123205: 07/08/20: Re: Multiplication Problem on Microblaze Software
123207: 07/08/20: Re: Multiplication Problem on Microblaze Software
<mfragola@worldcomc.ch>:
6261: 97/05/05: E-MAIL BLASTER
mg:
133629: 08/07/07: Understanding PPC405 execution.
134050: 08/07/23: MDM under EDK 9.2i with PowerPC
MGreim:
156318: 14/03/02: Oberon Operating System + Compiler + Graphic on a Spartan 3 FPGA
156325: 14/03/07: Re: Oberon Operating System + Compiler + Graphic on a Spartan 3 FPGA
MGT78000:
125578: 07/10/29: Re: 3 input adder in Spartan 3E
MH:
37443: 01/12/11: Re: About special promotion of Synplicity's Synplify? FPGA synthesis solution
37457: 01/12/11: Re: About special promotion of Synplicity's Synplify? FPGA synthesis solution
37581: 01/12/16: Re: About special promotion of Synplicity's Synplify? FPGA synthesis solution
39738: 02/02/18: Re: JTAG CABLE
39807: 02/02/20: Re: Virtex II multiplier pipeline
103819: 06/06/12: Re: Xilinx ISE S/W Install kernel version "mismatch"
117703: 07/04/07: Re: can anyone give me a reference price of the following Xilinx boards?
118831: 07/05/04: Re: FPGA board for video processing
121128: 07/06/26: Re: VGA 1080x1920 pixel chipset
131527: 08/04/24: Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860
mh:
104724: 06/07/05: using cores exported from Xilinx plan Ahead with verilg design
104834: 06/07/06: Re: using cores exported from Xilinx plan Ahead with verilg design
105659: 06/07/27: Re: Guided MAP/PAR in ISE
106679: 06/08/17: Re: Problems about the synthesis(XST)
109008: 06/09/19: maximum life of FPGA based products ????
109113: 06/09/20: Re: maximum life of FPGA based products ????
115767: 07/02/19: Managing input clock of 20MHz at input of DCM
118292: 07/04/23: Re: Virtex-4 module based partial reconfiguration problem
118904: 07/05/07: Re: ISE Simulator :Does nothing when double click
119200: 07/05/15: Re: Uart problem, xapp223 + Spartan3A
119527: 07/05/22: using FPGA JTAG as GPIO
120656: 07/06/12: Re: Virtex 5 static and dynamic (re)configuration
120951: 07/06/21: Re: Suggestions for Xilinx based evaluation board for image processing
121156: 07/06/27: Re: CameraLink to Hotlink-II video converter
125174: 07/10/17: Re: FPGA quiz2: spartan3A return Virtex JTAGID. Also prizes for quiz1 and quiz2
125176: 07/10/17: Re: FPGA quiz2: spartan3A return Virtex JTAGID. Also prizes for quiz1 and quiz2
125278: 07/10/19: Re: Dynamic Reconfiguration books
126033: 07/11/13: Re: bidirectional in fpga
126432: 07/11/22: Re: partial dynamic reconfiguration on Virtex-4 SX35
126597: 07/11/28: Re: Xilinx Multilink Connection not working
126599: 07/11/28: Re: area group constraint problem
126600: 07/11/28: Re: Behavioral Simulation working but Post-route Simulation is not.
127170: 07/12/12: Re: WARNING:PAR:289 and bitgen error.
127446: 07/12/26: Re: video capturing+ filter + vga output
127626: 08/01/04: Re: Camera connection on XUPV2P
127779: 08/01/07: Re: Camera connection on XUPV2P
128570: 08/01/30: Re: About 10-bit pixel datum from CMOS image sensor
128636: 08/02/01: Re: Xilinx BSCAN primitives proper use
128687: 08/02/04: Re: Xilinx BSCAN primitives proper use
128811: 08/02/06: Re: Xilinx BSCAN primitives proper use
129081: 08/02/13: Re: Erratic Behavior of Virtex 4 FPGA
129222: 08/02/19: Re: FPGA Programming solution
129674: 08/03/02: Re: HELP > Face/Edge detection on FPGA
129934: 08/03/10: Re: Virtex-4 VLX25 DCM problem
130456: 08/03/24: Re: total cost for virtex II pro FPGA
MHB:
11164: 98/07/21: Aldec's Active-VHDL Behavorial Simulator-Thanx
<mhelshou@hotmail.com>:
138515: 09/02/25: Re: Converting state machine encoding to std_logic_vector
138525: 09/02/25: Re: Converting state machine encoding to std_logic_vector
<mhkohne@discordia.org>:
25391: 00/09/09: Re: bga->dip?
<mhosni80@gmail.com>:
88902: 05/08/31: Low Power RTL Design
Miad Faezipour:
48901: 02/10/26: A PCI Data Aqcuisition Card Design
Micah Dowty:
43082: 02/05/13: Architecture for high-level reconfigurable computing
43130: 02/05/14: Re: Architecture for high-level reconfigurable computing
43140: 02/05/14: Re: Architecture for high-level reconfigurable computing
43144: 02/05/14: Re: Architecture for high-level reconfigurable computing
43163: 02/05/15: Re: Announce:GPLed 6502 IP core
43173: 02/05/15: Re: PCI Board Project
43314: 02/05/18: Re: Need Help on FPGA and Spiking Neurons
43474: 02/05/22: Re: Architecture for high-level reconfigurable computing
mice:
89820: 05/09/27: Spartan-3 starter kit and digilent jtag-usb cable
89831: 05/09/27: re:Spartan-3 starter kit and digilent jtag-usb cable
90269: 05/10/07: 9bit vga with resistors.
90270: 05/10/07: re:9bit vga with resistors.
91258: 05/11/02: Newbie. Clocks.
91328: 05/11/03: re:Newbie. Clocks.
Mich:
91408: 05/11/05: USB host
97225: 06/02/19: Addressing BRAM in a V2 pro
97507: 06/02/23: Re: Addressing BRAM in a V2 pro
97512: 06/02/23: Re: Addressing BRAM in a V2 pro
97598: 06/02/24: Re: IP2IP_Addr in IPIF
97600: 06/02/24: a master-IPIF problem on the PLB bus
97686: 06/02/26: ERROR:MapLib:482
97690: 06/02/26: Re: ERROR:MapLib:482
97704: 06/02/26: Re: ERROR:MapLib:482
97707: 06/02/26: Re: ERROR:MapLib:482
99528: 06/03/26: ERROR:NgdBuild:604
99540: 06/03/26: Re: ERROR:NgdBuild:604
99628: 06/03/27: Re: ERROR:NgdBuild:604
99779: 06/03/29: problem with IO in EDK 8.1
99790: 06/03/29: Re: problem with IO in EDK 8.1
99817: 06/03/29: Re: problem with IO in EDK 8.1
100149: 06/04/04: HDL Options @ EDK
103471: 06/06/03: Difference Logic Cells <=> Slices
Michael:
1782: 95/08/31: Altera flex10k
32537: 01/06/29: Asynchronous design in Virtex FPGA
42399: 02/04/22: Prototyping Boards for Hobbyist CPU/System Designs
49680: 02/11/18: Common sense and pin assignment.
51835: 03/01/23: free x86 core ip
51857: 03/01/23: Re: dualport ram instantiation in Spartan IIE
51867: 03/01/24: Re: free x86 core ip
51892: 03/01/24: Re: VHDL or Verilog?
52287: 03/02/06: xsvf, CoolrunnerII and XAPP058
59907: 03/09/01: Different types of ASICs?
59914: 03/09/01: Complex digital ICs visual simulation?
59936: 03/09/02: Re: Complex digital ICs visual simulation?
66616: 04/02/24: CardBus prototype in FPGA
66729: 04/02/25: Re: Stratix 2 ALUT architecture patented ?
66802: 04/02/26: Re: Stratix 2 ALUT architecture patented ?
72128: 04/08/09: Board suggestions
73369: 04/09/20: Virtex 4 integrated A/Ds?
87724: 05/07/29: VHDL 200x? when?
89055: 05/09/04: Partial Reconfiguration : New Forum
92753: 05/12/06: IDE for Nios2 does not compile on windows XP
92755: 05/12/06: Re: IDE for Nios2 does not compile on windows XP
92808: 05/12/07: Re: FPGA development board with digital image camera
92866: 05/12/08: Re: FPGA development board with digital image camera
99330: 06/03/23: Re: OpenSPARC released
99488: 06/03/25: Re: How to write compact DFF chain?
104397: 06/06/26: Re: Space invaders on Spartan3e starter board
104409: 06/06/26: Re: Space invaders on Spartan3e starter board
118827: 07/05/04: FPGA board for video processing
127243: 07/12/15: Getting started guide for Digilent Spartan 3E Starter Board?
127264: 07/12/16: Re: Getting started guide for Digilent Spartan 3E Starter Board?
131159: 08/04/13: Question about Spartan 3E starter kit
131161: 08/04/13: Re: Question about Spartan 3E starter kit
131174: 08/04/14: Which to learn: Verilog vs. VHDL?
131198: 08/04/15: Simulation tools for Xilinx ISE
131208: 08/04/15: Re: Simulation tools for Xilinx ISE
131212: 08/04/15: Re: Simulation tools for Xilinx ISE
131215: 08/04/15: Re: Simulation tools for Xilinx ISE
131282: 08/04/17: Re: Simulation tools for Xilinx ISE
131336: 08/04/19: Very simple VHDL problem
131342: 08/04/20: Re: Very simple VHDL problem
131345: 08/04/20: Re: Very simple VHDL problem
131346: 08/04/20: Re: Very simple VHDL problem
131354: 08/04/20: Problem writing quadrature decoder
131361: 08/04/20: Re: Problem writing quadrature decoder
131362: 08/04/20: Re: Problem writing quadrature decoder
131377: 08/04/20: Re: Problem writing quadrature decoder
131381: 08/04/20: Re: Problem writing quadrature decoder
131384: 08/04/20: Re: Problem writing quadrature decoder
131386: 08/04/20: Re: Problem writing quadrature decoder
131387: 08/04/20: Re: Problem writing quadrature decoder
131425: 08/04/21: Re: Problem writing quadrature decoder
144016: 09/11/07: Re: Cyclone IV announced
150544: 11/01/26: ISE 12.4
150570: 11/01/26: Re: ISE 12.4
150571: 11/01/26: Re: ISE 12.4
150605: 11/01/27: Re: ISE 12.4
151070: 11/03/03: Re: ISE 12.4
151155: 11/03/12: Re: ISE 12.4
151364: 11/03/28: Spartan IOB Input Switching Characteristic
151366: 11/03/28: Re: Spartan IOB Input Switching Characteristic
151681: 11/05/05: remove Xilinx webtalk
151683: 11/05/05: Re: ise 10.1 (Linux) contraints problem
151685: 11/05/05: Re: remove Xilinx webtalk
151690: 11/05/05: Re: remove Xilinx webtalk
151691: 11/05/05: Re: remove Xilinx webtalk
151697: 11/05/06: Re: ise 10.1 (Linux) contraints problem
151705: 11/05/08: Re: ise 10.1 (Linux) contraints problem
151734: 11/05/13: Best syntheses
151737: 11/05/13: Re: Best syntheses
151744: 11/05/14: Re: Best syntheses
151747: 11/05/14: Re: Best syntheses
151758: 11/05/15: Re: Best syntheses
151888: 11/05/30: Re: Best syntheses
151981: 11/06/17: Re: Xilinx or Altera
153228: 12/01/13: Virtex 5 GC clock pin vs GC//CC clock pins
153419: 12/02/21: Using both Verilog and VHDL for Xilinx simulation
157645: 15/01/15: Altera Cyclone II
157647: 15/01/15: Re: Altera Cyclone II
157650: 15/01/20: Re: Altera Cyclone II
michael:
116621: 07/03/14: interface ad9229 with altera stratix II
131343: 08/04/20: Re: Very simple VHDL problem
131450: 08/04/21: Re: Problem writing quadrature decoder
Michael A. Covington:
54607: 03/04/14: Re: Testing engineering ability prior to work?
54608: 03/04/14: Re: Testing engineering ability prior to work?
Michael A. Terrell:
95065: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95068: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95205: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95206: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95238: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95248: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95249: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95283: 06/01/22: Re: OT:Shooting Ourselves in the Foot
95284: 06/01/22: Re: OT:Shooting Ourselves in the Foot
95286: 06/01/22: Re: OT:Shooting Ourselves in the Foot
95287: 06/01/22: Re: OT:Shooting Ourselves in the Foot
95340: 06/01/22: Re: OT:Shooting Ourselves in the Foot
95350: 06/01/22: Re: OT:Shooting Ourselves in the Foot
95546: 06/01/24: Re: OT:Shooting Ourselves in the Foot
95550: 06/01/24: Re: OT:Shooting Ourselves in the Foot
100040: 06/04/02: Re: deglitching a clock
100042: 06/04/02: Re: deglitching a clock
100057: 06/04/02: Re: deglitching a clock
107905: 06/09/02: Re: Performance Appraisals
107907: 06/09/02: Re: Performance Appraisals
107948: 06/09/03: Re: Performance Appraisals
107967: 06/09/03: Re: Performance Appraisals
107969: 06/09/03: Re: Performance Appraisals
107994: 06/09/04: Re: Performance Appraisals
108002: 06/09/04: Re: Please help me with (insert task here)
108048: 06/09/04: Re: Please help me with (insert task here)
108049: 06/09/04: Re: Please help me with (insert task here)
108069: 06/09/05: Re: Performance Appraisals
108071: 06/09/05: Re: Please help me with (insert task here)
108072: 06/09/05: Re: Please help me with (insert task here)
108073: 06/09/05: Re: Please help me with (insert task here)
108074: 06/09/05: Re: Please help me with (insert task here)
108094: 06/09/05: Re: Please help me with (insert task here)
108241: 06/09/07: Re: Please help me with (insert task here)
108244: 06/09/07: Re: Please help me with (insert task here)
108249: 06/09/07: Re: Performance Appraisals
108253: 06/09/07: Re: Please help me with (insert task here)
108347: 06/09/08: Re: Performance Appraisals
108353: 06/09/08: Re: Performance Appraisals
108419: 06/09/11: Re: Performance Appraisals
108460: 06/09/11: Re: Performance Appraisals
108778: 06/09/16: Re: Performance Appraisals
112640: 06/11/27: Re: board - T562.jpg
113589: 06/12/17: Re: electrical level conversion
115675: 07/02/16: Re: Building Coaxial transmission line on PCB?
115718: 07/02/17: Re: Building Coaxial transmission line on PCB?
131355: 08/04/20: Re: Survey: FPGA PCB layout
131358: 08/04/20: Re: Survey: FPGA PCB layout
131391: 08/04/21: Re: Survey: FPGA PCB layout
131426: 08/04/21: Re: Survey: FPGA PCB layout
131627: 08/04/26: Re: Survey: FPGA PCB layout
131646: 08/04/27: Re: Survey: FPGA PCB layout
131651: 08/04/27: Re: Survey: FPGA PCB layout
Michael Alan Filippo:
3177: 96/04/19: Do ECL, PECL gate arrays or FPGAs exist?
MICHAEL ALEX:
42072: 02/04/15: Re: iMPACT FPGA detection error
42153: 02/04/17: Re: JTAG cable and iMPACT
42154: 02/04/17: Re: FPGA Timing Problem
42336: 02/04/21: Re: Looking for SpartanXL demo board
45169: 02/07/14: EDIF netlist from XST
Michael Alexander - EECS:
5563: 97/02/25: ISPD-97 Advance Pgm & Registration: (April 14-16, Napa CA)
6519: 97/05/30: New Reconfigurable Computing newsgroup?
Michael Amling:
40453: 02/03/07: Re: Announcement: Freely available AES/Rijndael Core in Virtex FPGAs
Michael Ardai:
46891: 02/09/10: Looking for programming algorithm for Xilinx 18v00 family
Michael Attenborough:
55248: 03/05/01: ModelSim 5.4d eats up memory as the simulation progresses
55440: 03/05/08: Re: ModelSim 5.4d eats up memory as the simulation progresses
59011: 03/08/06: Behaviour of Xilinx 'LDC' cell - simulation model doesn't match documentation
Michael Ayton:
16240: 99/05/11: Re: Need Altera 10k Prototype bd
16406: 99/05/20: Re: Is schmitt trigger possible with Xilinx 9536?
17281: 99/07/15: Re: Mixed Design Problem (FPGA Express/ACTEL)
18707: 99/11/08: PLD Quesiton
18708: 99/11/08: Reverse Engineering a 16L8
Michael Barr:
15229: 99/03/15: New Book: Programming Embedded Systems in C and C++
15605: 99/04/02: New Book: Programming Embedded Systems in C and C++
15591: 99/04/01: Re: Reconfigurable Computing
15839: 99/04/16: Re: High speed reconfigurability
16000: 99/04/27: Embedded Systems Resources
16380: 99/05/19: Re: High Speed Reconfigurability, Re:
16523: 99/05/26: Re: C to VHDL translator?
16721: 99/06/04: Re: FPGA Introduction is needed, right?
17252: 99/07/15: Embedded Systems Resources
20026: 00/01/24: Embedded Glossary and Bibliography
22345: 00/05/05: ANNOUNCE: Embedded Systems Glossary and Bibliography
23134: 00/06/15: ANNOUNCE: Embedded Systems Glossary and Bibliography
23135: 00/06/15: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
23898: 00/07/14: Embedded Systems Resources
26286: 00/10/10: ANNOUNCE: Bibliography Update!
26927: 00/11/03: ANNOUNCE: Memory Test Code/Article
27011: 00/11/07: ANNOUNCE: New article about Network Processors
27026: 00/11/08: Re: ANNOUNCE: New article about Network Processors
27218: 00/11/15: ANNOUNCE: Checksum and CRC Code/Article
29033: 01/02/02: ANNOUNCE: New Article on Run-Time Calibration
Michael Baxter:
4575: 96/11/16: Re: Async with FPGA?
4589: 96/11/18: Re: Async with FPGA?
4608: 96/11/20: Re: Async with FPGA?
Michael Bills:
55598: 03/05/13: Spartan3 DLL?
55842: 03/05/21: Re: problem with modelsim 5.7d on winXP system
55887: 03/05/22: Spartan 3 Power up
55888: 03/05/22: Re: Spartan 3 Power up
Michael Bodenbach:
86891: 05/07/08: Re: Running prog from PROM
86948: 05/07/11: Re: Search for FPGA
92489: 05/11/30: Xilinx EDK GPIO IP with FIFO function (input only)
Michael Boehnel:
23761: 00/07/07: Virtex Debug
25567: 00/09/14: Ethernet MII + bit ordering
26494: 00/10/18: F3.1i, Win2k, LMACs
26497: 00/10/18: Re: F3.1i, Win2k, LMACs
27845: 00/12/12: Synplify PRO 6.1 + Foundation 3.1i
27849: 00/12/12: Re: Synplify PRO 6.1 + Foundation 3.1i
27853: 00/12/12: Re: Synplify PRO 6.1 + Foundation 3.1i
27866: 00/12/13: Re: Synplify PRO 6.1 + Foundation 3.1i
28341: 01/01/08: Foundation P&R + location constraint
28395: 01/01/11: Re: VIRTEX : pad location
28561: 01/01/17: Re: Foundation P&R + location constraint
28628: 01/01/18: Tool to partially, dynamically reconfigure Virtex?
29135: 01/02/07: Re: 8B/10B Encoding
29544: 01/02/26: Virtex bidirectional pins
30244: 01/03/29: Re: Programmble Logic Sequencer
30265: 01/03/30: Re: Programmble Logic Sequencer
30500: 01/04/11: Exit F3.1 Simulator automatically?
32414: 01/06/26: Alpha Particle
33240: 01/07/20: FND Timing Simulator - Watch *
33311: 01/07/23: EDN
33832: 01/08/06: Bitgen persist option
33837: 01/08/06: Re: Bitgen persist option
34349: 01/08/22: Logic Emulation
34591: 01/08/30: Big SR in Virtex-E
34724: 01/09/05: Special counter for scheduling
34732: 01/09/05: Re: Special counter for scheduling
34753: 01/09/06: Re: Special counter for scheduling
34771: 01/09/07: Re: Special counter for scheduling
34773: 01/09/07: Re: Special counter for scheduling
34923: 01/09/14: Virtex-E1600 unsupported?
34931: 01/09/14: Re: Foundation 3.1i REINSTALLATION
34983: 01/09/17: Re: Virtex-E1600 unsupported?
35017: 01/09/18: Re: Virtex-E1600 unsupported?
36208: 01/11/02: Re: Synplicity, Xilinx, & unwanted BUFGs
36283: 01/11/05: Re: Synplyfy to Xilinx pipe
36456: 01/11/09: Unknown Timing Sim Warnings
36545: 01/11/12: Re: Unknown Timing Sim Warnings
37408: 01/12/10: Timing Simulation Model
38151: 02/01/07: Article FPGA + Reliable Systems
38305: 02/01/11: Runtime reconfiguration internals
38414: 02/01/14: Re: Runtime reconfiguration internals
38989: 02/01/29: Re: Soft errors climb in 0,13u SRAM
39471: 02/02/11: Sequential commands in statemachine
39475: 02/02/11: Re: Sequential commands in statemachine
40704: 02/03/13: Single-event upsets in ROM
43795: 02/06/03: FPGA destruction possible?
43844: 02/06/04: Re: FPGA destruction possible?
43854: 02/06/04: Re: FPGA destruction possible?
Michael Brown:
134002: 08/07/22: Xilinx FPGA editor tips?
134009: 08/07/22: Re: Xilinx FPGA editor tips?
134010: 08/07/22: Re: Xilinx FPGA editor tips?
135876: 08/10/20: Any more news on an Windows x64-compatible WebPack?
136380: 08/11/14: Re: Efficient clock dividers
136451: 08/11/18: Re: Digilent Spartan3e starter kit, Not working.
136456: 08/11/18: Re: Xilinx-3E Starter Kit - USB connection with Linux
136595: 08/11/25: Re: Student FPGAs
138421: 09/02/21: Re: Very fast counter in VirtexII
michael brown:
40686: 02/03/13: Re: Mystery two wire interface, or am I being dense?
40691: 02/03/13: Re: Mystery two wire interface, or am I being dense?
Michael C. Kim:
1916: 95/09/19: Re: Fast FPGA's?
1944: 95/09/22: Re: LFSR's solution
Michael Cameron:
171: 94/09/08: iFX780 problems
Michael Chan:
59133: 03/08/09: DDR-ram interface (xapp200)
59156: 03/08/11: Re: DDR-ram interface (xapp200)
59383: 03/08/18: Parallel interface to an FPGA
59427: 03/08/19: Re: random address
61474: 03/10/06: Free timing diagram drawing software
67026: 04/03/04: Jitter in DLLs vs PLLs
67075: 04/03/05: Re: mersenne twister
69025: 04/04/26: Re: PLL and DLL
69077: 04/04/27: Re: PLL and DLL
77528: 05/01/10: Clock Domains with PLL
77592: 05/01/12: Re: Clock Domains with PLL
77597: 05/01/12: Re: Clock Domains with PLL
90228: 05/10/07: Question about metastability that's been on my mind for a while
90237: 05/10/07: Re: Question about metastability that's been on my mind for a while
91928: 05/11/17: Suggestions on good books
91958: 05/11/18: Re: Suggestions on good books
99162: 06/03/21: Re: Urgent Help Needed!!!!!
Michael Condon:
55055: 03/04/25: Re: Boycott All Xilinx products untill they correct all ISE softwareerrors
55079: 03/04/25: Re: need help converting Verilog to VHDL
55207: 03/04/30: Re: Boycott All Xilinx products untill they correct all ISE softwareerrors
55237: 03/05/01: Re: Boycott All Xilinx products untill they correct all ISE softwareerrors
55382: 03/05/06: Re: flash-disk
Michael Covington:
4105: 96/09/11: Re: Quick and Easy Money (NOT A SCAM!)
Michael Cozza:
45456: 02/07/24: Field Programmable SoC's
Michael D. Scott:
3593: 96/07/02: LCA to Schematic
Michael Daldrup:
25396: 00/09/09: Tutorial for ABEl-HDL
Michael Dales:
31714: 01/06/04: Virtex LUT4 problems in FPGA Express
31717: 01/06/04: Re: Virtex LUT4 problems in FPGA Express
31753: 01/06/05: Re: Virtex LUT4 problems in FPGA Express
31756: 01/06/05: Re: Xilinx Configuration Bitstream
32140: 01/06/15: Using the Triscend A7 UART
32342: 01/06/23: Re: Virtex LUT4 problems in FPGA Express
56988: 03/06/20: Re: FPGA device + CPU
63737: 03/12/02: Triscend Fastchip software under Windows XP?
69800: 04/05/20: Trying to build simple demo using XPS and XC2VP20
70849: 04/06/30: Problems with custom IP in Xilinx Project Navigator
72289: 04/08/13: Using SDRAM on Xilinx AFX V2P board
72348: 04/08/16: Re: Using SDRAM on Xilinx AFX V2P board
72378: 04/08/17: Re: Using SDRAM on Xilinx AFX V2P board
73947: 04/10/01: COMMA_ALIGN_MSB being ignored?
73951: 04/10/01: Re: COMMA_ALIGN_MSB being ignored?
73956: 04/10/01: Re: COMMA_ALIGN_MSB being ignored?
74341: 04/10/08: 3.3 V ref VCC on Xilinx AFX FF1152 board?
76331: 04/11/30: System ACE programming solution?
85859: 05/06/17: IPIF LogiCore?
87163: 05/07/18: Lab machine xmd/debugger install?
87168: 05/07/18: Re: Lab machine xmd/debugger install?
103331: 06/05/31: Problems simulation plb_gemac core for Virtex-II Pro
Michael David Scott:
7314: 97/08/25: .vho file creation in MaxplusII
7500: 97/09/17: Altera Internal PLL
7793: 97/10/16: Re: I looked up Altera in an Italian dictionary.....
7801: 97/10/16: Re: I looked up Altera in an Italian dictionary.....
Michael Decosta III:
161: 94/09/05: Opal jr
Michael Dombrowski:
71483: 04/07/19: Re: 32-channel PC-based logic analyzers
Michael Dreschmann:
84127: 05/05/12: Update Picoblaze Code in Bitstream
84171: 05/05/13: Re: Update Picoblaze Code in Bitstream
84821: 05/05/28: Control asynchronous SRAM like synchronous SRAM
84829: 05/05/29: Re: Control asynchronous SRAM like synchronous SRAM
85631: 05/06/13: Searching FPGA board for private use
85723: 05/06/14: Re: Searching FPGA board for private use
86410: 05/06/27: USB 2.0 core with 1.1 tranceiver problem
86423: 05/06/28: Re: USB 2.0 core with 1.1 tranceiver problem
86424: 05/06/28: Re: USB 2.0 core with 1.1 tranceiver problem
86484: 05/06/29: Re: USB 2.0 core with 1.1 tranceiver problem
92319: 05/11/27: async fifo design
92358: 05/11/28: Re: async fifo design
92443: 05/11/30: Re: async fifo design
92501: 05/11/30: Re: async fifo design
106159: 06/08/08: 100 Mbit manchester coded signal in FPGA
106171: 06/08/08: Re: 100 Mbit manchester coded signal in FPGA
106180: 06/08/08: Re: 100 Mbit manchester coded signal in FPGA
106195: 06/08/09: Re: 100 Mbit manchester coded signal in FPGA
106196: 06/08/09: Re: 100 Mbit manchester coded signal in FPGA
134949: 08/09/08: No connect pins on xc4vfx20
135048: 08/09/12: Ultra low power FPGAs
135054: 08/09/12: Re: Ultra low power FPGAs
135081: 08/09/15: Re: Ultra low power FPGAs
135082: 08/09/15: Re: Ultra low power FPGAs
135083: 08/09/15: Re: Ultra low power FPGAs
136123: 08/11/03: 2D DCT algorithm
136261: 08/11/08: Re: 2D DCT algorithm
149256: 10/10/12: IODEALY with IOBUFDS in V6
Michael Dunbar:
60600: 03/09/17: Actel Desktop Schematic Viewer
60646: 03/09/18: Re: Actel Desktop Schematic Viewer
Michael Eisenring:
19797: 00/01/12: Benchmarks
Michael Ellis:
19681: 00/01/07: Re: Newbie question on CPU's
Michael Engel:
142916: 09/09/08: Spartan 3E current usage
144426: 09/12/05: Re: spartan 3 and multiprocessor
154481: 12/11/12: ST Micro GOSPL open source EDA tools?
155837: 13/09/28: Re: Legal Issues Reproducing Old CPU
Michael F. Coyle:
8260: 97/12/04: Re: what is metastability time of a flip_flop
8303: 97/12/06: Re: what is metastability time of a flip_flop
Michael Feygin:
35520: 01/10/09: Help in speeding up image processing
Michael Filippo:
3178: 96/04/19: ECL, PECL gate arrays or FPGA's
Michael Fluet:
26132: 00/10/04: 3DES VHDL
Michael G Wrighton:
18954: 99/11/22: Virtex FIFO w/ Block RAM
Michael G. Mansell:
7160: 97/08/07: FPGA help required immediately
Michael Gallen:
55215: 03/04/30: Re: Advice on FPGA IIR Filter
63524: 03/11/25: ANN: Tyd-IP Code Generator ....VHDL for DSP
64040: 03/12/13: Re: Question about filters and verilog etc..
Michael García Lorenz:
21861: 00/04/04: Curso gratuito de VHDL
Michael Garvie:
53814: 03/03/24: Permanent Local Damage to FPGA
53842: 03/03/25: Re: Permanent Local Damage to FPGA
53918: 03/03/27: Re: How failures happen, and how they don't
Michael Gauckler:
53624: 03/03/18: Modelsim - FPGA - Simulink integration
Michael Gernoth:
115910: 07/02/25: Xilinx Platform cable USB and impact on linux without windrvr
116638: 07/03/14: Re: Xilinx Platform cable USB and impact on linux without windrvr
117107: 07/03/23: Re: Xilinx Platform cable USB and impact on linux without windrvr
117108: 07/03/23: Re: Xilinx Platform cable USB and impact on linux without windrvr
120554: 07/06/09: Re: linux and USB JTAG at Spartan 3e starter
125964: 07/11/10: Re: Problem using xilinx usb download cable in linux
126028: 07/11/12: Re: Problem using xilinx usb download cable in linux
Michael Gillies:
16884: 99/06/16: Timing Benchmark for FPGA based DSP
Michael Greene:
2117: 95/10/17: Re: Bet you can't do these....
Michael Grunberg:
1195: 95/05/12: VMEbus interface logic in FPGA?
Michael Gschwind:
675: 95/02/03: CFP: IG/ITG Workshop on VLSI Architectures
734: 95/02/20: Re: Synopsys FPGA Compiler
1102: 95/04/28: Re: How to use XBLOX librariers in VHDL in Synopsys?
1793: 95/09/03: WWW Site about Synthesis for FPGAs
1939: 95/09/22: Re: Help needed-how to instantiate Xbloc component with synopsys
1940: 95/09/22: Re: Altera and Synopsys Interface
2367: 95/11/24: Re: request for synthesizable VHDL for RAM
Michael Hann:
1770: 95/08/29: Any FPGA FAQ?
Michael Hasselberg:
92: 94/08/13: Re: Would you like a free C to netlist compiler?
2346: 95/11/21: Re: [q][Reverse Engineering Protection]
Michael Helduser:
19388: 99/12/17: Altera Quartus 99.10
Michael Hennebry:
96436: 06/02/03: why such fast placement?
96620: 06/02/07: Re: why such fast placement?
97728: 06/02/26: Re: Combinatorial Division?
97792: 06/02/27: Re: Combinatorial Division?
97843: 06/02/28: Re: tricks to make large PLAs fast?
97990: 06/03/02: Re: Combinatorial Division?
100735: 06/04/17: Re: Counting bits
100867: 06/04/19: Re: Counting bits
101230: 06/04/27: Re: Spartan 3 documentation confusing...
Michael Hodson:
10527: 98/05/27: Re: Altera 10k pin function ??
10535: 98/05/28: Re: Altera FLEX8k configuration problem
Michael Holley:
3281: 96/05/08: Re: FPGA leaders - Who are they? Xilinx, Altera, Actel?
3321: 96/05/13: Re: Xilinx Mapping & Placing in HDL
4509: 96/11/06: A new vendor for Xilinx parts.
Michael Hopey:
23806: 00/07/10: AHDL question
Michael Hosemann:
33431: 01/07/26: Architecture Evaluation Tools
48841: 02/10/25: FPGA board recommendation
Michael Ismert:
4549: 96/11/13: AAL5 SAR Design?
Michael J Sharples:
15104: 99/03/06: micro computer using Xilinx
15176: 99/03/10: Re: micro computer using Xilinx
Michael J Watts:
6134: 97/04/15: Re: Cadence dfII Layout Plotter: which type are the best solution ?
Michael J.:
44173: 02/06/13: Altera APEX reconfigurates endlessly
44223: 02/06/14: Re: Altera APEX reconfigurates endlessly
Michael J. Alexander:
6554: 97/06/02: Re: New Reconfigurable Computing newsgroup?
Michael J. Ferrador:
21655: 00/03/28: Re: FPGA openness
Michael J. Johnson:
9857: 98/04/09: Summer Job
Michael J. Kelly:
24233: 00/07/31: Re: Spartan-II / Virtex-E / DC linear regulators
Michael J. Wirthlin:
202: 94/09/20: Re: Partly reconfigurable FPGAs
1079: 95/04/25: How much performance is enough?
1069: 95/04/24: Re: (none)
1125: 95/05/02: Re: Compression algo's for FPGA's
1168: 95/05/10: Re: Compression algo's for FPGA's
1422: 95/06/20: Re: Low cost ISA board
1439: 95/06/22: Re: Low cost ISA board
1976: 95/09/27: Re: NEW person
2276: 95/11/16: Re: [Q] FPGA Software for Linux
3213: 96/04/26: Re: run time reconfiguration
Michael J?rgensen:
121081: 07/06/25: Re: How to choose FPGA for a huge computation?
Michael Johnen:
32833: 01/07/10: assigning signals with Altera Max+PlusII vhdl
Michael Johnson:
3690: 96/07/16: Radiation resistance
"Michael Jones":
1752: 95/08/25: Re: Quicklogic/Cypress/Warp3
1767: 95/08/29: Re: AMD MACH eval package ?
1772: 95/08/29: Re: AMD MACH eval package ?
2963: 96/03/06: Re: Languages for reconfigurable computing.
7602: 97/09/25: Re: Hacking bitstream formats
Michael Jřrgensen:
116581: 07/03/13: Re: VHDL and Latch
116668: 07/03/15: Re: .bit file to VHDL/verilog source code
116689: 07/03/15: Re: .bit file to VHDL/verilog source code
121121: 07/06/26: Re: Graduate/Junior FPGA Designer concerns
121122: 07/06/26: Re: Graduate/Junior FPGA Designer concerns
Michael K. Hinazumi:
152: 94/09/01: Re: QuickLogic (was Re: FPGA Hobbyist...)
169: 94/09/07: Re: QuickLogic (was Re: FPGA Hobbyist...)
Michael Karas:
148987: 10/09/18: Re: interrupt handler arguments
149716: 10/11/20: Re: Multiple Reset Inputs
152376: 11/08/16: Re: Help needed to emulate a microcontroller.
152793: 11/10/23: Re: FPGA development
152794: 11/10/23: Re: FPGA development
153525: 12/03/24: Re: Spartan 3A counter speed ?
153541: 12/03/26: Re: Digital Tachometer VHDL
153818: 12/05/27: Re: Xilinx ISE Multiple Drivers Error
153981: 12/07/07: Re: XC9500XL keeper ?
Michael Keith:
153273: 12/01/23: Re: Semi-OT: Good Tcl Book
Michael Kellett:
147882: 10/05/29: Re: Anyone else need bigger parts in small (low pin count) packages
148115: 10/06/22: Re: Xilinx BULLSHITIX-8, when?
148714: 10/08/18: Re: Getting started with FPGA
148737: 10/08/19: Re: CE compliance testing
149234: 10/10/11: Re: Is Spartan 6 good for this project?
149918: 10/12/02: Re: Help for a embeded system with SPARTAN-6 project
149947: 10/12/03: Re: Opinions on Lattice ECP3
150657: 11/02/01: Re: Looking for contractor for FPGA-based multiUART
150695: 11/02/04: Re: Trivia: Where are you on the HDL Map?
151390: 11/04/01: Re: Ideal FPGA Development Kit
158035: 15/07/25: Free Lattice FPGA
158350: 15/10/23: Re: DC Blocker
158609: 16/01/23: Re: Altera MAX10 image capture application
159217: 16/09/03: Re: Help me choose an FPGA to design network protocols
159997: 17/05/07: Re: Lattice iCE40 UltraLite DIPSY - what happened?
160001: 17/05/09: Re: Lattice iCE40 UltraLite DIPSY - what happened?
160118: 17/06/01: Re: baud_generator (16x baud) used in UART transmitter logic
160142: 17/06/20: Re: Create FPGA to replace 1974 MOSTEK MK5017
160165: 17/06/23: Re: VHDL or Verilog?
160636: 18/07/02: Re: Stepper motor controller
160637: 18/07/02: Re: 8 bits vs. 9 bits in RAM Blocks
160645: 18/08/11: Re: FPGA simplest processor
160654: 18/08/16: Re: FPGA simplest processor
160659: 18/09/04: Re: What to do with an improved algorithm?
160666: 18/09/07: Re: Need Advice regarding Interfacing of Max9850 audio DAC with
160724: 18/10/27: Re: FPGA Market Entry Barriers
161166: 19/02/08: Re: Is it possible to implement Ethernet on bare metal FPGA, Without
161372: 19/06/13: Re: bare-metal ZYNQ
161378: 19/06/14: Re: bare-metal ZYNQ
161381: 19/06/15: Re: bare-metal ZYNQ
161386: 19/06/16: Re: bare-metal ZYNQ
161387: 19/06/16: Re: bare-metal ZYNQ
161388: 19/06/16: Re: bare-metal ZYNQ
161496: 19/11/09: Re: FPGA config sizes
161505: 19/11/12: Re: Lattice XO3D New
161508: 19/11/13: Re: Lattice XO3D New
161527: 19/11/26: Re: New coding method for a state machine in groups in HDL
161533: 19/11/27: Re: New coding method for a state machine in groups in HDL
161534: 19/11/27: Re: New coding method for a state machine in groups in HDL
161549: 19/11/29: Re: Lattice's ECP5 - half of the program went MIA - WTF ?
161582: 19/12/05: Re: Efinix and their new Trion FPGAs -
161591: 19/12/11: Re: Efinix and their new Trion FPGAs -
Michael Kim:
2134: 95/10/18: one-hot encoding for fsm's
Michael Kleinkes:
42607: 02/04/29: Re: Hack an bitstream file for AT40Kxx
42617: 02/04/29: MGL Editor for AT40K
Michael Koch:
5305: 97/02/05: Re: DES Challenge
5324: 97/02/06: Re: DES Challenge
5408: 97/02/14: Installation Problem with ACTEL Designer 3.1 on SunSolaris
Michael Kohne:
31230: 01/05/16: Counter problem in Altera AHDL...
31247: 01/05/16: Re: Counter problem in Altera AHDL...
33178: 01/07/18: possibly stupid lpm_fifo question...
33189: 01/07/19: Re: possibly stupid lpm_fifo question...
Michael Kraemer:
109970: 06/10/09: Quartus II 6.0: System clock has been set back
109978: 06/10/09: Re: Quartus II 6.0: System clock has been set back
Michael Kramer:
92300: 05/11/26: Distributed RAMs / SRL: Why not, Altera?
92307: 05/11/27: Re: Distributed RAMs / SRL: Why not, Altera?
92320: 05/11/27: Re: Distributed RAMs / SRL: Why not, Altera?
Michael Kwak:
12149: 98/10/01: open drain output in Altera MAX7000S
Michael L. Bates:
2553: 96/01/02: Re: Need help: Actel "bibuf" working with Quicksim II (Men 8.4)
Michael Laajanen:
14296: 99/01/23: Re: Hard porting to FPGA Express
96435: 06/02/03: quartus and VHDL/Verilog libraries
96482: 06/02/04: Xilinx compxlib error using VCS
96660: 06/02/08: Re: vhdl to edif
96672: 06/02/08: Re: vhdl to edif
96705: 06/02/09: Re: vhdl to edif
100868: 06/04/19: XILINX 7.1 EDK Solaris 10
103876: 06/06/14: Quartus 6.0 and VCS
106447: 06/08/13: Altera Cyclone-II FIFOs
106451: 06/08/13: Re: Altera Cyclone-II FIFOs
117142: 07/03/23: Solaris 10
126554: 07/11/27: Fedora 8 and ISE 9.2
126792: 07/12/02: Re: Fedora 8 and ISE 9.2
126848: 07/12/04: XILINX XABEL
126865: 07/12/05: Re: XILINX XABEL
127736: 08/01/06: Xilinx MIG onm Solaris
127771: 08/01/08: Re: Xilinx MIG onm Solaris
127944: 08/01/11: Re: Multiple UCF support in Xilinx ISE
128008: 08/01/12: Re: Multiple UCF support in Xilinx ISE
128494: 08/01/29: Re: Active-HDL 7.3 vs Modelsim 6.3d-PE (for Verilog/Systemverilog)
128516: 08/01/29: Re: Active-HDL 7.3 vs Modelsim 6.3d-PE (for Verilog/Systemverilog)
153053: 11/11/24: Xilinx chipscope via Virtualbox
153059: 11/11/24: Re: Xilinx chipscope via Virtualbox
153107: 11/12/02: Re: XC7V2000T, the perfect Thanksgiving gift
153124: 11/12/08: Re: Xilinx 7 series PCIe core models vs. Icarus Verilog
153125: 11/12/08: Re: Horsepower On Tap
153129: 11/12/08: Re: Horsepower On Tap
153130: 11/12/08: Re: Xilinx 7 series PCIe core models vs. Icarus Verilog
153134: 11/12/09: Re: Horsepower On Tap
153143: 11/12/12: Re: D-Type Flip flop with negated Q in Webise for a schematic capture
Michael Lawnick:
79302: 05/02/17: Re: PPC405 sleep?
79318: 05/02/17: Re: PPC405 sleep?
Michael Lee:
19682: 00/01/07: Re: Design security
21645: 00/03/27: Re: Difference between FPGA, PLD, CPLD ?
Michael Lees:
6277: 97/05/08: Test do not read
Michael Leibowitz:
16: 94/07/28: What should I use
Michael Ljunggren:
24875: 00/08/21: Usage of ROC (Foundation 2.1i)
Michael Lodman:
2547: 95/12/30: Re: Career value: VHDL or Verilog?
2554: 96/01/02: Re: Career value: VHDL or Verilog?
2596: 96/01/10: Re: [q][Reverse Engineering Protection]
Michael Long:
2958: 96/03/05: ABEL
michael m:
42962: 02/05/08: Bit file format
Michael M.Y. Hui:
2562: 96/01/02: Re: Career value: VHDL or Verilog?
2780: 96/02/06: Re: Chosing VHDL or Verilog Does Have An Impact For U.S. Engineers
Michael McGuirk:
84413: 05/05/18: Re: open support question to Xilinx. should be fairly simple to answer.
Michael McNamara:
2513: 95/12/21: Re: Career value: VHDL or Verilog?
9322: 98/03/06: Re: The case for Linux and EDA
Michael Meeuwisse:
128700: 08/02/04: Possible CRC error on XC3S400 - now what?
128730: 08/02/05: Re: Possible CRC error on XC3S400 - now what?
128734: 08/02/05: Re: Possible CRC error on XC3S400 - now what?
128750: 08/02/05: Re: Possible CRC error on XC3S400 - now what?
128758: 08/02/05: Re: Possible CRC error on XC3S400 - now what?
128795: 08/02/06: Re: Possible CRC error on XC3S400 - now what?
128826: 08/02/07: Re: Possible CRC error on XC3S400 - now what?
128862: 08/02/07: impact bug or wrong interpretation of xsvf layout?
128884: 08/02/08: Re: impact bug or wrong interpretation of xsvf layout?
128892: 08/02/08: Re: Looking for a development board
128893: 08/02/08: Re: impact bug or wrong interpretation of xsvf layout?
131109: 08/04/11: Split register in smaller segments
131111: 08/04/11: Re: Split register in smaller segments
131114: 08/04/11: Re: Split register in smaller segments
Michael Mellone:
33606: 01/07/31: Programming Altera EPC16
Michael Metzner:
147907: 10/06/01: Re: Graphical User Interface project on Spartan-3 FPGA
Michael Milway:
123: 94/08/18: fpga family help
Michael Moller:
7335: 97/08/28: Re: VHDL Synthesis for Linux?
7324: 97/08/27: VHDL Synthesis for Linux?
Michael Morell:
30472: 01/04/09: Hot - FPGA System Design Engineer
Michael Mustermann:
71590: 04/07/23: XILINX RocketIO / MGT signal quality problems
71716: 04/07/28: Re: XILINX RocketIO / MGT signal quality problems
71778: 04/07/30: Re: XILINX RocketIO / MGT signal quality problems
Michael N. Moran:
124738: 07/10/02: Re: Basic VHDL Development kit
130576: 08/03/27: Re: A Challenge for serialized processor design and implementation
Michael Nicklas:
48488: 02/10/18: Cyclic Redundancy Check generator
48496: 02/10/18: Testbenches
48641: 02/10/22: Re: Cyclic Redundancy Check generator
48846: 02/10/25: Xilinx ISE 4.2i Student edition on Windows XP
53012: 03/02/28: Avnet Cilicon Xilinx Virtex-E development kit
53128: 03/03/04: Re: Avnet Cilicon Xilinx Virtex-E development kit
54009: 03/03/31: ModelSIM XE wave files
54016: 03/03/31: Re: ModelSIM XE wave files
54055: 03/04/01: Re: ModelSIM XE wave files
54138: 03/04/03: Xilinx MicroBlaze opinions
55233: 03/05/01: mcs files
55236: 03/05/01: Re: mcs files
56753: 03/06/13: Altering implementation options in ISE 5.1i
58065: 03/07/14: library issues
58128: 03/07/15: what are libraries for??
58264: 03/07/18: Logiblox library
58337: 03/07/21: Logiblox library - help please!
Michael Niechziol:
5896: 97/03/24: ZYCAD's 'browse'
Michael P. Hartnett:
276: 94/10/11: Multipliers in FPGA's
Michael Paar:
32939: 01/07/12: Re: file flush in VHLD for synopsys VSS
Michael Payne:
4168: 96/09/21: Q: PLD vs. FPGA
4170: 96/09/21: What's the difference between PLD and FPGA?
4171: 96/09/21: What's the difference between PLD and FPGA?
Michael Petry:
58591: 03/07/28: xilinx programing interface
Michael Pieber:
78871: 05/02/09: Beginner question: How to interface ram an Memec Spartan IIE - Board
81008: 05/03/16: Help with ram controller on Xilinx Spartan IIE
81068: 05/03/17: Re: Help with ram controller on Xilinx Spartan IIE
Michael Polovykh:
79386: 05/02/18: Re: CRC-4 algorithm using in G.704(&G.706)
79387: 05/02/18: Re: CRC-4 algorithm using in G.704(&G.706)
79390: 05/02/18: Re: CRC-4 algorithm using in G.704(&G.706)
79580: 05/02/21: Re: Is Altera Cyclone a good choice ?
79589: 05/02/21: Re: Is Altera Cyclone a good choice ?
79632: 05/02/22: Re: Is Altera Cyclone a good choice ?
Michael Pot:
571: 95/01/08: Re: Xchecker programming limits
Michael Quinlan:
4684: 96/11/29: Re: Addressbility.
Michael R. Harris:
1669: 95/08/13: Re: Xilinx PROMs
Michael R. Kesti:
92586: 05/12/01: Re: Quick question, how do I supply +-5V?
Michael R. Palmer:
7287: 97/08/21: make problem
Michael Randelzhofer:
24424: 00/08/08: Place&Route report of spartan2
25407: 00/09/11: Re: How many 4005s (4010s) does it take to make a general purpose CPU?
27920: 00/12/15: Re: Setup violation
Michael Rhotert:
25684: 00/09/17: Re: Are SpartanIIs in FG456 drop in replacements for Virtex FG456
25685: 00/09/17: Re: Virtex clock fanout
43679: 02/05/29: Re: XST since ISE 4.x can actually generate an EDIF netlist!!!
43938: 02/06/06: Re: XST since ISE 4.x can actually generate an EDIF netlist!!!
43939: 02/06/06: Re: XST since ISE 4.x can actually generate an EDIF netlist!!!
44237: 02/06/14: Re: Xilinx primitives & ModelSim
45637: 02/07/30: Re: Dual Port Block RAM
49501: 02/11/13: Re: EDIF generation from XST of ISE 5.1i
54018: 03/03/31: Re: ModelSIM XE wave files
55708: 03/05/16: Re: Exploting the DDR input registers in Virtex2
69057: 04/04/26: Re: pcix core master dma
70393: 04/06/15: Re: pulse generation using SRL16E on a Virtex-II
70512: 04/06/18: Re: How to create an EDIF file from ISE Foundation?
94703: 06/01/16: Re: How to drive 4 output ports with one combinational signal
Michael Rickey:
1821: 95/09/06: Looking for a Chip Supplier
Michael Ruettger:
1859: 95/09/11: Re: Re: pci board design guide
Michael S:
49607: 02/11/17: Re: Metastability in FPGAs
49630: 02/11/18: Re: Metastability in FPGAs
49633: 02/11/18: Re: Metastability in FPGAs
49653: 02/11/18: Re: Metastability in FPGAs
49683: 02/11/19: Re: Metastability in FPGAs
49685: 02/11/19: Re: Metastability in FPGAs
49686: 02/11/19: Re: Metastability in FPGAs
49899: 02/11/24: Re: Global clock routing
50030: 02/11/28: Re: Metastability in FPGAs
51468: 03/01/14: Re: SChematic design approach compared to VHDL entry approach
51711: 03/01/20: Re: PLX PCI DMA address
53547: 03/03/15: Re: Cyclone power up problem - Summery
53663: 03/03/19: Re: Cyclone power up problem - Summery
53734: 03/03/20: Re: Using FPGAs as coprocessors in a PC
53792: 03/03/23: Re: Using FPGAs as coprocessors in a PC - findings
53801: 03/03/24: Re: FPGA FFT Questions
53836: 03/03/25: Re: FPGA FFT Questions
53885: 03/03/26: Re: FPGA FFT Questions
54054: 03/04/01: Re: [Question] FPGA/PLX9054
54068: 03/04/01: Re: [Question] FPGA/PLX9054
54070: 03/04/01: Re: DSP-FPGA interface
54256: 03/04/06: Re: Xilinx announces 90nm sampling today!
54519: 03/04/12: Re: fastest PLD
55327: 03/05/04: Re: PLL chips
55515: 03/05/11: Re: Altera Flex EPF81188A
55621: 03/05/14: Re: how to calculate the gate count required for a FPGA design
55993: 03/05/26: Re: New Architectures
57415: 03/06/30: Re: MIPS instruction set?
57418: 03/06/30: Quartus produces wrong parameters for Stratix PLL
57472: 03/07/01: Re: Quartus produces wrong parameters for Stratix PLL
58122: 03/07/15: Is a Virtex-II Pro family a hands-down winner for DSP ?
58226: 03/07/17: Re: Is a Virtex-II Pro family a hands-down winner for DSP ?
58440: 03/07/23: Re: asynchronous FIFO
58704: 03/07/31: Re: DDS question. How to generate a square from a sine wave?
58864: 03/08/03: Re: Speed Grade...
64273: 03/12/23: Re: Spartan3 availability
64283: 03/12/24: Re: Spartan3 availability
64287: 03/12/24: Re: Spartan3 availability
68316: 04/04/01: Re: Quartus removes Tristate Buffer
68336: 04/04/01: Re: Quartus removes Tristate Buffer
70078: 04/06/01: Seven leading PC processors benchmarked on Quartus-II Web Ed place&route
144159: 09/11/14: Altera Stratix IV GX Dev.Kit: PCI-E x4 device doesn't work in x8 slot
144271: 09/11/23: Re: Altera Stratix IV GX Dev.Kit: PCI-E x4 device doesn't work in x8
144272: 09/11/23: Re: Altera Stratix IV GX Dev.Kit: PCI-E x4 device doesn't work in x8
144277: 09/11/24: Re: NIOS and ftoa()
144291: 09/11/25: Re: Going mad trying to solve PLL setup/hold timing violation issues
144368: 09/12/01: Re: Altera Stratix IV GX Dev.Kit: PCI-E x4 device doesn't work in x8
144945: 10/01/16: Re: Altera Quartus II on Debian GNU/Linux
144949: 10/01/17: Re: Altera Quartus II on Debian GNU/Linux
145214: 10/02/01: Re: In system memory editor of Altera for Xilinx
145215: 10/02/01: Re: In system memory editor of Altera for Xilinx
145217: 10/02/01: Re: In system memory editor of Altera for Xilinx
145541: 10/02/13: Re: VHDL vs Verilog
145840: 10/02/25: Re: FPGA platform??
145924: 10/02/28: Re: Frustration with Vendors!
145936: 10/02/28: Re: Frustration with Vendors!
145949: 10/03/01: Re: Frustration with Vendors!
146140: 10/03/06: Re: Laptop for FPGA design?
146141: 10/03/06: Re: Laptop for FPGA design?
146172: 10/03/07: Re: Laptop for FPGA design?
146178: 10/03/07: Re: Laptop for FPGA design?
146558: 10/03/22: Re: Why hardware designers should switch to Eclipse
146770: 10/03/28: Re: Maximum output rate
146781: 10/03/28: Re: Maximum output rate
146800: 10/03/29: Re: Maximum output rate
147524: 10/04/29: Re: xilinx arm finally announced
148025: 10/06/14: Re: Altera Quartus - how to create small roms & rams for Cyclone 3
148246: 10/07/01: Re: DMA operation to 64-bits PC platform
148273: 10/07/03: Re: DMA operation to 64-bits PC platform
148274: 10/07/03: Re: DMA operation to 64-bits PC platform
148276: 10/07/04: Re: DMA operation to 64-bits PC platform
148280: 10/07/04: Re: DMA operation to 64-bits PC platform
148290: 10/07/05: Re: xilinx leadtimes
148292: 10/07/05: Re: xilinx leadtimes
148305: 10/07/06: Re: DMA operation to 64-bits PC platform
148306: 10/07/06: Re: DMA operation to 64-bits PC platform
148647: 10/08/11: Re: DMA operation to 64-bits PC platform
148815: 10/08/28: Re: Stratix iv PLLs ref clock
149045: 10/09/23: Re: Xilinx dropping Modelsim XE
149326: 10/10/16: Re: FPGA or CPLD?
149824: 10/11/25: Re: Atom 6000C perspective, anyone?
150300: 11/01/09: Re: OT: Fast Circuits
150301: 11/01/09: Re: OT: Fast Circuits
150303: 11/01/09: Re: OT: Fast Circuits
152888: 11/10/30: Re: Altera FPGA weirdness
152904: 11/10/31: Re: Altera FPGA weirdness
152966: 11/11/05: Re: Choose between Cyclone II and Spartan II
152969: 11/11/06: Re: PCI Express development board
152976: 11/11/07: Re: PCI Express development board
153010: 11/11/12: Re: PCI Express development board
153017: 11/11/14: Re: PCI Express development board
153019: 11/11/15: Re: PCI Express development board
153465: 12/03/03: Re: configuring an Altera Cyclone 3
153580: 12/04/01: Re: FPGA + Mess o' RAM
153582: 12/04/01: Re: Low latency FPGA options
154393: 12/10/22: Re: tell QuartusII to use registers and not RAM
154411: 12/10/27: Re: Altera delivery
154413: 12/10/27: Re: Altera delivery
154416: 12/10/27: Re: Altera delivery
154564: 12/11/28: Re: VHDL expert puzzle
154565: 12/11/28: Re: VHDL expert puzzle
154566: 12/11/28: Re: VHDL expert puzzle
154574: 12/11/29: Re: VHDL expert puzzle
154579: 12/11/29: Re: VHDL expert puzzle
154581: 12/11/29: Re: VHDL expert puzzle
154677: 12/12/16: Re: DC fifo behaviour at underflow/overflow
154679: 12/12/16: Re: DC fifo behaviour at underflow/overflow
154681: 12/12/16: Re: DC fifo behaviour at underflow/overflow
154683: 12/12/16: Re: DC fifo behaviour at underflow/overflow
154684: 12/12/16: Re: DC fifo behaviour at underflow/overflow
154686: 12/12/16: Re: DC fifo behaviour at underflow/overflow
154688: 12/12/16: Re: DC fifo behaviour at underflow/overflow
154691: 12/12/17: Re: DC fifo behaviour at underflow/overflow
154692: 12/12/17: Re: DC fifo behaviour at underflow/overflow
154728: 12/12/29: Re: Which to learn: Verilog vs. VHDL?
154770: 13/01/06: Re: Chisel as alternative HDL
154785: 13/01/09: Re: Which to learn: Verilog vs. VHDL?
154787: 13/01/10: Re: Which to learn: Verilog vs. VHDL?
154790: 13/01/10: Re: Which to learn: Verilog vs. VHDL?
154796: 13/01/10: Re: Which to learn: Verilog vs. VHDL?
154881: 13/01/26: Re: Ray Andraka's Book?
154906: 13/02/12: Re: Idea Hunt, FPGA + ARM Cortex-M3
Michael Schmid:
10268: 98/05/08: Re: Help: 25Mhz XC4025E-2 FPGA having hold time errors during simulation
10339: 98/05/13: Re: Help: 25Mhz XC4025E-2 FPGA having hold time errors during simulation
18713: 99/11/09: Re: Problems in Viewlogic's Workview office
18927: 99/11/22: Re: Programming Virtex device via JTAG
19038: 99/11/25: Re: Programming Virtex device via JTAG
19058: 99/11/26: Re: Programming Virtex device via JTAG
24000: 00/07/20: Foundation 3.1i in Germany
24010: 00/07/21: Re: Foundation 3.1i in Germany
24029: 00/07/24: Re: 17 clocks in a Virtex
73639: 04/09/27: Re: embedded linux on FPGA?
Michael Schmidl:
46223: 02/08/21: combinatorial clocks
Michael Schnell:
4260: 96/10/07: 1 Download -> alle Mails in allen Global foren weg
Michael Schuerig:
16436: 99/05/21: Re: High Speed Reconfigurability
Michael Schumacher:
7621: 97/09/29: design Simple Video chip with FLEX10K30 ?
8439: 97/12/15: parallel counters: which device is suitable?
Michael Schuster:
77531: 05/01/10: Starting with xilinix and Linux
77602: 05/01/12: Re: Starting with xilinix and Linux
77610: 05/01/12: Re: Starting with xilinix and Linux
77612: 05/01/12: Re: Starting with xilinix and Linux
77642: 05/01/13: Re: Starting with xilinix and Linux
77643: 05/01/13: Re: Starting with xilinix and Linux
77658: 05/01/13: Re: Starting with xilinix and Linux
77660: 05/01/13: Re: Starting with xilinix and Linux
77789: 05/01/17: Re: Starting with xilinix and Linux
90315: 05/10/10: Re: evaluation edk in Spartan-3 starter kit
90862: 05/10/24: Re: evaluation edk in Spartan-3 starter kit
90962: 05/10/26: Re: evaluation edk in Spartan-3 starter kit
91526: 05/11/08: Re: Suggestions/Recommendations with CPLD's and Software
Michael Schwingen:
143055: 09/09/17: Re: To Xilinx: Regarding the download manager
143560: 09/10/16: Spam / was: Win a Dev Kit--Join Us on Twitter & Facebook
145321: 10/02/05: Re: using an FPGA to emulate a vintage computer
148782: 10/08/22: Re: CE compliance testing
Michael Seery:
153320: 12/01/31: Re: Active-HDL/Xilinx Core FIFO Gen Sim Problem
Michael Smith:
71347: 04/07/15: Re: FSM in illegal state (conclusion)
Michael Spencer:
24691: 00/08/16: jpeg 2000
59905: 03/09/01: Compact FIR filters with multiplier blocks?
Michael Stanton:
18258: 99/10/11: Re: Can't detect Flex 10K Altera device through JTAG port
18917: 99/11/22: Re: configure_flex10k30e_jtag_jam
19401: 99/12/20: Re: JamPlayer and 10K10
19418: 99/12/21: Re: JamPlayer and 10K10
Michael Stevens:
32417: 01/06/26: Re: Xilinx Configuration Bitstream
Michael Strayer:
34914: 01/09/13: Specifing global clocks on a Spartan II (Newbee Quest)
Michael Strothjohann:
26913: 00/11/03: Re: cryptography/Block ciphers
27207: 00/11/15: Re: Des warning matter?
27235: 00/11/16: Re: Basic question on PLD & FPGA
27236: 00/11/16: Re: Xilinx Foundation Sudent Version 1.5
27289: 00/11/17: Re: VHDL & Spartan: How to power-up a Register to '1' ?
27291: 00/11/17: Re: Can FPGA perform float point calculation?
27439: 00/11/22: Re: Low Power FPGA?
29137: 01/02/07: Re: 8B/10B Encoding
29396: 01/02/19: Re: Emacs VHDL Mode 3.31 released
30202: 01/03/28: Re: speech
30880: 01/05/02: Re: ccd imaging with fpga
31219: 01/05/15: Re: FREE IP CORES
31644: 01/06/01: Re: Help on Xilinx 6200
32313: 01/06/22: Re: Xilinx Software free
32660: 01/07/04: Re: uart rs232? (for free)
33216: 01/07/19: Re: Xilinx WebPACK - ROM
33217: 01/07/19: Re: SystemC
33219: 01/07/19: Re: SystemC
Michael T. Horne:
11707: 98/09/02: A critique of the Synopsys/Mentor Design Reuse Methodology Manual
11724: 98/09/03: Way-Cool Verilog and VHDL Quick Reference Cards Available
11937: 98/09/20: Revision 1.27 of David Black's LOGSCAN utility in Qualis Library
12199: 98/10/04: Paper on "Managing VHDL Models with Makefiles" in the Qualis library
12846: 98/11/01: New Online Seminar in the Qualis Library: "A Strategic Process for System-Level Verification"
12873: 98/11/03: New additions to the Qualis Library: SoC Verification, RMM review, point tools
13091: 98/11/15: New in the Qualis Library: SoC Verification Online Seminar, Behavioral Synthesis hints, more
16659: 99/06/01: New in the Qualis Library: BC case studies, design reuse, productivity scripts, info resources
16665: 99/06/01: Special Workshop on Design Reuse, June 16-17-18, San Jose, CA
16804: 99/06/09: Last chance to register: Workshop on Design Reuse, June 16-17-18, San Jose, CA
Michael T. Mayers:
3901: 96/08/16: PCI FPGA card
Michael Tchou:
0: 94/07/27: This (new) froup
8: 94/07/28: Re: This (new) froup
130: 94/08/18: Re: FPGA Hobbyist and their software/programmer/hardware
Michael Thompson:
3134: 96/04/10: Re: Sun bpp bidirectional parallel port
Michael Thomsen:
94341: 06/01/10: Re: Programming Xilinx PowerPC
Michael Tornow:
47512: 02/09/27: Quartus 2 Error: "Full compilation was cancelled due to an error"
47936: 02/10/08: Re: Quartus 2 Error: "Full compilation was cancelled due to an error"
Michael Traxler:
11534: 98/08/21: professional autorouters
Michael Tremel:
1243: 95/05/22: Searching >Programmable Logic - News and View<
Michael Trim:
129181: 08/02/17: Re: Linux and the Digilent Basys ?
131149: 08/04/12: Re: ISE 9.2 and Windriver
Michael Tzvetkov:
32565: 01/06/30: Re: Xilinx System Generator Simulation Problem
Michael Unger:
28338: 01/01/08: Re: 2-D DCT implementation
Michael Van Oostende:
48961: 02/10/28: Linux driver support for Spartan II
<Michael Vilain <vilain@spamcop.net>>:
Michael Vincze:
4019: 96/09/03: Re: MAXPLUS2 6.2. setup problem (with synopsys)
4285: 96/10/09: Re: 16x16 multiplier needer (Altera or VHDL)
19568: 00/01/01: Re: Using internal RAM in Altera Flex 10KE
19782: 00/01/12: Re: HW resources increased
Michael w-y Lai:
31112: 01/05/12: How to make FPGA_Express recongize my RAM code? Urgent.....
31172: 01/05/14: how to transfer startup cell to gates
31422: 01/05/23: replace_fpga problem
Michael W. Ellis:
10012: 98/04/22: Xilinx Serial Proms
10052: 98/04/24: Re: Xilinx Serial Proms
10128: 98/04/28: Re: Xilinx Serial Proms
Michael Warner:
25465: 00/09/12: Is this practical?
25523: 00/09/13: Re: Is this practical?
25524: 00/09/13: Re: Is this practical?
Michael Werner:
66227: 04/02/15: Programming an EPC1 conf.Dev. from Altera
66230: 04/02/15: Re: Programming an EPC1 conf.Dev. from Altera
66231: 04/02/15: Re: Programming an EPC1 conf.Dev. from Altera
Michael Wichmann:
33286: 01/07/22: Altera ISP - JTAG
Michael Williams:
2650: 96/01/19: Re: [q][Reverse Engineering Protection]
Michael Wilspang:
51611: 03/01/17: Booting Spartan IIE from SPI
51640: 03/01/17: Re: Booting Spartan IIE from SPI
118906: 07/05/07: VHDL core for Hitachi H8S or H8/300H CPU?
Michael Winter:
49794: 02/11/21: Problems with simulation after synthesis
Michael Wojcik:
145504: 10/02/12: Re: using an FPGA to emulate a vintage computer
145803: 10/02/24: Re: using an FPGA to emulate a vintage computer
145877: 10/02/26: Re: using an FPGA to emulate a vintage computer
145878: 10/02/26: Re: using an FPGA to emulate a vintage computer
145879: 10/02/26: Re: using an FPGA to emulate a vintage computer
145881: 10/02/26: Re: using an FPGA to emulate a vintage computer
145882: 10/02/26: Re: using an FPGA to emulate a vintage computer
145883: 10/02/26: Re: using an FPGA to emulate a vintage computer
145985: 10/03/02: Re: using an FPGA to emulate a vintage computer
145986: 10/03/02: Re: using an FPGA to emulate a vintage computer
145987: 10/03/02: Re: using an FPGA to emulate a vintage computer
145988: 10/03/02: Re: using an FPGA to emulate a vintage computer
145989: 10/03/02: Re: using an FPGA to emulate a vintage computer
145990: 10/03/02: Re: using an FPGA to emulate a vintage computer
146225: 10/03/09: Re: using an FPGA to emulate a vintage computer
146227: 10/03/09: Re: using an FPGA to emulate a vintage computer
146228: 10/03/09: Re: using an FPGA to emulate a vintage computer
146231: 10/03/09: Re: using an FPGA to emulate a vintage computer
146232: 10/03/09: Re: using an FPGA to emulate a vintage computer
146233: 10/03/09: Re: using an FPGA to emulate a vintage computer
146234: 10/03/09: Re: using an FPGA to emulate a vintage computer
146247: 10/03/09: Re: using an FPGA to emulate a vintage computer
146248: 10/03/09: Re: using an FPGA to emulate a vintage computer
Michael Wrighton:
53249: 03/03/07: best way to read/write contents of BRAM to a file during simulation?
53365: 03/03/11: Re: best way to read/write contents of BRAM to a file during simulation?
Michael Zhu Ning:
1393: 95/06/13: Help! R.J. Francis' Ph.D thesis
Michael Zirngibl:
31848: 01/06/07: FPGA / starterkit / VHDL
michael.e.schueler@googlemail.com:
137408: 09/01/14: Re: VHDL data sampling question
<michael.e.schueler@googlemail.com>:
137402: 09/01/14: Vitrex-5 FPGA Tuning with timing contraints
<michael.lee@actel.com>:
10143: 98/04/29: Re: High Speed FPGAs??
<michael.muellerm@med.ge.com>:
30559: 01/04/17: Re: state encoding in Synplify!!!
<michael@webuyparts.com>:
13024: 98/11/11: FS: XC3142A5PC84C
<michael_23@my-dejanews.com>:
12269: 98/10/07: Help Desperately Needed with Altera Microprocessor Design.
12360: 98/10/10: Re: Help Desperately Needed with Altera Microprocessor Design.
<Michael_R_Hicks-NR@raytheon.com>:
103813: 06/06/12: Re: Problem with DCM simulation models
<michaellewis@my-dejanews.com>:
15326: 99/03/18: FPGA Express FSM Synthesis Concern
<michaelrbodnar@gmail.com>:
109034: 06/09/20: Re: VHDL oddity
Michal:
14912: 99/02/25: WTB: MPA1036DH FPGAs
14982: 99/03/01: WTB: MPA1036DH FPGAs
14985: 99/03/02: WTB: OTP 87C51
18802: 99/11/16: Orcad 7.0 to Altera MAX?
72756: 04/08/31: Re: FPGA Floating Point Multiplier Design
72823: 04/09/03: Re: Unisim Library
78682: 05/02/05: Re: Altera's NIOS2 examples...
Michal HUSEJKO:
70266: 04/06/11: Re: Cores into fpga
112868: 06/11/30: Re: Old XCell journals gone?
114776: 07/01/24: Re: Xilinx ISE 8.2
Michal Jurewicz:
13507: 98/12/07: WTB: MPA1036DH FPGAs
13705: 98/12/19: WTB: MPA1064DH FPGAs
Michal Kvasnicka:
29956: 01/03/19: TOA measurement
29967: 01/03/19: Re: TOA measurement
29980: 01/03/20: Re: TOA measurement
29989: 01/03/20: Re: TOA measurement
29996: 01/03/20: Re: TOA measurement
29997: 01/03/20: Re: TOA measurement
30003: 01/03/20: Re: TOA measurement
30005: 01/03/20: Re: TOA measurement
30032: 01/03/21: Re: TOA measurement
30036: 01/03/21: Re: TOA measurement
30046: 01/03/21: Re: TOA measurement
30063: 01/03/22: Re: TOA measurement
40094: 02/02/27: methods implementation
Michal Prokes:
26970: 00/11/06: Encoding of FSMs internal states
27032: 00/11/08: Re: Encoding of FSMs internal states
Michal Rutka:
34845: 01/09/11: Using falling and rising clock mistery.
34873: 01/09/12: Re: Using falling and rising clock mistery.
46033: 02/08/15: Re: Modelsim VHDL problem
Michal Smulski:
20791: 00/02/22: Xilinx App 058
Michback:
42485: 02/04/25: Hack an bitstream file for AT40Kxx
<miche>:
121671: 07/07/11: Strange warning message from ise8.2i ?
121689: 07/07/11: Re: Strange warning message from ise8.2i ?
121700: 07/07/11: Re: Strange warning message from ise8.2i ?
121791: 07/07/13: Counter ?
121796: 07/07/13: Re: Counter ?
121797: 07/07/13: Re: Counter ?
121812: 07/07/13: Re: Counter ?
121817: 07/07/13: Re: Counter ?
121832: 07/07/13: Re: Counter ?
121842: 07/07/13: Re: Counter ?
121847: 07/07/13: Re: Counter ?
121849: 07/07/13: Re: Counter ?
121854: 07/07/13: Re: Counter ?
121855: 07/07/13: Re: Counter ?
<micheal_thompson@my-deja.com>:
16550: 99/05/27: FPGA express + VHDL: strange SR implementation?
16576: 99/05/28: Re: FPGA express + VHDL: strange SR implementation?
16617: 99/05/31: Re: FPGA express + VHDL: strange SR implementation?
16677: 99/06/02: FPGA/ VHDL books: any stores in central London
17079: 99/06/29: Altera SDF file missing some DFF VITAL generics?
18026: 99/09/24: Flex 10k: power-on initialisation of FSM. How to do?
18067: 99/09/27: Re: Flex 10k: power-on initialisation of FSM. How to do?
19325: 99/12/14: Re: State machine ok with binary encoding but unstable with one hot encoding
19404: 99/12/20: Necessary to 'synchronise' an asynchronous FSM reset?
19428: 99/12/21: Re: Necessary to 'synchronise' an asynchronous FSM reset?
<micheal_thompson@my-dejanews.com>:
16342: 99/05/17: Post route simulation: EDIF or VHDL?
16516: 99/05/26: FPGA express : Schematic viewing options w/o Vista?
michel:
75625: 04/11/11: about ISE6.2.03 module design
76108: 04/11/24: Problem of module design
Michel Baguet:
72937: 04/09/08: HELP : need an old version Xilinx software key -> Alliance Serie 2.1i !
Michel Bieleveld:
76992: 04/12/18: RAM programming by JTAG (i need some serious help)
77289: 05/01/03: Skew between signals
77365: 05/01/05: Re: Skew between signals
Michel Billaud:
79495: 05/02/20: why are PCI-based FPGA cards so expensive ?
80014: 05/02/28: Re: publishing IP
80074: 05/03/01: Re: OT: funny idea
80413: 05/03/05: Q: state encoding in FSM for simple cases ?
81962: 05/04/05: Re: Structural vs Behavioral
84267: 05/05/16: Re: FPGA design under Mac OS X ?
84276: 05/05/17: Re: Universal logic modules vs NAND-like modules
84552: 05/05/20: Re: Universal logic modules vs NAND-like modules
84554: 05/05/20: Re: Universal logic modules vs NAND-like modules
85109: 05/06/04: Re: Basics FPGA
95383: 06/01/23: Re: OT:Shooting Ourselves in the Foot
Michel Eftimakis:
3898: 96/08/16: Re: Quick question for Model Tech. experts:
5607: 97/02/28: Re: Rising_Edge/Falling_Edge Functions
Michel Le Mer:
22755: 00/05/23: Re: Error with Quartus for Altera APEX20K device: clock skew is greater then data delay
22814: 00/05/25: Re: Error with Quartus for Altera APEX20K device: clock skew is greater then data delay
22815: 00/05/25: Apex supply problem
22823: 00/05/25: Re: Apex supply problem
22916: 00/06/02: Re: Apex supply problem
michel leconte:
77758: 05/01/16: Problems in timing simulations
77775: 05/01/17: Problems in timing simulations (clarifications)
77810: 05/01/17: Problems in timing simulations
<michel.talon@gmail.com>:
117490: 07/04/02: verilog genvar, and 2D array access
117491: 07/04/02: Re: verilog genvar, and 2D array access
118061: 07/04/17: define variable in ISE9.1 Tcl scripts
119281: 07/05/16: how to delay a signal in virtex FPGA
119291: 07/05/16: Re: how to delay a signal in virtex FPGA
119293: 07/05/16: Re: how to delay a signal in virtex FPGA
122380: 07/07/26: Problem with X_FF primitive acting as a latch instead of a fliflop
122383: 07/07/26: Re: Problem with X_FF primitive acting as a latch instead of a fliflop
122385: 07/07/26: Re: Problem with X_FF primitive acting as a latch instead of a fliflop
122419: 07/07/27: Re: Problem with X_FF primitive acting as a latch instead of a fliflop
122590: 07/08/01: Re: ASIC Digital Design Blog
123815: 07/09/05: clock skew problems
124117: 07/09/12: Re: clock skew problems
124855: 07/10/08: kicad or orcad virtex5 symbol
124865: 07/10/09: Re: kicad or orcad virtex5 symbol
125197: 07/10/17: difference between XC5VLX50-1FFG676C and XC5VLX50-1FFG676CES
125380: 07/10/24: Multilinx and chipscope
125431: 07/10/25: Re: difference between XC5VLX50-1FFG676C and XC5VLX50-1FFG676CES
126441: 07/11/22: Virtex 5 PCB Designers Guide: required capacitors
127836: 08/01/09: Spartan3 vs cyclone
127842: 08/01/09: Re: Spartan3 vs cyclone
127862: 08/01/09: Re: Spartan3 vs cyclone
127969: 08/01/11: Timing constraints not applied, ISE & SynplifyPro
128540: 08/01/30: difference between net skew in the clock report and clock skew in
128546: 08/01/30: Re: difference between net skew in the clock report and clock skew in
128949: 08/02/11: Virtex5 DCM lower limit
128972: 08/02/12: Re: Virtex5 DCM lower limit
129192: 08/02/18: Re: Virtex5 DCM lower limit
129257: 08/02/19: Virtex5 BUFR min frequency
Michele:
144190: 09/11/18: Re: Avalon-ST to Avalon-MM Bridge
michele bergo:
59612: 03/08/24: Interfacing to pc parallel port?
59622: 03/08/25: parallel port and cyclone?
Michele Bergo:
75443: 04/11/05: Epp interface with Cyclone
75487: 04/11/07: Re: Epp interface with Cyclone
Michelle:
9514: 98/03/20: Front page help please // what idems to up load???
9531: 98/03/21: question fpga?
59008: 03/08/06: ERROR:iMPACT:1210
62716: 03/11/05: Linux and FPGA compatibility
62931: 03/11/11: Re: Linux and FPGA compatibility
62932: 03/11/11: Re: Linux and FPGA compatibility
62933: 03/11/11: Re: Linux and FPGA compatibility
62948: 03/11/11: Re: Linux and FPGA compatibility
Michelle Lee:
58973: 03/08/05: Re: ERROR:iMPACT:1210
Michelle Tran:
9535: 98/03/21: FPGA Design services
9544: 98/03/22: FPGA Design Center
9623: 98/03/26: FPGA design services
13394: 98/11/30: ASIC to FPGA conversion, low NRE
17037: 99/06/26: IP Cores for FPGA
Michiel De Wilde:
32225: 01/06/20: LVDS questions
Michol:
40359: 02/03/05: Re: FPGA exp with "timing constraint export"
Michol Bauer:
42095: 02/04/15: Re: JTAG cable and iMPACT
52017: 03/01/28: Re: JTAG
56622: 03/06/10: Re: FPGA Development Board
Mickey:
66736: 04/02/26: Re: difference btw H/W & S/W implementations !!
Mickey Balter:
14561: 99/02/04: Re: Foundation v1.5i Spartin Problems
mickyc:
157576: 14/12/17: Re: MIPI M-PHY and FPGA?
157584: 14/12/19: Re: MIPI M-PHY and FPGA?
micro:
148781: 10/08/20: TCP Client using lwIP API
148804: 10/08/27: Checking whether the client is connected to the Server
@micronas.com (remove digits):
63782: 03/12/04: Re: Xilinx Virtex-II: DCM int & ext feedback
MicroPix Technologies:
15279: 99/03/17: Vacancy - FPGA/ASIC engineer - Scotland
<microprocsobsolete@angelfire.com>:
8709: 98/01/21: Opinions of My FPGA - Like Chip Design Wanted
Midou:
118236: 07/04/20: FPGA Full Custum Design
Miele di Vespa:
56937: 03/06/19: porting Jam STAPL Player Version 2.3 to MS-DOS
Miem Chan:
37275: 01/12/05: ISA bus adr decoder with GAL16V8D
37429: 01/12/11: Re: ISA syncronization?
Miguel:
83060: 05/04/22: Virtex-4 Routing
Miguel Angel Aguirre:
24774: 00/08/18: Re: Xilinx chip not programming correctly
Miguel Arias:
31943: 01/06/08: Triscend A5: can it reconfigure itself?
67693: 04/03/17: CFP - ReConFig'04 - International Conference on Reconfigurable Computing and FPGAs
Miguel Arias-Estrada:
15078: 99/03/04: Looking for Mexicans working with FPGA
Miguel Silva:
31801: 01/06/06: Re: Xilinx Configuration Bitstream
65678: 04/02/04: XPART : Will it be released
65679: 04/02/04: Re: Reconfiguring at runtime internally?
65716: 04/02/05: XPART : Will it be released
66999: 04/03/03: Re: frame length, frame addressing ?
71390: 04/07/16: OPB_HWICAP clock
73058: 04/09/13: Re: JBits 3.0 and Virtex-II Pro
74419: 04/10/11: Unguided slices
74471: 04/10/12: Re: Problem in Constraining Routing in Xilinx PAR
Miha Dolenc:
30923: 01/05/03: PCI bridge core
31165: 01/05/14: Re: Serial UART
31166: 01/05/14: FREE IP CORES
31249: 01/05/16: OPEN CORES design GUIDELINES
31424: 01/05/23: Block Select RAM+ Memory and NCSim
34278: 01/08/18: Spartan2 5V PCI IO
Mihai Statovici:
561: 95/01/04: multipliers!
Mihai T. LAZARESCU:
8246: 97/12/03: Re: REPOST: "Verilog Won & VHDL Lost -- You Be The Judge"
mihau:
71342: 04/07/15: Re: micron sdram module
72039: 04/08/06: CAN Controller
72053: 04/08/06: Re: CAN Controller
Miika Pekkarinen:
31755: 01/06/05: Help needed on Max7000 pin assignments (Max-plus II)
31812: 01/06/06: Re: Help needed on Max7000 pin assignments (Max-plus II)
32549: 01/06/29: Converting character to integer in VHDL
70547: 04/06/20: Altera Quartus II on Linux
Mij Kelly:
Mik e Payne:
41271: 02/03/23: Help with Xilinx CoolRunner Problem
41315: 02/03/25: Re: Help with Xilinx CoolRunner Problem
41370: 02/03/26: Re: Help with Xilinx CoolRunner Problem
41371: 02/03/26: Re: Help with Xilinx CoolRunner Problem
Mik Kim:
40051: 02/02/25: Spartan 2E JTAG
Mika Iisakkila:
788: 95/03/02: Re: Lattice ispLSI starter kit
1423: 95/06/21: Re: Understanding Lattice equations
4627: 96/11/22: Re: Lattice ISP Question
4916: 96/12/30: Re: I2C Bus Interface in FPGAs
Mika Leinonen:
65383: 04/01/27: Re: isp Cable for Lattice CPLD
65384: 04/01/27: Re: isp Cable for Lattice CPLD
80820: 05/03/11: Re: Interfacing Compact Flash with Spartan 3
85060: 05/06/03: Re: ispLSI1016
90506: 05/10/15: CPLD design software under WINE?
93308: 05/12/20: Re: Mixing XC9500 and XC9500XL, also small qty suppliers
Mikael:
32139: 01/06/15: FPGA programing via the parallel port
Mike:
6882: 97/07/05: Re: Fast sampling techniques. Was: Fast scopes, How?
6941: 97/07/11: Re: fast scopes: how?
8176: 97/11/24: Re: what is metastability time of a flip_flop
9202: 98/03/01: FP problem in win/95
18223: 99/10/08: Can't detect Flex 10K Altera device through JTAG port
18228: 99/10/08: Re: Can't detect Flex 10K Altera device through JTAG port
18229: 99/10/08: Re: External Cloking of Altera MAX 7000S
18283: 99/10/12: Re: Can't detect Flex 10K Altera device through JTAG port
18306: 99/10/13: Re: Can't detect Flex 10K Altera device through JTAG port
18679: 99/11/07: I've gotta buncha FPGA chips, but.....
19227: 99/12/07: AM2901 bit slice processor
27397: 00/11/20: Altera FLEX 10k F.S.
27737: 00/12/05: Re: Using CPLD to configure SpartanII from parallel ROM.
27739: 00/12/05: Re: Using CPLD to configure SpartanII from parallel ROM.
29287: 01/02/12: Re: Need help using bitgen
29698: 01/03/05: Re: Bad Xilinx bitstream=big bang?
31660: 01/06/01: Re: bitstream compression in Xilinx
31688: 01/06/02: Re: bitstream compression in Xilinx
33743: 01/08/03: Re: 4 (8) bit Microporcessor Implementation
34437: 01/08/24: Re: Principles of Verifiable RTL Design (2nd ed)
35947: 01/10/24: Re: JTAG question
35948: 01/10/24: Re: comp.arch.fpg : Reconfiguring of a virtex via JTAG
35999: 01/10/25: Re: JTAG question
36963: 01/11/27: Re: Xilinx JTAG programmer: how to generate SVF
42093: 02/04/15: Re: Xilinx BSCAN_SPARTAN2 component
44203: 02/06/13: Re: Altera APEX reconfigurates endlessly
48175: 02/10/12: Re: .13 micron - what does it indicate
57687: 03/07/03: Questions about Design Compiler.
57829: 03/07/07: std_logic_vector type port doesn't work after synthesis.
57902: 03/07/09: Re: std_logic_vector type port doesn't work after synthesis.
60778: 03/09/22: Cheapest programmer for a ICT 7572J Peel device
62430: 03/10/29: Reconfigurable Computing Pointers?
70156: 04/06/06: Re: Three-phase PWM generator in VHDL
71383: 04/07/16: How to refresh pins in Xilinx PACE
72290: 04/08/13: We can supply obsolete Xilinx parts
74266: 04/10/07: FPGA not turning off
78643: 05/02/04: VoIP on XESS XSB
83325: 05/04/27: Re: XC9500 - creating RS485 Mux
84509: 05/05/19: FFT with FPGA
84512: 05/05/19: Re: FFT with FPGA
88842: 05/08/29: Re: CPLD Jitter
88855: 05/08/30: Re: CPLD Jitter
89439: 05/09/14: Re: PCI configuration questions.
89466: 05/09/15: Re: PCI configuration questions.
90461: 05/10/13: Anyone remember the really early Xilinx FPGAs?
95044: 06/01/20: Re: OT:Shooting Ourselves in the Foot
126608: 07/11/28: FPGA not in boundary scan
126662: 07/11/29: Re: FPGA not in boundary scan
126688: 07/11/29: Re: FPGA not in boundary scan
126689: 07/11/29: Re: FPGA not in boundary scan
126699: 07/11/29: Re: FPGA not in boundary scan
126810: 07/12/03: Xilinx ISE Bugs
mike:
30724: 01/04/26: Configuration via PCI JTAG
31308: 01/05/18: eprom configuration
45092: 02/07/12: HDL generate from handel-C can be accepted by synthesis tools?
47146: 02/09/19: Re: C\C++ to VHDL Converter
55038: 03/04/24: WANTED ALTERA CYCLONE PCI BOARD
55143: 03/04/28: Re: WANTED ALTERA CYCLONE PCI BOARD
55288: 03/05/02: Re: WANTED ALTERA CYCLONE PCI BOARD
55487: 03/05/09: Re: WANTED ALTERA CYCLONE PCI BOARD
57079: 03/06/23: Re: vga controller
87570: 05/07/26: comprehension of clck to pad,clock to setup,etc
87824: 05/08/02: lut problem
89230: 05/09/08: xilinx virtex 2 multimedia board ( XC2V2000)
113401: 06/12/12: Next Xilinx starter Kit
142318: 09/08/04: Re: File I/O read in verilog
148000: 10/06/11: Re: how to interface a ddr2 memory controller to a processor
149209: 10/10/07: Re: FPGA design not working!
152099: 11/07/06: Re: What's the black and while round on FPGA slice?
Mike Panson:
8530: 98/01/05: Newbe to fpga
Mike & Jen:
13397: 98/11/30: Re: Will XILINX survive?
Mike Albaugh:
10378: 98/05/15: Re: Minimal ALU instruction set.
10388: 98/05/15: Re: Minimal ALU instruction set.
12761: 98/10/28: Re: New free FPGA CPU
13299: 98/11/24: Re: Integer divide algorithms
17394: 99/07/24: Re: EVERYTHING YOU WANT !!!! 7306
22598: 00/05/12: Re: OT ANNOUNCE: Embedded Systems Glossary and Bibliography
Mike Budwey:
2883: 96/02/23: Re: Xilinx is NOT specified MINIMUM delay -
2912: 96/02/28: Re: Xilinx is NOT specified MINIMUM delay -
2913: 96/02/28: Re: Xilinx is NOT specified MINIMUM delay -
2991: 96/03/09: Re: actel act2 ta161 library element
Mike Butts:
93: 94/08/13: Re: Response to Emulation Systems
111: 94/08/16: Re: Emulation Systems
118: 94/08/17: Re: QuickTurn
479: 94/11/30: Re: ASIC emulation (Quickturn, etc.)
519: 94/12/17: Re: L-Edit and Benchmarks
1170: 95/05/10: Overheating (was Re: Compression algo's for FPGA's)
1217: 95/05/16: Re: 1000 pin fpga's ?
1466: 95/06/26: Re: Place-n-Route service
2673: 96/01/22: Re: good interview questions ?
2877: 96/02/22: Re: Floating Point and Reconfigurable Architectures
3022: 96/03/15: Pointers?
3116: 96/04/05: Dataflow thread on comp.arch
3223: 96/04/29: Re: On FPGAs as PC coprocessors
3277: 96/05/08: Re: Please help with CRC hardware implementation - crcgen.zip (0/1)
5516: 97/02/21: Re: Fifth International Symposium on FPGAs
5912: 97/03/25: FCCM '96 Top Ten Predictions
6188: 97/04/23: Primes / long integer multiplication
6283: 97/05/08: Scientific American cover on Configurable Computing
6282: 97/05/08: Re: Cheap way to develop for FPGAs?
10102: 98/04/27: FCCM '98 Top 10 Predictions for FCCMs in 2003
10407: 98/05/17: Re: Minimal ALU instruction set.
10447: 98/05/19: FPGA-based CPUs (was Re: Minimal ALU instruction set)
10464: 98/05/20: Re: FPGA-based CPUs (was Re: Minimal ALU instruction set)
11586: 98/08/25: Re: Newbie seeks cheap fun w/FPGAs
17232: 99/07/12: Re: 100 Billion operations per sec.!
19798: 00/01/12: Re: Xilinx Spartan2
19845: 00/01/13: Re: Xilinx Spartan2
30130: 01/03/24: How to find out where par placed things?
30133: 01/03/24: Re: How to find out where par placed things?
30177: 01/03/26: Re: How to find out where par placed things?
32575: 01/06/30: xr16vx: a GPL 16-bit xr16 microcontroller in JHDL
32580: 01/06/30: Re: xr16vx: a GPL 16-bit xr16 microcontroller in JHDL
32581: 01/06/30: Re: xr16vx: a GPL 16-bit xr16 microcontroller in JHDL
32590: 01/07/01: Re: Virtex II Block RAM's - Is the second port free?
32649: 01/07/03: Re: xr16vx: a GPL 16-bit xr16 microcontroller in JHDL
34023: 01/08/11: Re: Reconfigurable Computational Accelerator
37356: 01/12/07: Re: where is designed FPGA for apple II computer...?
51040: 02/12/27: Re: FPGA accelerated FPGA/ASIC tools
51201: 03/01/06: Re: interface DRAM to FPGA
55957: 03/05/24: Re: FPGA design: firmware or hardware?
56116: 03/05/28: An FPGA is flying to Mars
58049: 03/07/13: Re: Wanted: Orcad Capture symbol for Xilinx Spartan IIE XC2S300E PQ208
66951: 04/03/01: Re: Xilinx iMPACT error: "Done did not go high"
155000: 13/03/25: Xilinx tools for XC3020???
155007: 13/03/26: Re: Xilinx tools for XC3020???
155013: 13/03/27: Re: What a Xilinx fpga could do in 1988
155061: 13/04/04: Re: Xilinx tools for XC3020???
157798: 15/03/28: Re: Intel in Talks to buy Altera
160658: 18/09/03: Re: What to do with an improved algorithm?
160661: 18/09/04: Re: What to do with an improved algorithm?
Mike Ciholas:
4530: 96/11/09: Xilinx and cost of tools
4566: 96/11/14: Re: Xilinx and cost of tools
Mike Collier:
71113: 04/07/08: Xilinx Student Foundation Edition on Windows-XP ??
Mike Cowlishaw:
64434: 04/01/04: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
Mike D:
46942: 02/09/12: Post Synthesis Simulation w/Mentor
46953: 02/09/12: Re: 2-D resistor array
47473: 02/09/26: Re: mapping of fpga
49706: 02/11/19: What is a big design?
49712: 02/11/19: Re: Free FPGA Development Board
49965: 02/11/27: Re: The "Do"s and "Don't"s of Synthesizing VHDL?
51275: 03/01/09: Xilinx 5.1i Map question
51974: 03/01/28: Re: vhdl core of PCI bridge
52041: 03/01/29: Re: vhdl core of PCI bridge
52134: 03/02/02: Re: FPGA Overclocking
Mike Damiano:
33804: 01/08/06: Principal FPGA design/verification contractor available
Mike Deblis:
65800: 04/02/06: Newbie question about VHDL & Xilinx CoolrunnerII kit...
Mike DeBruin:
20455: 00/02/10: Re: FPGA IP complexity
20456: 00/02/10: Re: Simulation problem
Mike DeCellis:
29109: 01/02/06: Digital/Hardware Designer with Ericsson
Mike DeKoker:
25927: 00/09/26: VirtexE readback via JTAG
Mike DeLaney:
10071: 98/04/25: FPGA Eng: WANTED Excellent Opportunity
10281: 98/05/09: FPGA Eng WANTED : excellent opportunity
11942: 98/09/20: WANTED: FPGA/ASIC Eng's telecom
12067: 98/09/26: Digital/ASIC/FPGA Eng...Needed
14049: 99/01/09: FPGA Eng WANTED : excellent opportunity
17223: 99/07/11: FPGA Eng(s) interested in an excellent opportunity
31088: 01/05/11: using FPGAs in communication products....
Mike Delaney:
74038: 04/10/02: Floating Point Powers and Logs?
74043: 04/10/02: Hardware Log and EXP
75012: 04/10/24: Virtex-II Pro DDR Memory Controller
75341: 04/11/02: FPGA Advantage and Xilinx Specific Libs (like Unisim)
Mike Diack:
1755: 95/08/26: AMD MACH eval package ?
1835: 95/09/07: WTB:Max2PLUS software
1997: 95/09/29: Re: cheap (free) fpga design software
2223: 95/11/05: simulation (.hst) file compatability
2743: 96/02/01: WTB : Xilinx development system
2784: 96/02/07: FPGA entry for <$1000?
2828: 96/02/13: FPGA software for <$1000
2824: 96/02/13: Re: Looking for OPAL, PALASM, PLAN
2995: 96/03/11: DIY Bitblaster ?
3309: 96/05/12: Re: Looking for free FPGA softw./Xilinx
3450: 96/06/01: PldShell -> Max+Plus2 conversion
5294: 97/02/05: Re: Altera BitBlaster
Mike E. Wazlowski:
385: 94/11/03: Xilinx chip partitioning
Mike Field:
157129: 14/10/15: Re: Need ideas for FYP
157133: 14/10/16: Re: Need ideas for FYP
157136: 14/10/16: Re: Need ideas for FYP
157156: 14/10/19: Re: Need ideas for FYP
157625: 15/01/07: Re: Image rotation
157636: 15/01/11: Re: Name this pipelining technique
157859: 15/04/21: Re: Choosing the right FPGA board
157941: 15/05/19: Re: Clock triggered FSM
158032: 15/07/13: Aligning symbols with IDELAY / ISERDES in Xilinx 7-series devices.
158157: 15/09/06: Why is this group so quiet?
158174: 15/09/09: Re: How to understand obfuscated IP codes?
158215: 15/09/16: Can anybody knowledgeable on DisplayPort help me?
158216: 15/09/17: Can anybody knowledgeable on DisplayPort help me?
158220: 15/09/23: Re: Why is this group so quiet?
158375: 15/10/24: ERROR:MapLib:30 - LOC constraint P11 on vga_b_out<1> is invalid: No
158376: 15/10/25: Re: DC Blocker
158436: 15/11/24: Re: ERROR:HDLParsers:409 .... at left hand side. Please help
158495: 15/12/03: Re: Simulation vs Synthesis
160583: 18/04/26: engineered data path versus inferred data path
160587: 18/04/28: Re: engineered data path versus inferred data path
160588: 18/04/28: Re: engineered data path versus inferred data path
160638: 18/07/02: Re: Stepper motor controller
160656: 18/09/03: What to do with an improved algorithm?
160662: 18/09/04: Re: What to do with an improved algorithm?
160669: 18/09/09: Re: What to do with an improved algorithm?
Mike Fisher:
32349: 01/06/24: NEED VHDL DEBUGGER
32445: 01/06/26: LOOKING FOR VHDL DEBUGGER
Mike Forster:
630: 95/01/23: Re: ViewLogic simulation without master reset
1602: 95/07/25: Re: ACTEL PLACE AND ROUTE
4687: 96/11/29: Re: Xilinx Foundation
Mike Froggatt:
4946: 97/01/03: Re: What Does ASIC Stand For?
Mike Frysinger:
93805: 05/12/31: Re: Is there anybody that have ported the linux to the nios or microblaze?
93868: 06/01/02: Re: Is there anybody that have ported the linux to the nios or microblaze?
mike gibson:
50761: 02/12/18: parameterized priority encoder in AHDL
Mike Goldsmith:
52635: 03/02/17: Re: BLACK BOX
Mike Gragger:
127045: 07/12/10: ERROR iMPACT 477 - The bsdl for the device 'UNKNOWN' is out of date
Mike H.:
14914: 99/02/25: Re: JTAG HANG UP......
22149: 00/04/27: Re: ? economical SPROM programmer for Xilinx
23738: 00/07/06: Re: Altera's promises unfulfilled???
23759: 00/07/07: Re: Altera's promises unfulfilled???
26626: 00/10/23: Re: PCB's for re-casting the form factor of a QFP
26926: 00/11/03: Re: I2C bus driven by Xilinx
27034: 00/11/08: Re: Anything wrong with Xilinx website?
27295: 00/11/17: Re: VHDL & Spartan: How to power-up a Register to '1' ?
28690: 01/01/21: Re: UK parts
29768: 01/03/08: Problem with Xilinx 3.3-sp7
29780: 01/03/09: Re: Problem with Xilinx 3.3-sp7
Mike Harding:
74996: 04/10/23: Re: Looking for FPGA design services in India or similar
Mike Harris:
26400: 00/10/14: Re: Sinusoidal PWM on Xilinx FPGA
26401: 00/10/14: Re: clk'event
Mike Harrison:
4607: 96/11/20: Re: VHDL code editor for Windows NT.
51188: 03/01/06: Re: Contracting in the UK
54010: 03/03/31: Re: $4000 FPGAs
54964: 03/04/23: Re: Very low pin count FPGA
57272: 03/06/26: Re: Free PAL synth tools (ABEL, PALASM, VHDL, etc.)?
58526: 03/07/25: Re: Should I use ABEL?
70385: 04/06/15: Re: Atmel WinCupl
71305: 04/07/14: Re: WinCUPL state machine for 16V8
71323: 04/07/14: Re: WinCUPL state machine for 16V8
75087: 04/10/26: Re: Clock Extraction from Bi-Phase Data
74114: 04/10/04: Re: meaning of "field-programmable" in FPGA
77229: 04/12/31: Xilinx ISE : How to make Modelsim reload when design changed ?
77230: 04/12/31: Re: SDRAM
77363: 05/01/05: Re: Extracting BRAM data from bitsream
77948: 05/01/21: Re: How does a SDRAM controller work?
78010: 05/01/22: Re: How to get 1.8432 MHz out of 24 MHz with Sparten-3?
78261: 05/01/27: Re: 60Hz clock on XC9572
78668: 05/02/05: Re: Spartan-3 Starter Kit supplier in the UK?
78731: 05/02/07: Re: Xilinx makes dreams true :)
80003: 05/02/28: Re: Maximum Current utilized by Spartan-3
80071: 05/03/01: Re: FPGA interface to an asynchronous microcontroller memory bus
80314: 05/03/03: Re: XC9572 64 pin VQFP package
80455: 05/03/06: Re: Help with 22v10 and WinCupl :(
80460: 05/03/06: Re: Help with 22v10 and WinCupl :(
80479: 05/03/07: Re: Newby Getting started with FPGA
80480: 05/03/07: Re: Newby Getting started with FPGA
80481: 05/03/07: Re: Help with 22v10 and WinCupl :(
80958: 05/03/15: Re: XCF01's in the UK
81354: 05/03/22: Re: Altera free web FPGA software license question
83299: 05/04/27: Re: *RANT* Ridiculous EDA software "user license agreements"?
84627: 05/05/23: Re: more and more and more issues with Xilinx tools
85412: 05/06/09: Re: General gripe session ....
85489: 05/06/10: S3 not auto-loading from platform flash
85491: 05/06/10: X-Fest devkit order leadtimes & software silliness....
85501: 05/06/10: Re: X-Fest devkit order leadtimes & software silliness....
85510: 05/06/10: Re: X-Fest devkit order leadtimes & software silliness....
85531: 05/06/10: Re: X-Fest devkit order leadtimes & software silliness....
85589: 05/06/11: Re: Selecting FPGA synthesis, place and route and simulation tools
85790: 05/06/16: Re: VHDL Synthesis tutorial
85865: 05/06/17: Re: comp.arch.fpga.<mfr>
85888: 05/06/17: Re: BGA Rework/Prototype Placement Anyone?
85929: 05/06/18: Re: CPLD fusemap data - why the secrecy?
85973: 05/06/19: Spartan 3 availability
86045: 05/06/21: Re: Spartan 3 availability
86046: 05/06/21: Re: 5 Volt tolerance - Altera
86589: 05/06/30: Re: read & write on SDRAM speed with PPC 300 MHz
87858: 05/08/02: Re: 5V non-volatile reprogrammable FPGA/CPLD
88064: 05/08/08: Re: Hiding data inside a FPGA
88092: 05/08/09: What are IO standard defaults in S3 ?
88228: 05/08/12: Re: high speed image capture
88395: 05/08/17: Easy USB2.0 hi-speed device solutions ?
88608: 05/08/23: Re: FPGA Development Board Wish List
88630: 05/08/24: Re: FPGA Development Board Wish List
88631: 05/08/24: Re: xilinx or digilent
88846: 05/08/30: Re: FPGA Development Board Wish List
88931: 05/08/31: Spartan-3 LVDS driving TFT LCD panel..?
88950: 05/09/01: Re: Spartan-3 LVDS driving TFT LCD panel..?
88951: 05/09/01: Re: Spartan-3 LVDS driving TFT LCD panel..?
89170: 05/09/07: Re: Spartan-3E Starter Kit availability slips to December
89306: 05/09/12: Re: SDRAM quality
89467: 05/09/15: Re: SDRAM quality
89481: 05/09/16: Re: SDRAM HOW?
89482: 05/09/16: Re: SDRAM HOW?
89923: 05/09/30: Re: Preloading SDRAM?
90265: 05/10/07: Re: FPGA behaviour when its used resource is >90% ?
90870: 05/10/24: Re: 24 to 32 8-bit PWM outputs
91114: 05/10/29: Re: Spartan-3E starter kit
91286: 05/11/02: Re: Spartan-3E starter kit
91729: 05/11/11: Re: fastest possible USB
91884: 05/11/16: Re: RoHS
91917: 05/11/16: Re: Raggedstone1, MINI-CAN - Low Cost Carriage
92047: 05/11/21: Re: Sounds or other means to indicate end of compilation in Xilinx ISE
92311: 05/11/27: Re: Distributed RAMs / SRL: Why not, Altera?
93765: 05/12/30: Re: Brute Force Examination of a PLD
94124: 06/01/06: Re: Do you name your FPGA?
94147: 06/01/06: Re: PCI compliance ?
94253: 06/01/09: Question on Alias in VHDL
94312: 06/01/09: Re: Question on Alias in VHDL
94412: 06/01/11: Re: FPGA and video generation
94511: 06/01/13: Re: How to create a delay BUF?
94510: 06/01/13: Re: FPGA Journal Article
95752: 06/01/26: Re: Spartan-3 Starter Board
96437: 06/02/03: Re: why such fast placement?
96897: 06/02/13: Re: spartan3 starter kit.
96901: 06/02/13: Re: spartan3 starter kit.
97102: 06/02/16: Re: VHDL or verilog
97119: 06/02/16: Re: WIFI Compact Flash
97153: 06/02/17: Re: Communication between FPGA and PC with ethernet
97182: 06/02/18: Re: Maxim anounce MAX3421E SPI-USB Host/Peri
97238: 06/02/19: Re: help with VGA timings
98317: 06/03/08: Re: Digilent Spartan-3 Starter Kit w/ JTAG-USB Problem/Solution
99904: 06/03/30: Re: USB Interface to Virtex-4
100695: 06/04/16: Re: Where is the xilinx online store gone?
100721: 06/04/17: Re: Where is the xilinx online store gone?
100781: 06/04/18: Re: Petition about the xilinx online store ?
100782: 06/04/18: Re: Where is the xilinx online store gone?
100797: 06/04/18: Re: FPGA + FTDI
100931: 06/04/21: Re: Bluetooth with FPGA?????
101171: 06/04/26: Re: Picoblaze C Compiler
101616: 06/05/03: Re: Measuring Light with LED and FPGA
101638: 06/05/04: Re: Xilinx 3s8000?
101874: 06/05/08: Re: Can an FPGA be operated reliably in a car wheel?
101935: 06/05/08: UK source for Digilent S3 board?
101943: 06/05/08: Re: Xilinx 3s8000?
101944: 06/05/08: Re: Putting the Ring into Ring oscillators
101997: 06/05/09: Re: UK source for Digilent S3 board?
102156: 06/05/11: Re: CoolRunner XPLA3 getting axed?
102237: 06/05/12: Re: CoolRunner XPLA3 getting axed?
102622: 06/05/18: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
104361: 06/06/26: Re: newbie wants to do VHDL on an FPGA
104412: 06/06/27: Re: ISE WebPack 8.2
105934: 06/08/03: Re: generating sine-like waveforms
106205: 06/08/09: Re: Spartan 3 StarterKit Weirdness
106520: 06/08/14: Re: Spartan3 dev board... will USB keyboard work?
108846: 06/09/18: Re: Writing VHDL, Software dummy!
109467: 06/09/27: Re: Configuration of Spartan 3 devices
110198: 06/10/12: Re: VGA timing
110237: 06/10/12: Re: SPAM -- FPGA image processing camera
110650: 06/10/19: Re: Cheapest FPGA board to study VHDL on
110652: 06/10/19: Re: Cheapest FPGA board to study VHDL on
110801: 06/10/23: Re: Spartan 3 Configuration Questions
111296: 06/11/01: Re: Need just a few 5V Spartan
111701: 06/11/08: Re: Graphics-2-FPGA
113211: 06/12/08: Looking for simple Cycone 2 example design
116384: 07/03/08: Re: Where do I find CMOS image sensors and lenses?
116951: 07/03/21: Re: Why is Xilinx's WebPACK so inferior?
118001: 07/04/16: Re: How to design a SDIO peripheral card?
118199: 07/04/19: Re: Summer with fpgas
118278: 07/04/21: Re: FPGA Newbie
118833: 07/05/04: Re: FPGA board for video processing
119055: 07/05/10: Re: Darnaw1 - PGA Spartan-3E Module
122269: 07/07/24: Re: tiny Spartan 3 module?
123806: 07/09/05: Re: Multiple CPLDs on a PCB.
124938: 07/10/11: Re: UK Supplier XILINX spartan 3 development board??
124940: 07/10/11: Re: UK Supplier XILINX spartan 3 development board??
126929: 07/12/06: Re: Drigmorn1 - The Cheapest FPGA Development Board???
126931: 07/12/06: Re: Drigmorn1 - The Cheapest FPGA Development Board???
128459: 08/01/27: Re: buying fpga kits in denmark
129043: 08/02/13: Re: When are FPGAs the right choice?
129107: 08/02/14: Re: Is a FPGA the solution ?
129108: 08/02/14: Re: Rom Implementation in a CPLD
131407: 08/04/21: Re: Xilinx DDR2 Interface
132776: 08/06/06: Re: A new FPGA company comes out of Stealth mode - SiliconBlue
133919: 08/07/19: Re: Which FPGA has most ram in a TQFP144 or smaller non-BGA?
134791: 08/09/01: Re: FPGA on a DIMM module, performing encryption
139086: 09/03/20: R/A FX2 connectors for S3A board - anyone have a couple spare?
139089: 09/03/20: Re: R/A FX2 connectors for S3A board - anyone have a couple spare?
139132: 09/03/21: Re: R/A FX2 connectors for S3A board - anyone have a couple spare?
139273: 09/03/24: Which ISE Webpack version for S3A..?
139296: 09/03/25: Re: Which ISE Webpack version for S3A..?
139401: 09/03/28: VHDL : how to make a bunch of arbitary signals into a vector?
139779: 09/04/13: Re: Xilinx ISE bug, or?
139856: 09/04/16: Re: Xilinx ISE bug, or?
139940: 09/04/20: Re: Atari VCS 2600 FPGA Cartridge
139977: 09/04/21: Re: Atari VCS 2600 FPGA Cartridge
140417: 09/05/13: cheapest FPGA?
140436: 09/05/13: Re: cheapest FPGA?
140450: 09/05/13: Re: cheapest FPGA?
140463: 09/05/14: Re: cheapest FPGA?
140499: 09/05/15: Re: cheapest FPGA?
140500: 09/05/15: Re: cheapest FPGA?
141111: 09/06/06: Re: digital RGB Video to Analog VGA triple DAC question
141114: 09/06/06: Re: digital RGB Video to Analog VGA triple DAC question
141220: 09/06/11: Re: Latest Xilinx Discontinuations
141959: 09/07/20: Re: FPGA to PC connection
141960: 09/07/20: How do you handle build variants in VHDL?
142016: 09/07/22: Re: How do you handle build variants in VHDL?
142025: 09/07/22: Re: How do you handle build variants in VHDL?
142026: 09/07/22: Re: building a card reader into a virtex 2 or 5 based FPGA device.
142036: 09/07/22: Re: How do you handle build variants in VHDL?
142050: 09/07/23: Re: How do you handle build variants in VHDL?
142157: 09/07/27: Lattice EC - some .bit files not loading from SPI flash
142169: 09/07/28: Re: Lattice EC - some .bit files not loading from SPI flash
142196: 09/07/28: Re: Lattice EC - some .bit files not loading from SPI flash
142277: 09/08/01: Re: Lattice EC - some .bit files not loading from SPI flash
142305: 09/08/03: Re: Xilinx 3E design programs fine with 500E but fails with 250E
142460: 09/08/12: Re: Spartan-6 Boards - Your Wish List
142470: 09/08/12: Re: Spartan-6 Boards - Your Wish List
142833: 09/09/03: Re: Choice of Language for FPGA programming
144040: 09/11/09: Re: OK Xilinx users, it's time I was let in on the joke...
144720: 09/12/28: Re: Info on heritage Nallatech board?
144807: 10/01/05: Re: EPCS vs SPI Flash
145322: 10/02/05: Re: Board layout for FPGA
145685: 10/02/18: Re: Unpredictable design
148318: 10/07/07: Re: xilinx leadtimes
148357: 10/07/15: Re: Another Xilinx webpack download rant
148762: 10/08/19: Re: CE compliance testing
148763: 10/08/19: Re: CE compliance testing
148764: 10/08/19: Re: CE compliance testing
148765: 10/08/19: Re: CE compliance testing
148766: 10/08/19: Re: CE compliance testing
148767: 10/08/19: Re: CE compliance testing
149996: 10/12/06: Lattice XO2 video
150187: 10/12/29: Lattice ISPLever - how to prevent inferred latch
150539: 11/01/26: Re: tft lcd with xilinx fpga
150581: 11/01/27: Re: tft lcd with xilinx fpga
150619: 11/01/28: Re: tft lcd with xilinx fpga
150727: 11/02/07: Re: Looking for contractor for FPGA-based multiUART
150817: 11/02/14: Re: Xilinx USB programming cable.
150825: 11/02/15: Re: Xilinx USB programming cable.
151129: 11/03/09: Re: Anti-benchmarking clauses
152694: 11/10/03: most stable version of ISE ?
153173: 12/01/03: Verilog module in VHDL project - ISE 13
153177: 12/01/04: slimming down ISE install
Mike Hicks:
32690: 01/07/05: Tcl/Tk VHDL Automatic Testbench Generator - tb_gen.tcl (0/1)
32691: 01/07/05: Tcl/Tk VHDL Automatic Testbench Generator - tb_gen.tcl (1/1)
107763: 06/09/01: XPLA3 and Spartan3 Devices Do Not Respond to Programming via Parallel 3 Cable
Mike Hoffberg:
1479: 95/06/27: Digital IO capture board / Digital Camera
Mike Holley:
1279: 95/05/25: Re: CUPL manual/info
Mike Hollinger:
54077: 03/04/01: Shove a binary file into Xilinx 4.2 as input for testing...
Mike Hore:
145389: 10/02/08: Re: using an FPGA to emulate a vintage computer
Mike Horwath:
6279: 97/05/08: Quicklogic Input Only Pins
20140: 00/01/28: Program Xilinx Through TI DSP Serial McBSP
Mike Hubert:
42427: 02/04/23: Xilinx: IP Capture/CoreGenerator
47532: 02/09/27: Xilinx CoreGenerator/IP Capture
53377: 03/03/12: footprints
53384: 03/03/12: Re: footprints
53504: 03/03/14: more footprints...
Mike Hutton:
100662: 06/04/14: Re: 8:1 MUX implementaion in XILINX and ALTERA
mike johnson:
21053: 00/03/04: Re: PCI Core Problem
24008: 00/07/20: Re: jtag connections for Spartan II on PCI ?
Mike Johnson:
23166: 00/06/16: Re: 68k - core, a free core 1, and 2 worth money = time.
23471: 00/06/26: Re: inferring global buffers in Leonardo?
26134: 00/10/05: Re: 3DES VHDL
30941: 01/05/04: Re: Translator from Xchecker´s files to PROM´s files.
37312: 01/12/06: Re: I need a Xilinx Spartan PCI Development Board
38853: 02/01/26: New Risc5x cpu core on Opencores
38885: 02/01/27: Re: Xilinx PCI logicore: clarification on nature of COMPLETE
39387: 02/02/08: Re: Xilinx ISE 3.3 upgrade to 4.1
39423: 02/02/08: Re: Xilinx ISE 3.3 upgrade to 4.1
39625: 02/02/14: Re: Lean serial communication processor
41276: 02/03/24: Re: Too many clocks
mike kelly:
3068: 96/03/26: Re: Low-power FPGA or EPLD
Mike Kelly:
6645: 97/06/09: Re: PCI how to
7016: 97/07/23: Epitaxial Layer on EPLD
9955: 98/04/16: Job Opening
9987: 98/04/21: Problem with Minc Fitter - MACH
10013: 98/04/22: Re: Problem with Minc Fitter - MACH
Mike Kopp:
4514: 96/11/07: VHDL synthesis tools?
Mike Lamond:
108059: 06/09/04: Re: Please help me with (insert task here)
108065: 06/09/04: Re: Please help me with (insert task here)
Mike Lardner:
10978: 98/07/08: SCSI Modeling
mike lee:
Mike Lewis:
15010: 99/03/03: Re: Selt-Timed circuit
15050: 99/03/04: Re: Selt-Timed circuit
63968: 03/12/10: Re: Q:Altera's excalibur device
63970: 03/12/10: Re: FIFO design
63971: 03/12/10: Re: Maximum bus speed of APB.
63997: 03/12/11: Re: Maximum bus speed of APB.
63998: 03/12/11: Re: Latches inferred ?
64002: 03/12/11: Re: FIFO design
65780: 04/02/06: Re: need desperate help!
65829: 04/02/07: Re: A small clock synchronization challenge with Virtex E
65833: 04/02/07: Re: A small clock synchronization challenge with Virtex E
65951: 04/02/10: Re: sdram controller problems
67190: 04/03/08: Re: FPGA hangs
72829: 04/09/03: Re: [XC96xxXL] Maximum Value for the external Pull-Up resistor ...
72982: 04/09/09: Re: AMBA AHB
77101: 04/12/22: Re: AHB master related
78470: 05/02/01: Re: Synchronizing multibit bus - 2
83624: 05/05/04: Re: Altera Excalibur EBI problem
83883: 05/05/09: Re: true dual port memory v/s simple dual port memory
84019: 05/05/11: Re: Test the code on FPGA Board...
84156: 05/05/13: Re: how can i save my received data into the SDRAM?
84730: 05/05/25: Re: Synopsys Designware IP... can be used for Xilinx FPGA??
84842: 05/05/30: Re: SPI slave select signals
85154: 05/06/06: Re: USB interface With AMBA AHB
85211: 05/06/06: Re: USB interface With AMBA AHB
85269: 05/06/07: Re: USB interface With AMBA AHB
90809: 05/10/21: Re: EDK/ISE : unroutable design
104752: 06/07/05: Re: stable reset in fpga
105274: 06/07/19: Re: Need for reset in FPGAs
112188: 06/11/17: Re: Maximum Operating Frequency
113678: 06/12/19: Re: Frequency divider ?
114118: 07/01/04: Re: DC timing violation, what to do first?
114147: 07/01/05: Re: DC timing violation, what to do first?
115072: 07/01/30: Re: How to use the test bench wave form simulator?
117640: 07/04/05: Re: having a state machine in a datapath element a bad design practice?
118141: 07/04/18: Re: BFM simulation and number of Masters?
118843: 07/05/04: Re: Select pullup, pulldown or none via embedded S/W
120134: 07/06/01: Re: After PAR simulation, should I assume that it will work on FPGA board?
122187: 07/07/23: Re: On I2C protocol
122433: 07/07/27: Re: X values in ASIC
122622: 07/08/01: Re: Static Timing Analysis Using Primetime for FPGAs
124308: 07/09/18: Re: Tristate bus on spartan FPGA
124387: 07/09/20: Re: Gated Clock Problems
124485: 07/09/24: Re: Gated Clock Problems
124486: 07/09/24: Re: Answer: maximum number of state machines in a current chip: > 500k
124552: 07/09/26: Re: Never buy Altera!!!!
125198: 07/10/17: Re: difference between XC5VLX50-1FFG676C and XC5VLX50-1FFG676CES
125658: 07/10/31: Re: Is it possible to check how cache memories are mapped to FPGA block rams?
125701: 07/11/01: Re: can i use dual edge or two clocks?
125705: 07/11/01: Re: can i use dual edge or two clocks?
126522: 07/11/26: Re: Measuring setup and hold time in Lab
129545: 08/02/27: Re: Interview questions
132349: 08/05/22: Re: asic gate count
132367: 08/05/23: Re: asic gate count
132543: 08/05/30: Re: asic gate count
133049: 08/06/16: Re: FPGA clock frequency
133388: 08/06/26: Re: synthesis error
134249: 08/08/01: Re: question about fifo
135164: 08/09/18: Re: Clock Enable safe?
Mike Lottridge:
3709: 96/07/18: Opinions on Graphical/Schematic capture vs HDL-text only design
mike lottridge:
1742: 95/08/22: Synario/OrCad/Viewlogic
1746: 95/08/24: Re: Synario/OrCad/Viewlogic
1753: 95/08/25: Re: Synario/OrCad/Viewlogic
4842: 96/12/19: Consulting Opportunity
5785: 97/03/14: Re: A viewlogic story
Mike Lowey:
32749: 01/07/06: 3.1 on Win2000 with restricted (student) user?
32875: 01/07/10: Re: 3.1 on Win2000 with restricted (student) user?
Mike Lundy:
118484: 07/04/27: Re: N00b question about DCM
118497: 07/04/27: Re: Is there a reset signal available in verilog in Xilinx FPGAs?
118924: 07/05/07: Re: Xilinx software quality - how low can it go ?!
118977: 07/05/08: Re: Xilinx software quality - how low can it go ?!
118980: 07/05/08: Re: Xilinx software quality - how low can it go ?!
123402: 07/08/27: Re: Null statement in VHDL
123415: 07/08/27: Re: Null statement in VHDL
Mike M:
59216: 03/08/12: Re: Q: async flip-flop reset by a signal from a different clock domain
Mike Marlow:
Mike McCarty:
5190: 97/01/29: Re: ASICs Vs. FPGA in Safety Critical Apps.
11590: 98/08/25: Re: New Evolutionary Electronics Book
12813: 98/10/30: Re: New free FPGA CPU
12819: 98/10/30: Re: New free FPGA CPU
12854: 98/11/02: Re: New free FPGA CPU
12886: 98/11/03: Re: New free FPGA CPU
12887: 98/11/03: Re: New free FPGA CPU
12897: 98/11/04: Re: New free FPGA CPU
12916: 98/11/04: Re: New free FPGA CPU
12917: 98/11/04: Re: New free FPGA CPU
12933: 98/11/05: Re: New free FPGA CPU
12934: 98/11/05: Re: New free FPGA CPU
12935: 98/11/05: Re: New free FPGA CPU
Mike McDonald:
133637: 08/07/07: SBC with ADC, 1GE, and SATA2?
mike mcginn:
11880: 98/09/16: Strange switching inside 4020e
Mike McManus:
10352: 98/05/13: Re: Looking for Ultra 2 SCSI Synthesizable Core
Mike Mitchener:
50355: 02/12/09: Re: clock recovery suggestions
50696: 02/12/17: Re: Xilinx PAR looks as if it is adding X_BUF instances in my clock tree
50700: 02/12/17: Re: Is it true that if you have a clock routed to non-clock resources then you are not allowed to use the clock nets?
Mike Monett:
84916: 05/06/01: Re: need a book: Hilbert transform
84973: 05/06/02: Re: need a book: Hilbert transform
85015: 05/06/02: Re: need a book: Hilbert transform
136642: 08/11/27: Re: FMC/VITA 57
136657: 08/11/28: Re: FMC/VITA 57
Mike Nelson:
11830: 98/09/11: Re: Code coverage tools
Mike Neufeld:
45899: 02/08/09: Using Quartus with an EPC2 and a Flex 6000?
45901: 02/08/09: Does Altera Jam work?
Mike Neuman:
45821: 02/08/06: Asynchronous signals recommendations?
Mike Ng:
143209: 09/09/25: Re: USB programmable Open Source Hardware
156032: 13/11/11: Re: Zynq devices, boards and suppliers
Mike Nicklas:
66615: 04/02/24: Driving INOUT signals
66680: 04/02/25: Re: Driving INOUT signals
66691: 04/02/25: Re: Driving INOUT signals
66934: 04/03/01: Re: Driving INOUT signals
67323: 04/03/10: Re: Xilinx ISE 6.1, .mcs prom files
67324: 04/03/10: Re: Xilinx ISE 6.1, .mcs prom files
67350: 04/03/10: Re: Xilinx ISE 6.1, .mcs prom files
67397: 04/03/11: Re: Xilinx ISE 6.1, .mcs prom files
Mike Oxlarge:
93802: 05/12/30: Newbie question - using library "design elements"
93816: 05/12/31: Re: Newbie question - using library "design elements"
93960: 06/01/03: Using posedge and negedge causing me grief
93962: 06/01/03: Re: Using posedge and negedge causing me grief
94022: 06/01/04: Re: Using posedge and negedge causing me grief
94209: 06/01/07: Re: Using posedge and negedge causing me grief
Mike Palmer:
9329: 98/03/06: Re: The case for free operating systems and EDA
Mike Panson:
10575: 98/06/02: BiPolar Prom 2 PLD
10583: 98/06/03: Re: Xilinx Foundation
Mike Peattie:
13876: 98/12/30: Re: How to import EDIF file in Foundation Software?
15018: 99/03/03: Re: combining multiple xilinx designs into one
20591: 00/02/15: Re: Master/Serial mode for Virtex
21131: 00/03/07: Re: setup and hold times for data during configuration (Xilinx Virtex
22005: 00/04/11: Re: Specifying PCI buffer for Xilinx 4000XLA
24422: 00/08/07: Re: Verilog multiplier in Xilinx...
75343: 04/11/02: Re: "frying" FPGAs
74914: 04/10/21: Assembler for PicoBlaze in Perl
75380: 04/11/03: Re: "frying" FPGAs
Mike Perkins:
150511: 11/01/25: Re: FPGA changes behaviour when the resource's usage percentage changes
150626: 11/01/28: Re: FPGA changes behaviour when the resource's usage percentage changes
150627: 11/01/28: Re: FPGA changes behaviour when the resource's usage percentage changes
152259: 11/07/29: Re: Bitstream compression
152276: 11/08/02: Re: Bitstream compression
152636: 11/09/19: SIM card 1.8V / 3V sensing
152643: 11/09/20: Re: SIM card 1.8V / 3V sensing
154041: 12/07/19: Re: Xilinx UCF: Adding "Virtual Grounds"
154177: 12/08/28: Re: recruit FPGA design engineer in Scotland
154513: 12/11/22: Re: Set-up and hold times and metastability
154516: 12/11/22: Re: Set-up and hold times and metastability
154522: 12/11/23: Re: Set-up and hold times and metastability
154523: 12/11/23: Re: Set-up and hold times and metastability
154526: 12/11/23: Re: Set-up and hold times and metastability
154561: 12/11/28: Re: VHDL expert puzzle
155213: 13/06/09: Re: A Question about FPGA IO Standard
155226: 13/06/13: DDR2 Concurrent Auto Precharge
155238: 13/06/16: Re: DDR2 Concurrent Auto Precharge
155249: 13/06/18: Re: DDR2 Concurrent Auto Precharge
155971: 13/10/30: Re: draw lines, circles, squares on FPGA by mouse and display on
156536: 14/04/17: Spartan 3 JTAG problems
156543: 14/04/18: Re: Spartan 3 JTAG problems
156688: 14/06/04: Re: Partial Reconfiguration clock enable problem
156854: 14/07/10: Re: Using FPGA as dual ported ram
156860: 14/07/11: Re: Using FPGA as dual ported ram
157087: 14/10/08: USB PHY recommendations
157095: 14/10/09: Re: USB PHY recommendations
157173: 14/10/24: Re: USB PHY recommendations
157216: 14/11/05: Re: USB PHY recommendations
157227: 14/11/05: Re: USB PHY recommendations
157266: 14/11/10: Re: USB PHY recommendations
157312: 14/11/20: Re: disadvantages of inferring latches
157316: 14/11/21: Re: disadvantages of inferring latches
158963: 16/05/29: Re: Advice to a newbie
159140: 16/08/19: Re: Multi-port memory
159155: 16/08/26: Re: Four_Bit_Counter in VHDL
159221: 16/09/04: Re: eliminating a DDS
159228: 16/09/05: Re: eliminating a DDS
159680: 17/01/29: Re: Anyone use 1's compliment or signed magnitude?
160182: 17/07/29: Re: sram
160475: 18/02/03: Re: Interface on board ADC to Spartan 3E startkit
160482: 18/02/05: Re: Interface on board ADC to Spartan 3E startkit
160483: 18/02/05: Re: Interface on board ADC to Spartan 3E startkit
160520: 18/03/13: Re: How to handle a data packet while calculating CRC.
160523: 18/03/15: Re: How to handle a data packet while calculating CRC.
160598: 18/05/20: Re: CPLD 1.8V to 3.3V bidirectional SDA
160604: 18/05/23: Re: CPLD 1.8V to 3.3V bidirectional SDA
160775: 18/11/26: Re: New(ish) FPGA Company
160867: 18/12/11: Re: How to make Altera-Modelsim free download version to work?
160881: 18/12/14: Re: How to make Altera-Modelsim free download version to work?
Mike Playle:
10549: 98/05/29: Re: Altera FLEX8k configuration problem
Mike R.:
35270: 01/09/27: Re: Programming flash connected to CPLD via JTAG
35293: 01/09/28: Re: Programming flash connected to CPLD via JTAG
47961: 02/10/08: Re: Why can Xilinx sw be as good as Altera's sw?
Mike Randelzhofer:
12913: 98/11/04: Re: Q: 3.3 V regulators suitable for XILINX - ?
13014: 98/11/11: Re: CCLK on Spartan
15337: 99/03/19: Re: Xilinx Spartan configuration troubles
57495: 03/07/01: Re: Cyclone vs Spartan-3
Mike Reeves:
639: 95/01/25: FLEXlogic
1285: 95/05/27: ABEL optimization
1327: 95/06/01: Re: ABEL optimization
1308: 95/05/31: Re: ABEL optimization
8562: 98/01/08: Re: simple FPGA project for somebody...
Mike Reynolds:
1117: 95/05/01: Crosspoint FPGA Users?
1543: 95/07/12: Exemplar users in Australia (or elsewhere)?
Mike Roberts:
15101: 99/03/06: Re: Looking for advice on CPLD's
15481: 99/03/25: Re: Info about VHDL syntesis
15507: 99/03/28: Re: Info about FPGA/PLD
15514: 99/03/28: Re: Info about FPGA/PLD
15524: 99/03/29: Re: Info about FPGA/PLD
15525: 99/03/29: Re: Info about FPGA/PLD
15547: 99/03/30: Re: Info about FPGA/PLD
15651: 99/04/06: Re: XILINX CLB architecture
19776: 00/01/11: Re: Virtex Temperature Sensing diode pins DXP, DXN
20037: 00/01/24: Re: Easy to program PLD
Mike Romine:
6062: 97/04/08: test
6228: 97/04/30: test
Mike Rosing:
26448: 00/10/16: Re: CHES 2001 Workshop
45000: 02/07/09: Advice on tools and question on Virtex2
45028: 02/07/10: Re: Security features
45126: 02/07/13: Re: Security features
45148: 02/07/13: Re: How to add BUFG to an internal signal?
45168: 02/07/14: Re: How to add BUFG to an internal signal?
45184: 02/07/15: Re: How to add BUFG to an internal signal?
45185: 02/07/15: Re: Advice on tools and question on Virtex2
45358: 02/07/19: Re: cpld programming
45723: 02/08/02: Re: Qn: Low Level Design
45724: 02/08/02: How to use distributed ram/luts ?
45742: 02/08/03: Re: How to use distributed ram/luts ?
45757: 02/08/04: VHDL primitives: what am I doing that's stupid?
45759: 02/08/04: Re: VHDL primitives: what am I doing that's stupid?
45760: 02/08/05: Re: VHDL primitives: what am I doing that's stupid?
45761: 02/08/05: Re: VHDL primitives: what am I doing that's stupid?
45862: 02/08/07: Re: VHDL primitives: what am I doing that's stupid?
45863: 02/08/07: Re: articles about FPGA based DSP design
45864: 02/08/07: Re: changing width of array
45910: 02/08/09: Re: Reed-Solomon polynom transform....
45921: 02/08/10: Re: Reed-Solomon polynom transform....
46316: 02/08/25: Re: Question on Fast CPLDs
46659: 02/09/04: Re: atmel CPLD documentation
47026: 02/09/14: Re: xilinx jtag chain question
48845: 02/10/25: Re: Virtex2 Prototyping Board
48892: 02/10/25: Re: Concepts: What is "Clock Edge"?
49944: 02/11/26: Re: Where can find MPEG-2 codec SOFT-IP CORE module, DCT、Motion-estimation...etc
56007: 03/05/26: Re: JTAG madness
56045: 03/05/27: Re: JTAG madness
56117: 03/05/28: Re: JTAG madness
Mike Rumsey:
5475: 97/02/19: Altera FLEX10K debug Probing
Mike Saltmarsh:
2306: 95/11/18: Re: [q][Reverse Engineering Protection]
2526: 95/12/27: Re: [q][Reverse Engineering Protection]
2629: 96/01/15: Re: [q][Reverse Engineering Protection]
Mike Santarini:
142256: 09/07/30: Xilinx Xcell Journal 68
144006: 09/11/06: Xcell Journal Issue 69: FPGAs in the Networked Battlefield
144137: 09/11/12: Re: Xcell Journal Issue 69: FPGAs in the Networked Battlefield
145996: 10/03/02: Xcell Journal Issue 70: FPGAs in the TV Broadcast market
147670: 10/05/13: 2 New issue of Xcell Now available
148777: 10/08/20: Xilinx Xcell Journal Issue 72 Now available
148838: 10/09/01: Tutorial on timing constraints
149508: 10/11/01: Xcell Journal issue 73: Cray on Spartan FPGA & How to do Partial Reconfiguration
149541: 10/11/03: Chance to win a SP601 board in Xcell Journal Caption Contest
149585: 10/11/08: Re: Chance to win a SP601 board in Xcell Journal Caption Contest
150980: 11/02/25: Xcell Journal 74: Stacked & Loaded: Xilinx SSI & 28-Gbps I/O Yield
151644: 11/04/29: Xcell Journal issue 75 now available
Mike Saunders:
2708: 96/01/26: Xilinx MC68681 Emulation
6878: 97/07/05: Quicklogic PASIC1 to PASIC2 problems?
Mike Scott:
15498: 99/03/26: IBM 600MHz FPGA
Mike Seningen:
2041: 95/10/05: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
7424: 97/09/09: Large FPGA
Mike Shogren:
151087: 11/03/04: Re: Xilinx FPGA Clocking resources and design implementation.
151088: 11/03/04: Re: Finding cheap PCI-E FPGA board for a student
151089: 11/03/04: Re: Finding cheap PCI-E FPGA board for a student
151210: 11/03/15: Re: ping pong buffer overflow issue
151219: 11/03/15: Re: ping pong buffer overflow issue
151431: 11/04/07: Re: Ethernet MAC on Virtex 4
Mike Shonle:
53923: 03/03/27: Re: DSP-FPGA interface
Mike Siersema:
3015: 96/03/13: Re: Xact6.o too slow
3016: 96/03/13: Re: Xact6.o too slow
Mike Silva:
62455: 03/10/29: Some FPGA questions
62561: 03/11/01: Re: Some FPGA questions
62637: 03/11/03: Re: Some FPGA questions
63177: 03/11/17: Is this a good starter kit?
63448: 03/11/21: Re: Is this a good starter kit?
63461: 03/11/21: Re: Is this a good starter kit?
63481: 03/11/22: Re: Is this a good starter kit?
63482: 03/11/22: Re: Is this a good starter kit?
129036: 08/02/13: When are FPGAs the right choice?
129050: 08/02/13: Re: When are FPGAs the right choice?
129066: 08/02/13: Re: When are FPGAs the right choice?
Mike Stump:
277: 94/10/11: Re: Xilinx configuration
Mike Thyer:
17800: 99/09/06: Re: What's meaning of "Partial Evaluation"
17804: 99/09/06: Re: What's meaning of "Partial Evaluation"
Mike Treseler:
4286: 96/10/09: Re: Anyone using Altera MaxPlus VHDL ???
4645: 96/11/26: Re: Moore vs Mealy state machines
9399: 98/03/09: Re: Whats wrong with this method
9400: 98/03/09: Re: Whats wrong with this method
11720: 98/09/03: Re: Spartan and VHDL-design "Problem"
12244: 98/10/06: Re: A Johnson counter
11800: 98/09/10: Re: 22V10 programming
11897: 98/09/17: Re: Help a confused teacher
14019: 99/01/07: Re: fpga socket
16264: 99/05/12: Re: Fancy Dram problem
16407: 99/05/20: Re: DSP Board for PC/104 Bus
17601: 99/08/12: Re: port name reg_input won't sim.
17600: 99/08/12: port name reg_input won't sim.
18273: 99/10/11: Re: CLOCK assignment in MAXPLUS2
18494: 99/10/27: Re: Altera UNIX licence
18500: 99/10/27: Re: schematics ==> www
18576: 99/11/01: Re: StateCAD versus Viewdraw
18957: 99/11/22: Re: VHDL vs. schematic entry
18992: 99/11/23: Re: VHDL vs. schematic entry
19354: 99/12/15: Re: State machine ok with binary encoding but unstable with one hot
20024: 00/01/24: Re: How to access standard sdram ?
20225: 00/02/01: Re: Count 1's algorithm...
20313: 00/02/04: Re: Conditional compilation in VHDL?
20317: 00/02/04: Re: Conditional compilation in VHDL?
20363: 00/02/07: Re: ADC to DSP... FIFO?
20367: 00/02/07: Re: Conditional compilation in VHDL?
20944: 00/02/29: Re: Delay Lines using FPGA ??
23846: 00/07/12: Re: C++/Java generators vs. synthesizers
23909: 00/07/14: Re: Boundary-Scan Tests with JTAG Technologies Tools
23915: 00/07/14: Re: Boundary-Scan Tests with JTAG Technologies Tools
24889: 00/08/21: Re: Mealy vs Moore FSM model
24937: 00/08/22: Re: Mealy vs Moore FSM model
25083: 00/08/25: Re: Xilinx 3.1i ISE
25084: 00/08/25: Re: "generate" and instance name indexes in Synopsys
25846: 00/09/22: Re: memory interface trouble...
25947: 00/09/27: Re: Altera EPM3256ATC144 equivalents
27072: 00/11/09: Re: Xilinx PCI Core
27106: 00/11/10: Re: Leonardo for Altera
29638: 01/03/02: Re: Differences in VHDL coding for FPGA & CPLD
30159: 01/03/26: Re: Asynchronus Mashine States
30527: 01/04/12: Re: *help* how to count clock cycles in a design? how can i know its
30597: 01/04/18: Re: FPGAs & Combinatorial Chew
30904: 01/05/02: Re: VHDL coding question.
30925: 01/05/03: Re: Serial UART
31024: 01/05/09: Re: Licensing PB in Synplify_pro 6.2
31320: 01/05/18: Re: Can anyone comment on the difference between modelsim PE and XE
31433: 01/05/23: Re: Can anyone comment on the difference between modelsim PE and XE
32033: 01/06/11: Re: safe state machine design problem
32182: 01/06/18: Re: Flexlm license and windows 2000
32740: 01/07/06: Re: WTB:50 Mhz 24 CHANNEL LOGIC ANALYZER only $199
32798: 01/07/09: Re: Max+2 and multi-cycle timing analysis WAS: Altera ACEX
32811: 01/07/09: Re: Simulation problems with BlockRAM's INIT values !
32952: 01/07/12: Re: Xilinx BRAM failures
32999: 01/07/14: Re: Design entry
33000: 01/07/14: Re: Which Chip Family?
33117: 01/07/17: Re: Working Design - Anyone
33168: 01/07/18: Re: Spartan2XC2S30 vs ACEXEP1K30
33182: 01/07/18: Re: possibly stupid lpm_fifo question...
33250: 01/07/20: Re: Modelsim and bidir ports?
33333: 01/07/23: Re: Measuring power consumption
33369: 01/07/24: Re: Register Chain
33370: 01/07/24: Re: Schematic libraries in webpack ?
33405: 01/07/25: Re: FPGA Express or Spectrum?
33608: 01/07/31: Re: RAM - VHDL - Altera,...
33650: 01/08/01: Re: RAM - VHDL - Altera,...
33652: 01/08/01: Re: RAM - VHDL - Altera,...
33699: 01/08/02: Re: RAM - VHDL - Altera,...
33703: 01/08/02: Re: RAM - VHDL - Altera,...
33718: 01/08/02: Re: Does Flexlm Licensing Work on Windows 2000 Pro?
33761: 01/08/03: Re: Altera EPM7064.............HELP
34111: 01/08/14: Re: Use of lpm in Xilinx Foundation 2.1i
34520: 01/08/28: Re: Level sensitive latches in Xilinx Virtex
34561: 01/08/29: Re: Urgent Help Needed
34562: 01/08/29: Re: Any body used ACEX1K series for testing the design??
34563: 01/08/29: Re: global VHDL signals and FPGA express
34602: 01/08/30: Re: Ethernet CRC
34633: 01/08/31: Re: Defending Austin Franklin
34764: 01/09/06: Re: strange behaviour of LPM_FIFO_DC in altera 10k130e
34882: 01/09/12: Re: LeonardoSpectrum Timing reports
35040: 01/09/18: Re: BUGs ?
35315: 01/09/28: Re: Meta-stability
35385: 01/10/02: Re: Barrel Shifter
35457: 01/10/05: Re: ROM based FSMs
35500: 01/10/08: Re: ROM based FSMs
35501: 01/10/08: Re: Synplify vs. Leonardo
35554: 01/10/10: Re: Linking components in VHDL
35662: 01/10/12: Re: Timing constraints for unrelated clocks?
35664: 01/10/12: Re: Reassemble a BGA560 device
35812: 01/10/18: Re: Career advice in fpga/asic design
35824: 01/10/18: Re: Timing Constarint Error message
36032: 01/10/26: Re: Probing BGA Designs
36036: 01/10/26: Re: Bi directional pin
36042: 01/10/26: Re: Cloning someone else's IP core
36118: 01/10/30: Re: timing difference
36126: 01/10/30: Re: Can anyone guide me in selecting an FPGA?
36130: 01/10/30: Re: Leonardo bugs
36361: 01/11/07: Re: FPGA BGA and decoupling
36367: 01/11/07: Re: FPGA BGA and decoupling
36371: 01/11/07: Re: Xilinx machine readable package info
36484: 01/11/09: Re: How to convert unsigned integer into std_logic_vector in VHDL
36581: 01/11/12: Re: Incrementing counter from state-machine
36624: 01/11/13: Re: 'Timing' simulation in ModelSIM
36629: 01/11/13: Re: Hex numbers in VHDL
36658: 01/11/14: Re: Incrementing counter from state-machine
36940: 01/11/26: Re: Which vendor to choose
37135: 01/11/30: Re: PCI card - 2 layers versus four layers
37261: 01/12/05: Re: quartus post simulation setup problem
37264: 01/12/05: Re: quartus post simulation setup problem
37305: 01/12/06: Re: quartus post simulation setup problem
37420: 01/12/10: Re: Translating....
37423: 01/12/10: Re: Altera pin drivers
37557: 01/12/14: Re: Dual-port ram templates
37584: 01/12/16: Re: Dual-port ram templates
37730: 01/12/19: Re: Low area barrel shift puts 3 to 1 mux in a Xilinx LUT:
37854: 01/12/21: Re: Dual-port ram templates
38133: 02/01/06: Re: simprims_ver/xilinxcorelib_ver /unisims_ver
38202: 02/01/08: Re: Repost: Should clock skew be included for setup time analysis?
38436: 02/01/14: Re: Leonardo + Xilinx tools help
38492: 02/01/15: Re: Leonardo + Xilinx tools help
38493: 02/01/15: Re: Altera Compiling Error..WHY?????
38524: 02/01/16: Re: Leonardo + Xilinx tools help
38525: 02/01/16: Re: Leonardo + Xilinx tools help
38566: 02/01/17: Re: Leonardo + Xilinx tools help
38593: 02/01/18: Re: APEX-II vs VIRTEX-II
38666: 02/01/21: Re: Quartus 2 and bus ripping
38747: 02/01/23: Re: boot manager
38959: 02/01/28: Re: Altera support sites
39112: 02/01/31: Re: metastability: failsafe solution???
39270: 02/02/05: Re: Leonardo=>MaxPlus/Quartus Vs Synopsys=>MaxPlus/Quartus
39321: 02/02/06: Re: FPGA --> SDRAM & Groundbounce: Latchup Possible?
39324: 02/02/06: Re: Pseudorandom Bitstream
39419: 02/02/08: Re: Modelsim questions
39570: 02/02/13: Re: Pseudorandom Bitstream
39571: 02/02/13: Re: Is Leonardo spectrum OEM version for Altera limited?
39669: 02/02/15: Re: Xilinx synthesis tools
39772: 02/02/19: Re: "DONT TOUCH" with Xilinx XST?
40201: 02/03/01: Re: Pin assignments in QUARTUS
40230: 02/03/02: Re: Embedding counting in an FSM.
40233: 02/03/02: Re: What FPGA to use?
40281: 02/03/04: Re: max3000a odd behavior -- is the bug in my vhdl code? help!
40282: 02/03/04: Re: Has anyone got Quartus II 2.0/LeonardoSpectrum-Altera NativeLink to
40299: 02/03/04: Re: convert_hex2ver can not generate the *.ver file
40332: 02/03/05: Re: Has anyone got Quartus II 2.0/LeonardoSpectrum-Altera NativeLink to
40334: 02/03/05: Re: FPGA problems
40590: 02/03/11: Re: Newbie choosing a language - Verilog, VHDL, or ABEL
40667: 02/03/12: Re: Newbie choosing a language - Verilog, VHDL, or ABEL
40680: 02/03/12: Re: DPRAM implementation in altera
40682: 02/03/12: Re: Timing Simulations
40739: 02/03/14: Re: Synthesis tools comparison?
40848: 02/03/16: Re: just bought
40887: 02/03/17: Re: just bought
41075: 02/03/20: Re: how to deal with signal pass through two clock domain
41092: 02/03/20: Re: virtex 2 orcad symbols?
41154: 02/03/21: Re: how to deal with signal pass through two clock domain
41155: 02/03/21: Re: Possibility of RTL and Gate-level simulation dont match?
41305: 02/03/25: Re: Can't detect Altera MAX7000s using JTAG
41351: 02/03/26: Re: clock multiplier
41352: 02/03/26: Re: clock source
41363: 02/03/26: Re: ByteblasterMV EPM7064S voltage problem
41450: 02/03/28: Re: I need an advice regarding a switch to a Digital Design Career
41499: 02/03/30: Re: Compiler library ...
41653: 02/04/04: Re: Monostable multivibrator
41818: 02/04/08: Re: Modelsim from Altera vs Modelsim from Menthors
41821: 02/04/08: Re: XST Synthesis tool
41898: 02/04/10: Re: differences betw. EPF10K30E and EP1K30?
41964: 02/04/11: Re: Attributes *and* generics!?
42043: 02/04/13: Re: Attributes *and* generics!?
42046: 02/04/13: Re: Attributes *and* generics!?
42228: 02/04/18: Re: just bought Cohen's book...Real Chip Design and Verification using Verilog and VHDL
42382: 02/04/22: Re: FPGA Express problems
42383: 02/04/22: Re: Post-synthesis simulation
42622: 02/04/29: Re: function usage
42624: 02/04/29: Re: Controller Initial State
43120: 02/05/14: Re: Driving high speed external devices from an FPGA
43136: 02/05/14: Re: Altera/Quartus II: unconditional loop?
43156: 02/05/14: Re: Altera/Quartus II: unconditional loop?
43548: 02/05/23: Re: FPGA, VHDL : RAM initialization
43681: 02/05/29: Re: Addressable shift register
43742: 02/05/31: Re: State machine synthesis
45618: 02/07/29: Re: VHDL configurations with Xilinx ISE 4.1i
45648: 02/07/30: Re: Who can compare the synthesis tools for me ?
45873: 02/08/08: Re: Is it necessary to instantiate IPAD, OPAD, IBUF, OBUF...?
45955: 02/08/12: Re: Symplify Hacking/munging question...
45988: 02/08/13: Re: Symplify Hacking/munging question...
45991: 02/08/13: Re: Xilinx XST inferred Block-RAM Initialization
46064: 02/08/15: Re: rising_edge detector?
46189: 02/08/21: Re: TQFP 176 socket
46201: 02/08/21: Re: Logic Analyzers with an Altera Board
46402: 02/08/28: Re: Webpack : Order of compiling modules
46416: 02/08/28: Re: WebPack FSM woes...
46525: 02/09/02: Re: synthesizing hard coded numbers
46720: 02/09/06: Re: QUARTUS II V2.1 LINUX (C) ALTERA
46802: 02/09/09: Re: symplicity conv_integer problem
46875: 02/09/10: Re: Modelsim-Altera gate level simulation
46911: 02/09/11: Re: Quartus 2 flow
46944: 02/09/12: Re: Saving results with modelsim
47061: 02/09/16: Re: scan insertion is easily feasible
47062: 02/09/16: Re: ieee.math_real for presynthesis table calculation in vhdl
47223: 02/09/20: Re: Functional VHDL Simulation Problem with Xilinx Coregen Async FIFOs with Modelsim
47531: 02/09/27: Re: Quartus 2 Error: "Full compilation was cancelled due to an error"
47958: 02/10/08: Re: Quartus 2 Error: "Full compilation was cancelled due to an error"
48015: 02/10/09: Re: Simple Counters in Xilinx Spartan II
48074: 02/10/10: Re: Why can Xilinx sw be as good as Altera's sw?
48129: 02/10/11: Re: HELP !/ How to mark (find) signals in VHDL simulation.
48138: 02/10/11: Re: Active HDL
48659: 02/10/22: Re: slow slew rate signal...
48798: 02/10/24: Re: Interface to SPI-3 (sys packet interface Level 3) in fpga
48800: 02/10/24: Re: Pin locking Virtex 2 FPGA
48983: 02/10/28: Re: Leonardo and lpm (Altera)
49054: 02/10/30: Re: How important is simulation?
49081: 02/10/31: Re: How important is simulation?
49082: 02/10/31: Re: UCF files how to use???
49084: 02/10/31: Re: Concepts: What is "Clock Edge"?
49140: 02/11/01: Re: How important is simulation?
49185: 02/11/04: Re: read and write same address of the ESB memory in the same cycle
49230: 02/11/05: Re: C\C++ to VHDL Converter
49315: 02/11/08: Re: Pros and Cons of using Xilinx CoreGen components
49442: 02/11/12: Re: The "Do"s and "Don't"s of Synthesizing VHDL?
49444: 02/11/12: Re: vhdl inout question
49509: 02/11/13: Re: Registering inputs or outputs of modules
49571: 02/11/15: Re: Registering inputs or outputs of modules
49573: 02/11/15: Re: Asynchronous FIFOs using Handel-C?
49574: 02/11/15: Re: C\C++ to VHDL Converter
49606: 02/11/17: Re: Asynchronous FIFOs using Handel-C?
49956: 02/11/26: Re: Custom FPGA synthesis
50106: 02/12/02: Re: string to int conversion
50230: 02/12/05: Re: series termination question
50287: 02/12/07: Re: and vs. nand
50320: 02/12/08: Re: LFSR question
50350: 02/12/09: Re: Synthesis and Design Hierarchy
50351: 02/12/09: Re: How to assign pins in VHDL?
50567: 02/12/12: Re: Hold violation in synthesis but not fitting
50633: 02/12/14: Re: Two clocks for the same module
50648: 02/12/15: Re: EDIF LPM Support in Synthesis
50672: 02/12/16: Re: EDIF LPM Support in Synthesis
51056: 02/12/28: Re: probing modesim simulator state
51065: 02/12/29: Re: probing modesim simulator state - elaborated question
51147: 03/01/03: Re: Running 2 inter related programs on the FPGA
51624: 03/01/17: Re: Multiple FPGA-boards integration issues
51648: 03/01/17: Re: XST vs Synplify observations
51962: 03/01/27: Re: FSM and XST
52069: 03/01/30: Re: Reading External .txt files in Quartus II
52105: 03/01/31: Re: STATE PROBLEM!
52180: 03/02/03: Re: Group Multiple tables
52204: 03/02/04: Re: Can't start server quartus_cmp in quartus II 1.0
52206: 03/02/04: Re: Project fits in Leonardo, not in maxplus?!?
52228: 03/02/04: Re: Group Multiple tables
52461: 03/02/10: Re: Quartus / ModelSim
52487: 03/02/11: Re: Can't start server quartus_cmp in quartus II 1.0
52802: 03/02/22: Re: Lpm equivalent for Xilinx devices
52813: 03/02/23: Re: Code layout considerations
52814: 03/02/23: Re: Timing diagram input
52843: 03/02/24: Re: two-clock FSM?
53020: 03/02/28: Re: PCB board design software vs outsourcing?
53089: 03/03/03: Re: Design Flow --basic questions
53094: 03/03/03: Re: scripting leonardo spectrum
53140: 03/03/04: Re: Implementation of latch in FPGA
53141: 03/03/04: Re: xilinx HDL bencher
53344: 03/03/11: Re: Using divided clock
53388: 03/03/12: Re: RESET --- Synchronous Vs Asynchronous
53445: 03/03/13: Re: RESET --- Synchronous Vs Asynchronous
53510: 03/03/14: Re: IFDs in Xilinx Foundation 4.1i
53521: 03/03/14: Re: IFDs in Xilinx Foundation 4.1i
53782: 03/03/22: Re: Xpower problems - can't load vcd
53851: 03/03/25: Re: xst removes useful signals
53859: 03/03/25: Re: xst removes useful signals
53965: 03/03/28: Re: Leonardo problem
53984: 03/03/29: Re: DSP-FPGA interface
54101: 03/04/02: Re: quartus_cmd under Linux
54105: 03/04/02: Re: uP interface question
54116: 03/04/02: Re: quartus_cmd under Linux
54117: 03/04/02: Re: XC9572XL Macrocell power
54159: 03/04/03: Re: Really long vectors in VHDL
54354: 03/04/08: Re: OK, where does an FPGA newbie start?
54489: 03/04/11: Re: Really long vectors in VHDL
54773: 03/04/17: Re: Boycott All Xilinx products untill they correct all ISE software
54845: 03/04/20: Re: how to synthesize Xilinxcorelib in leonardo or ISE 5.1
54939: 03/04/22: Re: Initial values for internal RAM
55061: 03/04/25: Re: Boycott All Xilinx products untill they correct all ISE softwareerrors
55065: 03/04/25: Re: Any experience (good or bad) with Northwest Logic PCI core?
55085: 03/04/25: Re: question about modelsim
55139: 03/04/28: Re: Any experience (good or bad) with Northwest Logic PCI core?
55212: 03/04/30: Re: Implementing FPGA based network packet filtering
55358: 03/05/05: Re: 802.11
55359: 03/05/05: Re: LPM_ROM problem with Altera EP1K50 parts
55479: 03/05/09: Re: LPM_ROM problem with Altera EP1K50 parts
55484: 03/05/09: Re: help on FPGA-programming tutorial for students
55485: 03/05/09: Re: Encrypted bitstream - battery lifetime problem
55587: 03/05/13: Re: CLK_SIGNAL CONSTRAINT
55588: 03/05/13: Re: OK I am pissed off with Xilinx webpack.
55589: 03/05/13: Re: VitalGlitch
55595: 03/05/13: Re: Problems with Leonardo Spectrum
55626: 03/05/14: Re: VitalGlitch
55628: 03/05/14: Re: CLK_SIGNAL CONSTRAINT
55630: 03/05/14: Re: Problems with Leonardo Spectrum
55674: 03/05/15: Re: Moore Vs Mealy machine ..
55676: 03/05/15: Re: VitalGlitch
55711: 03/05/16: Re: Moore Vs Mealy machine ..
56109: 03/05/28: Re: Moore Vs Mealy machine ..
56157: 03/05/29: Re: Moore Vs Mealy machine ..
56455: 03/06/05: Re: Mealy FSM
56464: 03/06/05: Re: Modifing a Case Statement with a text file (looking for an Example)
56559: 03/06/09: Re: Ranking of FPGA synthesis tools, specifically actel support
56621: 03/06/10: Re: Acex1k100 & Quartus
56689: 03/06/11: Re: Acex1k100 & Quartus
56722: 03/06/12: Re: error compiling
56854: 03/06/17: Re: Automatic FPGA testing
57004: 03/06/20: Re: Output signal problem.
57013: 03/06/20: Re: Reducing synthesize time for state machines
57400: 03/06/29: Re: Xlilin xc9572XL Default register values
57439: 03/06/30: Re: Xlilin xc9572XL Default register values
57575: 03/07/02: Re: why so many problems Xilinx ?
57588: 03/07/02: Re: Process variable setup times and propogations
57671: 03/07/03: Re: UART -- Process variable setup times and propogations
57851: 03/07/08: Re: std_logic_vector type port doesn't work after synthesis.
57917: 03/07/09: Re: std_logic_vector type port doesn't work after synthesis.
57919: 03/07/09: Re: Synplify and then Quartus
57998: 03/07/11: Re: Quartus warning in NUMERIC_STD.vhd
58034: 03/07/12: Re: Quartus warning in NUMERIC_STD.vhd
58069: 03/07/14: Re: Combinational logic and gate delays - Help
58139: 03/07/15: Re: what are libraries for??
58188: 03/07/16: Re: what are libraries for??
58234: 03/07/17: Re: Digital Design with just one clock at one edge
58235: 03/07/17: Re: An All Digital Phase Lock Loop
58302: 03/07/19: Re: using block rams in FPGAs
58374: 03/07/21: Re: Leonardo spectrum synthesis result
58477: 03/07/24: Re: XST fails to recognize FSM with registered outputs
58479: 03/07/24: Re: FPGA Editor
58482: 03/07/24: Re: Pricing question....
58486: 03/07/24: Re: FPGA Editor
58490: 03/07/24: Re: Should I use ABEL?
58619: 03/07/29: Re: VHDL Book Recommendations Please
58662: 03/07/30: Re: apex20ke library and simulation
58676: 03/07/30: Re: Downloading into XCV600
58718: 03/07/31: Re: binary to BCD assistance
58724: 03/07/31: Re: binary to BCD assistance
58728: 03/07/31: Re: apex20ke library and simulation
58729: 03/07/31: Re: Novice problem with Altera MaxPlusII and VHDL
58872: 03/08/03: Re: Showing my ignorance of VHDL again...
58976: 03/08/05: Re: Block ram simulation
58977: 03/08/05: Re: model sim block ram sim
59023: 03/08/06: Re: Using 3rd Party IP Cores...
59077: 03/08/07: Re: Error Generate Statement
59092: 03/08/07: Re: Quartus II and fixing hold timing
59126: 03/08/08: Re: speeding up quartus
59340: 03/08/15: Re: Problem with Modelsim Lisence server...
59346: 03/08/15: Re: Data Structure Viewer
59347: 03/08/15: Re: Problems with ModelSim (Atmel's System Designer)
59605: 03/08/23: Re: Signal within block
59668: 03/08/25: Re: Thinking out loud about metastability
59810: 03/08/28: Re: HDL Designer from Mentor
59875: 03/08/30: Re: Configuration vhdl
59551: 03/08/21: Re: Xilinx XC3000 with Xilinx ISE student edition 4.2i
59960: 03/09/02: Re: HDL Designer from Mentor
60011: 03/09/03: Re: altera latch synthesis
60012: 03/09/03: Re: OT: Block diagramming tools?
60083: 03/09/04: Re: Measuring metastability.
60145: 03/09/05: Re: Schematic simulation and then FPGA programming?
60368: 03/09/11: Re: Time Killing Post P&R Simulation
60434: 03/09/12: Re: Altera's Quartus II "smart compilation" feature killed my design?
60435: 03/09/12: Re: Time Killing Post P&R Simulation
60699: 03/09/19: Re: Xilinx
60717: 03/09/19: Re: LVDS in Xilinx (Spartan-3)
60953: 03/09/25: Re: Regulator for Spartan 2
61008: 03/09/26: Re: FF with CE doesn't synthesize correctly by XST?
61017: 03/09/26: Re: FF with CE doesn't synthesize correctly by XST?
61148: 03/09/29: Re: Counting ones
61149: 03/09/29: Re: OT: spam poll
61153: 03/09/29: Re: development-tools under linux for altera excalibur
61291: 03/10/01: Re: Looking for recent Altera Quartus Verilog synthesis experience
61371: 03/10/02: Re: High-performance workstation
61380: 03/10/02: Re: Safe state machine design problem
61383: 03/10/02: Re: Safe state machine design problem
61430: 03/10/03: Re: Xilinx courses
61542: 03/10/06: Re: Xilinx courses
61591: 03/10/07: Re: synplify vqm not able to fit in Quartus
61737: 03/10/09: Re: Why no synthesis?
61781: 03/10/10: Re: Why no synthesis?
61825: 03/10/13: Re: Quartus 2.2, SOPC builder and leonardo
61868: 03/10/14: Re: Quartus 2.2, SOPC builder and leonardo
61872: 03/10/14: Re: Pass transistor logic in a FPGA
62056: 03/10/17: Re: Altera mySupport
62057: 03/10/17: Re: Ph.inisheD.
62061: 03/10/17: Re: Xilinx Slice and Altera ...?
62062: 03/10/17: Re: Error Message when using process with wait-statement in testbench
62143: 03/10/20: Re: Subroutine in VHDL?
62179: 03/10/21: Re: Altera programming problem
62180: 03/10/21: Re: 74 logic to CPLD. how easy for a Newbie?
62182: 03/10/21: Sort of Running Quartus II on SuSE Linux 8.1
62387: 03/10/28: Re: Sort of Running Quartus II on SuSE Linux 8.1
62391: 03/10/28: Re: Sort of Running Quartus II on SuSE Linux 8.1-- sp2=fix!
62490: 03/10/30: Re: Some FPGA questions
62514: 03/10/31: Re: Essential hazards in CPLD's?
62522: 03/10/31: Re: Wishbone interface, FPGA newbie and advice
62541: 03/10/31: Re: Shannon Entropy for Black Holes
62627: 03/11/03: Re: Altera "my support" :-(
62685: 03/11/04: Re: Tools Tree
62710: 03/11/05: Re: I/O on current FPGAs - deserialise first ??
62749: 03/11/06: Re: Crossing/muxing clocks thru TBUF mux (w/DLL "stunts")
62799: 03/11/07: Re: FPGA & handling reset of a logic block while running
63076: 03/11/13: Re: Xilinx UART Macro ERROR???
63102: 03/11/14: Re: Inferring Dual Port Block RAM
63128: 03/11/15: Re: getting started in FPGA
63172: 03/11/17: Re: SRL16 as synchronizer
63233: 03/11/18: Re: HDL-Designer 2002: cannot edit generic mapping in Block-Diagram-view
63234: 03/11/18: Re: HDL-Designer 2002: cannot edit generic mapping in Block-Diagram-view
63236: 03/11/18: Re: Memory Initialization: mif, coe, hex, etc,
63325: 03/11/19: Re: How do you keep layout info in VHDL?
63331: 03/11/19: Re: State Machines....
63386: 03/11/20: Re: Altera's altsyncram MAXIMUM_DEPTH
63388: 03/11/20: Re: State Machines....
63453: 03/11/21: Re: Memory Initialization: mif, coe, hex, etc,
63484: 03/11/22: Re: State Machines....
63511: 03/11/24: Re: Xilinx ISE 6.1i+SP2 And Modelsim 5.8
63512: 03/11/24: Re: store program in external sdram
63517: 03/11/24: Re: State Machines....
63739: 03/12/02: Re: Quartus generics and vhdl
63764: 03/12/03: Re: Command line in Windows?
63766: 03/12/03: Re: Design analyse methods
63770: 03/12/03: Re: Exact Timing Constraints vs. Over-Constraining
63774: 03/12/03: Re: Command line in Windows?
63814: 03/12/04: Re: Design analyse methods
63845: 03/12/05: Re: Synchronization between CPU-clock and FPGA clock.
63848: 03/12/05: Re: VHDL-Testbench-Simulation in QuartusII
63849: 03/12/05: Re: Hold violation and PLL
63949: 03/12/09: Re: FIFO design
64044: 03/12/13: Re: advantages of ethernet MAC ip core
64065: 03/12/15: Re: multiplier,CLK-insufficient RECOVERY time after async CLEAR
64067: 03/12/15: Re: VHDL-Testbench-Simulation in QuartusII
64070: 03/12/15: Re: Extracting timing from a demo board (V2MB1000)
64102: 03/12/16: Re: Altera Stratix 80: How to divide a bits stream to even bits
64103: 03/12/16: Re: multiplier,CLK-insufficient RECOVERY time after async CLEAR
64105: 03/12/16: Re: VHDL-Testbench-Simulation in QuartusII
64109: 03/12/16: Re: advantages of ethernet MAC ip core
64124: 03/12/17: Re: multiplier,CLK-insufficient RECOVERY time after async CLEAR
64199: 03/12/19: Re: multiplier,CLK-insufficient RECOVERY time after async CLEAR
64260: 03/12/22: Re: Spartan3 availability
64324: 03/12/28: Re: VHDL-Xilinx-Simulation (signal not connected to port) ?
64342: 03/12/29: Re: predictable timing for xilinx cpld?
64468: 04/01/05: Re: Getting up-to-date libraries for timing simulation
64480: 04/01/05: Re: Altera CPLD - Illegal assignment-global clock
64485: 04/01/05: Re: Newbie VHDL issue with CPLD
64518: 04/01/06: Re: fast mod (remainder) algorithm for V2?
64519: 04/01/06: Re: Something additional: Adding internal signals in MODELSIM
64628: 04/01/09: Re: submodules with their own constraint files
64631: 04/01/09: Re: Synthesis in VHDL vs. Verilog
64632: 04/01/09: Re: IP or Core
64661: 04/01/10: Re: Anybody know what the REAL story is? Jim figured it out.
64667: 04/01/10: Re: Altera Cyclone Serial Configuration devices.
64686: 04/01/11: Re: image file reading in vhdl
64773: 04/01/13: Re: How to generate a CSA tree?
64774: 04/01/13: Re: Error: (vsim-3341) Cannot open file
64778: 04/01/13: Re: logicore PCIX issue/question
64867: 04/01/15: Re: Synthesis in VHDL vs. Verilog
64890: 04/01/15: Re: mapper optimization
64957: 04/01/16: Re: Good software to experiment with VHDL
64993: 04/01/18: Re: Hardware to test (FPGA-based) prototype?
64995: 04/01/18: Re: Can XILINX run in multiple instances?
64996: 04/01/18: Re: Timing Simulation ModelSim / Quartus
64997: 04/01/18: Re: Simulation Speed when using Xilinx DCM
65039: 04/01/19: Re: simulating
65040: 04/01/19: Re: Memory Initialization Files in Modelsim
65043: 04/01/19: Re: Simulation Speed when using Xilinx DCM
65065: 04/01/19: Re: Good/Affordable Stater kits
65098: 04/01/20: Re: BIST FPGA testing - Applying a test vector
65099: 04/01/20: Re: Non deterministic routing in Quartus 3.0 ?
65102: 04/01/20: Re: Hardware to test (FPGA-based) prototype?
65116: 04/01/20: Re: changing values in a fifo
65242: 04/01/22: Re: error in Quartus
65290: 04/01/23: Re: error in Quartus
65292: 04/01/23: Re: xilinx 70% tracking rule
65455: 04/01/29: Re: Asking about FPGA-SPARTAN error in synthizer
65729: 04/02/05: Re: Quartus II and Synthesis
65731: 04/02/05: Re: Is it possible that a Virtex II device performs below its spec?
65736: 04/02/05: Re: Design Flow: PCI or any other high-speed PC interface ?
65748: 04/02/05: Re: dual port RAM - write cycle problems
65791: 04/02/06: Re: need desperate help!
65792: 04/02/06: Re: Help with BUFGMUX in Xilinx Virtex2 and Timing constraints ?
65836: 04/02/07: Re: Pricing, 101
65884: 04/02/09: Re: Xilinx training
66282: 04/02/16: Re: Manual Partitioning to Multiple FPGAs
66341: 04/02/17: Re: sdram controller problems
66886: 04/02/28: Re: netlist - technology remapping
66887: 04/02/28: Re: FSM in fpga's
67177: 04/03/07: Re: Release asynchrounous resets synchronously
67276: 04/03/09: Re: bit stream file examples ?
67279: 04/03/09: Re: sorting need help as soon as possible
67418: 04/03/11: Re: Quartus II 3.0 sp1 web, verilog input, memories optimized away
67419: 04/03/11: Re: very strange error
67652: 04/03/16: Re: Schematic Edition Tool : Suggestions
67659: 04/03/16: Re: Modelsim & ISE Foundation: Hierarchical update
67710: 04/03/17: Re: Schematic Edition Tool : Suggestions
67808: 04/03/19: Re: Why It Is not Recommended to Infer latches in VLSI Design...
67829: 04/03/19: Re: Leonardo Spectrum error message
67907: 04/03/22: Re: Why It Is not Recommended to Infer latches in VLSI Design...
68371: 04/04/02: Re: vcom in modelsim
68583: 04/04/08: Re: What is the use of MAX7128?
68853: 04/04/20: Re: State machines vs. Schematics
69016: 04/04/25: Re: Byteblaster Download cable schematics not available from altera site
69266: 04/05/03: Re: Best way to handle multiple common data busses in Altera FPGA (and others)
69308: 04/05/05: Re: How to drive record fields from procedure AND testbench?
69329: 04/05/06: Re: How to drive record fields from procedure AND testbench?
69418: 04/05/10: Re: Monolithic state machine or structured state machine?
69467: 04/05/11: Re: One issue about free hardware
69578: 04/05/14: Re: Instantiating subblock signals with VHDL
69594: 04/05/14: Re: One issue about free hardware
69595: 04/05/14: Re: Video Blob Analysis on FPGAs
69626: 04/05/16: Re: Internal Signals and other questions with ModelSim XE/II Starter
69865: 04/05/22: Re: More fun with VHDL
69895: 04/05/23: Re: Xilinx training
70043: 04/05/28: Re: VHDL test bench in Quartus
70044: 04/05/28: Re: Tool to help detecting race conditions with asych inputs?
70046: 04/05/29: Re: how to random generate packet for Ethernet MAC(802.3) with verilog in testbench ?
70047: 04/05/29: Re: Tool to help detecting race conditions with asych inputs?
70094: 04/06/02: Re: Tool to help detecting race conditions with asych inputs?
70274: 04/06/10: Re: Avoid action on very short peak on input signal (Xilinx Spartan 2)
70300: 04/06/11: Re: How to obtain original input/output signal name from SDF Timing Simulation within Modelsim?
70303: 04/06/11: Re: Interfacing FPGA to on-board SRAM Stratix EP1S40F780C5
70347: 04/06/13: Re: a newbie question
70358: 04/06/14: Re: How to obtain original input/output signal name from SDF Timing
70703: 04/06/23: Re: Trying to remember how to use Quartus
70715: 04/06/24: Re: booting fpga and xscale
70741: 04/06/25: Re: synchronizer and Reset question?
70758: 04/06/26: Re: a newbie question
70977: 04/07/03: Re: FPGAs starting with incorrect bitstream !?
71071: 04/07/07: Re: spartan3 board for newbie: xilinx XC3S200 starter kit or nu-horizons XC3S400 board???
71185: 04/07/11: Re: Modelsim crash (code 211) when using library
71267: 04/07/13: Re: Puzzled Simulating with 'X' input Quartus II v4.0 sp1
71337: 04/07/14: Re: Enum type as array range
72056: 04/08/06: Re: Need StateCAD 4.11!
72071: 04/08/07: Re: Synchronizing Reset De-assertion
72491: 04/08/20: Re: Quartus, building "Safe" FMSs
72584: 04/08/25: Re: 6.1 vs. 6.2
72602: 04/08/26: Re: 6.1 vs. 6.2
72630: 04/08/26: Re: 6.1 vs. 6.2
72652: 04/08/27: Re: 6.1 vs. 6.2 - one more question
72689: 04/08/28: Re: X propagation in Timing Simulation
72690: 04/08/28: Re: 6.1 vs. 6.2
72745: 04/08/31: Re: modelsim and rocketio
72954: 04/09/08: Re: Initializing memory from a testbench
73281: 04/09/17: Re: Synthesis problems with while and non-constant terminal point.
73320: 04/09/19: Re: doing 'slow' calculations in verilog
73721: 04/09/28: Re: VHDL inout used for non bidirectional uses
73894: 04/09/30: Wang Nam
72976: 04/09/09: Re: Initializing memory from a testbench
75213: 04/10/29: Re: Altera Quartus 4.0 - inconsistent simulation results
74226: 04/10/06: Re: ActGen to use or not to use?
74476: 04/10/12: Re: Actel Fusefile Reverse Engineering
74572: 04/10/14: Re: Same Bitstream: Different Performance
74702: 04/10/16: Re: What was the first FPGA?
74705: 04/10/16: Re: ModelSim
74904: 04/10/21: Re: Xilinx translate error : Cannot find signal "clk"
75427: 04/11/05: Re: SRL16E_1 primitive instantiation in VHDL
75429: 04/11/05: Re: chipscope pro problem (par)
75465: 04/11/06: Re: SRL16E_1 primitive instantiation in VHDL
75475: 04/11/07: Re: what's the scenario out there
75482: 04/11/07: Re: chipscope pro problem (par)
75483: 04/11/07: Re: Fifo problem in Cyclone devices
75539: 04/11/08: Re: Performing floating point in VHDL
75673: 04/11/11: Re: asynchronous bus transfers
75849: 04/11/16: Re: Xilinx, VHDL, Verilog, ModelSim, BMP
75865: 04/11/17: Re: Xilinx, VHDL, Verilog, ModelSim, BMP
75895: 04/11/18: Re: Async and sync resets
75917: 04/11/18: Re: Async and sync resets
75923: 04/11/19: Re: NIOSII problems?
75955: 04/11/20: Re: Performance of Xilinx System Generator RTL?
75964: 04/11/20: Re: Custom Megafunctions in Quartus II
75979: 04/11/21: Re: 18x18 Multipliers - Spartan III
75980: 04/11/21: Re: Custom Megafunctions in Quartus II
76028: 04/11/22: Re: Async and sync resets
76082: 04/11/23: Re: Choice of FPGA device
76166: 04/11/27: Re: Choice of FPGA device -- my view on benchmarks
76172: 04/11/27: Re: dual-write port BRAM with XST/Webpack
76183: 04/11/27: Re: dual-write port BRAM with XST/Webpack
76193: 04/11/28: Re: dual-write port BRAM with XST/Webpack
76194: 04/11/28: Re: dual-write port BRAM with XST/Webpack
76195: 04/11/28: Re: Choice of FPGA device -- my view on benchmarks
76201: 04/11/28: Re: dual-write port BRAM with XST/Webpack
76309: 04/11/30: Re: Verilog newbie with clocking question
76385: 04/12/01: Re: Weird XPower results for FSMs and different FPGAs
76495: 04/12/04: Re: how to start with development of eda tools
76520: 04/12/05: Re: how to speed up my accumulator ??
76686: 04/12/08: Re: Open source FPGA EDA Tools
76764: 04/12/10: Re: Lookup table simulation problems
76786: 04/12/11: Re: PCI design with vhdl
76800: 04/12/12: Re: Inconsistant compilations with quartus
76810: 04/12/13: Re: Inferring dual port RAMs with different bus widths.
76811: 04/12/13: Re: altera DDR core simulation with NCSim
76971: 04/12/17: Re: Exportability of EDA industry from North America?
77000: 04/12/19: Re: Seeking FPGA and 8MB SDRAM in a PCMCIA Type I card
77221: 04/12/30: Re: Quartus and Cyclone programming problem
77224: 04/12/30: Re: failed to write to SDRAM
77231: 04/12/31: Re: Xilinx ISE : How to make Modelsim reload when design changed
77232: 04/12/31: Re: Inter FPGA communication
77266: 05/01/02: Re: Verilog /DIP Switch Question....
77280: 05/01/03: Re: Recover FPGA Verilog or VHDL source from .SOF file
77281: 05/01/03: Re: Free IP-Core for FPGA Config from MMC-Cards
77306: 05/01/04: Re: Xilinx BlockRAM Memory initialization for ModelSim
77340: 05/01/04: Re: Procedure exit on global signal
77489: 05/01/07: Re: Master's Project
77501: 05/01/08: Re: Showing schematic changes
77510: 05/01/08: Re: weird problem printing Xilinx state machine
77513: 05/01/08: Re: a general question
77568: 05/01/11: Re: Asynchronous signals and simulation
77581: 05/01/11: Re: synthesizable RAM problem
77639: 05/01/12: Re: Modelsim Aliases
77701: 05/01/14: Re: Modelsim Aliases
78178: 05/01/25: Re: Another problem getting ISE 6.3i running on Linux
78179: 05/01/25: Re: Linux on V2P
78335: 05/01/29: Re: Sensitive List Question
78475: 05/02/01: Re: Any solution for solving setup or hold time violation?
78478: 05/02/01: Re: Init of BRAMs with ISE flow.
78548: 05/02/03: Re: problem with Modelsim 5.8 Xilinx Edition
78549: 05/02/03: Re: How to handle clock skew?
78550: 05/02/03: Re: Source of reset for synchronous reset can lead to metastability?
78949: 05/02/10: Re: FPGA synthesis problems
79075: 05/02/13: Re: Xilinx BRAM FIFO problems ModelSim Post Place and Route
79113: 05/02/14: Re: Xilinx BRAM FIFO problems ModelSim Post Place and Route
79140: 05/02/14: Re: ISE versus Modelsim inconsistency and attribute definition
79806: 05/02/24: Re: Synchronous design
79840: 05/02/24: Re: Synthesis question
79891: 05/02/25: Re: Synthesis question
79951: 05/02/26: Re: block adder for Altera!
79973: 05/02/27: Re: block adder for Altera!
79993: 05/02/27: Re: Quartus 4.2 SP1 woes with Samba & !@#$ "Flex"LM
80096: 05/03/01: Re: SR latches in Xilinx devices?
80117: 05/03/01: Re: Part of a ranged signal
80290: 05/03/03: Re: timing diagram tool linux
80361: 05/03/04: Re: RAM Address Calculating
80362: 05/03/04: Re: VHDL Instantiation
80363: 05/03/04: Re: SR latches in Xilinx devices?
80385: 05/03/04: Re: VHDL Instantiation
80429: 05/03/05: Re: Q: state encoding in FSM for simple cases ?
80457: 05/03/06: Re: Newby Getting started with FPGA
80515: 05/03/07: Re: Hierarchical Synchronous Design
80524: 05/03/07: Re: state encoding in FSM for simple cases ?
80534: 05/03/07: Re: state encoding in FSM for simple cases ?
80550: 05/03/08: Re: File I/O with Synplify
80576: 05/03/08: Re: Hierarchical Synchronous Design
80579: 05/03/08: Re: Hierarchical Synchronous Design (corrected)
80649: 05/03/09: Re: Xilinx vs Altera high-end solutions
80650: 05/03/09: Re: File I/O with Synplify
80660: 05/03/09: Re: Xilinx vs Altera high-end solutions
80661: 05/03/09: Re: Xilinx vs Altera high-end solutions
80667: 05/03/09: Re: Xilinx vs Altera high-end solutions
80700: 05/03/10: Re: Spontaneous Board Reset
80701: 05/03/10: Re: State Machine Coding?
80724: 05/03/10: Re: Xilinx vs Altera high-end solutions
80797: 05/03/11: Re: Xilinx vs Altera high-end product solutions?
80831: 05/03/11: Re: Hierarchical Synchronous Design (corrected)
80832: 05/03/11: Re: State Machine Coding?
80852: 05/03/12: Re: Hierarchical Synchronous Design (corrected)
80876: 05/03/13: Re: Newb: FSM in no valid state?
81023: 05/03/16: Re: Sensitivity list
81030: 05/03/16: Re: Xilinx webpack map/route questions
81032: 05/03/16: Re: Sensitivity list
81742: 05/03/30: Re: Achieving required speed in Virtex-II Pro FPGA
81859: 05/04/02: Re: Achieving required speed in Virtex-II Pro FPGA
82299: 05/04/10: Re: rules to assign pins to FPGA?
82580: 05/04/14: Re: Flowcharts and diagrams
82802: 05/04/18: Re: Odd Oversampling
82909: 05/04/19: Re: Odd Oversampling
83014: 05/04/21: Re: CAM for FPGA ...
83030: 05/04/21: Re: CAM for FPGA ...
83183: 05/04/25: Re: bad syncronous description
83436: 05/04/29: Re: Patent issues in implementing embedded fpgas
83471: 05/04/30: Re: Case statement illusions ?
83485: 05/04/30: Re: Case statement illusions ?
83714: 05/05/05: Re: Clock Gating
83784: 05/05/06: Re: newbie question
83833: 05/05/07: Re: newbie question
83892: 05/05/09: Re: Max7000ae and GCLRn
84104: 05/05/12: Re: "Mine is bigger than yours..."
84110: 05/05/12: Re: Tutorial on debug of packet processing in FPGA hardware using
84112: 05/05/12: Re: initializing fifo pointers to simulate overflow
84259: 05/05/16: Re: Universal logic modules vs NAND-like modules
84328: 05/05/17: Re: Universal logic modules vs NAND-like modules
84331: 05/05/17: Re: Stupid Question on the Urination Contest... Re: V4 vs. Stratix-II...
84356: 05/05/17: Re: Which Simulators
84359: 05/05/17: Re: About back annotated simulations...
84392: 05/05/18: Re: About back annotated simulations...
84488: 05/05/19: Re: Coloring by clock?
84545: 05/05/20: Re: Coloring by clock?
84888: 05/05/31: Re: StateCAD 7.1i is broken?
85002: 05/06/02: Re: Basics FPGA
85623: 05/06/12: Re: Best Practices for Hardware Designers
85655: 05/06/13: Re: RAM State Machine Examples
85712: 05/06/14: Re: Viewing internal signal in Modelsim (post P&R)
85748: 05/06/15: Re: VHDL Synthesis tutorial
85750: 05/06/15: Re: Best Practices for Hardware Designers
85801: 05/06/16: Re: Deisgn partitioning issues
85928: 05/06/18: Re: CPLD fusemap data - why the secrecy?
85931: 05/06/18: Re: SystemC comments
85932: 05/06/18: Re: CPLD fusemap data - why the secrecy?
86048: 05/06/21: Re: Altera SCFIFO
86049: 05/06/21: Re: Post Translate Timing
86378: 05/06/27: Re: Two Verilog FSM style compare
86402: 05/06/27: Re: Two Verilog FSM style compare
86451: 05/06/28: Re: Two Verilog FSM style compare
86523: 05/06/29: Re: Hex files in simulation
86667: 05/07/03: Re: Xilinx: XST synchronous FIFO using BRAMs
86672: 05/07/03: Re: Xilinx: XST synchronous FIFO using BRAMs
86779: 05/07/06: Re: VHDL Clock Domains
86786: 05/07/06: Re: Stratix open-drain pins
86927: 05/07/09: Re: Ethernet reference design for ML310?
86928: 05/07/09: Re: Announce: Impulse C-to-RTL Version 2 now available
86940: 05/07/10: Re: Quartus Timing Issues
86997: 05/07/12: Re: QII simulation annoyance
87090: 05/07/14: Re: Block Diagram Viewer / Hierarchy Parser for VHDL/Verilog?
87144: 05/07/17: Re: Serial vs Chipscope
87252: 05/07/20: Re: Using unregistered inputs in FSM
87253: 05/07/20: Re: Using unregistered inputs in FSM
87255: 05/07/20: Re: Using unregistered inputs in FSM
87282: 05/07/20: Re: Design is too large for the device! xc3s400
87322: 05/07/21: Re: Using unregistered inputs in FSM
87323: 05/07/21: Re: Does anyone have a NIOS Ethernet Development Kit?
87337: 05/07/21: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87383: 05/07/22: Re: Using unregistered inputs in FSM
87385: 05/07/22: Re: Using unregistered inputs in FSM
87466: 05/07/24: Re: July 20th Altera Net Seminar: Stratix II Logic Density
87537: 05/07/25: Re: VHDL soft-core portability to Xilinx, Altera, Atmel....
87600: 05/07/26: Re: ISE makes a mistake
87723: 05/07/29: Re: Using unregistered inputs in FSM
87801: 05/08/01: Re: struggling with general digital design
87802: 05/08/01: Re: Xilinx Best Source for Reset
87865: 05/08/02: Re: Porting Actel code
87903: 05/08/03: Re: Porting Actel code
87904: 05/08/03: Re: Xilinx Best Source for Reset
87974: 05/08/04: Re: Xilinx Best Source for Reset
88150: 05/08/10: Re: FPGA Programming using Block Design Files or Graphic Design Files
88317: 05/08/15: Re: Cypress CY7B923/33 models
88378: 05/08/16: Re: image sensor
88454: 05/08/18: Re: Modelsim on a remote display
88517: 05/08/21: Re: Using very large number in VHDL
88543: 05/08/22: Re: Problem in timing simulation(Altera)
88554: 05/08/22: Re: Generic Memory-Mapped VHDL Module
88559: 05/08/22: Re: Different Synthesis Results on Different Levels of Hierarchy
88595: 05/08/23: Re: uDMA Hard drive interface - putting together multiple programs.
88663: 05/08/24: Re: Help coding a bigger project
88708: 05/08/25: Re: Help coding a bigger project
88760: 05/08/27: Re: Problem with ModelSim XE
88762: 05/08/27: Re: infering a BRAM block for a dual ported ROM
88870: 05/08/30: Re: Simulation problems with EDK 7.1.02i and ModelSim SE 6.1a
88871: 05/08/30: Re: 8087 co-processor
88926: 05/08/31: Re: Simulation problems with EDK 7.1.02i and ModelSim SE 6.1a
88930: 05/08/31: Re: Fine grain vs. Coarse Grain Architectures
88974: 05/09/01: Re: Mentor FPGA Advantage, a simple question
89195: 05/09/07: Re: Spartan-3E Starter Kit availability slips to December
89240: 05/09/08: Re: [XST] FSM extraction question
89262: 05/09/09: Re: Post synthesis simulation errors
89280: 05/09/09: Re: Need advice: old Xilinx schematic design -> VHDL...GSR issue(s)
89414: 05/09/14: Re: FIFO design using Virtex-II block ram..
89422: 05/09/14: Re: VHDL: Address Decoder
89451: 05/09/15: Re: IP Protection of code block in Xilinx FPGA?
89525: 05/09/17: Re: Software tools for architectural diagrams and for timing diagram
89577: 05/09/19: Re: Using BRAMs in VHDL on Virtex II FPGAs
89609: 05/09/20: Re: problem with Thold violation under quartus
89789: 05/09/26: Re: External dpram similar to blockram of Xilinx device
89899: 05/09/29: Re: Synchronous & Asymchrnous Flip Flop Implementation
89939: 05/09/30: Re: Testbench using Modelsim/VHDL - simple signal generation problem
90049: 05/10/03: Re: vhdl question
90149: 05/10/05: Re: vhdl question
90463: 05/10/13: Re: Anyone remember the really early Xilinx FPGAs?
90611: 05/10/17: Re: FPGA timming
90762: 05/10/20: Re: EDK/ISE : unroutable design
90854: 05/10/23: Re: FPGA Design Docs
90929: 05/10/25: Re: FPGA Design Docs
90950: 05/10/25: Re: ETHERNET MAC
90954: 05/10/25: Re: a few questions
90996: 05/10/26: Re: crc on only data or including the address
91008: 05/10/26: Re: crc on only data or including the address
91010: 05/10/27: Re: Optimizing a State Machine
91077: 05/10/28: Re: crc on only data or including the address
91156: 05/10/31: Re: Mitrion-C
91182: 05/10/31: Re: hex rep. in VHDL
91212: 05/11/01: Re: hex rep. in VHDL
91215: 05/11/01: Re: can ethereal detect an ethernet packet for which crc is wrong
91380: 05/11/04: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
91389: 05/11/04: Re: FPGA : PCI core needed
91411: 05/11/05: Re: The HLL GUI multi-fpga DIME design environment
91428: 05/11/06: Re: Anybody understand this ISE 7.1 error, and what to do about it???
91433: 05/11/06: Re: Anybody understand this ISE 7.1 error, and what to do about it???
91585: 05/11/09: Re: Installing FPGA Advantage on Linux machine
91667: 05/11/10: Re: Signal timing problem
91682: 05/11/10: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries,
91687: 05/11/10: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries,
91697: 05/11/10: Re: Forcing carry-ripple adder ?
91741: 05/11/11: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries,
91743: 05/11/11: Re: Signal timing problem
91756: 05/11/11: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries,
91821: 05/11/14: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries,
91880: 05/11/15: Re: Having trouble Detecting ethernet packets using ethereal
91944: 05/11/17: Re: complexity of arithmetic
91957: 05/11/17: Re: FPGA CAM/TCAM
91999: 05/11/18: Re: Chipscope Pro License Problem
92017: 05/11/19: Re: Oh no! Resets Again? Yes, but it could be important.
92021: 05/11/19: Re: Oh no! Resets Again? Yes, but it could be important.
92062: 05/11/21: Re: Modelsim Verification : Retain FSM state names
92105: 05/11/22: Re: Quartus Problem
92152: 05/11/22: Re: Patient Monitors: Reading RS232 output w/ an FPGA
92177: 05/11/23: Re: Xst optimizes almost everything away
92195: 05/11/23: Re: Disabling Xilinx clock enable usage...
92318: 05/11/27: Re: Distributed RAMs / SRL: Why not, Altera?
92324: 05/11/27: Re: Distributed RAMs / SRL: Why not, Altera?
92352: 05/11/28: Re: Altera Pin not used in Quartus project but drives logic
92365: 05/11/28: Re: Difficulty compiling on Quartus 2 version 5
92500: 05/11/30: Re: systemC vs VHDL
92507: 05/11/30: Re: systemC vs VHDL
92525: 05/11/30: Re: systemC vs VHDL
92563: 05/12/01: Re: Xilinx LUT behavior question
92897: 05/12/08: Re: Simulating Post-Synthesis Model on Xilinx FPGA
93084: 05/12/13: Re: Xilinx floating point core 1.0
93086: 05/12/13: Re: Which decides my design's max frequency?
93193: 05/12/15: Re: Xilinx floating point core 1.0
93215: 05/12/15: Re: Inverter Chain Synthesis Problem
93360: 05/12/20: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar
93366: 05/12/20: Re: Place and Route Algorithms
93367: 05/12/20: Re: More beginner's verilog questions
93683: 05/12/28: Re: Using Synplicity to synthesize EDK user IP's
93862: 06/01/02: Re: Timing problem in ModelSim, Post-Route Simulation.
94023: 06/01/04: Re: Timing problem in ModelSim, Post-Route Simulation.
94032: 06/01/04: Re: Timing problem in ModelSim, Post-Route Simulation.
94024: 06/01/04: Re: Schematic Entry, Xilinx or Altera?
94029: 06/01/04: Re: Schematic Entry, Xilinx or Altera?
94036: 06/01/04: Re: Schematic Entry, Xilinx or Altera?
94207: 06/01/07: Re: Schematic Entry, Xilinx or Altera?
94309: 06/01/09: Re: ISE 7.1 & ModelSim - Simulating Internal Signals
94221: 06/01/08: Re: Help! FIR Filter - MATLAB fdatool - VHDL
94285: 06/01/09: Re: Verilog to VHDL translation tool
94289: 06/01/09: Re: "failed to create empty document"
94311: 06/01/09: Re: "failed to create empty document"
94346: 06/01/10: Re: "failed to create empty document"
94281: 06/01/09: Re: Question on Alias in VHDL
94314: 06/01/09: Re: Question on Alias in VHDL
94363: 06/01/10: Re: Breaking of Ethernet Frames
96079: 06/01/29: Re: tristate to logic conversion
96199: 06/01/31: Re: Digilent FPGA & Handel-C
96203: 06/01/31: Re: Digilent FPGA & Handel-C
96364: 06/02/02: Re: Die Area
96359: 06/02/02: Re: don't care condition
96467: 06/02/03: Re: fpga hardware "breakpoint"
96578: 06/02/06: Re: Software Defined Radio Transmitter Demo Board
96929: 06/02/13: Re: SCHEMATICS ... Is anybody as frustrated as I am with the software?
96932: 06/02/13: Re: digital logic library by 74xxxx part number?
97096: 06/02/16: Re: digital logic library by 74xxxx part number?
97377: 06/02/21: Re: Is FPGA code called gateware?
97390: 06/02/21: Re: Is FPGA code called gateware?
97392: 06/02/21: Re: Is FPGA code called gateware?
97523: 06/02/23: Re: project validation: best procedures?
97538: 06/02/23: Re: Variables in VHDL and simulation
97710: 06/02/26: Re: about Xilinx Chipscope
97781: 06/02/27: Re: FPGA: Model-SIm XE problem
98247: 06/03/07: Re: recommendation for JTAG Boundary Scan software??
98255: 06/03/07: Re: recommendation for JTAG Boundary Scan software??
98323: 06/03/08: Re: Asynchronous FIFO design question
98514: 06/03/11: Re: ModelSim 6.0 v 5.7 Can't read file
98551: 06/03/12: Re: ModelSim 6.0 v 5.7 Can't read file
98553: 06/03/12: Re: Shift Register synthesis??
98619: 06/03/13: Re: Why does Xilinx hate version control?
98674: 06/03/14: Re: Why does Xilinx hate version control?
98726: 06/03/15: Re: Variable problem
98812: 06/03/16: Re: PowerPC Problems in Virtex
98827: 06/03/16: Re: Measuring pulse width in ModelSim simulation without using cursors
98897: 06/03/17: Re: Instantiating addsub, comparators in Xilinx
98918: 06/03/17: Re: Debugging ideas.
99005: 06/03/18: Re: Support software for XC3042
99074: 06/03/19: Re: is conv_integer(unsigned(value)) synthesizable
99099: 06/03/20: Re: What are the major difference between MXE 6.0 and MXE 5.7?
99129: 06/03/20: Re: Instantiating addsub, comparators in Xilinx
99212: 06/03/21: Re: Simulation tool
99214: 06/03/21: Re: Xilinx Square Root Unit
99258: 06/03/21: Re: Variable problem
99440: 06/03/24: Re: FPGA introduction/FAQ?
99465: 06/03/24: Re: Accessing ModelSim Environment variables in Verilog code
99512: 06/03/25: Re: C-based FPGA programming/mixed languages
99548: 06/03/26: Re: need help,test on Spartan3 starter kit
99613: 06/03/27: Re: Memory leaks with ISE 8.1
99620: 06/03/27: Re: Memory leaks with ISE 8.1
99723: 06/03/28: Re: Variable problem
99724: 06/03/28: Re: C-based FPGA programming/mixed languages
99793: 06/03/29: Re: free synthesizer to synthesize VHDL to Actel 1280XL FPGA
99796: 06/03/29: Re: OpenSPARC released
99878: 06/03/30: Re: Help needed
99896: 06/03/30: Re: OpenSPARC released
100044: 06/04/01: Re: Hierarchical FSM?
100045: 06/04/02: Re: ModelSim Designer
100058: 06/04/02: Re: ModelSim Designer
100085: 06/04/03: Re: ModelSim Designer
100191: 06/04/04: Re: Dual-edge synthesizable D flip-flop - any pitfalls?
100228: 06/04/05: Re: Altera Stratix II GX LVDS max speed
100294: 06/04/06: Re: Bizarre behaviour by Quartus?
100317: 06/04/06: Re: Altera Talkback
100320: 06/04/06: Re: Bizarre behaviour by Quartus?
100417: 06/04/08: Re: Compiler to FPSLIC
100420: 06/04/08: Re: Infer dual-clock block RAM for Xilinx
100423: 06/04/08: Re: Infer dual-clock block RAM for Xilinx
100601: 06/04/12: Re: FPGA FAQ and the spam problem
100697: 06/04/16: Re: Where is the xilinx online store gone?
100698: 06/04/16: Re: Where is the xilinx online store gone?
100747: 06/04/17: Re: PLD610
100795: 06/04/18: Re: comparison with integer
100799: 06/04/18: Re: How to connect FPGA and =?ISO-8859-15?Q?=B5C?=
100819: 06/04/18: Re: MaxPlus2 and the Byteblaster MV
100885: 06/04/20: Re: Reliability CPLD/FPGA vs Microcontroller
100892: 06/04/20: Re: Synthesizer is creating unwanted global resources
100912: 06/04/20: Re: Synthesizer is creating unwanted global resources
100913: 06/04/20: Re: Xilinx PCIe core vs. Icarus Verilog
101014: 06/04/24: Re: Xilinx ISE Project Navigator bug
101023: 06/04/24: Re: CAM, TCAM in Stratix
101024: 06/04/24: Re: comp.arch.reconfig
101053: 06/04/24: Re: vhdl cpu emulator (any interest?)
101095: 06/04/25: Re: How to get divider in CRC32 , while implementatinh it in VHDL?
101199: 06/04/27: Re: How are constants stored ?
101233: 06/04/27: Re: Synplify is not translating xilinx template for block ram
101538: 06/05/02: Re: Quartus and source control
101668: 06/05/04: Re: Cordic-based Sine Computer in MyHDL
101674: 06/05/04: Re: Cordic-based Sine Computer in MyHDL
101749: 06/05/05: Re: Cordic-based Sine Computer in MyHDL
101823: 06/05/07: Re: The differences between behaviors of 'std_logic_vector' and 'unsigned'
101824: 06/05/07: Re: A constant value of 0 in block
102095: 06/05/10: Re: Quartus II 6.0 available
102950: 06/05/23: Re: Verilog vs VHDL
103007: 06/05/24: Re: Stopping Quartus using multipliers?
103093: 06/05/25: Re: Quartus and Cygwin X-server
103152: 06/05/26: Re: Independent clock FIFOs
103370: 06/05/31: Re: Quartus and source control
103419: 06/06/01: Re: Quartus and source control
103421: 06/06/01: Re: clockless arbiters on fpgas?
103422: 06/06/01: Re: timings
103424: 06/06/01: Re: Ethernet Snooping in the FPGA
103599: 06/06/06: Re: Efficient implementation of Address Decoding logic
103606: 06/06/06: Re: Efficient implementation of Address Decoding logic
103637: 06/06/07: Re: Efficient implementation of Address Decoding logic
103696: 06/06/08: Re: Rumor Control:: Will Quartus phase out supporting AHDL?
103823: 06/06/12: Re: How to get lowest price for a ModelSim license?
103824: 06/06/12: Re: from VHDL to FPGA
103853: 06/06/13: Re: How to get lowest price for a ModelSim license?
103866: 06/06/13: Re: FSM state minimization with ISE?
103909: 06/06/14: Re: FSM state minimization with ISE?
104040: 06/06/17: Re: How to get lowest price for a ModelSim license?
104042: 06/06/17: Re: FSM state minimization with ISE?
104046: 06/06/17: Re: How to get lowest price for a ModelSim license?
104176: 06/06/20: Re: FSM State Minimization on FPGAs
104181: 06/06/20: Re: FSM State Minimization on FPGAs
104210: 06/06/21: Re: Xilinx ISE 8.1i Trouble
104215: 06/06/21: Re: FSM State Minimization on FPGAs
104218: 06/06/21: Re: FSM State Minimization on FPGAs
104219: 06/06/21: Re: Xilinx ISE 8.1i Trouble
104235: 06/06/21: Re: Xilinx ISE 8.1i Trouble
104297: 06/06/22: Re: stimulus for FPGA
104318: 06/06/23: Re: stimulus for FPGA
104940: 06/07/10: Re: The FFs with synchronous reset perform worse?
105002: 06/07/11: Re: DIFFICULT MULTICYCLE PATH WITH QUARTUS II
105148: 06/07/14: Re: Need for reset in FPGAs
105154: 06/07/14: Re: Need for reset in FPGAs
105238: 06/07/18: Re: P160 Communications module 3 with V2PRO--> EDK 7.1 errors
105304: 06/07/19: Re: Inferring a Xilinx FIFO
105366: 06/07/20: Re: Hardware book like "Code Complete"?
105404: 06/07/21: Re: Hardware book like "Code Complete"?
105424: 06/07/22: Re: How to print a state flow graph for a state machine using Xilinx
105425: 06/07/22: Re: Using BUS'es in ISE WebPACK 3.3WP8.1 ???
105482: 06/07/24: Re: Hardware book like "Code Complete"?
105483: 06/07/24: Re: Hardware book like "Code Complete"?
105492: 06/07/24: Re: Hardware book like "Code Complete"?
105543: 06/07/25: Re: Hardware book like "Code Complete"?
105642: 06/07/27: Re: OT (2nd try): do you get paid for your travel time?
105685: 06/07/28: Re: Hardware book like "Code Complete"?
105689: 06/07/28: Re: Hardware book like "Code Complete"?
105691: 06/07/28: Re: Hardware book like "Code Complete"?
105774: 06/07/31: Re: DDR2 SRAM Stratix II questions
105851: 06/08/01: Re: Programmable pulse generator
105893: 06/08/02: Re: Hardware book like "Code Complete"?
105895: 06/08/02: Re: ISE8.2 + .ngo file + Leonardo
106073: 06/08/07: Re: WHAT SITUATION I NEED A BUFFER
106099: 06/08/07: Re: verilog versus vhdl
106102: 06/08/07: Re: WHAT SITUATION I NEED A BUFFER
106114: 06/08/07: Re: WHAT SITUATION I NEED A BUFFER
106136: 06/08/08: Re: WHAT SITUATION I NEED A BUFFER
106140: 06/08/08: Re: Newbie question
106154: 06/08/08: Re: verilog versus vhdl
106166: 06/08/08: Re: verilog versus vhdl
106168: 06/08/08: Re: verilog versus vhdl
106229: 06/08/09: Re: A Newbie question
106359: 06/08/12: Re: Compiler can't detect std_logic_1164 package
106404: 06/08/12: Re: Compiler can't detect std_logic_1164 package
106495: 06/08/14: Re: synthesis intelligence of quartus regarding range of values
106496: 06/08/14: Re: consistancy in synthesis/ simulation model
106558: 06/08/15: Re: synthesis intelligence of quartus regarding range of values
106571: 06/08/15: Re: IIR filter example ?
106575: 06/08/15: Re: IIR filter example ?
106706: 06/08/17: Re: Alternative for Mentor''s HDL Designer
106796: 06/08/19: Re: Speed vs Area Optimisation
107123: 06/08/24: Re: Style of coding complex logic (particularly state machines)
107131: 06/08/24: Re: Style of coding complex logic (particularly state machines)
107240: 06/08/25: Re: Installing Quartus 6 "web edition full"
107441: 06/08/28: Re: Style of coding complex logic (particularly state machines)
107445: 06/08/28: Re: Question about library update in Modelsim
107453: 06/08/28: Re: Style of coding complex logic (particularly state machines)
107508: 06/08/29: Re: Style of coding complex logic (particularly state machines)
107518: 06/08/29: Re: Style of coding complex logic (particularly state machines)
107613: 06/08/30: Re: Style of coding complex logic (particularly state machines)
108120: 06/09/05: Re: FIFO with EBR
108187: 06/09/06: Re: Global constants definition problem
108188: 06/09/06: Re: Exploring Quartus' Messages and Warnings
108198: 06/09/06: Re: Exploring Quartus' Messages and Warnings
108313: 06/09/07: Re: Managing small IP library
109779: 06/10/05: Re: An implementation of a clean reset signal
109781: 06/10/05: Re: How to accelerate bitstream file generation?
109784: 06/10/05: Re: EDIF
109786: 06/10/05: Re: Just a matter of time
109796: 06/10/05: Re: nicer code => slower code??
109880: 06/10/06: Re: An implementation of a clean reset signal
109881: 06/10/06: Re: Instantiating Altera M4K block without MegaWizard
109988: 06/10/09: Re: Antifuse, lower cost?
110065: 06/10/10: Re: FPGA to SRAM port interface
110074: 06/10/10: Re: FPGA to SRAM port interface
110238: 06/10/12: Re: Functional Languages in Hardware
110245: 06/10/12: Re: Glitches in post-layout (PAR) simulation
110252: 06/10/12: Re: Glitches in post-layout (PAR) simulation
110258: 06/10/12: Re: Glitches in post-layout (PAR) simulation
110339: 06/10/13: Re: Xilinx V4 not registering T at OLOGIC
110487: 06/10/16: Re: Libero 7.2
110488: 06/10/16: Re: Synthesizing Xilinx Coregen cores
110540: 06/10/17: Re: Libero 7.2
110601: 06/10/18: Re: Cheapest FPGA board to study VHDL on
110669: 06/10/19: Re: Cheapest FPGA board to study VHDL on
110917: 06/10/25: Re: What should I do with std.textio.all of ModelSim
110991: 06/10/26: Re: What should I do with std.textio.all of ModelSim
110997: 06/10/26: Re: What should I do with std.textio.all of ModelSim
111009: 06/10/26: Re: What should I do with std.textio.all of ModelSim
111074: 06/10/28: Re: Stratix II basic questions
111081: 06/10/28: Re: Stratix II basic questions
111163: 06/10/30: Re: Question about generic usage?
111328: 06/11/01: Re: Interface standards (was Re: Dual Port RAM)
111334: 06/11/01: Re: Interface standards (was Re: Dual Port RAM)
111404: 06/11/02: Re: Interface standards (was Re: Dual Port RAM)
111409: 06/11/02: Re: Interface standards (was Re: Dual Port RAM)
111484: 06/11/03: Re: Xilinx ISE Webpack - Any usable simulator for the Linux platform
111608: 06/11/06: Re: Interface standards (was Re: Dual Port RAM)
111649: 06/11/07: Re: Should I use an external synthesis tool?
111662: 06/11/07: Re: Modelsim problem - mixed VHDL,Verilog & VHO
111668: 06/11/07: Re: problems with using altera vhdl testbench in ModelSim
111677: 06/11/07: Re: problems with using altera vhdl testbench in ModelSim
111765: 06/11/09: Re: bidirectional bus
111767: 06/11/09: Re: bidirectional bus => mux
111806: 06/11/10: Re: bidirectional bus => mux
111927: 06/11/13: Re: simulating two-dimensional array in vhdl
111985: 06/11/14: Re: Compile error by Cadence NC-Sim
112001: 06/11/14: Re: Compile error by Cadence NC-Sim
112004: 06/11/14: Re: Why are there ModelSimAltera warning
112137: 06/11/16: Re: Validity of data on rising edge of clock
112466: 06/11/22: Re: Protecting netlist for Xilinx
112901: 06/11/30: Re: Can I see the detail timing parameter by Quartus II tools?
112909: 06/11/30: Re: Can I see the detail timing parameter by Quartus II tools?
112935: 06/12/01: Re: Avoiding meta stability?
112938: 06/12/01: Re: Can I see the detail timing parameter by Quartus II tools?
113260: 06/12/09: Re: testbench help
113489: 06/12/14: Re: How does FPGA tools infer FIFO
113789: 06/12/21: Re: timing?
113827: 06/12/23: Re: Help with xilinx simulation?
113845: 06/12/24: Re: mobius, from codetronix, anyone has been tested
114012: 07/01/02: Re: ISE Simulator radix question
114155: 07/01/05: Re: [XST 8.2.3] DSP48 inference multiply/add
114180: 07/01/06: Re: Problem with unused pin on Spartan 2E
114183: 07/01/06: Re: query
114185: 07/01/06: Re: Problem with unused pin on Spartan 2E
114188: 07/01/06: Re: email protection in the list
114214: 07/01/07: Re: Use Multi-cycle Path or Pipeline?
114237: 07/01/08: Re: Use Multi-cycle Path or Pipeline?
114370: 07/01/12: Re: How to get correct initial values from Xilinx Vertex II single
114376: 07/01/13: Re: ethernet checksum nightmare
114378: 07/01/13: Re: ethernet checksum nightmare
114385: 07/01/13: Re: IDELAY and whether pigs can fly...
114415: 07/01/15: Re: How to ensure Select signal arrives after Input signals changed
114454: 07/01/16: Re: microcode in verilog?
114677: 07/01/22: Re: edif format
114736: 07/01/23: Re: Good hardware design code re-use strategies, reference book
114738: 07/01/23: Re: NIOS II Application startup issues
114868: 07/01/25: Re: video buffering scheme, nonsequential access (no spatial locality)
115012: 07/01/29: Re: question about DCM usage in virtex 5
115021: 07/01/29: Re: question about DCM usage in virtex 5
115096: 07/01/30: Re: ahdl --> vhdl
115205: 07/02/02: Re: XST broken for XC9536?
115300: 07/02/06: Re: help with Design Compiler -> Quartus
115435: 07/02/10: Re: ModelSim - Do Files
115618: 07/02/15: Re: Need fair opinions on choosing either Altera or Xilinx as main
116085: 07/03/01: Re: How to implement pipeline in this case?
116161: 07/03/02: Re: How to implement pipeline in this case?
116341: 07/03/07: Re: Query regarding Project.Plz help very urgent
116355: 07/03/07: Re: DFF with clock and async-preset tied together
116563: 07/03/12: Re: Dual edge detection
116607: 07/03/13: Re: help !something wrong with Adaptive Filter (vhdl code)
117191: 07/03/26: Re: Small memories in Cyclone
117468: 07/04/01: Re: Question about initializing the ram value in test bench
117674: 07/04/06: Re: How to use the 8LEDs on DIO4 when connected to Virtex 2 Pro kit?
117722: 07/04/08: Re: How do I use the Xilinx USB download cable for testing?
117754: 07/04/09: Re: record type port in vhdl and simulation in ISE
117863: 07/04/11: Re: OT. Re: POC at Element CXI
117864: 07/04/11: Re: Timing violations though constraints have been met
117956: 07/04/14: Re: Order of the synchronous operations
117957: 07/04/14: Re: Order of the synchronous operations
117965: 07/04/14: Re: Order of the synchronous operations
117982: 07/04/15: Re: Order of the synchronous operations
117984: 07/04/15: Re: Order of the synchronous operations
118114: 07/04/17: Re: creating library in ISE 9
118351: 07/04/24: Re: XPS behavioral simulation fails: the design is not loaded
118389: 07/04/25: Re: The simulation library compilation wizard of EDK can't find modelsim
118390: 07/04/25: Re: Take verilog code from Xilinx Core generator
118534: 07/04/29: Re: debounce state diagram FSM
118595: 07/04/30: Re: synthesis tools
118608: 07/04/30: Re: Please help me fast !!!!!
118847: 07/05/04: Re: Use of "blocks" in Quartus design
118870: 07/05/04: Re: Atom HDL
118881: 07/05/05: Re: Atom HDL
119253: 07/05/15: Re: LF VHDL to FSM bubble diagram translator
119255: 07/05/15: Re: LF VHDL to FSM bubble diagram translator
119305: 07/05/16: Re: seeking insights for potential reconfigurable computing application
119503: 07/05/21: Re: Does FPGA need CPU for processing a packet/frame
119508: 07/05/21: Re: VHDL newbie: building sequential circuits with basic gates
119557: 07/05/22: Re: System-synchronous interface clocking between FPGA's
119692: 07/05/24: Re: Use BRAM as ROM (Xilinx)
119694: 07/05/24: Re: How to code a bidirectional databus?
119763: 07/05/25: Re: How to code a bidirectional databus?
119874: 07/05/28: Re: SignalTap Analyzer...
120342: 07/06/05: Re: Topics and Ideas for BS Project
120344: 07/06/05: Re: Mesa 5i21 Xilinx
120345: 07/06/05: Re: XST sythesizes fifos instead of creating black boxes
120398: 07/06/06: Re: How to Find false path in a design
120399: 07/06/06: Re: asynchronous circuit design
120400: 07/06/06: Re: Quartus Advisors
120523: 07/06/08: Re: EDK Simulation Problem
120640: 07/06/12: Re: XIlinx tools question - how to quickly identify unconstrained
120682: 07/06/13: Re: Newbie questions: Can I do this PLL all digitally in a FPGA?
120693: 07/06/13: Re: Incremental Compilation in Altera Quartus II version 7.1
120787: 07/06/16: Re: Simulating analogue signal using ISE simulator
120803: 07/06/17: Re: fitting problem on A54SX72A
120832: 07/06/18: Re: How to simulate testbenches using the ISE simulator in linux
121026: 07/06/22: Re: How to deal with unavoidable setup time violation in CoolRunner
121065: 07/06/24: Re: Multidimensional Register in Modul Port List
121087: 07/06/25: Re: Multidimensional Register in Modul Port List
121098: 07/06/25: Re: Xilinx FPGA: "after 10ns" constraint
121103: 07/06/25: Re: Xilinx FPGA: "after 10ns" constraint
121131: 07/06/26: Re: Coding style of verilog for FPGA synthesis
121370: 07/07/03: Re: Metastability in very slow clock domains
121383: 07/07/03: Re: cosimulation
121487: 07/07/05: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121494: 07/07/05: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121574: 07/07/08: Re: Question on Virtex2p DCMs usability
121593: 07/07/09: Re: regarding post place and route timing simulation steps........
121594: 07/07/09: Re: Spartan3A : timing Constraints / DCM Outputs
121597: 07/07/09: Re: Error message in ModelSIM PE
121612: 07/07/09: Re: Synplify Problem
121645: 07/07/10: Re: lpm_constant function in Altera Quartus 7.1
121660: 07/07/11: Re: ML555 SFP module
121707: 07/07/11: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121749: 07/07/12: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121766: 07/07/12: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121895: 07/07/14: Re: [ISE] How to create and map user library in command-line?
122060: 07/07/18: Re: Latches
122150: 07/07/20: Re: Writing to bram and reading from bram with microblazer
122202: 07/07/23: Re: QuartusII Web Edition software question
122270: 07/07/24: Re: Altera or Xilinx
122298: 07/07/25: Re: Altera or Xilinx
122331: 07/07/25: Re: Xilinx VHDL multidimensional array synthesis
122332: 07/07/25: Re: Altera or Xilinx
122343: 07/07/25: Re: Altera or Xilinx
122346: 07/07/25: Re: Timing simulation
122354: 07/07/25: Re: Timing simulation
122511: 07/07/29: Re: Timing simulation
122532: 07/07/30: Re: Xilinx VHDL multidimensional array synthesis
122569: 07/07/31: Re: Xilinx/ModelSim bug ? Clocking headache ...
122619: 07/08/01: Re: Xilinx/ModelSim bug ? Clocking headache ...
122625: 07/08/01: Re: Static Timing Analysis Using Primetime for FPGAs
122632: 07/08/01: Re: Xilinx/ModelSim bug ? Clocking headache ...
122684: 07/08/02: Re: Xilinx/ModelSim bug ? Clocking headache ...
122699: 07/08/03: Re: Static Timing Analysis Using Primetime for FPGAs
122705: 07/08/03: Re: Static Timing Analysis Using Primetime for FPGAs
122714: 07/08/04: Re: SDR SDRAM controller for Xilinx Spartan-3E
122771: 07/08/06: Re: Problem about clock switch in Quartus II 6.0
122860: 07/08/08: Re: New Xilinx forum.
122893: 07/08/09: Re: New Xilinx forum.
122896: 07/08/09: Re: Synthesizing fixed_pkg in ISE 9.2
123073: 07/08/15: Re: Xilinx PACKER warning bout carry
123114: 07/08/16: Re: Fighting with Compact Flash
123126: 07/08/16: Re: Xilinx PACKER warning bout carry
123131: 07/08/16: Re: Xilinx PACKER warning bout carry
123141: 07/08/16: Re: Xilinx PACKER warning bout carry
123190: 07/08/19: Re: Xilinx / ISE multi-cycle path constraint pitfall
123202: 07/08/19: Re: Xilinx / ISE multi-cycle path constraint pitfall
123254: 07/08/21: Re: Globally Asynchronous in FPGA
123274: 07/08/22: Re: Need to force all signals in a design to a known value at start
123325: 07/08/23: Re: Xilinx / ISE multi-cycle path constraint pitfall
123372: 07/08/25: Re: Xilinx / ISE multi-cycle path constraint pitfall
123397: 07/08/27: Re: Null statement in VHDL
123400: 07/08/27: Re: Null statement in VHDL
123454: 07/08/28: Re: Xilinx / ISE multi-cycle path constraint pitfall
123455: 07/08/28: Re: New keyword 'orif' and its implications
123462: 07/08/28: Re: bidirectional pin help
123482: 07/08/28: Re: New keyword 'orif' and its implications
123525: 07/08/29: Re: New keyword 'orif' and its implications
123596: 07/08/30: Re: New keyword 'orif' and its implications
123605: 07/08/30: Re: Xilinx / ISE multi-cycle path constraint pitfall
123998: 07/09/10: Re: VHDL Synthesis Error
124069: 07/09/11: Re: Uses of Gray code in digital design
124070: 07/09/11: Re: Uses of Gray code in digital design
124074: 07/09/11: Re: Stratix III Memory usage efficiency
124087: 07/09/11: Re: Uses of Gray code in digital design
124124: 07/09/12: Re: Stratix III Memory usage efficiency
124125: 07/09/12: Re: Uses of Gray code in digital design
124207: 07/09/14: Re: Open-Source VHDL Synthesis for FPSLIC?
124208: 07/09/14: Re: Is post-place and route simulation useful?
124210: 07/09/14: Re: Physical Design Contribution to FPGA/CPLD success
124214: 07/09/14: Re: Physical Design Contribution to FPGA/CPLD success
124216: 07/09/14: Re: Physical Design Contribution to FPGA/CPLD success
124227: 07/09/14: Re: Beginner Advice (Languages, tools etc.)
124322: 07/09/18: Re: Tristate bus on spartan FPGA
124396: 07/09/20: Re: Clock boundary crossing
124403: 07/09/20: Re: Comparing Adder synthesis techniques
124437: 07/09/21: Re: help! ACTEL PROASIC PLUS clock buffer
124464: 07/09/22: Re: CRC calculation of Virtex 4 bitstream
124507: 07/09/25: Re: Never buy Altera!!!!
124520: 07/09/25: Re: Never buy Altera!!!!
124710: 07/10/01: Re: Xilinx ISE 'feature': forcing a DUT signal
124720: 07/10/01: Re: FPGA NTSC signal with 2 resistors and PWM
124737: 07/10/02: Re: Basic VHDL Development kit
124746: 07/10/02: Re: Test and Measurements - Large FPGA
124760: 07/10/03: Re: Basic VHDL Development kit
124761: 07/10/03: Re: Detecting if an error happened in ModelSim
124765: 07/10/03: Re: Detecting if an error happened in ModelSim
124771: 07/10/03: Re: Detecting if an error happened in ModelSim
124774: 07/10/03: Re: Basic VHDL Development kit
124923: 07/10/10: Re: Xilinx ISE 'feature': forcing a DUT signal
124945: 07/10/11: Re: Quartus II 7.2 web edition - Linux or not?
124956: 07/10/12: Re: Graphical VHDL Viewer ?
124971: 07/10/13: Re: Quartus II 7.2 web edition - Linux or not?
125003: 07/10/15: Re: profiling in modelsim
125004: 07/10/15: Re: Clock boundary crossing
125011: 07/10/15: Re: Cyclone II on Altera DE2 Board - DRAM Timing on 18 inches?
125022: 07/10/15: Re: Xilinx timing constraints incorrect?
125043: 07/10/15: Re: FPGA quiz: what can be wrong
125136: 07/10/16: Re: ethernet phy or mac
125138: 07/10/16: Re: Quartus II Web Edition License - SOPC Builder generation?
125144: 07/10/16: Re: Xilinx timing constraints incorrect?
125154: 07/10/16: Re: Xilinx timing constraints incorrect?
125158: 07/10/16: Re: gold code - seed value
125181: 07/10/17: Re: High level FPGA work flow: available tool?
125207: 07/10/17: Re: High level FPGA work flow: available tool?
125299: 07/10/19: Re: Files produced by Quartus II compiler
125460: 07/10/25: Re: compile EDIF(generated by Celoxica DK4) using Quartus II
125598: 07/10/29: Re: registers are not shown in waveform (xilinx microblaze)
125646: 07/10/30: Re: Updating my bookshelf
125676: 07/10/31: Re: Is it possible to debug a vhdl design over jtag?
125757: 07/11/03: Re: Xilinx's System Generator versus Mathworks' Link for Modelsim
125837: 07/11/06: Re: Why dynamic partial reconfiguration is still not there?
125976: 07/11/10: Re: Why dynamic partial reconfiguration is still not there?
126024: 07/11/12: Re: [EDK tool] simulation setup
126092: 07/11/14: Re: FPGA for hobby use
126101: 07/11/14: Re: FPGA for hobby use
126204: 07/11/16: Re: simulating xilinx block ram with modelsim
126232: 07/11/17: Re: VHDL language is out of date! Why? I will explain.
126292: 07/11/19: Re: Quartus II warning: "pass-through logic has been added"
126452: 07/11/22: Re: VHDL language is out of date! Why? I will explain.
126466: 07/11/23: Re: VHDL language is still quite useful.
126472: 07/11/23: Re: How to simulate these example CORDIC code?
126500: 07/11/25: Re: converter
126518: 07/11/26: Re: vhdl state machine
126567: 07/11/27: Re: VHDL language is out of date! Why? I will explain.
126609: 07/11/28: Re: What's the difference for VHDL code between simulation and
126740: 07/11/30: Re: What tools do you use ? Why ?
126748: 07/11/30: Re: ise timing analysis + different clock domains
126768: 07/12/01: Re: Traffic Light with counter
126822: 07/12/03: Re: What's the difference for VHDL code between simulation and synthesis?
126826: 07/12/03: Re: can't genarate block memory cores in ISE 7.1i
126830: 07/12/03: Re: What's the difference for VHDL code between simulation and
126839: 07/12/03: Re: What's the difference for VHDL code between simulation and
126846: 07/12/04: Re: What's the difference for VHDL code between simulation and synthesis?
126847: 07/12/04: Re: EDK does not find Modelsim
126854: 07/12/04: Re: calculation of clock cycle /instructions...
126899: 07/12/05: Re: What's the difference for VHDL code between simulation and
126902: 07/12/05: Re: What's the difference for VHDL code between simulation and
126912: 07/12/05: Re: Mixed language design
126991: 07/12/07: Re: Pin assignment with Quartus II for PCB placement
127014: 07/12/08: Re: DDS generator with interpolated samples for Spartan3E development
127033: 07/12/09: Re: What's the difference for VHDL code between simulation and synthesis?
127048: 07/12/10: Re: How to simulate these example CORDIC code?
127158: 07/12/12: Re: VHDL code for component labeling
127228: 07/12/14: Re: VHDL language/MyHDL
127272: 07/12/16: Re: What timing constraint value should be set for input/output module?
127405: 07/12/20: Re: sampling error between 2 clocks
127453: 07/12/26: Re: Core Generators...
127467: 07/12/27: Re: Xilinx XST questions
127468: 07/12/27: Re: Video processing courses
127530: 08/01/01: Re: State machine with stack to implement "subroutines"
127651: 08/01/04: Re: question on AND
127684: 08/01/05: =?windows-1252?Q?Re=3A_about_=22tri-states_data_bus=22_?=
127824: 08/01/08: Re: Real examples of metastability causing bugs
127852: 08/01/09: Re: Real examples of metastability causing bugs
127915: 08/01/10: Re: Real examples of metastability causing bugs
127921: 08/01/10: Re: Real examples of metastability causing bugs
127976: 08/01/11: Re: Timing constraints not applied, ISE & SynplifyPro
128006: 08/01/12: Re: Real examples of metastability causing bugs
128074: 08/01/14: Re: ieee_ proposed library
128095: 08/01/15: Re: Real examples of metastability causing bugs
128186: 08/01/17: Re: Basic FPGA question about Reset
128229: 08/01/18: Re: Two's complement Coregen gone?
128438: 08/01/25: Re: Random Number Generation in VHDL
128469: 08/01/27: Re: Synplicy and Xilinx - no PAR
128471: 08/01/27: Re: Active-HDL 7.3 vs Modelsim 6.3d-PE (for Verilog/Systemverilog)
128568: 08/01/30: Re: ROM/LUT
128644: 08/02/01: Re: Active-HDL 7.3 vs Modelsim 6.3d-PE (for Verilog/Systemverilog)
128746: 08/02/05: Re: MG Leonardo Synthesis Options
128747: 08/02/05: Re: New leonardo spectrum version has license errors
128748: 08/02/05: Re: Modelsim Warning
128755: 08/02/05: Re: Modelsim Warning
128757: 08/02/05: Re: simulator options
128860: 08/02/07: Re: Weired Distributed Memory behaviour
128889: 08/02/08: Re: Timing Constraint not met
128890: 08/02/08: Re: Strange "Style guide" requirements...
128919: 08/02/10: Re: Strange "Style guide" requirements...
128920: 08/02/10: Re: Strange "Style guide" requirements...
128923: 08/02/10: Re: loading unisim in modelsim problem while testin xilinx ipcore
128929: 08/02/10: Re: Strange "Style guide" requirements...
128957: 08/02/11: Re: Virtex5 DCM lower limit
129076: 08/02/13: Re: setup time not met in Quartus
129200: 08/02/18: Re: Virtex5 DCM lower limit
129206: 08/02/18: Re: Define the primary clock with XST in VHDL
129211: 08/02/18: Re: TCL testcase in Modelsim.
129214: 08/02/18: Re: TCL testcase in Modelsim.
129230: 08/02/19: Re: Efficient division algorithm?
129240: 08/02/19: Re: Efficient division algorithm?
129242: 08/02/19: Re: Cyclone flash configuration data
129254: 08/02/19: Re: Efficient division algorithm?
129256: 08/02/19: Re: Efficient division algorithm?
129259: 08/02/19: Re: Cyclone flash configuration data
129350: 08/02/21: Re: Using Lattice ispLEVER with VHDL libraries
129363: 08/02/21: Re: How to use xilinx specific features from Modelsim Designer 6.3a
129392: 08/02/22: Re: Using Lattice ispLEVER with VHDL libraries
129404: 08/02/22: Re: How to use xilinx specific features from Modelsim Designer 6.3a
129415: 08/02/22: Re: How to use xilinx specific features from Modelsim Designer 6.3a
129435: 08/02/23: Re: How to use xilinx specific features from Modelsim Designer 6.3a
129472: 08/02/25: Re: Using Lattice ispLEVER with VHDL libraries
129473: 08/02/25: Re: Seed Values
129500: 08/02/26: Re: Synthesis of functions in Quartus
129503: 08/02/26: Re: Seed Values
129627: 08/02/29: Re: real to signed
129659: 08/03/02: Re: Software for FPGA-based PC scope
129666: 08/03/02: Re: Software for FPGA-based PC scope
129839: 08/03/06: Re: how to optimize a design for speed
129895: 08/03/08: Re: Cyclone III and Quartus 7.2sp2
129910: 08/03/09: Re: Cyclone III and Quartus 7.2sp2
129941: 08/03/11: Re: BRAM synthesis question
129944: 08/03/11: Re: vhdl code realization
129954: 08/03/11: Re: BRAM synthesis question
130030: 08/03/13: Re: Design complexity in Logic cells - Virtex-5 FPGA
130042: 08/03/13: Re: SDC of NCF?
130121: 08/03/15: Re: SiliconBlue enters the FPGA fray
130123: 08/03/15: Re: Virtex-5 FX when ? (III)
130163: 08/03/17: Re: ISE 9.2SP4 error
130239: 08/03/18: Re: to view vhdl variable with gtkwave
130247: 08/03/18: Re: vhdl type conversions
130257: 08/03/18: Re: Optimizing an inferred counter
130279: 08/03/19: Re: vhdl type conversions
130303: 08/03/19: Re: dual clock fifo
130370: 08/03/21: Re: Synoplify ???
130381: 08/03/21: Re: Synoplify ???
130386: 08/03/21: Re: Actel SX-A Timing Constraints Issues
130426: 08/03/23: Re: vhdl type conversions
130532: 08/03/26: Re: VHDL document generation utilities
130573: 08/03/27: Re: Synoplify ???
130584: 08/03/27: Re: VHDL document generation utilities
130630: 08/03/28: Re: Having trouble building an old Xilinx Spartan3 FPGA project I
130654: 08/03/29: Re: Newbies: Answer to "What is an FPGA?" in video
130661: 08/03/29: Re: async clk input, clock glitches
130861: 08/04/03: Re: coregenerator bram in synplify pro error
130904: 08/04/04: Re: synplify pro generates negative slack
130930: 08/04/05: Re: synplify pro generates negative slack
131097: 08/04/10: Re: clock instanciation
131175: 08/04/14: Re: Which to learn: Verilog vs. VHDL?
131182: 08/04/14: Re: case statements- verilog to vhdl
131188: 08/04/14: Re: case statements- verilog to vhdl
131220: 08/04/15: Re: Snythesis error
131222: 08/04/15: Re: asic gate count
131239: 08/04/16: Re: Snythesis error
131246: 08/04/16: Re: how do I test signals in a testbench that are 1 or 2 levels down
131268: 08/04/17: Re: Survey: FPGA PCB layout
131270: 08/04/17: Re: XST design frequency setting
131314: 08/04/18: Re: Has anyone dealt with Avnet? or NuHorizons when trying to purchase
131333: 08/04/19: Re: Synthesis Comparison
131350: 08/04/20: Re: synchronous reset problems on FPGA
131359: 08/04/20: Re: Problem writing quadrature decoder
131372: 08/04/20: Re: synchronous reset problems on FPGA
131374: 08/04/20: Re: Problem writing quadrature decoder
131423: 08/04/21: Re: ANNOUNCE: Maia 0.8.2: module-level HDL verification tool
131473: 08/04/22: Re: not inferred RAM, on QII
131487: 08/04/22: Re: FPGA Verilog state machine lock up
131594: 08/04/25: Re: Very simple VHDL problem
131614: 08/04/26: Re: ANNOUNCE: Maia 0.8.2: module-level HDL verification tool
131704: 08/04/29: Re: Style for Highly-Pipelined State Machines
131745: 08/04/30: Re: co-sim for handel C with modelsim vs pure modelsim VHDL simulation
131753: 08/04/30: Re: asic gate count
131760: 08/05/01: Re: Functional Simulation of Virtex-4 Block Memory
131785: 08/05/01: Re: Functional Simulation of Virtex-4 Block Memory
131796: 08/05/02: Re: Quartus v7.x fitting bug
131802: 08/05/02: Re: quick question
131803: 08/05/02: Re: Quartus v7.x fitting bug
131811: 08/05/02: Re: quick question
131820: 08/05/02: Re: quick question
131829: 08/05/02: Re: Style for Highly-Pipelined State Machines
131836: 08/05/03: Re: Aldec Active-HDL 7.3 sp1 [stimulators]
131837: 08/05/03: Re: Forking in One-Hot FSMs
131839: 08/05/03: Re: Using SRL16
131900: 08/05/06: Re: Getting started with VHDL and Verilog
131904: 08/05/06: Re: Call VHDL module from Verilog
132249: 08/05/19: Re: I cannot find how to map a "record type" in my ucf file.
132284: 08/05/20: Re: Stratix IV Announced
132291: 08/05/20: Re: bizarre state machine behavior
132319: 08/05/21: Re: Every newbie's favorite project: the Quadrature Rotary Encoder
132443: 08/05/27: Re: Video stream over bluetooth
132451: 08/05/27: Re: Downloading external data file to FPGA
132457: 08/05/27: Re: Mathstar plans to discontinue FPOA development
132470: 08/05/28: Re: Sequentially syncrhronous
132481: 08/05/28: Re: HDL - simulation vs synthesis
132527: 08/05/29: Re: Problem writing quadrature decoder
132567: 08/05/31: Re: cutoff frequency
132580: 08/06/01: Re: Combinatorial logic delay plus routing delay exceeds clock period
132581: 08/06/01: Re: Combinatorial logic delay plus routing -- typo
132798: 08/06/06: Re: FPGA clock frequency
132799: 08/06/06: Re: Compare and update in same clock cycle synthesis problem
132824: 08/06/07: Re: HDL tricks for better timing closure in FPGAs
132835: 08/06/08: Re: Aldec Active-HDL and Xilinx/Altera FPGA-vendor library support
132876: 08/06/09: Re: how to track down an optimised away signal
132879: 08/06/09: Re: how to track down an optimised away signal
132902: 08/06/10: Re: Aldec Active-HDL and Xilinx/Altera FPGA-vendor library support
132924: 08/06/10: Re: Cheating the FPGA clock speed
132927: 08/06/10: Re: how to track down an optimised away signal
132997: 08/06/12: Re: Altera Quartus Web Edition 8.0 available
133052: 08/06/16: Re: FPGA to solve the two most annoying problems on usenet - Suggestions
133053: 08/06/16: Re: WARP
133125: 08/06/18: Re: Synthesis results when testing for 'X' and 'U'
133142: 08/06/18: Re: which commercial HDL-Simulator for FPGA?
133169: 08/06/19: Re: Synthesis results when testing for 'X' and 'U'
133206: 08/06/20: Re: which commercial HDL-Simulator for FPGA?
133217: 08/06/20: Re: which commercial HDL-Simulator for FPGA?
133218: 08/06/20: Re: which commercial HDL-Simulator for FPGA?
133243: 08/06/22: Re: which commercial HDL-Simulator for FPGA?
133279: 08/06/23: Re: FPGA based database searching
133328: 08/06/24: Re: Configuration Management Best Practices
133349: 08/06/25: Re: FPGA based database searching
133353: 08/06/25: Re: FPGA based database searching
133492: 08/07/01: Re: VHDL libraries
133515: 08/07/01: Re: VHDL code for RCOM message
133583: 08/07/04: Re: FiFo Help Needed
133614: 08/07/06: Re: Help to SImulate Uart TX
133620: 08/07/06: Re: Help to SImulate Uart TX
133638: 08/07/07: Re: Help to SImulate Uart TX
133713: 08/07/10: Re: oversampling serializer?
133719: 08/07/11: Re: oversampling serializer?
133830: 08/07/16: Re: Xilinx/Altera gate equivalence
133834: 08/07/16: Re: Xilinx/Altera gate equivalence
133923: 08/07/19: Re: Howto disable Quartus infering M4Ks??
133929: 08/07/19: Re: Howto disable Quartus infering M4Ks??
134027: 08/07/22: Re: Help to SImulate Uart TX
134055: 08/07/23: Re: Quartus2 pin assignment
134057: 08/07/23: Re: Quartus2 pin assignment
134085: 08/07/24: Re: Quartus2 pin assignment
134113: 08/07/26: Re: Creating new operators
134130: 08/07/26: Re: Creating new operators
134170: 08/07/28: Re: Creating new operators
134198: 08/07/30: Re: Creating new operators
134225: 08/07/31: Re: Question on ModelSim wave viewer
134232: 08/07/31: Re: Using VHDL packages
134275: 08/08/04: Re: Schematic Capture tutorials/books?
134287: 08/08/04: Re: Is HDL-Designer not supporting records correctly?
134290: 08/08/04: Re: Chipscope - Clock Error
134293: 08/08/04: Re: Chipscope - Clock Error
134299: 08/08/05: Re: Altera sues Zilog - signs of desperation from Programmable Vendor
134300: 08/08/05: Re: vhdl or verilog code for 64 point ifft
134321: 08/08/06: Re: Downsizing Verilog synthesization.
134333: 08/08/06: Re: Downsizing Verilog synthesization.
134355: 08/08/07: Re: RTL Schematic as EDIF
134386: 08/08/08: Re: RTL Schematic as EDIF
134448: 08/08/11: Re: Altera question - MAX3000 vs MAX7000
134455: 08/08/11: Re: spartan sa dcm maximal frequency
134507: 08/08/14: Re: Real port types in VHDL
134652: 08/08/24: Re: Sample vhdl to write and read a value from a Spartan 3 block
134673: 08/08/25: Re: Sample vhdl to write and read a value from a Spartan 3 block
134687: 08/08/26: Re: AES decryption (ASIC)
134826: 08/09/02: Re: Is it possible to do incremental synthesis and placement?
134852: 08/09/03: Re: Strange Spartan2 behaviour
134874: 08/09/04: Re: XST bug on illegal states of a FSM ?
134875: 08/09/04: Re: EDK frequency problem
134879: 08/09/04: Re: Inferring dual-port RAM in Spartan-3A Starter Kit FPGA?
134884: 08/09/04: Re: Inferring dual-port RAM in Spartan-3A Starter Kit FPGA?
135412: 08/10/01: Re: Post-synthesis simulation
135426: 08/10/01: Re: Xilinx device not listed
135456: 08/10/02: Re: reasonable timing analysis without mapping design to IO
135460: 08/10/02: Re: Two questions about Xilinx constraints setting
135526: 08/10/06: Re: Barrel Shifter: Newbie's Attempt
135550: 08/10/07: Re: Newbie question
135638: 08/10/10: Re: VHDL Training Course
135683: 08/10/12: Re: Good reference for Static Timing Analysis
135785: 08/10/15: Re: Simulation
135886: 08/10/20: Re: Entry Level FPGA Jobs and Outsourcing
135887: 08/10/20: Re: Field update
135888: 08/10/20: Re: Cyclone III, DP RAM, and Verilog
135896: 08/10/20: Re: Entry Level FPGA Jobs and Outsourcing
135937: 08/10/22: Re: Virtex 5 DSP.
135969: 08/10/24: Re: again: statemachine bug in Quartus II Web Edition Software v8.0
135973: 08/10/24: Re: again: statemachine bug in Quartus II Web Edition Software v8.0
136064: 08/10/29: Re: Register File distributed all over the FPGA
136102: 08/10/31: Re: ISE 9.2.03i problem
136109: 08/11/01: Re: FPGA implementation of a PCI module
136174: 08/11/04: Re: RS-232 Bus controller design in VHDL
136239: 08/11/07: Re: Setting FSM encoding in VHDL or in UCF for Xilinx
136280: 08/11/09: Re: RS-232 Bus controller design in VHDL
136303: 08/11/10: Re: RS-232 Bus controller design in VHDL
136307: 08/11/10: Re: RS-232 Bus controller design in VHDL
136359: 08/11/12: Re: Bluespec
136375: 08/11/13: Re: Virtex5 XC5VFX70T
136376: 08/11/13: Re: Would like to try ISIM, simple question
136377: 08/11/13: Re: How to constrain time-multiplexed pathes
136386: 08/11/13: Re: How to constrain time-multiplexed pathes
136388: 08/11/13: Re: How to stop using a signed subtractor
136422: 08/11/15: Re: What happened to the Cyclone IV?
136459: 08/11/17: Re: Aligned PLL clocks in RTL simulation
136505: 08/11/19: Re: opinion about various code generators
136506: 08/11/19: Re: Spartan3 SRL16 + SliceFF, LUT stability
136542: 08/11/21: Re: Student FPGAs
136602: 08/11/24: Re: opinion about various code generators
136609: 08/11/25: Re: distributed dual port RAM with asynchronous read in ACTEL Smartgen
136628: 08/11/26: Re: Infer Dual Port Block ROM for Xilinx FPGA
136631: 08/11/26: Re: Problem with post-route simulation / timing simulation
136665: 08/11/29: Re: How to write driver for xilinx spartan iie xc2s50e
136675: 08/11/30: Re: How to evaluate program efficiency/functionality
136710: 08/12/02: Re: problem about V5 PCI Express endpoint
136711: 08/12/02: Re: how to read images from a microSD card ?
136765: 08/12/04: Re: Xilinx-ISE nets names after placement & routing
136778: 08/12/04: Re: Xilinx-ISE nets names after placement & routing
136801: 08/12/05: Re: SystemVerilog OOP and OVM Summary
136820: 08/12/07: Re: ISE doesn't work after a crash
136823: 08/12/07: Re: ISE doesn't work after a crash
136837: 08/12/08: Re: ISE doesn't work after a crash
136861: 08/12/09: Re: FPGA-ASIC Migration
136873: 08/12/10: Re: Sampling a clock
136912: 08/12/12: Re: How to insert ChipScope
137028: 08/12/19: Re: Looking for a strategy to identify nets in post-map netlist
137039: 08/12/20: Re: PLL and clock in altera cyclone 2 fpga
137066: 08/12/21: Re: Why MyHDL?
137070: 08/12/21: Re: Why MyHDL?
137131: 08/12/24: Re: Generation of WR and RD signal for ASYNC FIFO
137132: 08/12/24: Re: PCI newbie problems
137166: 08/12/29: Re: FPGA > ASIC
137169: 08/12/29: Re: Synthesis Problem
137170: 08/12/29: Re: Is Implementation in ISE10.1.03 really better than in ISE9.2.03
137224: 09/01/04: Re: MAX7000 power and slew rate control
137225: 09/01/04: Re: DE2 Board DDR Controller Problem
137297: 09/01/07: Re: problems with symbols and how to debug Quartus block diagrams
137298: 09/01/07: Re: problems with symbols and how to debug Quartus block diagrams
137330: 09/01/08: Re: fpga mac controller with tcp/ip/dhcp
137351: 09/01/10: Re: what is the difference between two process model & one process
137362: 09/01/11: Re: error during ise simulation
137447: 09/01/16: Re: Counter: natural VS std_logic_vector
137459: 09/01/18: Re: Counter: natural VS std_logic_vector
137462: 09/01/18: Re: Using memory blocks generated by CoreGen
137473: 09/01/19: Re: Time to de-assert RAM for changing CLK
137478: 09/01/19: Re: Differential bidirectional in VHDL (Xilinx)
137625: 09/01/24: Re: problem with test bench should be an easy one.
137680: 09/01/27: Re: Got UART Working!!! need syntax help with using ascii/buffer
137695: 09/01/27: Re: XST Makes Odd Choice
137703: 09/01/27: Re: XST Makes Odd Choice
137712: 09/01/28: Re: Got UART Working!!! need syntax help with using ascii/buffer
137796: 09/01/29: Re: XST Makes Odd Choice
137848: 09/01/31: Re: LUT design / Transmission gates or pass transistors?
137871: 09/02/01: Re: Heavily pipelined design
137872: 09/02/01: Re: Selecting a starter FPGA board
137885: 09/02/01: Re: Heavily pipelined design
137971: 09/02/03: Re: rs232 uart: testbench vs real world, and the missing first letter.
138109: 09/02/06: Re: Precedence of signal assignment in a clocked process
138173: 09/02/08: Re: Is this phase accumulator trick well-known???
138204: 09/02/09: Re: Is this phase accumulator trick well-known???
138604: 09/03/01: Re: Configure FPGA via PCIe
138658: 09/03/03: Re: Re-synthesizing with minor changes
138703: 09/03/05: Re: writing current date to a register
138710: 09/03/05: Re: writing current date to a register
138712: 09/03/05: make ise take ngc as source
138734: 09/03/06: Re: make ise take ngc as source
138735: 09/03/06: Re: make ise take ngc as source
138736: 09/03/06: Re: make ise take ngc as source
138737: 09/03/06: Re: New person to CPLD programming
138764: 09/03/09: Re: Timing requirements for generating off-chip clock with DDR register
138785: 09/03/10: Re: Checking HDL syntax on command line with xilinx tools
139097: 09/03/20: Re: How big is my vhdl and am I approaching some size limitation
139102: 09/03/20: Re: How big is my vhdl and am I approaching some size limitation
139272: 09/03/24: Re: Flow Control
139407: 09/03/28: Re: VHDL : how to make a bunch of arbitary signals into a vector?
139481: 09/03/31: Re: XST removes duplicate logic no matter what
139516: 09/04/01: Re: Xilinx partitions vs. smartguide
139569: 09/04/03: Re: Lattice EPIC Logic Block Editor for Slice in CCU2 mode
139702: 09/04/09: Re: Two stage synchroniser,how does it work?
139754: 09/04/11: Re: warning:impact:2217 error shows in the status register, CRC Error
139764: 09/04/12: Re: Irregular LDPC
139833: 09/04/15: Re: Synchronous clocking between Cyclone III and SDRAM
139992: 09/04/22: Re: MIG DDR2 controller functional model available
139994: 09/04/22: Re: MIG DDR2 controller functional model available
140132: 09/04/29: Re: Quartus Timing
140152: 09/04/30: Re: Quartus Timing
140172: 09/05/01: Re: Quartus Timing
140281: 09/05/07: Re: Setting top level VHDL generics in XST
140293: 09/05/07: Re: OpenCores CAN/Ethernet cores
140313: 09/05/08: Re: Dual Port RAM Inference
140323: 09/05/08: Re: Dual Port RAM Inference
140332: 09/05/09: Re: Dual Port RAM Inference
140483: 09/05/14: Re: EMACS VHDL mode: how to rescan project so that makefile generates
140518: 09/05/15: Re: Survey: What's a good FPGA-related conference?
140596: 09/05/19: Re: Sigasi Public Beta: future of VHDL design
140619: 09/05/20: Re: Sigasi Public Beta: future of VHDL design
140620: 09/05/20: Re: Muli-Cycle Path Constrains in RTL
140683: 09/05/21: Re: Online tool that generates parallel CRC and Scrambler
140685: 09/05/21: Re: Muli-Cycle Path Constrains in RTL
140687: 09/05/21: Re: Can we expect ISE Gui and makefile to produce identical bit
140743: 09/05/23: Re: Muli-Cycle Path Constrains in RTL
140807: 09/05/26: Re: When is it to generate transparent latch or usual combinational
140814: 09/05/26: Re: Online tool that generates parallel CRC and Scrambler
140820: 09/05/26: Re: EMACS VHDL mode: how to rescan project so that makefile generates
140850: 09/05/27: Re: how i can to send a sequence of bytes to the FPGA ?
140918: 09/05/29: Re: I don't like xilinx (again)
140924: 09/05/29: Re: Are Virtex-5 FPGA Handbook or Altera latest Handbooks available
141010: 09/06/02: Re: phase locking a slow (2Mhz) signal.
141038: 09/06/02: Re: BRAM/LUT Comparison
141049: 09/06/03: Re: Secure netlist
141078: 09/06/04: Re: Help with Remote debugging ideas.
141147: 09/06/08: Re: Xilinx Block RAM Sim
141154: 09/06/09: Re: ISE 11.1
141157: 09/06/09: Re: Xilinx Block RAM Sim
141160: 09/06/09: Re: Xilinx Block RAM Sim
141330: 09/06/18: Re: synplify script for constraint
141347: 09/06/19: Re: synplify script for constraint
141354: 09/06/19: Re: Lookup table in VHDL?
141383: 09/06/22: Re: Subtleties of Booth's Algorithm Implementation
141391: 09/06/22: Re: Subtleties of Booth's Algorithm Implementation
141397: 09/06/22: Re: Subtleties of Booth's Algorithm Implementation
141415: 09/06/23: Re: index in arrays doesn't work
141418: 09/06/23: Re: EPM7064 Altera PLD oe1\oe2\gclr1
141440: 09/06/24: Re: Subtleties of Booth's Algorithm Implementation
141449: 09/06/24: Re: True dual-port RAM in VHDL: XST question
141527: 09/06/26: Re: True dual-port RAM in VHDL: XST question
141528: 09/06/26: Re: True dual-port RAM in VHDL: XST question
141563: 09/06/27: Re: Expand unsigned 4*4 module to signed 16*16 module
141573: 09/06/28: Re: True dual-port RAM in VHDL: XST question
141574: 09/06/28: Re: True dual-port RAM in VHDL: XST question -typo
141575: 09/06/28: Re: Expand unsigned 4*4 module to signed 16*16 module
141602: 09/06/29: Re: dual port inference problem
141616: 09/06/30: Re: How to keep documentation of control and status registers and
141688: 09/07/03: Re: Active-HDL simulator recompile... or not recompiling
141689: 09/07/03: Re: default modelsim vsim options for verilog simulation
141933: 09/07/17: Re: Do you prefer paper or plastic... er, I mean paper or e-books?
141947: 09/07/18: Re: Do you prefer paper or plastic... er, I mean paper or e-books?
141971: 09/07/20: Re: How do you handle build variants in VHDL?
142028: 09/07/22: Re: Strange FPGA behavior
142029: 09/07/22: Re: How do you handle build variants in VHDL?
142039: 09/07/22: Re: How do you handle build variants in VHDL?
142055: 09/07/23: Re: How do you handle build variants in VHDL?
142061: 09/07/23: Re: FPGA development tools for FreeBSD?
142100: 09/07/24: Re: Xilinx ISE 11.x lossage
142140: 09/07/26: Re: Xilinx ISE 11.x lossage
142158: 09/07/27: Re: How do you handle build variants in VHDL?
142223: 09/07/29: Re: Implementing VHDL code in an embedded processor design and readout
142231: 09/07/29: Re: Implementing VHDL code in an embedded processor design and
142262: 09/07/30: Re: Xilinx Xcell Journal 68
142294: 09/08/02: Re: Questa price
142499: 09/08/13: Re: why synthesize not work?
142507: 09/08/13: Re: Mixed language simulation on the cheap
142527: 09/08/14: Re: why synthesize not work?
142824: 09/09/02: Re: Choice of Language for FPGA programming
142889: 09/09/05: Re: Choice of Language for FPGA programming
142944: 09/09/09: Re: ANN: Coding style guidance for FPGA memory
142951: 09/09/09: Re: Xilinx TCL and Cygwin
143000: 09/09/14: Re: ANN: Coding style guidance for FPGA memory
143037: 09/09/15: Re: ANN: Coding style guidance for FPGA memory
143109: 09/09/21: Re: timing simulation performance
143111: 09/09/21: Re: timing simulation performance
143125: 09/09/22: Re: view memory contents in modelsim
143127: 09/09/22: Re: Xilinx XST and counter synthesis problem
143169: 09/09/23: Re: Shift left arithmetic?
143183: 09/09/24: Re: Shift left arithmetic?
143210: 09/09/25: Re: Shift left arithmetic?
143256: 09/09/28: Re: Xilinx RTL view question
143303: 09/09/30: Re: Implement ARM cores on a FPGA chip?
143342: 09/10/03: Re: Implement ARM cores on a FPGA chip?
143350: 09/10/04: Re: Implement ARM cores on a FPGA chip?
143574: 09/10/16: Re: ModelSim fails to connect my project components
143588: 09/10/16: Re: What is the basis on flip-flop replaced by a latch
143694: 09/10/21: Re: Xilinx USB programmer - problems with Debian/Linux - Solved
143698: 09/10/21: Re: Done pin won't go high
143825: 09/10/27: Re: synplify question for FPGA
143863: 09/10/30: Re: Simple state machine output question
143866: 09/10/30: Re: Simple state machine output question
143867: 09/10/30: Re: Simple state machine output question
143869: 09/10/30: Re: Simple state machine output question
143925: 09/11/03: Re: ModelSim view internal signals in instantiated verilog modules
144086: 09/11/10: Re: Dealing wiht multiple clock domain...cleanly?
144155: 09/11/14: Re: New blog post on alphas in packagin
144176: 09/11/17: Re: Error:Place:645 on a non-clock pin.
144217: 09/11/20: Re: Error:Place:645 on a non-clock pin.
144286: 09/11/24: Re: Deskew Reginal clock input
144436: 09/12/07: Re: BRAM usage in synplify pro
144501: 09/12/11: Re: Please Help me
144502: 09/12/11: Re: Please Help me
144557: 09/12/14: Re: Please Help me
144851: 10/01/07: Re: Why are my pins being removed? LIT:243 and MapLib:701 warnings
144878: 10/01/11: Re: Old School Hurts
144944: 10/01/16: Re: Altera Quartus II on Debian GNU/Linux
144986: 10/01/18: Re: bit vs std_logic (was Re: Simulation of VHDL code for a vending
145004: 10/01/19: Re: bit vs std_logic (was Re: Simulation of VHDL code for a vending
145007: 10/01/19: Re: bit vs std_logic (was Re: Simulation of VHDL code for a vending
145009: 10/01/19: Re: bit vs std_logic (was Re: Simulation of VHDL code for a vending
145050: 10/01/22: Re: State Machine Initialization in Synplify Pro
145177: 10/01/30: Re: vhdl divider
145184: 10/01/31: Re: Quartus Web Edition on Linux - no simulation?
145212: 10/02/01: Re: Single Port Rom created by Core Generator configurable by generic
145333: 10/02/05: Re: using an FPGA to emulate a vintage computer
145436: 10/02/09: Re: Xilinx ISE 11.1 crash - Visual Studio error
145501: 10/02/12: Re: Synplify out of memory
145704: 10/02/19: Re: System design in FPGA
145726: 10/02/21: Re: Quartus II IDE freezing on Arch 64
145727: 10/02/21: Re: State machines in Quartus
147891: 10/05/30: Re: Estimating resource utilization of cores (from Xilinx CoreGen)
148615: 10/08/06: Re: A question from a VHDL beginner
148668: 10/08/16: Re: VDHL initializing
148689: 10/08/17: Re: Getting started with FPGA
148718: 10/08/18: Re: VDHL initializing
148860: 10/09/04: Re: Want to get into FPGA
149134: 10/10/04: Re: FPGA design not working!
149137: 10/10/04: Re: Starting a career with FPGAs
149154: 10/10/04: Re: Starting a career with FPGAs
149165: 10/10/05: Re: Starting a career with FPGAs
149218: 10/10/08: Re: help with bad synchronous description error
149219: 10/10/08: Re: FPGA design not working!
149608: 10/11/10: Re: XST - configuration - VHDL
149609: 10/11/10: Re: Modelsim Altera - Strange issue.
149733: 10/11/21: Re: Network stack on Xilinx, Alterra ?
149757: 10/11/22: Re: Procedures and Registers
149851: 10/11/28: Re: xilinx bitstream reading library & tool - legal issues?
149933: 10/12/02: Re: xilinx bitstream reading library & tool - legal issues?
149935: 10/12/02: Re: FSM single process...BIG question
149936: 10/12/02: Re: Brain Cramps...
150059: 10/12/08: Re: Concurrent Logic Timing
150199: 10/12/30: Re: Verilog inout, I2C
150208: 10/12/31: Re: Verilog inout, I2C
150209: 10/12/31: Re: I Give Up!
150219: 11/01/02: Re: I Give Up!
150241: 11/01/04: Re: Transfer data from one clock domain to another clock created
150252: 11/01/05: Re: Transfer data from one clock domain to another clock created
150294: 11/01/08: Re: spartan 3 xc3s1000 not getting programmed
150398: 11/01/16: Re: Verilog Book for VHDL Users
150527: 11/01/25: Re: FPGA changes behaviour when the resource's usage percentage changes
150529: 11/01/25: Re: Zero Padding Circuit Design
150751: 11/02/08: Re: Trivia: Where are you on the HDL Map?
150873: 11/02/17: Re: why an FSM is not a counter?!
150941: 11/02/23: Re: timing issues at high speed
151793: 11/05/18: Re: Scoping a glitch
151903: 11/06/02: Re: Connecting of IP core simulated in GHDL to pseudoterminal via
151917: 11/06/03: Re: verilog task and vhdl
151922: 11/06/04: Re: verilog task and vhdl
151926: 11/06/05: Re: verilog task and vhdl
152040: 11/06/24: Re: Sporadic simulation result with modelsim
152657: 11/09/24: Re: Registers at I/O
152660: 11/09/24: Re: Registers at I/O
152663: 11/09/25: Re: Registers at I/O
152666: 11/09/25: Re: Modelsim cannot run its example tcl
Mike Trowers:
23985: 00/07/19: Erasing PLD's
23986: 00/07/19: Re: Erasing PLD's
23991: 00/07/19: Re: Erasing PLD's
Mike Turco:
~Mike Turco:
23586: 00/07/01: Re: Which notebook is for you?
mike turner:
5974: 97/04/01: xess
mike v.:
147287: 10/04/21: Re: I'd rather switch than fight!
Mike Walsh:
7606: 97/09/26: Free Exemplar/Altera Workshops
7886: 97/10/27: Re: Anyone know of an I2C Controller design for an FPGA?
15847: 99/04/16: Top Down FPGA Hands On Workshop
16239: 99/05/11: Free FPGA Design Workshop
16553: 99/05/27: Free Hardware/Software Co-Verification Workshop - Raleigh, NC
Mike Williams:
5506: 97/02/21: Re: State Diagram Tools
5569: 97/02/25: Re: How are states changed in ALTERA
5721: 97/03/10: Re: A viewlogic story
Mike Wirthlin:
65783: 04/02/06: ERSA'04, CFP: Extended Deadline: Feb 16, 2004
69468: 04/05/11: MOCA Design 2005
Mike Yarwood:
93119: 05/12/14: Re: How can I surpress noise in an ADC board?
94991: 06/01/20: Re: Constellation symbol to bit's soft-probability?
Mike Young:
153871: 12/06/15: Re: FPGA FIFO MAX data speed
Mike Zhang:
89430: 05/09/15: PCI configuration questions.
<mike.santarini@gmail.com>:
155694: 13/08/06: Xilinx Xcell Journal 84--Xilinx Goes UltraScale
158031: 15/07/13: Special issue of Xcell Journal
mike0109:
154993: 13/03/22: ASIC prototyping question for Xilinx V7 2000
mike12:
154187: 12/08/31: Delay in Verilog for Asics design which is synthesizable
Mike_K:
74552: 04/10/13: EMAC ping Board
mike_la_jolla:
93785: 05/12/30: Re: Virtex 4 desing : ChipScope insertion impacts my timing problem debug
93948: 06/01/03: Re: What is the best solution for PCIe today ?
97801: 06/02/27: Re: Virtex2: can I really just leave M1,M2,M3 pins floating?
99825: 06/03/29: Re: deglitching a clock
99876: 06/03/30: Re: deglitching a clock
100402: 06/04/07: Re: Virtex-4 RocketIO and G.709 OTU-2
101459: 06/05/01: Re: Async FPGA ~2GHz
103311: 06/05/30: Need help reattaching top to FPGA
104022: 06/06/16: Re: Virtex-4 with Rocket IO capability??
107140: 06/08/24: Re: QuickLogic
114542: 07/01/18: Re: PCI Card with FPGA
115303: 07/02/06: Re: Xilinx Virtex5 board
118852: 07/05/04: Re: FPGA board for video processing
119877: 07/05/28: Re: Rodney Smith, long term Altera CEO, dies in accident
134674: 08/08/25: Re: Virtex 5 evaluation boards
135481: 08/10/03: Re: synopsys designware components on xilinx fpga
143069: 09/09/18: Re: 82S153 Fuse Map / Disassembler
143095: 09/09/19: Re: 82S153 Fuse Map / Disassembler
144435: 09/12/07: Re: ASIC Prototyping
147755: 10/05/21: Re: Any V6's available?
154985: 13/03/17: Re: full tcp offload solution with tcp session setup/teardown support
154987: 13/03/18: Re: full tcp offload solution with tcp session setup/teardown support
155544: 13/07/16: Re: FPGA Exchange
<mike_login@my-deja.com>:
26187: 00/10/07: TMS320C54x interface
mike_treseler:
67935: 04/03/22: Re: Synchronization of data
68161: 04/03/28: Re: Help with Xilinx Ram16X1S example VHDL code
74578: 04/10/14: Re: Where to buy cheap MAXII CPLD?
75489: 04/11/07: Re: Why Xilinx ChipScope (or similar FPGA OCI tool) is a *MUST* Have
75531: 04/11/08: Re: Partial reconfiguration, Special kind of bus macro
75710: 04/11/12: Re: Obsolete processors resurected in FPGAs
75797: 04/11/15: Re: LPM_MODOLUS warning
75942: 04/11/19: Re: Async and sync resets
76011: 04/11/22: Re: Modelsim library problem
76022: 04/11/22: Re: Beginers Question ModelSim Signals
76287: 04/11/29: Re: dual-write port BRAM with XST/Webpack
mike_treseler@comcast.net:
76587: 04/12/06: Re: how to speed up my accumulator ??
Mikeandmax:
11763: 98/09/08: Re: 22V10 programming
12640: 98/10/21: Re: Altera BGA packages
13305: 98/11/25: Re: Which parts are fastest for 3-state enables?
13662: 98/12/17: Re: Fast *Industrial* 22V10?
15717: 99/04/09: Re: Lattice PDS Software
17380: 99/07/23: Re: Low Cost latched I/O
17780: 99/09/02: Re: FPGA/PLD in fine pitch BGA or chip scale package ???
18120: 99/10/01: Re: Lattice ISP-cable
18325: 99/10/14: Re: Reading a Lattice ispLSI 1016
20420: 00/02/09: Re: Lattice isp programming problems
21195: 00/03/10: Re: pal design using GAL22V10 and PROTEL
24357: 00/08/04: Re: Large CPLD
26990: 00/11/07: Re: Crosspoint switch in CPLD/FPGA ??
27392: 00/11/20: Re: Xilinx and Tri state I/O
30122: 01/03/23: Re: Do I need to tie unused CPLD pins to GND?
32972: 01/07/13: Re: Help needed: why am I getting device programming errors on Webpack.
35731: 01/10/15: Re: help request about lattice isp 1032
37845: 01/12/21: Re: You take the low road and I'll ......
39588: 02/02/14: Re: Problem with Lattice Design Expert Starter
40489: 02/03/08: Re: Clamping Diode in the I/O !!!
40490: 02/03/08: Re: Converting old Mach 5 project from DSL to VHDL
41195: 02/03/22: Re: Altera Stratix compared to Xilinx Virtex
41203: 02/03/22: Re: Poor availability problems on Coolrunner
41220: 02/03/22: Re: Poor availability problems on Coolrunner
42987: 02/05/08: Re: OP-AMP in FPGA
44582: 02/06/24: Re: [Newbie] Help with 20L8 PAL
46729: 02/09/06: Re: XCR3384XL availability
46896: 02/09/11: Re: XCR3384XL availability
48299: 02/10/15: Re: VHDL v. Verilog, Xilinx v. Altera.
51417: 03/01/13: Re: Bidirectional Digital Switch in CPLD ?
53047: 03/03/01: Re: FPGA programming question.
55244: 03/05/01: Re: Low power, high temperature CPLD
56996: 03/06/20: Re: PALs, GALs and ABEL
57643: 03/07/03: Re: XPLA3 vs. MAX3000A
59451: 03/08/19: Re: 22V10, ABEL & Current Design Tools?
59476: 03/08/20: Re: 22V10, ABEL & Current Design Tools?
59537: 03/08/21: Re: 22V10, ABEL & Current Design Tools?
60714: 03/09/19: Re: ORCA fpga?
63311: 03/11/19: Re: Small PLD choices
66405: 04/02/18: Re: Using 3.3V compliant FPGA for 5V PCI
66665: 04/02/24: Re: CardBus prototype in FPGA
66813: 04/02/27: Re: Stratix 2 ALUT architecture patented ?
68058: 04/03/25: Re: How many times can I burn an FPGA?
69149: 04/04/28: Re: Altera EP320 to PAL16V8
71793: 04/07/30: Re: Altera Bidi ports, Tristate Buffers & Prop. Delay?
72486: 04/08/20: Re: GAL,PAL,PLD, CPLD,FPGA
72801: 04/09/02: Re: the global output enable pins of lattice ispxpld 5000mv
75223: 04/10/29: Re: explicitly define latch to avoid WARNING in xilinx webpack?
75603: 04/11/11: Re: Advice on Contemporary Low cost, Medium Density CPLDs
76484: 04/12/03: Re: making an fpga hot
76638: 04/12/08: Re: Xilinx's website
78076: 05/01/24: Re: Copying/Reverse Engineering PAL
78237: 05/01/27: Re: lowest-cost FPGA and CPLD
<mikeandmax@aol.com>:
104565: 06/06/29: Re: Stopping the clock for power management
115209: 07/02/02: Re: XST broken for XC9536?
115210: 07/02/02: Re: ProAsic-plus PLL
116955: 07/03/21: Re: Why is Xilinx's WebPACK so inferior?
121263: 07/06/29: Re: d-link router?
121757: 07/07/12: Re: Designing the right clock tree for a multi-FPGA setup
127094: 07/12/11: Re: GAL16V8
<mikechin2000@gmail.com>:
112394: 06/11/21: Re: master support for OPB device
129967: 08/03/11: avnet virtex-5 lx eval kit ddr problem
129996: 08/03/12: Re: avnet virtex-5 lx eval kit ddr problem
MikeD:
79827: 05/02/24: pld macrocell usage
79829: 05/02/24: Re: Altera available from Digikey
107457: 06/08/28: Actel Fusion?
108794: 06/09/16: independent reviews of EDA tools?
109499: 06/09/27: Max Plus II and Synthesis issues
111326: 06/11/01: Rad-hard (neutron/SEU and space) tutorial?
137999: 09/02/03: Re: Why the second flip-flop in Virtex-6?
MikeD':
89740: 05/09/23: I need an Altera Excalib EPXA10 DDR Dev Board...anybody got one?
89804: 05/09/26: Any suggestions for prototyping in an ARM environment?
90474: 05/10/13: Re: Any suggestions for prototyping in an ARM environment?
MikeF:
117188: 07/03/26: Small memories in Cyclone
<mikegurche@yahoo.com>:
105371: 06/07/20: Re: Hardware book like "Code Complete"?
105697: 06/07/28: Re: Hardware book like "Code Complete"?
107111: 06/08/24: Re: Style of coding complex logic (particularly state machines)
107127: 06/08/24: Re: Style of coding complex logic (particularly state machines)
107186: 06/08/25: Re: Style of coding complex logic (particularly state machines)
107265: 06/08/25: Re: Style of coding complex logic (particularly state machines)
107498: 06/08/29: Re: Style of coding complex logic (particularly state machines)
107512: 06/08/29: Re: Style of coding complex logic (particularly state machines)
107513: 06/08/29: Re: Style of coding complex logic (particularly state machines)
107582: 06/08/30: Re: Style of coding complex logic (particularly state machines)
107583: 06/08/30: Re: Style of coding complex logic (particularly state machines)
108671: 06/09/14: Re: Digilent 3S200 pcb + webpack ISE 8.2 + service pack
mikegw:
62597: 03/11/03: Building the 'uber processor'
62612: 03/11/03: Re: Building the 'uber processor'
62615: 03/11/03: Re: Vendor supplied symbol/part models?
62650: 03/11/04: Re: Building the 'uber processor'
62696: 03/11/05: Re: FPGA Prototyping Board
62740: 03/11/06: Re: Building the 'uber processor'
65209: 04/01/22: Re: References to good PCI boards and some newbie questions - please help!
69943: 04/05/25: www.opencores.org ???
<mikeh@winnet-corp.com>:
9122: 98/02/22: Re: PROBS W/ ALTERA MAX+PLUS II 8.2 S/W
<mikeharwood@yahoo.com>:
18310: 99/10/14: Re: Altera's MaxplusII: incremental compilation
MikeJ:
22141: 00/04/26: Help! going from ACTmap to Synplicity
43749: 02/06/01: Re: Virtex2 placement problem
43751: 02/06/01: Re: Engineering Samples for free?
43752: 02/06/01: Re: stability/timing problem on reset
43753: 02/06/01: Re: Why there is no clear signal in BRAM?
45577: 02/07/27: Re: ALU in VHDL and a bunch of questions
45622: 02/07/29: Re: ALU in VHDL and a bunch of questions
45623: 02/07/29: Re: logic elements v/s logic cells
46346: 02/08/27: Re: Logic Analyzers with an Altera Board
47033: 02/09/15: Re: Synthesis of 4:1 and 8:1 MUX devices in Virtex
47608: 02/09/30: Re: ... milk for free, Opencores?
47836: 02/10/04: Pacman in an FPGA
48026: 02/10/10: fpgaarcade update
48027: 02/10/10: Re: Why can Xilinx sw be as good as Altera's sw?
48072: 02/10/10: Re: fpgaarcade update
48088: 02/10/11: Re: fpgaarcade update
48462: 02/10/18: Re: ps/2 keyboard FSM code simplification....
48463: 02/10/18: Re: Hobbyist FPGA
48611: 02/10/22: Re: 6502 core available
48759: 02/10/24: Re: Xilinx POS Power On Surge Current
48801: 02/10/24: Re: Xilinx POS Power On Surge Current
48803: 02/10/24: Re: Pin locking Virtex 2 FPGA
48819: 02/10/25: Re: Xilinx POS Power On Surge Current
48821: 02/10/25: Re: Pin locking Virtex 2 FPGA
52077: 03/01/30: Re: Installing 2 versions of Xilinx software in the same machine
52711: 03/02/20: New Pacman in an FPGA released
54446: 03/04/11: vic-20 release on fpgaarcade
54599: 03/04/14: Re: Xilinx has released SpartanIII
55783: 03/05/19: Re: SID chip describtion
55826: 03/05/20: Re: SID chip describtion
57162: 03/06/24: Re: FPGA GPU (Spartan IIe 300K)
57164: 03/06/24: Re: FPGA GPU (Spartan IIe 300K)
65692: 04/02/05: Re: binary file to bram tool
70659: 04/06/23: Asteroids Deluxe in an FPGA
77941: 05/01/20: Re: Asic prototyping in Fpga - prototyping the gates.
78004: 05/01/22: Re: Copying/Reverse Engineering PAL
81937: 05/04/04: Re: Reverse engineering ASIC into FPGA
81938: 05/04/04: Re: Reverse engineering ASIC into FPGA
82441: 05/04/12: Re: 2 bit multiplier
83388: 05/04/28: Re: *RANT* Ridiculous EDA software "user license agreements"?
88555: 05/08/22: Re: Generic Memory-Mapped VHDL Module
93702: 05/12/28: Re: RTL for Z8000 series CPU?
96292: 06/02/01: Re: BPSK modulation on Xilinx FPGA
97113: 06/02/16: Re: Xilinx 1.5v HSTL-I for QDR-II. Anybody successful with it?
99382: 06/03/23: Re: help on RISC controller developed mikej
99402: 06/03/23: Pacman update
99403: 06/03/23: Re: this JTAG thing is a joke
99410: 06/03/24: Re: this JTAG thing is a joke
99490: 06/03/25: Re: this JTAG thing is a joke
103689: 06/06/08: Space invaders on Spartan3e starter board
103701: 06/06/08: Re: stable, tested 6502 core
103790: 06/06/11: Re: stable, tested 6502 core
104127: 06/06/19: Re: Aurora core example simulation
104128: 06/06/19: Re: Virtex-4FX embeded MAC and Rocket-IO data corruption??
104133: 06/06/19: Re: Virtex-4FX embeded MAC and Rocket-IO data corruption??
104134: 06/06/19: Re: Virtex-4FX embeded MAC and Rocket-IO data corruption??
104354: 06/06/25: Re: Xilinx RocketIO receiver reset problem
104467: 06/06/28: Spartan3e starter kit vga mod
104706: 06/07/04: Re: Spartan3e starter kit vga mod
106005: 06/08/04: Re: How to implement large ROM's from binary sources?
106015: 06/08/05: Re: How to implement large ROM's from binary sources?
106254: 06/08/09: xst synthesis with attributes failure
106290: 06/08/10: Re: xst synthesis with attributes failure
106291: 06/08/10: Re: Unpicking Logical Synthesis
106293: 06/08/10: Re: xst synthesis with attributes failure
106867: 06/08/21: Re: Modelsim SE Simulation
107125: 06/08/24: Re: RocketIO over cable
114289: 07/01/10: Re: inserting text into a video stream (from a pre-existing video source)
115555: 07/02/13: audio low pass filtering in FPGA
115562: 07/02/13: Re: audio low pass filtering in FPGA
115639: 07/02/15: Re: audio low pass filtering in FPGA
115918: 07/02/26: Re: Making a 32KB BRAM block, virtex-4
119687: 07/05/24: Re: 6502 and CPU licences in general
119798: 07/05/26: Re: 6502 and CPU licences in general
119835: 07/05/27: Re: VGA signal through breadboard?
120340: 07/06/05: Virtex4 CLKX2 DCM Jitter
120357: 07/06/05: Re: Virtex4 CLKX2 DCM Jitter
120377: 07/06/06: Re: Virtex4 CLKX2 DCM Jitter
120380: 07/06/06: Re: Virtex4 CLKX2 DCM Jitter
120381: 07/06/06: Re: Virtex4 CLKX2 DCM Jitter
120464: 07/06/07: Re: Virtex4 CLKX2 DCM Jitter
120465: 07/06/07: Re: Install two version of EDK/ISE (8.1, 8.2) in my windows xp?
120567: 07/06/10: Re: XST net splitting blocks placement
120595: 07/06/11: Re: DVI-D Tx directly from FPGA?
120596: 07/06/11: Re: XST net splitting blocks placement
120597: 07/06/11: Re: Virtex4 CLKX2 DCM Jitter
120658: 07/06/13: Re: DVI-D Tx directly from FPGA?
120666: 07/06/13: Frogger and Scramble released
120669: 07/06/13: Re: DVI-D Tx directly from FPGA?
120683: 07/06/13: Re: Frogger and Scramble released
123075: 07/08/15: Virtex 4 IBUFG to DCM routing question
123093: 07/08/16: Re: Virtex 4 IBUFG to DCM routing question
123117: 07/08/16: Re: Virtex 4 IBUFG to DCM routing question
123118: 07/08/16: Re: Virtex 4 IBUFG to DCM routing question
123130: 07/08/16: Re: Virtex 4 IBUFG to DCM routing question
124250: 07/09/16: Re: sounds
mikej:
138154: 09/02/08: Re: Experiencing problems when moving an FPGA-based implementation to
mikel:
100483: 06/04/10: ROM resource sharing
100504: 06/04/10: Re: ROM resource sharing
136127: 08/11/03: Altera simulation models performance
136201: 08/11/05: Re: Altera simulation models performance
Mikel Azkarate-askasua:
137563: 09/01/22: Readback CRC, CFGLUT5 and Scrubbing
138327: 09/02/16: Frame ECC and Virtex-4
mikelinyoho:
88512: 05/08/21: Why some firmware is made by lattice's FPGA instead of C language?
88546: 05/08/22: How can I see the waveform of my verilog codes?
98280: 06/03/08: Does xilinx ise 8.1 support linux red hat 4.0??????(with device Spartan-3 400k)
98390: 06/03/09: since xilinx ise 8.1 support linux red hat 4.0 (with device Spartan-3 400k)
<mikelinyoho@gmail.com>:
88509: 05/08/20: What is the diffrences between lattice's FPGA and Xilinx's FPGA
<mikeotp999@yahoo.com.tw>:
118284: 07/04/21: =?big5?q?Re:_CPLD_+_=A3gC_with_reasonably-priced_tools=3F?=
<mikeotp@gmail.com>:
99526: 06/03/25: chip reverse engineering
<mikep@oakmicros.com>:
138341: 09/02/16: Re: Logic Analyzer
&miker:
8937: 98/02/07: Free FPGA tools???
8951: 98/02/08: Re: Free FPGA tools???
<MikeShepherd564@btinternet.com>:
99560: 06/03/27: Altera web site inaccessible
99592: 06/03/27: Re: Altera IP address?
99597: 06/03/27: Re: Altera web site inaccessible
100292: 06/04/06: Bizarre behaviour by Quartus?
100298: 06/04/06: Re: Bizarre behaviour by Quartus?
100329: 06/04/06: Re: Bizarre behaviour by Quartus?
101730: 06/05/05: Re: detailed description on the archetecture of FPGA's/CPLD's
101850: 06/05/08: Re: Can an FPGA be operated reliably in a car wheel?
102012: 06/05/09: Re: help me to about clock in fpga
102204: 06/05/12: Re: reverse engineering ?
102227: 06/05/12: Re: JTAG tutorial
102285: 06/05/14: Re: filter design
102286: 06/05/14: Re: reverse engineering ?
102382: 06/05/15: Re: reverse engineering ?
102440: 06/05/16: Re: sending multiple char on RS232
102504: 06/05/17: Re: hy I need a code example for spartan 3 series in Xilinx regarding the implementation of a PID alghoritm
102505: 06/05/17: Re: getting good deals on small qty?
102541: 06/05/17: Re: "disappointing" 550Mhz performance of V5 DSP slices
102784: 06/05/20: Re: Why do the electronics manufacturers have to spam me?
102799: 06/05/21: Re: CPLD (CoolRunner failures)
102915: 06/05/23: Re: xilinx pricing discrepancy
103057: 06/05/25: Re: problem programming Altera Cyclone device
103071: 06/05/25: Re: ISE sends sensitive information to Xilinx site!
103090: 06/05/25: Re: ISE sends sensitive information to Xilinx site!
123412: 07/08/27: Re: ANNC: FPGA Noise Fundamentals Webcast
124689: 07/09/30: Re: Walking 1's
125109: 07/10/16: Re: FPGA quiz: what can be wrong
125333: 07/10/22: Re: Alter RBF Compression
125336: 07/10/22: Re: Alter RBF Compression
125364: 07/10/24: Re: Changing refresh rate for DRAM while in operation?
125377: 07/10/24: Re: Addresses of subsystems
125482: 07/10/26: Re: Power supply filter capacitors
125510: 07/10/26: Re: Power supply filter capacitors
125524: 07/10/27: Re: Power supply filter capacitors
125525: 07/10/27: Re: Bitfile checking
125550: 07/10/28: Re: Power supply filter capacitors
125560: 07/10/29: Re: FPGA Configuration
125576: 07/10/29: Re: FPGA Configuration
125769: 07/11/04: Re: Static PLL
125787: 07/11/05: Re: Audio Output from Spartan 3 Starter Kit
125806: 07/11/06: Re: Audio Output from Spartan 3 Starter Kit
125934: 07/11/09: Re: not totally repulsive
125944: 07/11/09: Re: ROM (altsyncram) corruption
126041: 07/11/13: Re: bidirectional in fpga
126077: 07/11/14: Re: FPGA for hobby use
126114: 07/11/14: Re: FPGA for hobby use
126247: 07/11/18: Re: Quartus II warning: "pass-through logic has been added"
126256: 07/11/18: Re: Low cost FPGA w/serdes
126411: 07/11/21: Re: Measuring setup and hold time in Lab
126505: 07/11/25: Re: VHDL language is out of date! Why? I will explain.
126575: 07/11/28: Re: What tools do you use ? Why ?
126636: 07/11/28: Re: Quartus memory init file
126684: 07/11/29: Re: lossless compression in hardware: what to do in case of uncompressibility?
126725: 07/11/30: Re: Hand solder that FPGA on your prototype
126812: 07/12/03: Re: Interfacing Cyclone III to 3.3v LVDS devices
126894: 07/12/05: Mixed language design
126906: 07/12/05: Re: Mixed language design
126907: 07/12/05: Re: Low cost FPGA w/serdes
126923: 07/12/06: Re: Mixed language design
127234: 07/12/15: Re: VHDL language/MyHDL
127238: 07/12/15: Re: Using LVDS_25 with 3.3V Vcco.
127242: 07/12/15: Re: Using LVDS_25 with 3.3V Vcco.
127439: 07/12/25: Re: FPGA Project Support
127475: 07/12/27: Re: TechXclusives from Xilinx
127506: 07/12/30: How to inhibit a timing warning
127509: 07/12/30: Re: How to inhibit a timing warning
127516: 07/12/31: Re: State machine with stack to implement "subroutines"
127628: 08/01/04: Re: Differential output drive-strength in spartan-3
127653: 08/01/04: Re: converting floating point number to integer and vice versa
127682: 08/01/05: Re: Ethernet on recent FPGAs
127694: 08/01/05: Re: Ethernet on recent FPGAs
127702: 08/01/06: Re: Ethernet on recent FPGAs
127707: 08/01/06: Re: Ethernet on recent FPGAs
127709: 08/01/06: Re: How to connect a LED with a clock?
127723: 08/01/06: Re: How to connect a LED with a clock?
127724: 08/01/06: Re: How to connect a LED with a clock?
127791: 08/01/08: Re: passive serial quaestion
127811: 08/01/08: Re: Real examples of metastability causing bugs
127812: 08/01/08: Re: Bad micro blaze behaviour during power off
127926: 08/01/10: Re: Purchasing IC components at a good price
127956: 08/01/11: Re: VirtexE LVDS driver
128076: 08/01/15: Re: fpga pin to pin conecting
128210: 08/01/18: Re: How is FIFO implemented in FPGA and ASIC?
128224: 08/01/18: Re: How is FIFO implemented in FPGA and ASIC?
128241: 08/01/18: Re: Source of accurate frequency
128485: 08/01/28: Re: effect of xray on fpga electronic circuits
128606: 08/01/31: Re: new to NIOS II
128818: 08/02/07: Re: beleive
128904: 08/02/09: Re: My first verilog/cpld project
129010: 08/02/13: Re: Newbie looking for guidance
129143: 08/02/15: Re: Virtex 4 package layout
129144: 08/02/15: Re: microblaze firmware + UART handshaking blues
129148: 08/02/15: Re: Virtex 4 package layout
129225: 08/02/19: Re: FPGA Programming solution
129229: 08/02/19: Re: FPGA Programming solution
129237: 08/02/19: Re: FPGA Programming solution
129243: 08/02/19: Re: FPGA Programming solution
129245: 08/02/19: Re: Cyclone flash configuration data
129274: 08/02/19: Re: FPGA Programming solution
129283: 08/02/20: Re: FPGA Programming solution
129288: 08/02/20: Re: FPGA Programming solution
129316: 08/02/20: Re: FPGA Programming solution
129338: 08/02/21: Re: Further Thoughts...
129347: 08/02/21: Re: Software Defined Radio auf Xilinx Virtex 4
129428: 08/02/23: Re: FPGA Editor Tutorial based on examples
129458: 08/02/25: Re: Online Engineering Calculator Tool for Electronic Engineers - FREE to use
129491: 08/02/26: Re: Interview questions
129576: 08/02/28: Re: sd card slave interface
129614: 08/02/29: Re: Software for FPGA-based PC scope
129615: 08/02/29: Re: Software for FPGA-based PC scope
129654: 08/03/02: Re: Software for FPGA-based PC scope
129664: 08/03/02: Re: Software for FPGA-based PC scope
mikest:
45997: 02/08/13: Divider in Xilinx System Generator
MikeT:
23946: 00/07/17: Atmel 1508 EPLD's
MikeTreseler:
76403: 04/12/01: Re: Altera equivalent for Xilinx's
mikew:
3238: 96/05/01: Cerritos, CA opportunity
MikeWhy:
132315: 08/05/21: Every newbie's favorite project: the Quadrature Rotary Encoder revisited
132335: 08/05/22: Re: Every newbie's favorite project: the Quadrature Rotary Encoder revisited
132346: 08/05/22: Re: Yay! We're done with the quadrature encoder!
132426: 08/05/27: Re: using EXP connector of Spartan 3a board
132466: 08/05/28: Sequentially syncrhronous
132478: 08/05/28: Re: Sequentially syncrhronous
132482: 08/05/28: Re: Sequentially syncrhronous
132488: 08/05/28: Re: Sequentially syncrhronous
132502: 08/05/29: Re: Sequentially syncrhronous
132504: 08/05/29: Re: Sequentially syncrhronous
132526: 08/05/29: Re: (won't even attempt to try again .. .. ..)
132534: 08/05/29: Re: (won't even attempt to try again .. .. ..)
132569: 08/05/31: Re: cutoff frequency
132574: 08/06/01: Re: cutoff frequency
132637: 08/06/04: Re: Using ethernet on a Xilnx board (Help appreciated)
132714: 08/06/05: Re: Your favourite DSP textbooks/websites?
132724: 08/06/05: Re: Xilinx vs Altera
132728: 08/06/05: Re: Xilinx vs Altera
132739: 08/06/05: Re: Xilinx cuts 250 jobs.
132740: 08/06/05: Re: FPGA clock frequency
132745: 08/06/05: Re: Xilinx cuts 250 jobs.
132812: 08/06/07: Re: Xilinx cuts 250 jobs.
132931: 08/06/10: Re: FPGA clock frequency
132996: 08/06/12: Re: FPGA clock frequency
133013: 08/06/13: Re: FPGA clock frequency
133086: 08/06/17: Re: FPGA configuration Beginner questions...
133136: 08/06/18: Re: Xilinx Webpack
133181: 08/06/19: =?Windows-1252?Q?Re:_NVIDIA=92s_Tesla_T10P_Blurs_Some_Lines?=
133188: 08/06/19: =?Windows-1252?Q?Re:_NVIDIA=92s_Tesla_T10P_Blurs_Some_Lines?=
133189: 08/06/19: =?Windows-1252?Q?Re:_NVIDIA=92s_Tesla_T10P_Blurs_Some_Lines?=
133208: 08/06/20: =?Windows-1252?Q?Re:_NVIDIA=92s_Tesla_T10P_Blurs_Some_Lines?=
133210: 08/06/20: Re: beginner
133230: 08/06/21: Re: help using lwIP with xilinx EMAC
133251: 08/06/22: Re: Image Sensor Interface.
133290: 08/06/23: Re: Image Sensor Interface.
133291: 08/06/23: Re: Image Sensor Interface.
133295: 08/06/24: Re: Image Sensor Interface.
133332: 08/06/25: Re: Image Sensor Interface.
133403: 08/06/27: Re: Beginner : Rotary switch (quad sw)
133438: 08/06/28: Re: Signal forwarding between FPGAs
133533: 08/07/02: Re: Nintendo DS Screenshots / Video Capture
133564: 08/07/03: Re: Have you ever experimented some problem with External Memory?
133606: 08/07/05: Re: OPB_CENTRAL_DMA
133704: 08/07/10: Re: Can I store the output of my FPGA logic inside FPGA memory for debug data values?
134237: 08/07/31: Re: Fixed point number hardware implementation
134251: 08/08/01: Re: Fixed point number hardware implementation
134378: 08/08/08: Re: What's the deal with PSoC programmers?
134631: 08/08/21: Re: Xilinx extends Spartan 3A series
134740: 08/08/28: Re: Genode FPGA graphics project launched
134748: 08/08/28: Re: Genode FPGA graphics project launched
134776: 08/08/29: Re: Genode FPGA graphics project launched
134784: 08/08/30: Re: Genode FPGA graphics project launched
134787: 08/08/31: Re: FPGA on a DIMM module, performing encryption
134789: 08/09/01: Re: FPGA on a DIMM module, performing encryption
134801: 08/09/01: Re: FPGA on a DIMM module, performing encryption
134807: 08/09/01: Re: FPGA on a DIMM module, performing encryption
134886: 08/09/04: Re: Open source licenses for hardware
134942: 08/09/08: Re: Spartan 3E evaluation board manufacturers
134977: 08/09/09: Re: Spartan 3E evaluation board manufacturers
135024: 08/09/10: Re: Spartan 3E evaluation board manufacturers
135039: 08/09/11: Re: Load Application from External Memory without the use of XMD???
135059: 08/09/12: Re: Load Application from External Memory without the use of XMD???
136316: 08/11/11: Re: Learning programming an FPGAs
140141: 09/04/30: Re: ISE 10.1 installation troubles on windows Vista 32bit
140162: 09/05/01: Re: ISE/EDK/SDK 11.1 licensing
140173: 09/05/01: Re: ISE/EDK/SDK 11.1 licensing
140182: 09/05/01: Re: ISE/EDK/SDK 11.1 licensing
140184: 09/05/01: Re: ISE/EDK/SDK 11.1 licensing
140201: 09/05/03: Re: Spartan3E Starter Kit MISO and Flash pin shared
140232: 09/05/05: Darnit! Broke MXE...
140233: 09/05/05: Re: Spartan3E Starter Kit MISO and Flash pin shared
140234: 09/05/05: Re: ISE/EDK/SDK 11.1 licensing
140253: 09/05/06: Re: Spartan3E Starter Kit MISO and Flash pin shared
140339: 09/05/09: Re: ISE 10.1 installation troubles on windows Vista 32bit
140354: 09/05/10: Re: Which alternative prog to use for hdl handling ?
140398: 09/05/12: Re: how i can use the external SRAM of FPGA
140485: 09/05/14: Re: connecting FPGA with PC using ethernet MAC layer only
140520: 09/05/15: Re: Coolrunner II: what's wrong up here ?
140521: 09/05/15: Re: Coolrunner II: what's wrong up here ?
140525: 09/05/15: Re: some soft-processors
140526: 09/05/15: Re: Open source processors
140543: 09/05/16: Re: Coolrunner II: what's wrong up here ?
140547: 09/05/16: Re: Coolrunner II: what's wrong up here ?
140564: 09/05/18: Re: some soft-processors
140567: 09/05/18: Re: Setting top level VHDL generics in XST
140621: 09/05/20: Re: ISIM and CONV_INTEGER warnings
140627: 09/05/20: Re: ISIM and CONV_INTEGER warnings
140659: 09/05/21: Re: ISIM and CONV_INTEGER warnings
140775: 09/05/25: Multple architectures in ISE top level module?
140776: 09/05/25: Re: Multple architectures in ISE top level module?
140795: 09/05/26: Re: Multple architectures in ISE top level module?
140801: 09/05/26: Re: Can we expect ISE Gui and makefile to produce identical bit files?
140817: 09/05/26: Re: Can we expect ISE Gui and makefile to produce identical bit files?
140929: 09/05/29: Re: Are Virtex-5 FPGA Handbook or Altera latest Handbooks available to sell?
140979: 09/06/01: Re: Are Virtex-5 FPGA Handbook or Altera latest Handbooks available to sell?
140993: 09/06/01: Re: Has anyone tried to install a Xilinx floating license? The documentation (UG631 (v 11.1.0) April 27, 2009) says that the required
140998: 09/06/02: Re: Has anyone tried to install a Xilinx floating license? The documentation (UG631 (v 11.1.0) April 27, 2009) says that the required
141013: 09/06/02: Re: Open Source FPGA circuit design.
141066: 09/06/04: Re: Urgent help with a Simple AND simulation
141072: 09/06/04: Re: Need help VHDL code 5-to-7 decoder (Xilinx)
141077: 09/06/04: Re: the reach of VHDL
141085: 09/06/04: Re: the reach of VHDL
141119: 09/06/06: Re: Microblaze and external block memory
141123: 09/06/07: Re: Help with Remote debugging ideas.
141150: 09/06/08: Re: AT&T Usenet Netnews Service Shutting Down
141258: 09/06/12: Re: USB3300 - Xilinx ML401 interface
141672: 09/07/02: Re: how to use ram or memory
141683: 09/07/03: Re: how to use ram or memory
141702: 09/07/03: Re: how to use ram or memory
141719: 09/07/04: Re: how to use ram or memory
141722: 09/07/04: Re: how to use ram or memory
141851: 09/07/13: Re: Xilinx Spartan 3 DCM no output!
141979: 09/07/20: Re: Xilinx WebPack 10.1 ISIM under Linux ?
142127: 09/07/26: Re: Xilinx ISE 11.x lossage
153587: 12/04/03: Expectations from newly minted EE?
153590: 12/04/03: Re: Expectations from newly minted EE?
153597: 12/04/03: Re: Expectations from newly minted EE?
153598: 12/04/03: Re: Expectations from newly minted EE?
153604: 12/04/03: Re: Expectations from newly minted EE?
153752: 12/05/11: Neurons as the ultimate field programmable logic element, or Temporal displacement leads to spatial disorientation.
153757: 12/05/15: FDE vs latch?
153771: 12/05/16: Re: FDE vs latch?
153773: 12/05/16: Re: FDE vs latch?
153776: 12/05/16: Re: FDE vs latch?
153802: 12/05/24: Re: Logic Glitches in Spartan-3?
153816: 12/05/25: Re: Read output from external chip using microblaze
Mikhail:
54517: 03/04/12: Re: fastest PLD
55377: 03/05/06: flash-disk
55416: 03/05/07: Re: flash-disk
Mikhail Matusov:
9056: 98/02/17: Altera CPLD power-up procedure?
9432: 98/03/13: Re: The case for Linux and EDA
20257: 00/02/02: Visualizing EDIF netlist for Xilinx
20281: 00/02/03: Re: Visualizing EDIF netlist for Xilinx
20307: 00/02/04: Conditional compilation in VHDL?
20316: 00/02/04: Re: Conditional compilation in VHDL?
20366: 00/02/07: Re: Conditional compilation in VHDL?
20386: 00/02/08: Re: Conditional compilation in VHDL?
24378: 00/08/05: Help! Troubles using async FIFO cores in Virtex
24393: 00/08/06: Re: Help! Troubles using async FIFO cores in Virtex
24634: 00/08/15: Re: Help! Troubles using async FIFO cores in Virtex
25132: 00/08/27: Re: "generate" and instance name indexes in Synopsys
25710: 00/09/18: Looking for an Altera APEX eval board
25820: 00/09/21: Re: Uart core?
25973: 00/09/28: Re: FPGA Express pb
28247: 01/01/03: Fixing pins on Spartan II
43925: 02/06/06: Re: Xilinx ise software?
43935: 02/06/06: Re: How to find a big, EEPROM based CPLD in a PGA package?
43964: 02/06/07: Re: Xilinx ise software?
43980: 02/06/07: Re: Xilinx JTAG verification failed
47166: 02/09/19: Apex unused pins voluntarily assigned by Quartus?
47168: 02/09/19: Re: Apex unused pins voluntarily assigned by Quartus?
47302: 02/09/23: Re: Apex unused pins voluntarily assigned by Quartus?
47438: 02/09/25: Re: FPGA programming via microcontroller
59176: 03/08/11: Q: async flip-flop reset by a signal from a different clock domain
Mikko:
28921: 01/01/29: Xilinx JEDEC files to SVF format
28933: 01/01/30: Re: Xilinx JEDEC files to SVF format
28957: 01/01/31: Re: Xilinx JEDEC files to SVF format
mikomatik:
84944: 05/06/01: mc8051 v1.4 free ip core from Oregano Systems
85034: 05/06/03: re:mc8051 v1.4 free ip core from Oregano Systems
Milan Vasilko:
666: 95/02/01: "on-fly" reprogrammable devices/research
5164: 97/01/28: ANNOUNCE: Dynamically Reconfigurable HW Page
Mile:
149243: 10/10/11: Calculating SFDR in FPGA
500milesaway:
135748: 08/10/14: Unexpected output in Post-translate Simulation: PLZ HELP
135983: 08/10/25: how to program virtex 4?
135993: 08/10/26: Re: how to program virtex 4?
136027: 08/10/28: Re: how to program virtex 4?
136125: 08/11/02: needs help on CLOCK
136534: 08/11/20: how to display on LCD of FPGA board?
Milind:
100221: 06/04/05: Delay value for FDDRCPE in Virtex-II Pro FGPA
100270: 06/04/05: Re: Delay value for FDDRCPE in Virtex-II Pro FGPA
100281: 06/04/06: Re: Delay value for FDDRCPE in Virtex-II Pro FGPA
milind:
92267: 05/11/24: MapLib error for EDK application
Milind Toke:
98981: 06/03/18: CAS signal problem with OPB DDR SDRAM controller in PPC system in EDK
<milind.parelkar@gmail.com>:
81852: 05/04/02: Question regarding EDK
81855: 05/04/02: Re: RAMB16_S9
81857: 05/04/02: Re: Question regarding EDK
81858: 05/04/02: IPIF Signals
81918: 05/04/04: Re: Need Help
millim:
50549: 02/12/12: Help:encode FSM into Block RAM
57941: 03/07/10: Xilinx Spartan-3 samples, how to get?
67196: 04/03/08: copy protection on FPGA using embedded serial number
Milliwave:
19105: 99/11/29: Using Altera to pipeline a CLA adder
19298: 99/12/11: FPGA to ASIC Conversion?
<milne@egenera.com>:
77238: 04/12/31: Dead FPGA?
miloje984:
137007: 08/12/18: IMPACT: Verification fails with inidirect SPI programming
Milos Becvar:
14210: 99/01/20: Boundary Scan & FPGA
37782: 01/12/20: Re: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu < 7 ns?
38041: 02/01/02: Re: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu < 7 ns requirement?
Miloslaw Smyk:
23709: 00/07/06: A diary of a battle: Wild-One, 2.1i and FPGA Express3.3
Milostnik:
7583: 97/09/24: Re: Lattice Synario and ISPLSI1048
10981: 98/07/08: Simulation at powerup
10984: 98/07/08: Re: Simulation at powerup
<milostnik@my-dejanews.com>:
11781: 98/09/09: Re: free version of synario for atmel - where?
11957: 98/09/21: Re: Confused teacher's THANKS
11959: 98/09/21: Xilinx 3000 family
12510: 98/10/14: Re: Schematic entry?
12682: 98/10/23: Re: Need VHDL tools for Win NT/ Win 95
13448: 98/12/03: Re: Minimum clock freq reqd
14706: 99/02/12: Re: Opinions requested : Minc/Synario alternatives
milter:
83958: 05/05/10: re:Lattice's XP (flash + sram) fpga
Min Zhao:
154: 94/09/02: FPGA Programmer and etc. (TI Activator 2), anyone interested ?
Minchuan Wang:
77767: 05/01/16: newbie question regarding netlist resource constraint (EDIF)
mindenpilot:
90557: 05/10/16: Re: Best Async FIFO Implementation
91416: 05/11/05: Re: Font requirements for patent applications
Mindroad:
76240: 04/11/29: Avnet Xilinx Virtex-II Pro Development Board
76526: 04/12/05: Re: Avnet Xilinx Virtex-II Pro Development Board
80584: 05/03/08: dsbram memory addressing
80635: 05/03/09: Re: dsbram memory addressing
80716: 05/03/10: Re: dsbram memory addressing
81173: 05/03/18: Avnet Xilinx Virtex-II Pro Development Kit
82352: 05/04/11: PLB IPIF on Virtex 2 Pro
Mindspring Newsgroups:
124152: 07/09/12: Re: PCI byte enalbes in read cycles
mindy:
68021: 04/03/24: Time measurement with Xilinx Spartan-3 - Help
<minexew@gmail.com>:
158926: 16/05/25: Explicitly setting a variable to undefined
158928: 16/05/25: Re: Explicitly setting a variable to undefined
158931: 16/05/25: Re: Explicitly setting a variable to undefined
158959: 16/05/28: Re: Explicitly setting a variable to undefined
mingyuexin:
140242: 09/05/05: Re: problem with high speed data transfer
Minh Nguyen:
30174: 01/03/27: a newbie question
Minhee Cho:
18920: 99/11/22: IWDRS 2000 Final Call for Papers
mini_monkey:
116335: 07/03/07: DCI termination mismatch error reported in ise91
Minimum:
83802: 05/05/06: IP core supply
83922: 05/05/09: Re: IP core supply
83923: 05/05/09: Re: IP core supply
84020: 05/05/11: Re: IP core supply
84416: 05/05/18: Re: IP core supply
86584: 05/06/30: ip core supply
86611: 05/06/30: Re: ip core supply
Minlin Fan:
44234: 02/06/14: BGA package
44242: 02/06/14: Xilinx JTAG embedded programming
44690: 02/06/27: blank CPLD
44786: 02/07/01: combine the Verilog code
mintchoco:
61594: 03/10/07: Avnet Xilinx Virtex II Development Board - getting started
61626: 03/10/07: Re: Avnet Xilinx Virtex II Development Board - getting started
Minti:
80862: 05/03/12: Re: (Stupid/Newbie) Question on UART
80865: 05/03/12: Re: (Stupid/Newbie) Question on UART
Mir:
121127: 07/06/26: Re: Coding style of verilog for FPGA synthesis
127499: 07/12/29: JTAG chain detects Xilinx FPGA XCV150 instead of XC2S150...
127505: 07/12/30: Re: JTAG chain detects Xilinx FPGA XCV150 instead of XC2S150...
127520: 08/01/01: Re: JTAG chain detects Xilinx FPGA XCV150 instead of XC2S150...
Miranda Baten:
2786: 96/02/07: FPGA density
2846: 96/02/16: ASIC& full-cust versus FPGA-future 5 jears
Mircea R Stan:
724: 95/02/17: Re: Looking for Tech Info
728: 95/02/18: Re: PLA? PAL? PLD? GAL?
794: 95/03/03: area of RAM cells in FPGAs
880: 95/03/20: Re: Free Viewlogic design kits?
996: 95/04/10: FS: ABEL book + software $35
1007: 95/04/13: Re: Neocad merges with Xilinx
1008: 95/04/13: Re: Need "fusemap" information from vendor, likely?
Mirek:
27287: 00/11/17: Re: Can FPGA perform float point calculation?
Mirek Klaczek:
29901: 01/03/16: Xiilinx Web Pack error
34788: 01/09/07: Re: FPU core
Mirembe:
72659: 04/08/27: Newbie question--> Obtaining RTL netlist from Xilinx ISE 6.2i Project navigator
Miriam Leeser:
1986: 95/09/28: Re: Functional Languages for Hardware Description was REPOST: Design Contest Write-up
<miriemer@rumms.uni-mannheim.de>:
128430: 08/01/25: Endpoint Block Plus v1.5 example design
Mirko Kovacevic:
11621: 98/08/26: Re: How to design a PLL
Mirko Roller:
86082: 05/06/21: dru files for eagle ?
86083: 05/06/21: Re: dru files for eagle ?
86090: 05/06/21: Re: dru files for eagle ?
Mirko Scarana:
49591: 02/11/16: Global clock routing
49772: 02/11/20: Re: Global clock routing
Miro:
113719: 06/12/20: Re: unpredictable FPGA behaviour
Miron Abramovici:
4796: 96/12/16: Re: ASICs Vs. FPGA in Safety Critical Apps.
Mirza Luqman:
62743: 03/11/06: Re: latch and shift 15 bits.
mis-spelt!:
4233: 96/10/03: Q on Xilinx/Viewsim macros
4239: 96/10/03: Re: Q on Xilinx/Viewsim macros
4240: 96/10/03: Re: Viewlogic 4.1 (DOS) mouse alternatives?
4257: 96/10/05: Re: Q on Xilinx/Viewsim macros
4268: 96/10/08: Viewlogic v4.1 Plotter.exe cmd line usage?
Misi:
118715: 07/05/02: Xilinx Spartan 3 XC3S200 and Xilinx Foundation Series 3.1i beginner problems
118720: 07/05/02: Re: Xilinx Spartan 3 XC3S200 and Xilinx Foundation Series 3.1i beginner problems
Misiu:
143608: 09/10/18: Xilinx ISim and FSM states names
misiu:
103590: 06/06/06: Xlinix ML403 evaluation board
103629: 06/06/07: Re: Xlinix ML403 evaluation board
104719: 06/07/05: Xilinx ML403 hard mac (xapp443)
105760: 06/07/31: Ethernet wrapper IP core with ML403
108935: 06/09/19: Ethernet MAC wrapper & ML403
miso@sushi.com:
151874: 11/05/26: Re: PCI Express Cable
mit:
152168: 11/07/15: Re: FPGA not getting programmed
152190: 11/07/18: Re: FPGA not getting programmed
mital1:
82501: 05/04/13: help neeeded for byteblaster of altera
Mitch:
3959: 96/08/24: I had to try it!
3962: 96/08/25: Sorry: I had to try it!
Mitch Thornton:
14161: 99/01/16: Reed-Muller99 CFP
14540: 99/02/03: CFP: =?iso-8859-1?Q?Reed=2DM=FCller?= Workshop RM99
15276: 99/03/17: CFP: Reed-Muller Workshop
24478: 00/08/10: 2001 Reed-Muller Workshop CFP
<mitch.hayenga@gmail.com>:
121290: 07/06/30: Re: How to use UART on Spartan 3E Starter Kit
MitchAlsup:
125403: 07/10/24: Re: Changing refresh rate for DRAM while in operation?
146838: 10/03/29: Re: Which is the most beautiful and memorable hardware structure in a
146912: 10/04/01: Re: Which is the most beautiful and memorable hardware structure in a
146920: 10/04/01: Re: Which is the most beautiful and memorable hardware structure in a
146946: 10/04/03: Re: Which is the most beautiful and memorable hardware structure in a
150296: 11/01/08: Re: OT: Fast Circuits
150305: 11/01/09: Re: OT: Fast Circuits
150306: 11/01/09: Re: OT: Fast Circuits
mitchell:
8910: 98/02/06: The PARALLEL Processing Connection-February 9 meeting notice
8915: 98/02/06: The PARALLEL Processing Connection - What Is It?
8938: 98/02/07: Re: Free FPGA tools???
Mitchell Crago:
43478: 02/05/22: Xilinx Serial IO Data rates
43480: 02/05/22: Xilinx configuration times
43481: 02/05/22: Re: Xilinx configuration times
45601: 02/07/29: Wishbone <-> CoreConnect
mitho:
149053: 10/09/27: FPGA For Image Processing[Economical]
<mitra.subhrajit007@gmail.com>:
155147: 13/04/29: Re: comparing Xilinx XC3S500E-4CPG132C vs Altera Cyclone IV FPGA
155148: 13/04/29: Re: comparing Xilinx XC3S500E-4CPG132C vs Altera Cyclone IV FPGA
<mitrusc1980-newsgroup@yahoo.com.br>:
139457: 09/03/30: Toolchain for programming Mach211SP PLD.
mits130:
124000: 07/09/10: 1/2 Convolutional Encoding of CNAV Data
mitshek:
121066: 07/06/24: Control Panel application for Altera Cyclone II Starter Kit, help?
121154: 07/06/27: Re: Control Panel application for Altera Cyclone II Starter Kit, help?
121155: 07/06/27: Re: VGA 1080x1920 pixel chipset
Mittens:
150061: 10/12/09: Re: Lattice XO2 video
151300: 11/03/22: Re: RAM - DIMM vs SO-DIMM: price vs. (hardware & software) ease of
151319: 11/03/22: Re: RAM - DIMM vs SO-DIMM: price vs. (hardware & software) ease of
153179: 12/01/04: Re: slimming down ISE install
<mittra@gmail.com>:
123405: 07/08/27: tricking bitgen into creating rom-like behavior
Mives:
140481: 09/05/14: Re: sync vs async reset
140509: 09/05/15: Re: Data buffering scheme problem for PCI-E interface
mizrahi_lior:
147589: 10/05/05: rtl simulation model for microblaze
MJ:
mj:
12487: 98/10/13: Re: VHDL Editor
13201: 98/11/19: Re: VHDL testbench supporting reconfiguration?
MJ Pearson:
113385: 06/12/12: Camera Link to XUP V2Pro Board
119154: 07/05/14: Camera Control
124171: 07/09/13: Peripheral Trouble!
124318: 07/09/18: Re: Peripheral Trouble!
127593: 08/01/03: Camera connection on XUPV2P
127640: 08/01/04: Re: Camera connection on XUPV2P
127755: 08/01/07: Re: Camera connection on XUPV2P
127790: 08/01/08: Re: Camera connection on XUPV2P
127905: 08/01/10: Re: Camera connection on XUPV2P
127951: 08/01/11: Re: Camera connection on XUPV2P
mjackson:
109438: 06/09/26: uBlaze prototype PCB UART issues
109495: 06/09/27: Re: uBlaze prototype PCB UART issues
109506: 06/09/27: Re: uBlaze prototype PCB UART issues
mjd001:
31506: 01/05/28: Re: xilinx webpack warning !!
31507: 01/05/28: Xilinx Reset
32333: 01/06/23: Clock Derivation
32364: 01/06/24: Re: Clock Derivation
mjl296@hotmail.com:
113337: 06/12/11: Re: @(posedge clk)
123955: 07/09/07: Re: How does the PIO Core generate a interrupt?
mjodalfr:
721: 95/02/16: Re: VERILOG
805: 95/03/03: Re: Power gain when moving from FPGA to Gate Array
907: 95/03/27: Re: Need 100 MHz, relatively low power FPGAs
963: 95/04/05: Re: Aptix (Field Programmable Interconnect) ??
<mjunaidelahi@gmail.com>:
138095: 09/02/06: Experiencing problems when moving an FPGA-based implementation to an
138129: 09/02/06: Re: Experiencing problems when moving an FPGA-based implementation to
138130: 09/02/06: Re: Experiencing problems when moving an FPGA-based implementation to
138136: 09/02/07: Re: Experiencing problems when moving an FPGA-based implementation to
MK:
35791: 01/10/17: Re: Recommended Newsgroup
36924: 01/11/26: Re: fpga programming using microcontroller
41213: 02/03/22: Re: Poor availability problems on Coolrunner
53723: 03/03/20: Re: FPGA choice (UK)
85529: 05/06/10: Re: X-Fest devkit order leadtimes & software silliness....
85797: 05/06/16: Re: Availability of Spartan3
92403: 05/11/29: Re: Cypress FX2 bandwidth problem
112783: 06/11/29: Re: So who has used Lattice FPGAs recently?
116455: 07/03/09: Xilin X-Fest Lunacy
116456: 07/03/09: Re: Xilin X-Fest Lunacy
121520: 07/07/06: Re: Xilinx ISE, EDK and some ground roules in software development
126250: 07/11/18: Re: Low cost FPGA w/serdes
133160: 08/06/19: Re: Synplify beeping
135622: 08/10/10: Re: Lattice vs Altera (Mico32 / NIOS)....or?
137604: 09/01/23: Re: Spartan-6
141547: 09/06/27: Re: 6/6 infos
142242: 09/07/30: Re: Antti-Brain, should I keep going?
143070: 09/09/18: Re: FPGA for acoustic adaptive beamforming
143306: 09/10/01: Re: Antti-Brain one year anniversary
143889: 09/11/02: Re: 50+ pages fresh from Antti's brain
144996: 10/01/19: Re: Easy PC software tool - Bad experience
146657: 10/03/25: Re: USB 3.0 implementation on FPGA
152959: 11/11/05: Re: PCI Express development board
153317: 12/01/31: Re: TCP/IP
153413: 12/02/20: Re: gigabit ethernet problem
153417: 12/02/21: Re: gigabit ethernet problem
153566: 12/03/28: Re: FPGA communication with a PC (Windows)
153572: 12/03/29: Re: FPGA communication with a PC (Windows)
153588: 12/04/03: Re: Expectations from newly minted EE?
153910: 12/06/29: Re: Replacement for XC4005E
154162: 12/08/23: Re: recruit FPGA design engineer in Scotland
154252: 12/09/16: Re: Looking for an extremely cheap FPGA board (in quantity, academic
155839: 13/09/29: Re: Lattice diamond / MachXO2
155875: 13/10/10: Re: Book recommendation
155878: 13/10/10: Re: Book recommendation
155933: 13/10/17: Re: Zynq devices, boards and suppliers
156162: 14/01/03: Re: Optimising pin allocation
156251: 14/01/24: Re: chip-to-chip serial comms
156822: 14/07/05: Re: ECP5 support in Latest Diamond 3.2 IDE from Lattice ( 64-bit
156824: 14/07/05: Re: ECP5 support in Latest Diamond 3.2 IDE from Lattice ( 64-bit
157024: 14/09/03: Re: Easy PC software tool - Bad experience
157342: 14/11/25: IC40HX PLL Simulation
mk:
57785: 03/07/07: Re: QuartusII software licencing
73870: 04/09/30: Re: Read back FPGA configuration
74048: 04/10/03: Re: FPGA vs ASIC area
74617: 04/10/15: Re: Metastability pipeline causes bad juju
74753: 04/10/18: Re: Constrained Random Value in verilog
74894: 04/10/21: Re: Async reset
74919: 04/10/21: Re: Async reset
75466: 04/11/06: Re: how to force DC to use a specific cell ?
75676: 04/11/12: Re: I can't set inout port in vhdl code
75697: 04/11/12: Re: Why does NCVerilog fail to annotate these timing checks?
76229: 04/11/29: Re: fpga prices
76294: 04/11/30: Re: Adder Tree Placement
77921: 05/01/20: Re: Asic prototyping in Fpga - prototyping the gates.
77980: 05/01/21: Re: Asic prototyping in Fpga - prototyping the gates.
78434: 05/02/01: Re: Any solution for solving setup or hold time violation?
78802: 05/02/08: Re: Retaining not used nodes
79086: 05/02/14: Re: Fast counting
79726: 05/02/23: Re: The real performance leader: V4
79775: 05/02/24: Re: Looking for some rules of thumb - migrating a discrete 74HCxxx design into an FPGA
79780: 05/02/24: Re: Multiple additions
79952: 05/02/26: Re: setup-hold time problems
80508: 05/03/07: Re: Asynchronous processor !?!
80853: 05/03/12: Re: (Stupid/Newbie) Question on UART
81198: 05/03/19: Re: LVDS as general differential input ?
81740: 05/03/30: Re: Bi-directional Pin Use
81916: 05/04/04: Re: Reverse engineering ASIC into FPGA
81922: 05/04/04: Re: Stupid question
82253: 05/04/09: Re: ISE 7.1 for 64 bit Linux ???
82737: 05/04/17: Re: Spartan 3E slower that Spartan 3?
83932: 05/05/10: Re: true dual port memory v/s simple dual port memory
84273: 05/05/16: Re: Universal logic modules vs NAND-like modules
85616: 05/06/12: Re: How to pipeline Loop Logic?
85640: 05/06/13: Re: FPGA or SSE2 ?
87062: 05/07/14: Re: Modulo division in Verilog
87482: 05/07/25: Re: July 20th Altera Net Seminar: Stratix II Logic Density
87927: 05/08/03: Re: Xilinx Best Source for Reset
87978: 05/08/04: Re: Xilinx Best Source for Reset
87980: 05/08/04: Re: Xilinx Best Source for Reset
88042: 05/08/07: power of two multiplier
88267: 05/08/13: Re: Peter Alfke's SPDT Switch Debouncer
88770: 05/08/28: Re: Clock skew in FPGA Xilinx?
88789: 05/08/28: Re: Best FPGA for floating point performance
88796: 05/08/29: Re: Best FPGA for floating point performance
89047: 05/09/03: Re: Modelling latches in Verilog
89228: 05/09/08: Re: ISE 64bit question
89695: 05/09/22: Re: Hints for efficient 32 bit multiplier
92075: 05/11/22: Re: Oh no! Resets Again? Yes, but it could be important.
92081: 05/11/22: Re: How do I find the datasheet of this device "TIOPA 690 3BZL9"?
92524: 05/12/01: Re: systemC vs VHDL
92526: 05/12/01: Re: systemC vs VHDL
92703: 05/12/05: Re: Synthesize: Error
92714: 05/12/05: Re: What's wrong with the document?
93081: 05/12/13: Re: Xilinx floating point core 1.0
93595: 05/12/26: Re: Can somone work on the pci express project?
93829: 06/01/01: Re: FPGA running diff with simulation
94306: 06/01/09: Re: Why 'a plurality of N' must be used for 'N' in patent claims
93965: 06/01/04: Re: Using posedge and negedge causing me grief
94045: 06/01/05: Re: Using posedge and negedge causing me grief
94054: 06/01/05: Re: ModelSim vsim-3601 message
94095: 06/01/05: Re: Do you name your FPGA?
94119: 06/01/05: Re: Do you name your FPGA?
94364: 06/01/10: Re: Asynch. signal
94186: 06/01/07: Re: Programming Xilinx PowerPC
94327: 06/01/10: Re: "failed to create empty document"
94243: 06/01/09: Re: "failed to create empty document"
94528: 06/01/13: Re: PCI e clocking
95357: 06/01/22: Re: The attributes specified to DCM instance doesnot get written to the .vm file
95453: 06/01/23: FPGA board with High Speed LVDS
96646: 06/02/08: Re: cheap USB analyzer based on FPGA
97158: 06/02/17: Re: Communication between FPGA and PC with ethernet
97296: 06/02/20: Re: Problem with multple clcok domains
97311: 06/02/20: Re: Is FPGA code called firmware?
97318: 06/02/20: arctangent again
97408: 06/02/22: Re: Communication between FPGA and PC with ethernet card
97409: 06/02/22: Re: Is FPGA code called gateware?
97560: 06/02/24: Re: Kalman filters
98367: 06/03/09: Re: Shift Register synthesis??
99292: 06/03/22: Re: Going from CLK1X to CLK2X.. really safe?
99532: 06/03/26: Re: OpenSPARC released
99565: 06/03/27: Re: OpenSPARC released
99575: 06/03/27: Re: OpenSPARC released
99649: 06/03/27: Re: ERROR:Xst:827 - bad synchronous description
99881: 06/03/30: Re: Help needed
99887: 06/03/30: GTKWave 1.3.86 for Windows is available
99891: 06/03/30: Re: Xilinx Schematic Entry
99919: 06/03/31: Synplicity cuts structured ASIC tools, 8% of workforce
100187: 06/04/05: Re: Xilinx Schematic Entry
100255: 06/04/05: Re: Xilinx Schematic Entry
100315: 06/04/06: Re: Bizarre behaviour by Quartus?
100316: 06/04/06: Re: Bizarre behaviour by Quartus?
100321: 06/04/06: Re: Bizarre behaviour by Quartus?
100689: 06/04/16: Re: systemc
100746: 06/04/17: Re: PLD610
102945: 06/05/23: Re: Verilog vs VHDL
103117: 06/05/25: Re: DSP48E, What are the internal implementations used?
103130: 06/05/26: Re: DSP48E, What are the internal implementations used?
103449: 06/06/02: Re: Simulating post par simulation model
103709: 06/06/09: Re: (Stupid/Newbie) Question on UART
103916: 06/06/14: Re: Time for a new "Largest FPGA with free tool support"?
103975: 06/06/16: Re: clockless arbiters on fpgas? [here's how it's done in ASICs]
104069: 06/06/18: Re: High speed differential to single ended
104445: 06/06/27: Re: keys to the Kingdom
104448: 06/06/27: Re: Once synthesized RAMs are vanishing in WebPACK 8.1i03
104501: 06/06/28: xilinx ml423 boards available ?
104557: 06/06/29: Re: How to evaluate the space efficiency of a historic design.
104717: 06/07/05: Re: stable reset in fpga
104818: 06/07/06: Re: Fastest platform to run ISE?
104879: 06/07/07: Re: Chaos in FF metastability
104922: 06/07/10: Re: The FFs with synchronous reset perform worse?
104952: 06/07/10: Re: The FFs with synchronous reset perform worse?
105076: 06/07/13: Re: Micorblaze post place and route simulation...
105079: 06/07/13: Re: Micorblaze post place and route simulation...
105172: 06/07/17: 2048 input or gate ?
105198: 06/07/17: Re: 2048 input or gate ?
107183: 06/08/25: Re: Linear priority encoder in Xilinx Virtex4
107926: 06/09/02: Re: Qestion about the ability of synthesis
108119: 06/09/05: Re: LUT Blocks?
109010: 06/09/20: Re: synchronous clocks
109154: 06/09/21: Re: Fast Platform for ISE?
109158: 06/09/21: Re: Fast Platform for ISE?
109190: 06/09/21: Re: Are you ready for Virtex-5? We are...
109599: 06/09/30: Re: state machine dead problem
109810: 06/10/05: Re: An implementation of a clean reset signal
109965: 06/10/09: Re: Antifuse, lower cost?
110000: 06/10/09: Re: a clueless bloke tells Xilinx to get a move on
110025: 06/10/09: Re: a clueless bloke tells Xilinx to get a move on
110026: 06/10/09: Re: a clueless bloke tells Xilinx to get a move on
110507: 06/10/17: GTKWave 3.0.13 for win32
110736: 06/10/20: Re: FAQ: Re: Fastest ISE Compile PC?
111663: 06/11/07: Re: Fastest ISE Compile PC?
112058: 06/11/15: Re: Microblaze store
112089: 06/11/16: Re: Microblaze store
112289: 06/11/19: Re: board - T562.jpg
112481: 06/11/23: Re: Altera configuration with microcontroller
112806: 06/11/29: Re: FPGA workstation - should I wait for Window Vista?
112817: 06/11/29: Re: FPGA workstation - should I wait for Window Vista?
113505: 06/12/15: gtkwave 3.0.18 for win32
113968: 06/12/31: Re: Help with ISE (multi-source in unit error)
113977: 07/01/01: Re: Help with ISE (multi-source in unit error)
114547: 07/01/19: Re: "Gate" = ???
114956: 07/01/28: gtkwave 3.0.20 for win32
120210: 07/06/03: Re: Microcontrollers have a better predictable time behaviour than FPGAs
120317: 07/06/05: Re: Lattice XP2 finally announced
120371: 07/06/06: Re: Virtex4 CLKX2 DCM Jitter
120589: 07/06/11: Re: Unexpected resources utilization
122171: 07/07/21: GTKWave 3.0.29 for win32
122272: 07/07/24: Re: VCD file doesn't show anything in GtkWave
122451: 07/07/27: Re: or1200 uses more than 100% of resources. how to reduce?
122970: 07/08/13: Re: New Xilinx forum.
123194: 07/08/19: Re: Xilinx / ISE multi-cycle path constraint pitfall
123719: 07/09/02: GTKWave 3.1.0 for win32
124392: 07/09/20: Re: Is it possible for two wires to share the same FPGA pin?
124395: 07/09/20: Re: Gated Clock Problems
124458: 07/09/22: Re: Gated Clock Problems
124881: 07/10/09: Re: 8B/10B Xilinx Paper
125536: 07/10/27: Re: FPGA vs ASIC
125585: 07/10/29: Re: FPGA vs ASIC
125626: 07/10/30: Re: FPGA vs ASIC
125644: 07/10/31: Re: FPGA vs ASIC
125645: 07/10/30: Re: FPGA vs ASIC
125661: 07/10/31: Re: FPGA vs ASIC
125686: 07/10/31: Re: FPGA vs ASIC
125690: 07/11/01: Re: FPGA vs ASIC
125742: 07/11/02: Re: Synthesizing with specific primitive-elements
126264: 07/11/18: Re: Quartus II warning: "pass-through logic has been added"
126267: 07/11/18: Re: VHDL language is out of date! Why? I will explain.
126269: 07/11/18: GTKWave 3.1.1 for win32
126378: 07/11/20: Re: Why doesnt XST RAM for this VHDL description
126583: 07/11/28: Re: Behavioral Simulation working but Post-route Simulation is not.
127364: 07/12/19: Re: sampling error between 2 clocks
127371: 07/12/19: Re: sampling error between 2 clocks
127389: 07/12/20: Re: sampling error between 2 clocks
127916: 08/01/10: Re: Real examples of metastability causing bugs
127946: 08/01/11: Re: Can you help me about SAS IP core implementing
128032: 08/01/14: Re: Virtex4 burn-in failure
128333: 08/01/22: Re: Is it possible to define an Integer so it could be incremented and return to 0.
128524: 08/01/30: GTKWave 3.1.3 for win32
128649: 08/02/01: Re: Xilinx BSCAN primitives proper use
128671: 08/02/02: Re: Internal signal names in ModelSim
129589: 08/02/28: Re: How to connect FPGA to a ASIC Board?
130622: 08/03/28: Re: quick question
130658: 08/03/29: Re: async clk input, clock glitches
130659: 08/03/29: Re: async clk input, clock glitches
131177: 08/04/14: Re: XST support for User Defined Primitives
132547: 08/05/30: Re: Xilinx Clock Doubler
MK Wong:
111276: 06/11/01: Blog from Lattice Semiconductor
MK Yap:
19559: 99/12/31: Using internal RAM in Altera Flex 10KE
19602: 00/01/04: Re: Using internal RAM in Altera Flex 10KE
19607: 00/01/04: Decoding RSPC (Reed Solomon Product Code)
19726: 00/01/10: Re: Decoding RSPC (Reed Solomon Product Code)
19751: 00/01/11: Re: Decoding RSPC (Reed Solomon Product Code)
19918: 00/01/18: Which VHDL synthesizer/compiler?
21695: 00/03/29: tristate /driving a bidirectional port
21803: 00/04/01: Re: tristate /driving a bidirectional port
21978: 00/04/11: Re: Multiple Clock design, setup & hold time violation
22008: 00/04/12: Re: Multiple Clock design, setup & hold time violation
22059: 00/04/17: Re: Multiple Clock design, setup & hold time violation
22082: 00/04/20: Interface with Altera's LPM_RAM_IO && Multiple cycle instruction with Synplify??
22145: 00/04/27: Re: Interface with Altera's LPM_RAM_IO && Multiple cycle instruction with Synplify??
22534: 00/05/11: Shifting with STD_LOGIC_VECTOR???
22558: 00/05/12: Re: Shifting with STD_LOGIC_VECTOR???
23126: 00/06/15: Error: Clock skew plus hold time of destination register exceeds register-to-register delay
23356: 00/06/23: Re: Error: Clock skew plus hold time of destination register exceeds register-to-register delay
24114: 00/07/27: Which one is good coding style?
24120: 00/07/27: Re: Which one is good coding style?
24122: 00/07/27: Re: Which one is good coding style?
<MK2000@Juno.com>:
10758: 98/06/16: Re: Free Computer --BULLSHIT! ADMAX/ComputerMania/PCmania MLM/Spam/ SCAM !!!
mkaras:
111021: 06/10/27: Re: Xilinx Virtex-4 Clock Multiplexer Inputs
150865: 11/02/16: Re: Xilinx USB programming cable.
mkl:
73453: 04/09/22: Re: Virtex 4 integrated A/Ds? Yes it does.
73455: 04/09/22: Re: Stratix II vs. Virtex 4 - features and performance
mkr:
135235: 08/09/22: duty cycle significance
135303: 08/09/25: wishbone interface
135319: 08/09/25: Re: wishbone interface
MKraus:
3383: 96/05/23: Re: socket wanted for xilinx or other way to
mksuth:
149871: 10/11/30: PCI Architecture Question for Data Acquisition Board
149873: 10/11/30: Re: PCI Architecture Question for Data Acquisition Board
149879: 10/11/30: Re: PCI Architecture Question for Data Acquisition Board
149911: 10/12/01: Re: PCI Architecture Question for Data Acquisition Board
<MKULTRA2@gmail.com>:
105518: 06/07/25: Xilkernel: Using the shared memory API
105519: 06/07/25: Re: EDK + Assembly Output Files + External Memory Usage
105520: 06/07/25: Re: Xilkernel: Using the shared memory API
<mkumarsampath@gmail.com>:
123004: 07/08/14: SATA OOB using Rocket IO (Virtex 5)
ML:
97074: 06/02/16: What is 1QN and 2QN in Xilinx CORDIC ?
97381: 06/02/21: Virtex2: can I really just leave M1,M2,M3 pins floating?
ML402:
121682: 07/07/11: MiG : Memory Interface (DDR SDRAM) as an ISE schematic symbol
121690: 07/07/11: Re: MiG : Memory Interface (DDR SDRAM) as an ISE schematic
121692: 07/07/11: Re: MiG : Memory Interface (DDR SDRAM) as an ISE schematic
121746: 07/07/12: Re: MiG : Memory Interface (DDR SDRAM) as an ISE schematic
121751: 07/07/12: Re: MiG : Memory Interface (DDR SDRAM) as an ISE schematic
121844: 07/07/13: Re: MiG : Memory Interface (DDR SDRAM) as an ISE schematic
121850: 07/07/13: Re: MiG : Memory Interface (DDR SDRAM) as an ISE schematic
Mladen Veselic:
28537: 01/01/16: Oscillator for FPGA - low cost
mlajevar:
144754: 09/12/30: ADC problem on spartan3E
144760: 09/12/30: Re: ADC problem on spartan3E
144793: 10/01/03: Re: Digital-to-Analog Converter LTC 2624, Spartan-3A
144794: 10/01/03: Re: Digital-to-Analog Converter LTC 2624, Spartan-3A
144814: 10/01/06: Re: ADC problem on spartan3E
144988: 10/01/18: working with ADC and DAC together
<mlesha@hotmail.com>:
128200: 08/01/17: Using PECL inputs and PLL's in ProASIC Plus.
mlin:
143057: 09/09/17: Memory Interface Generator
143103: 09/09/20: Re: Memory Interface Generator
<mljohnson00@yahoo.com>:
102931: 06/05/23: Re: PCI 64/66 fpga eval boards
<mlms@fe.up.pt>:
28237: 01/01/03: Partial reconfiguration using jbits
<mlmtkv@hotmail.com>:
16097: 99/05/03: I want your support 8565
<mlpei279@gmail.com>:
87064: 05/07/14: why my programm has no response after i added some opb_bram_if_ctrl core my project?
mludwig:
118486: 07/04/27: constraints for design-generated clock
118573: 07/04/30: weird PACE Error, not one google result
118632: 07/05/01: Re: weird PACE Error, not one google result
118811: 07/05/03: JTAG Loader tools won't execute
118823: 07/05/04: Re: JTAG Loader tools won't execute
118840: 07/05/04: Re: JTAG Loader tools won't execute
118846: 07/05/04: Re: JTAG Loader tools won't execute
<mlzfgl@4r5g6hv5.net>:
22216: 00/05/02: L.E,G.A,L C,A.B,L.E T,V D,E-S,C.R,A.M,B.L,E.R............. 3277
MM:
49966: 02/11/27: Has anyone implemented a IEEE1394 LLC?
49968: 02/11/27: Re: question about PCB traces for FPGA board... ?
50081: 02/11/30: Re: Interfacing DSP to PCI bridge using a FPGA
50092: 02/12/02: Re: Interfacing DSP to PCI bridge using a FPGA
50102: 02/12/02: Re: Interfacing DSP to PCI bridge using a FPGA
50146: 02/12/03: Re: PROM for XC2S300
51003: 02/12/26: Has anyone implemented IEEE1394 LLC in a FPGA?
51023: 02/12/26: Re: Digital Resampling
60469: 03/09/14: Re: DDC design
61006: 03/09/26: FF with CE doesn't synthesize correctly by XST?
61012: 03/09/26: Re: FF with CE doesn't synthesize correctly by XST?
61021: 03/09/26: Re: FF with CE doesn't synthesize correctly by XST?
61023: 03/09/26: Re: FF with CE doesn't synthesize correctly by XST?
61026: 03/09/26: Re: FF with CE doesn't synthesize correctly by XST?
61029: 03/09/26: Re: FF with CE doesn't synthesize correctly by XST?
61032: 03/09/26: Re: Xilinx: LOC'd IO internal to VHDL Module
61034: 03/09/26: Re: FF with CE doesn't synthesize correctly by XST?
61040: 03/09/26: Re: FF with CE doesn't synthesize correctly by XST?
61097: 03/09/27: Re: FF with CE doesn't synthesize correctly by XST?
61194: 03/09/30: Is Xilinx Webpack 6.1 help crippled?...
61214: 03/09/30: Re: Is Xilinx Webpack 6.1 help crippled?...
61258: 03/09/30: Re: Is Xilinx Webpack 6.1 help crippled?...
61278: 03/10/01: Re: Is Xilinx Webpack 6.1 help crippled?...
61366: 03/10/02: Re: Is Xilinx Webpack 6.1 help crippled?...
61375: 03/10/02: Safe state machine design problem
61381: 03/10/02: Re: Safe state machine design problem
61404: 03/10/03: Re: Safe state machine design problem
61405: 03/10/03: Re: Safe state machine design problem
62147: 03/10/20: Re: BIT files
62176: 03/10/21: Re: bitstream compatibility
62239: 03/10/22: Re: Any problems with Xilinx 6.1i ISE?
62295: 03/10/24: Re: Thank to you and Google
62496: 03/10/30: Re: Xilinx XC95108 Chip
63168: 03/11/17: Re: PCI Slot Expansion
63179: 03/11/17: Virtex II multipler performance
63182: 03/11/17: Re: Is this a good starter kit?
63189: 03/11/17: Re: Virtex II multipler performance
63294: 03/11/19: Re: State Machines....
63295: 03/11/19: Re: 400 Mb/s ADC
63327: 03/11/19: Re: 400 Mb/s ADC
63351: 03/11/20: Re: 400 Mb/s ADC
63452: 03/11/21: Re: Is this a good starter kit?
63468: 03/11/22: Re: Is this a good starter kit?
63479: 03/11/22: Re: Affordable Development Board
63667: 03/11/27: Re: Any integesting article about PLD for short presentation
65570: 04/02/02: Is it possible that a Virtex II device performs below its spec?
65573: 04/02/02: Re: Is it possible that a Virtex II device performs below its spec?
65578: 04/02/02: Re: Is it possible that a Virtex II device performs below its spec?
65623: 04/02/03: Re: Is it possible that a Virtex II device performs below its spec?
65625: 04/02/03: Re: Is it possible that a Virtex II device performs below its spec?
65631: 04/02/03: Re: Design Flow: PCI or any other high-speed PC interface ?
65632: 04/02/03: Re: dual port RAM - write cycle problems
65647: 04/02/04: Re: Is it possible that a Virtex II device performs below its spec?
65671: 04/02/04: Re: Design Flow: PCI or any other high-speed PC interface ?
65732: 04/02/05: Re: installing stand alone xilinx impact
65737: 04/02/05: Re: Is it possible that a Virtex II device performs below its spec?
65782: 04/02/06: Re: Is it possible that a Virtex II device performs below its spec?
66273: 04/02/16: Re: using fpga for sampling audio
66382: 04/02/18: Re: GZIP algorithm in FPGA
66634: 04/02/24: Re: SHARC 21062/21060 link port implementation on Virtex 2 FPGA
66658: 04/02/24: Re: Driving INOUT signals
66688: 04/02/25: Re: Driving INOUT signals
66694: 04/02/25: Re: Driving INOUT signals
66727: 04/02/25: Re: Modular Design in WebPack
66760: 04/02/26: Re: VHDL FSM Problem
66944: 04/03/01: Re: Driving INOUT signals
68702: 04/04/14: Re: Help - DDS Control in Virtex II
69049: 04/04/26: Virtex II Pro and 3rd party devices in one JTAG chain?
69076: 04/04/26: Re: Virtex II Pro and 3rd party devices in one JTAG chain?
69267: 04/05/03: Re: frequency multiplication
69597: 04/05/14: 5V signals at Spartan-IIE inputs
69676: 04/05/17: Re: question about filter design vhdl
71212: 04/07/12: Re: Same bitstream files give different behavior.
71216: 04/07/12: Re: FPGA to PCI Bus Interface
71225: 04/07/12: Re: FPGA to PCI Bus Interface
71247: 04/07/13: MicroBlaze in Spartan3, external memory interface
71265: 04/07/13: Re: MicroBlaze in Spartan3, external memory interface
71324: 04/07/14: Re: FPGA to PCI Bus Interface
72183: 04/08/10: Understanding Xilinx Timing Constraints Analysis Report
72301: 04/08/13: Re: [CPLD] Novice
72320: 04/08/14: Re: [CPLD] Novice
72538: 04/08/23: Ethernet
72655: 04/08/27: Re: How to Figure out EPLD can be socketed or not!
72722: 04/08/30: Re: The Effect of Pin Assginment
72743: 04/08/31: Re: The Effect of Pin Assginment
73068: 04/09/13: Re: Adding a Delay
77806: 05/01/17: Time constraints in ISE, help required
77814: 05/01/17: Re: Time constraints in ISE, help required
77838: 05/01/18: Re: Time constraints in ISE, help required
77845: 05/01/18: Re: Time constraints in ISE, help required
78647: 05/02/04: Re: PPC on Virtex2P: Jumpstart, recommended reading?
80031: 05/02/28: RocketIO, where to start?
80084: 05/03/01: Re: RocketIO, where to start?
80085: 05/03/01: Re: RocketIO, where to start?
80114: 05/03/01: Re: RocketIO, where to start?
80184: 05/03/02: Re: RocketIO, where to start?
80817: 05/03/11: Re: RocketIO and Gigabit Ethernet
80849: 05/03/12: Re: RocketIO and Gigabit Ethernet
81708: 05/03/30: Xilinx EDK tool flow
83029: 05/04/21: Looking for a RocketIO expert in Ottawa, ON
84985: 05/06/02: Re: problem with edk 7.1
85016: 05/06/02: How do I instantiate GT11CLK_MGT?
85017: 05/06/02: Re: How do I instantiate GT11CLK_MGT?
85180: 05/06/06: Why does RocketIO Wizard always create dual GT11 tranceiver blocks?
85219: 05/06/06: Re: Why does RocketIO Wizard always create dual GT11 tranceiver blocks?
85281: 05/06/07: Re: Why does RocketIO Wizard always create dual GT11 tranceiver blocks?
85520: 05/06/10: ISE7.1 PAR Warinng: excessive skew because 1 NON-CLK pins...
87631: 05/07/27: Re: [JTAG] How to force a FPGA to reprogram itself from a prom with JTAG ?
87695: 05/07/28: Re: [JTAG] How to force a FPGA to reprogram itself from a prom with JTAG ?
87763: 05/07/31: Re: struggling with general digital design
87816: 05/08/02: Re: struggling with general digital design
88547: 05/08/22: Re: Using very large number in VHDL
89131: 05/09/06: Re: SI newsgroup
90369: 05/10/11: Re: converting 12v signal to 3.3v
92294: 05/11/25: LF: XC4VFX20 samples
97015: 06/02/14: Xilinx EDK BRAM confusion
97049: 06/02/15: Re: EDK Woes and Worries
97054: 06/02/15: Re: EDK Woes and Worries
97062: 06/02/15: Re: Xilinx EDK BRAM confusion
97120: 06/02/16: Xilinx EDK GPIO: Can I drive internal logic with it?
97150: 06/02/17: Re: Xilinx EDK GPIO: Can I drive internal logic with it?
97171: 06/02/17: Re: Xilinx UCF area constraints disappearing
97902: 06/03/01: Re: PPC Linux SoC on Virtex4 in 4 hours !?
98063: 06/03/03: EDK: choices for simple internal control
98072: 06/03/03: Re: EDK: choices for simple internal control
98102: 06/03/04: Re: EDK: choices for simple internal control
98121: 06/03/05: Re: EDK: choices for simple internal control
98165: 06/03/06: Re: EDK: choices for simple internal control
98171: 06/03/06: Re: EDK: choices for simple internal control
98180: 06/03/06: Re: Simulation of Xilinx Rocket IO
98181: 06/03/06: Re: Question for the EDK ppc users ...
98218: 06/03/07: Re: Simulation of Xilinx Rocket IO
98424: 06/03/09: EDK: DCR bus doesn't work
98451: 06/03/10: EDK8.1: Is adding IP core parameters stiil possible?
98461: 06/03/10: Re: EDK8.1: Is adding IP core parameters stiil possible?
98466: 06/03/10: Re: EDK8.1: Is adding IP core parameters stiil possible?
98490: 06/03/10: Re: DCR bus doesn't work
98515: 06/03/11: Re: EDK: choices for simple internal control
98561: 06/03/12: Re: using EDK with the gcc -g option...
98736: 06/03/15: Any PCAD users here by any chance?
98738: 06/03/15: Re: Any PCAD users here by any chance?
99017: 06/03/18: Can one use MGT clock input for global clock in Virtex4
99024: 06/03/19: Re: Can one use MGT clock input for global clock in Virtex4
99354: 06/03/23: Re: Those yellow markers .... (ISE8.1)
99397: 06/03/23: Re: Digital filter design software?
99721: 06/03/28: Re: basic doubts about chipscope pro
100090: 06/04/03: Re: Problem erasing EEPROM XCF08P
100430: 06/04/08: Re: shared BRAM between PPC and FPGA fabric
100432: 06/04/09: Re: Testing sample Aurora design on ML321 board
100619: 06/04/13: Re: PCB Stack
100621: 06/04/13: Re: PCB Stack
100622: 06/04/13: RGMII mode on V4 Hard Tri-EMAC core
100626: 06/04/13: Re: RGMII mode on V4 Hard Tri-EMAC core
100628: 06/04/13: Re: RGMII mode on V4 Hard Tri-EMAC core
100812: 06/04/18: Re: RGMII mode on V4 Hard Tri-EMAC core
100854: 06/04/19: Re: RGMII mode on V4 Hard Tri-EMAC core
101536: 06/05/02: Re: Deadlock PLB
102561: 06/05/17: Re: IEEE-1394 (aka FireWire) Core
102580: 06/05/17: Looking for DDC/DUC customizable cores
102929: 06/05/23: Re: Building a board with Spartan 3 FPGA.
103539: 06/06/05: Xilinx Floorplanner basic question
103603: 06/06/06: EDK: TCL scripts in pcores directories
103730: 06/06/09: Re: Current from FPGA pins to ADC
103852: 06/06/13: Re: RocketIO AC coupling
104225: 06/06/21: Re: Xilinx ISE 8.1i Trouble
104228: 06/06/21: Re: Xilinx ISE 8.1i Trouble
104322: 06/06/23: Achieving timing in Xilinx EDK designs
104334: 06/06/23: Re: Achieving timing in Xilinx EDK designs
104374: 06/06/26: Re: multisource on signal in XPS
104480: 06/06/28: Re: Achieving timing in Xilinx EDK designs
104538: 06/06/29: Re: Problem to extend Xilinx GSRD Design
104546: 06/06/29: Re: Achieving timing in Xilinx EDK designs
104560: 06/06/29: Re: Problem to extend Xilinx GSRD Design
104571: 06/06/29: Re: Problem to extend Xilinx GSRD Design
104585: 06/06/30: Re: rocketIO simulation
104625: 06/07/02: Re: component instantiation ISE7.1
104667: 06/07/03: Re: component instantiation ISE7.1
104678: 06/07/04: Re: component instantiation ISE7.1
104679: 06/07/04: Re: Inferring multiple-DSP48 pipelined multiplier in VHDL
104775: 06/07/05: Re: component instantiation ISE7.1
104812: 06/07/06: Fastest platform to run ISE?
104941: 06/07/10: Re: component instantiation ISE7.1
104981: 06/07/11: Re: High-speed DAC/ADC with FPGA
104998: 06/07/11: Re: High-speed DAC/ADC with FPGA
105013: 06/07/11: Re: component instantiation ISE7.1
105065: 06/07/12: Re: Can't get my Verilog Peripheral to import into XPS! Any tricks?
105101: 06/07/13: EDK - Debugging software applications located in ISOCM
105361: 06/07/20: Re: ISE 8.2i and EDK8.1i
105436: 06/07/22: Trouble meeting EMAC RGMII timing in V4FX
105503: 06/07/24: Re: EDK Using External Ports to toggle FPGA pins
105504: 06/07/24: Re: EDK Using External Ports to toggle FPGA pins
105616: 06/07/27: Re: *.bit and *.elf Files
105617: 06/07/27: Guided MAP/PAR in ISE
105624: 06/07/27: Re: Guided MAP/PAR in ISE
105647: 06/07/27: Re: Guided MAP/PAR in ISE
105673: 06/07/28: Re: EDK : *.bit and *.elf Files
105686: 06/07/28: Re: Does MAC FIR filter need special care?
105726: 06/07/30: Re: Does MAC FIR filter need special care?
105732: 06/07/30: Re: Does MAC FIR filter need special care?
105762: 06/07/31: Re: EDK : *.bit and *.elf Files
105764: 06/07/31: Re: EDK : *.bit and *.elf Files
105826: 06/08/01: Re: XPS 7.1 to 8.1 Warnings
105946: 06/08/03: Re: Coregen help
105963: 06/08/03: Re: Coregen help
105965: 06/08/03: Re: Coregen help
106022: 06/08/05: Re: FPGA interface to serial ADC
106225: 06/08/09: Re: ISE software bug???
106234: 06/08/09: Re: ISE software bug???
106241: 06/08/09: Re: Avnet V2Pro dev board "Hello world"
106243: 06/08/09: Re: ISE software bug???
106246: 06/08/09: Re: ISE software bug???
106250: 06/08/09: Re: ISE software bug???
106251: 06/08/09: Re: Avnet V2Pro dev board "Hello world"
106277: 06/08/10: Re: EDK peripherals and CoreGen netlists
106335: 06/08/11: EDK: OPB_IPIF, too many versions...
106336: 06/08/11: Re: OPB_IPIF, too many versions...
106337: 06/08/11: Re: OPB_IPIF, too many versions...
106498: 06/08/14: Re: OPB_IPIF, too many versions...
106505: 06/08/14: Re: RocketIO MGT Tile/Column Question
106511: 06/08/14: Re: Error building mpmc2
106557: 06/08/15: Re: RocketIO MGT Tile/Column Question
106572: 06/08/15: Re: IIR filter example ?
106641: 06/08/16: Re: Open-source JTAG software?
106644: 06/08/16: Re: Open-source JTAG software?
106649: 06/08/16: Re: Is necessary to use Modsim on DDR Memory development?
106690: 06/08/17: Re: Problems about the synthesis(XST)
106692: 06/08/17: Re: FFT on an FPGA
106693: 06/08/17: Re: Open-source JTAG software?
106704: 06/08/17: Re: EDK vs. ISE for image processing
106727: 06/08/17: Re: EDK vs. ISE for image processing
107102: 06/08/24: Re: Why isn't there a thermal diode on large FPGAs?
107208: 06/08/25: Re: UltraController II + SystemAce
107209: 06/08/25: Re: Virtex 4 TEMAC and MII questions
107232: 06/08/25: Re: UltraController II + SystemAce
107381: 06/08/27: Re: UltraController II + SystemAce
107515: 06/08/29: Re: Location of Virtex4 ASCII pinout tables
107746: 06/08/31: Re: MPMC2 : npi issues
108038: 06/09/04: Re: gpio help...
108545: 06/09/12: EDK8.2: bidirectional signals when top-level is ISE
108867: 06/09/18: Re: MPMC2 : npi issues #2
108868: 06/09/18: Re: A strange problem of Chipscope
108920: 06/09/19: Re: A strange problem of Chipscope
109174: 06/09/21: Re: DCM multiplier and EDK design
109428: 06/09/26: Re: Newbee question - how to upgrade to Xilinx ISE/EDK 8.2 from 8.1
109433: 06/09/26: Re: Newbee question - how to upgrade to Xilinx ISE/EDK 8.2 from 8.1
109662: 06/10/02: Re: Net names from EDK => ISE
110855: 06/10/24: Re: DDR SDRAM access with MPMC2, Databus Width
110864: 06/10/24: Can I unstantiate IBERT core in a V4FX design?
110916: 06/10/25: Re: DDR SDRAM access with MPMC2, Databus Width
110993: 06/10/26: Chipscope and debugger through the same JTAG port
111002: 06/10/26: Re: DDR SDRAM access with MPMC2, Databus Width
111155: 06/10/30: Re: Chipscope and debugger through the same JTAG port
111165: 06/10/30: Re: Chipscope and debugger through the same JTAG port
111600: 06/11/06: Re: surprised output of Xilinx Virtex-4
112002: 06/11/14: Aurora IP core vs. RocketIO wizard
112259: 06/11/18: Re: EDK 8.2 Block RAM error
112286: 06/11/19: Re: EDK 8.2 Block RAM error
112333: 06/11/20: Re: DDR_VDHL_models
112403: 06/11/21: Re: EDK 8.2 Block RAM error
112428: 06/11/21: Re: EDK 8.2 Block RAM error
112473: 06/11/22: Re: EDK 8.2 Block RAM error
112758: 06/11/28: Re: EDK 8.2 Block RAM error
112764: 06/11/28: Re: EDK 8.2 Block RAM error
112799: 06/11/29: Re: EDK 8.2 Block RAM error
112897: 06/11/30: Re: EDK 8.2 Block RAM error
112941: 06/12/01: Aurora simplex channel problems
113067: 06/12/05: Re: Xilinx MPMC2 "External Ports" question
113265: 06/12/09: Re: Xilinx MPMC2 "External Ports" question
113335: 06/12/11: Re: Xilinx MPMC2 "External Ports" question
113343: 06/12/11: Re: Aurora v2.5
113344: 06/12/11: Re: linking two fpga boards
113490: 06/12/14: Re: How to get ISE to create a _bd.bmm file for BRAM initialization
113695: 06/12/19: Slightly OT: Need a USB-to-LPT adapter for Xilinx Parallel IV Cable
113705: 06/12/19: Re: Slightly OT: Need a USB-to-LPT adapter for Xilinx Parallel IV Cable
113734: 06/12/20: Re: Slightly OT: Need a USB-to-LPT adapter for Xilinx Parallel IV Cable
114456: 07/01/16: Re: RocketIO, MGT documentation. Does MGT clcok have to be 50% duty cycle?
114770: 07/01/24: Re: system generator from Xilinx
114807: 07/01/24: Re: system generator from Xilinx
116245: 07/03/05: EDK 9.1 when?
116252: 07/03/05: Re: Multiple devices within one ISE project
116255: 07/03/05: Re: EDK 9.1 when?
116300: 07/03/06: Re: help read a pixel for picture
116357: 07/03/07: Re: Routing problem of DCM
116474: 07/03/09: Re: How to get ISE to create a _bd.bmm file for BRAM initialization
116698: 07/03/15: Re: Xilinx Xplorer misfunction
116703: 07/03/15: Re: ChipScope problem: "Waiting for core to be armed".
116705: 07/03/15: Re: Programming XCF from MicroBlaze over JTAG???
116706: 07/03/15: Re: ChipScope problem: "Waiting for core to be armed".
116709: 07/03/15: Re: ChipScope problem: "Waiting for core to be armed".
116721: 07/03/16: Re: Programming XCF from MicroBlaze over JTAG???
116742: 07/03/16: Re: Programming XCF from MicroBlaze over JTAG???
116772: 07/03/17: Re: ChipScope problem: "Waiting for core to be armed".
116841: 07/03/19: Re: Programming XCF from MicroBlaze over JTAG???
116995: 07/03/21: Re: Why is Xilinx's WebPACK so inferior?
117000: 07/03/21: Re: Off topic: what is the purpoe of XST?
117070: 07/03/22: Re: Off topic: what is the purpoe of XST?
117075: 07/03/22: Re: Off topic: what is the purpoe of XST?
117081: 07/03/22: Re: Off topic: what is the purpoe of XST?
117090: 07/03/22: Re: Xilinx Virtex-4 Embedded Ethernet Wrapper IP Core - HELP with UCF
117100: 07/03/23: Re: URGENT HELP NEEDED: LVDS
117139: 07/03/23: Re: Custom IP ports to be used as GPIOs
118285: 07/04/22: Symbol names in the Design Hierarchy Window of the Xilinx Floorplanner
118295: 07/04/23: Re: Symbol names in the Design Hierarchy Window of the Xilinx Floorplanner
118315: 07/04/23: Re: Problem with real data type
118985: 07/05/08: Re: SelectMap or serial: How does the PROM know?
119110: 07/05/11: Re: how to choose the perfect fpga support
119249: 07/05/15: LF VHDL to FSM bubble diagram translator
119254: 07/05/15: Re: LF VHDL to FSM bubble diagram translator
119301: 07/05/16: Re: how to delay a signal in virtex FPGA
119924: 07/05/29: ISE/EDK Kubuntu linux installation issues
120036: 07/05/31: Re: ISE/EDK Kubuntu linux installation issues
120089: 07/06/01: Re: ISE/EDK Kubuntu linux installation issues
120141: 07/06/01: Re: ISE/EDK Kubuntu linux installation issues
120144: 07/06/01: Re: ISE/EDK Kubuntu linux installation issues
120147: 07/06/01: Re: ISE/EDK Kubuntu linux installation issues
120149: 07/06/01: Re: ISE/EDK Kubuntu linux installation issues
120150: 07/06/01: Re: ISE/EDK Kubuntu linux installation issues
120182: 07/06/02: Re: LocalLink TEMAC Data Corruption
120193: 07/06/02: Re: LocalLink TEMAC Data Corruption
120259: 07/06/04: Re: MGT Clock
120348: 07/06/05: Re: Unable to connect to PowerPC target. Invalid Processor Version No 0x00000000
120542: 07/06/09: Re: adaptive filter FPGA
120685: 07/06/13: Re: Recommendation for creating a DDR Sdram core for custom board and integrate in XPS
120720: 07/06/14: Re: Recommendation for creating a DDR Sdram core for custom board and integrate in XPS
120744: 07/06/15: Re: Recommendation for creating a DDR Sdram core for custom board and integrate in XPS
120827: 07/06/18: Re: V4FX60, hard temac, MPMC2 and SoDIMM
121028: 07/06/22: Has anyone seen a vxWorks driver for the Xilinx LL_TEMAC?
121233: 07/06/28: Re: EDK Custom IP
121243: 07/06/29: Re: A strange error during PAR process in EDK, could anyone in xilinx help me?
121244: 07/06/29: Re: A strange error during PAR process in EDK, could anyone in xilinx help me?
121389: 07/07/03: Re: Why PLL and not DCM for V5?
121394: 07/07/03: Re: Hobbyist trying to decide which device to start with...
121536: 07/07/06: Re: Multiple Core generator MAC FIR Filter 5.1 Cores
121540: 07/07/06: Re: Xilinx ISE, EDK and some ground roules in software development
121575: 07/07/08: Re: Multiple Core generator MAC FIR Filter 5.1 Cores
121747: 07/07/12: Re: highly-parallel highspeed connection between two FPGA boards
121827: 07/07/13: Re: highly-parallel highspeed connection between two FPGA boards
121868: 07/07/13: Re: What is the resistance of a big FPGA for VCCINT (unpowered)
122129: 07/07/19: Re: Can multiple Ferrite Beads be used to connect ...?
122145: 07/07/20: Re: Xilinx fpgas...
122155: 07/07/20: Re: Running Virtex5 GTP at lower data rate
122194: 07/07/23: Re: xilinx multichannel fir alignment
122243: 07/07/24: Re: hard_temac : mdio conflict
122255: 07/07/24: Re: hard_temac : mdio conflict
122404: 07/07/26: Re: Timing simulation
122524: 07/07/30: Question on using RLOC_RANGE
122533: 07/07/30: Re: Question on using RLOC_RANGE
122536: 07/07/30: Re: Question on using RLOC_RANGE
122681: 07/08/02: Re: Best CPU platform(s) for FPGA synthesis
122687: 07/08/03: Re: Best CPU platform(s) for FPGA synthesis
122695: 07/08/03: Re: Best CPU platform(s) for FPGA synthesis
123120: 07/08/16: Re: MGT Link
123396: 07/08/27: Re: bidirectional pin help
123520: 07/08/29: Re: bidirectional pin help
123524: 07/08/29: Re: Strange behaviour of a design
123532: 07/08/29: Re: bidirectional pin help
123537: 07/08/29: Re: bidirectional pin help
123550: 07/08/29: Re: bidirectional pin help
123551: 07/08/29: Re: bidirectional pin help
123635: 07/08/31: Re: Is it possible to make bit files generated by Xilinx ISE readable?
123888: 07/09/06: Re: EDK9.1 linux registration fails (vista ok)
123896: 07/09/06: Problem locking a DCM driven by FX output of another DCM
123897: 07/09/06: Re: Problem locking a DCM driven by FX output of another DCM
123899: 07/09/06: Re: Problem locking a DCM driven by FX output of another DCM
123902: 07/09/06: Re: Problem locking a DCM driven by FX output of another DCM
123906: 07/09/06: Re: Problem locking a DCM driven by FX output of another DCM
123907: 07/09/06: Re: Problem locking a DCM driven by FX output of another DCM
123911: 07/09/06: Re: Problem locking a DCM driven by FX output of another DCM
123946: 07/09/07: Re: Problem locking a DCM driven by FX output of another DCM
123953: 07/09/07: Re: Problem locking a DCM driven by FX output of another DCM
124142: 07/09/12: Re: FPGA Archives
124493: 07/09/24: Re: Configuring Impact on any version of linux
124495: 07/09/24: Re: [ANN] FPGAOptim - Do you know where your slices are going...?
125017: 07/10/15: Re: FPGA quiz: what can be wrong
125030: 07/10/15: Re: FPGA quiz: what can be wrong
125122: 07/10/16: Re: FPGA quiz: what can be wrong
125155: 07/10/16: Re: FPGA quiz: what can be wrong
125182: 07/10/17: Re: FPGA quiz: what can be wrong
125345: 07/10/22: Re: ISE or EDK?
125390: 07/10/24: Re: MGT
125405: 07/10/24: Re: MPMC2 NPI Help!
125435: 07/10/25: Re: MGT
125436: 07/10/25: Re: MGT
125501: 07/10/26: Re: MPMC2 NPI Help!
125670: 07/10/31: Re: Is it possible to debug a vhdl design over jtag?
125718: 07/11/01: Re: can i use dual edge or two clocks?
125867: 07/11/07: Re: did i miss edk 9.2
126521: 07/11/26: Re: xilinx spartan 3 + 16 adc
126543: 07/11/27: Re: xilinx spartan 3 + 16 adc
127504: 07/12/30: Re: JTAG chain detects Xilinx FPGA XCV150 instead of XC2S150...
128764: 08/02/06: Re: BPSK CORDIC tracking
129002: 08/02/12: Redundant Ethernet connection
129007: 08/02/12: Re: Redundant Ethernet connection
129011: 08/02/12: Re: Newbie looking for guidance
129321: 08/02/20: V4FX: LVCMOS25 vs LVCMOS33 output buffer
129342: 08/02/21: Re: V4FX: LVCMOS25 vs LVCMOS33 output buffer
129571: 08/02/27: Re: Why must a V4 be configured within 10 minutes of power up?
129602: 08/02/28: Re: Why must a V4 be configured within 10 minutes of power up?
129651: 08/03/02: Re: FPGA's be afraid, very afraid, of my wife!
129652: 08/03/02: Re: HELP > Face/Edge detection on FPGA
129653: 08/03/02: Re: DSP Ip Core
129717: 08/03/03: Re: clock distribution accross boards
129749: 08/03/04: Re: clock distribution accross boards
129817: 08/03/06: Re: Anyone to open "FPGA museum" ? Here is first item :)
129818: 08/03/06: Re: Anyone to open "FPGA museum" ? Here is first item :)
129876: 08/03/07: Danger of having JTAG TAP controller always enabled in Xilinx parts
129879: 08/03/07: Re: Danger of having JTAG TAP controller always enabled in Xilinx parts
129882: 08/03/07: Re: Danger of having JTAG TAP controller always enabled in Xilinx parts
130029: 08/03/13: Re: Almost offtopic about HDL optimizing.
130188: 08/03/17: Re: Xilinx Webcase Workflow
130500: 08/03/25: Re: Timing constraints in ucf
130531: 08/03/26: VHDL document generation utilities
130550: 08/03/26: Re: Places to visit in Amsterdam and Brussells
130552: 08/03/27: Re: Places to visit in Amsterdam and Brussells
130555: 08/03/27: Re: Places to visit in Amsterdam and Brussells
130625: 08/03/28: Can't read external Flash in a V4 based PPC system through gdb
130634: 08/03/28: Re: Having trouble building an old Xilinx Spartan3 FPGA project I did on ISE 8.2i and EDK8.2 for microblaze. Also have ISE9.2i installed.
130635: 08/03/28: Re: Having trouble building an old Xilinx Spartan3 FPGA project I did on ISE 8.2i and EDK8.2 for microblaze. Also have ISE9.2i installed.
130802: 08/04/02: Re: Simple (?) timing constraint for output pins
130865: 08/04/03: Re: Protecting design from being downloaded on other (similar) FPGA devices
130902: 08/04/04: Re: Xilinx FPGA + SMPS
130954: 08/04/06: Re: Protecting design from being downloaded on other (similar) FPGA devices
131484: 08/04/22: Re: DCM configuration in Virtex-4 FPGA
131538: 08/04/24: Re: DCM configuration in Virtex-4 FPGA
131586: 08/04/25: Virtex-4 inrush power-on current
131674: 08/04/28: Re: Virtex-4 power-on current
131705: 08/04/29: Re: Virtex-4 power-on current
131713: 08/04/29: Re: understanding xilinx silicon revisions (does ES come before CES4, etc.)
131738: 08/04/30: Re: Virtex4 DCM doesn't work unless freezing cold
131767: 08/05/01: Re: Chirp generator / CORDIC algo ?
131781: 08/05/01: Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
131806: 08/05/02: Re: xilinx remote platform flash program
131809: 08/05/02: Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
131834: 08/05/02: Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
131862: 08/05/05: Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
131889: 08/05/06: Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058)
131927: 08/05/07: Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058) RESOLVED
131950: 08/05/08: Re: Argh! Need help debugging Xilinx .xsvf Player (XAPP058) RESOLVED
132072: 08/05/12: Re: How to input an analog signal to FPGA board for processing?
132460: 08/05/28: Re: XILINX core generator question
132933: 08/06/10: Trouble programming V4FX40
132937: 08/06/10: Re: Trouble programming V4FX40
132938: 08/06/10: Re: Trouble programming V4FX40
132942: 08/06/10: Re: Trouble programming V4FX40
132944: 08/06/10: Re: Trouble programming V4FX40
132952: 08/06/11: Re: Trouble programming V4FX40
132960: 08/06/11: Re: Trouble programming V4FX40
132969: 08/06/11: Re: Trouble programming V4FX40
132970: 08/06/11: Re: Trouble programming V4FX40
132976: 08/06/11: Re: Trouble programming V4FX40
133561: 08/07/03: Effect of reheating and reballing on reliability of Xilinx chips
133568: 08/07/03: Re: FiFo Help Needed
133582: 08/07/04: Re: FiFo Help Needed
133590: 08/07/04: Re: Single ended interface at 70Mhz for FPGAs
133595: 08/07/04: Xilinx ISE speed files compatibility
133615: 08/07/06: Re:V4FX20 upgrade to FX40 problem (was: Xilinx ISE speed files compatibilit)
133643: 08/07/08: Re: Re:V4FX20 upgrade to FX40 problem (was: Xilinx ISE speed files compatibilit)
134340: 08/08/06: Re: cpu,fpga, clock, dac, initialize sequence
134694: 08/08/26: Re: Xilinx Virtex 4 Newbie
134741: 08/08/28: Re: Mass storage device on ML403 board
134981: 08/09/09: Re: IEEE 1394 interface for FPGA??
135012: 08/09/10: Re: IDELAYCTRL Locking problem with ISE10.1i
135018: 08/09/10: Re: IDELAYCTRL Locking problem with ISE10.1i
135113: 08/09/16: Re: Two JTAG Parallel IV Cable in a single PC.
135132: 08/09/17: Re: Two JTAG Parallel IV Cable in a single PC.
135217: 08/09/22: Re: Peter says Good Bye
135270: 08/09/23: Re: Ethernet MDI termination
135291: 08/09/24: Re: Ethernet MDI termination
135297: 08/09/24: Re: Ethernet MDI termination
135329: 08/09/26: Re: Having problems with using flash in EDK
135530: 08/10/06: Re: ISE Question - FPGA Program.jpg (0/1)
135987: 08/10/25: Re: how to program virtex 4?
136065: 08/10/29: Re: PLBv4.6 with more than 16 slaves
136083: 08/10/30: Re: Possibility of Driving FPGA clock from an other FPGA ?
136103: 08/10/31: Re: PLBv4.6 with more than 16 slaves
136405: 08/11/14: Re: MAC PHY Configuration
136406: 08/11/14: Re: platform cable usb II problem
136995: 08/12/17: Advanced google group search doesn't work?
137010: 08/12/18: Re: Advanced google group search doesn't work?
137189: 08/12/31: Re: Xilinx QUIZ 2008
138868: 09/03/12: Hidden debug print in ISE ( XIL_PROJNAV_FLOW_DEBUG_LEVEL)
139479: 09/03/31: XST removes duplicate logic no matter what
139482: 09/03/31: Re: XST removes duplicate logic no matter what
139483: 09/03/31: Re: XST removes duplicate logic no matter what
139568: 09/04/03: Xilinx AREA_GROUP constraint and relative placement
139573: 09/04/04: Re: Chipscope problem
139579: 09/04/05: Re: Chipscope problem
139586: 09/04/05: Re: Chipscope problem
139595: 09/04/06: Re: Chipscope problem
139620: 09/04/07: V4 DSP48 Clock to out from P register to P output timing
139632: 09/04/07: Re: V4 DSP48 Clock to out from P register to P output timing
139636: 09/04/07: Re: Chipscope problem
139659: 09/04/08: Re: Chipscope problem
139990: 09/04/22: Differences in PAR results when running standalone vs. from ISE
140036: 09/04/24: Re: How to put area routing constraints in a xilinx flow
140080: 09/04/27: Re: How to put area routing constraints in a xilinx flow
140101: 09/04/28: ISE11.1 environment variables mess
140128: 09/04/29: Re: a basics question: using input pins, pullup, short to ground vs driven signal.
140150: 09/04/30: Re: a basics question: using input pins, pullup, short to ground vs driven signal.
140156: 09/04/30: Re: Xilinx ground pin
140160: 09/04/30: ISE/EDK/SDK 11.1 licensing
140168: 09/05/01: Re: offset out
140170: 09/05/01: Re: ISE/EDK/SDK 11.1 licensing
140171: 09/05/01: Re: ISE/EDK/SDK 11.1 licensing
140174: 09/05/01: Re: ISE/EDK/SDK 11.1 licensing
140179: 09/05/01: Re: offset out
140185: 09/05/02: Re: ISE/EDK/SDK 11.1 licensing
140204: 09/05/03: Re: High-speed signals crossing a split-ground
140214: 09/05/04: Re: High-speed signals crossing a split-ground
140219: 09/05/04: Re: High-speed signals crossing a split-ground
140224: 09/05/04: Re: FIFO that latches data asynchronic manner
140241: 09/05/05: Re: High-speed signals crossing a split-ground
140248: 09/05/05: Re: Xilinx XPS_INTC and XPS_UARTLITE interrupt issues
140251: 09/05/05: MPPR weirdness in ISE8.2.03
140283: 09/05/07: Re: Xilinx XPS_INTC and XPS_UARTLITE interrupt issues
140669: 09/05/21: Re: No integer interpolation ...
140673: 09/05/21: Re: No integer interpolation ...
140705: 09/05/22: Re: No integer interpolation ...
140731: 09/05/22: Re: No integer interpolation ...
140755: 09/05/25: Re: Architecture of FPGA
140798: 09/05/26: Re: Architecture of FPGA
140845: 09/05/27: Re: URGENT help with a CPLD and LCD display chip SED1278F
140855: 09/05/27: Re: phase locking a slow (2Mhz) signal.
140888: 09/05/28: Re: phase locking a slow (2Mhz) signal.
140904: 09/05/29: Re: I don't like xilinx (again)
141032: 09/06/02: Re: Xilinx GbE performance
141044: 09/06/03: Re: Xilinx ISE doesn't recognize a signal added in Xilinx Platform Studio
141047: 09/06/03: Re: Has anyone tried to install a Xilinx floating license? The documentation (UG631 (v 11.1.0) April 27, 2009) says that the required
141068: 09/06/04: Re: Xilinx ISE doesn't recognize a signal added in Xilinx Platform Studio
141073: 09/06/04: Re: MPPR weirdness in ISE8.2.03 (Solution)
141091: 09/06/04: Re: Has anyone tried to install a Xilinx floating license? The documentation (UG631 (v 11.1.0) April 27, 2009) says that the required
141184: 09/06/10: Re: Use XMD to configure more than one board
141187: 09/06/10: Re: Use XMD to configure more than one board
141198: 09/06/11: Re: Safe margin in FPGA static timing analysis
141318: 09/06/17: Re: 5.0V and 3.3V PCI interfacing with Altera Cyclone III
141682: 09/07/03: Re: Active-HDL simulator recompile... or not recompiling
141690: 09/07/03: Re: How to keep documentation of control and status registers and VHDL code in sync
141691: 09/07/03: Re: FPGA / CPLD Group on LinkedIn -- Networking Group
141697: 09/07/03: Re: FPGA / CPLD Group on LinkedIn -- Networking Group
141724: 09/07/04: Re: FPGA / CPLD Group on LinkedIn -- Networking Group
141860: 09/07/14: Re: Generating a negated clock
141871: 09/07/14: Re: Generating a negated clock
141888: 09/07/15: Re: parallel processing
141893: 09/07/15: Re: parallel processing
141931: 09/07/17: Re: Generating a negated clock
141936: 09/07/17: MPMC4.03 DDR1 question
142010: 09/07/21: Re: MPMC4.03 DDR1 question
142146: 09/07/26: Re: mpmc kills plb bus on v4fx20
142147: 09/07/26: Re: tri-state port in edk
142257: 09/07/30: Re: ISE error messages
142273: 09/07/31: Re: ERROR:Pack:679 - Unable to obey design constraints
142374: 09/08/07: Re: Peter Alfke
142375: 09/08/07: Re: What would be the best method to terminate GTX_CLK signal in Gigabit Ethernet PHY
142376: 09/08/07: Re: What would be the best method to terminate GTX_CLK signal in Gigabit Ethernet PHY
142417: 09/08/10: Re: What would be the best method to terminate GTX_CLK signal in Gigabit Ethernet PHY
142482: 09/08/12: V5 GTX and V4 MGT interoperability
142500: 09/08/13: Re: V5 GTX and V4 MGT interoperability
142515: 09/08/13: Re: V5 GTX and V4 MGT interoperability
142562: 09/08/17: Re: Virtex 4 package code
142564: 09/08/17: Re: Virtex 4 package code
143690: 09/10/21: Re: External IO Port without using Xilinx's GPIO IP
144009: 09/11/06: Microblaze performance in V6
144011: 09/11/06: Re: Microblaze performance in V6
144046: 09/11/09: Re: Microblaze performance in V6
144078: 09/11/10: Re: order
144223: 09/11/20: EDK11 under 64-bit OS
144225: 09/11/20: Re: EDK11 under 64-bit OS
144248: 09/11/23: Re: EDK11 under 64-bit OS
144249: 09/11/23: Re: LDPC FADING
144251: 09/11/23: Re: EDK11 under 64-bit OS
144259: 09/11/23: Re: PCI card unrecognized
144268: 09/11/23: Re: PCI card unrecognized
144373: 09/12/02: Re: XST 11.2 Takes a lot of memory and never completes the synthesis
144448: 09/12/08: Re: Problems reading from PHY registers using plb_temac and hard_temac, using Xilinx EDK 9.1i
144449: 09/12/08: Re: Possible memory leak in xst in ISE 11.3
144476: 09/12/09: Re: Problems reading from PHY registers using plb_temac and hard_temac, using Xilinx EDK 9.1i
148104: 10/06/21: Re: Xilinx BULLSHITIX-8, when?
148384: 10/07/16: Re: Dumb VHDL Question -- Type Conversion
148653: 10/08/12: Re: XC5VTX240T-2FF1759I4177
148827: 10/08/30: Re: FPGA DAC Interface
149280: 10/10/13: ISE/EDK12.2 Translate fails with "NgdBuild:467 - output pad net 'Ddr_Ck_N_0_OBUF' has an illegal buffer" and similar messages.
149292: 10/10/14: Re: ISE/EDK12.2 Translate fails with "NgdBuild:467 - output pad net 'Ddr_Ck_N_0_OBUF' has an illegal buffer" and similar messages.
149296: 10/10/14: How to disable EDK instantiated IOBs?
149298: 10/10/14: Re: ISE/EDK12.2 Translate fails with "NgdBuild:467 - output pad net 'Ddr_Ck_N_0_OBUF' has an illegal buffer" and similar messages.
149299: 10/10/14: Re: ISE/EDK12.2 Translate fails with "NgdBuild:467 - output pad net 'Ddr_Ck_N_0_OBUF' has an illegal buffer" and similar messages.
149300: 10/10/14: Re: ISE/EDK12.2 Translate fails with "NgdBuild:467 - output pad net 'Ddr_Ck_N_0_OBUF' has an illegal buffer" and similar messages.
149310: 10/10/15: Re: ISE/EDK12.2 Translate fails with "NgdBuild:467 - output pad net 'Ddr_Ck_N_0_OBUF' has an illegal buffer" and similar messages.
149311: 10/10/15: Re: How to disable EDK instantiated IOBs?
149315: 10/10/15: Old LOC constraint stuck somewhere
149320: 10/10/15: Re: Old LOC constraint stuck somewhere
149373: 10/10/19: Re: Old LOC constraint stuck somewhere
149386: 10/10/20: Re: Old LOC constraint stuck somewhere
149387: 10/10/20: Xilinx: How to save all invalid constraints to a file?
149395: 10/10/21: Re: Xilinx: How to save all invalid constraints to a file?
149396: 10/10/21: Analysis of the same path by two different tools in ISE yields different results.
149398: 10/10/21: Re: Analysis of the same path by two different tools in ISE yields different results.
149405: 10/10/22: Re: Analysis of the same path by two different tools in ISE yields different results.
149411: 10/10/22: Re: Analysis of the same path by two different tools in ISE yields different results.
149414: 10/10/22: Re: Analysis of the same path by two different tools in ISE yields different results.
149435: 10/10/25: Re: Virtex 5 GTP Clocking
149458: 10/10/26: Re: Xilinx: How to save all invalid constraints to a file?
149460: 10/10/26: Re: Xilinx: How to save all invalid constraints to a file?
149469: 10/10/27: Re: using FPGA editor to add a new output pin
149489: 10/10/29: Re: Can't migrate from 11.5 to 12.3
150163: 10/12/22: Re: Xilinx support makes me want to scream
mm:
41837: 02/04/08: where can i find service pack 7 for xilinx foundation 3.1i??
42099: 02/04/15: why does my counter pause while its enable signal is still active?
42213: 02/04/18: how comes the clk suddenly pause?
42338: 02/04/21: Re: how comes the clk suddenly pause?
<mma@mack.rt66.com>:
360: 94/10/28: Re: High Bus Drive (24mA) FPGAs/CPLDs?
MMartin950:
2731: 96/01/31: Re: GAL programming for hobby use...Is there no hope?
mmcshmi11:
144256: 09/11/23: Initializing color bars on CH7301
144269: 09/11/23: Re: Initializing color bars on CH7301
144540: 09/12/13: Re: Initializing color bars on CH7301
144542: 09/12/14: XUPV5-LX110T, DDR2, and EDK (10.1 to be precise)
<mmeraliuk@yahoo.co.uk>:
27629: 00/11/30: Routing constraints & A2.1i
mmihai:
102496: 06/05/16: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
114368: 07/01/12: Re: xc3sprog
114377: 07/01/13: Re: xc3sprog
115221: 07/02/03: Re: ISE 9.1 SAY YOURS OPINION
115335: 07/02/07: Re: xc3sprog
115568: 07/02/13: Re: Typical clock frequencies of FPGA designs
117264: 07/03/27: Re: Open-source CPU-core for standard-cell ASIC?
117983: 07/04/15: [xilinx] par [placer] consistency
118040: 07/04/16: Re: par [placer] consistency
118045: 07/04/16: Re: par [placer] consistency
119081: 07/05/11: xc3sprog and spartan 3e/3a
123321: 07/08/23: Re: comparison with embedded processor
123333: 07/08/23: Re: comparison with embedded processor
128443: 08/01/25: Re: microblaze question
128854: 08/02/07: Re: microblaze question
128865: 08/02/07: Re: impact bug or wrong interpretation of xsvf layout?
128894: 08/02/08: Re: impact bug or wrong interpretation of xsvf layout?
154349: 12/10/11: ise 32b or 64b?
154353: 12/10/12: Re: ise 32b or 64b?
154584: 12/11/29: V6 BUFR -> BUFG clocking structure (hold issue?)
154587: 12/11/29: Re: V6 BUFR -> BUFG clocking structure (hold issue?)
154601: 12/11/30: Re: V6 BUFR -> BUFG clocking structure (hold issue?)
154602: 12/11/30: Re: V6 BUFR -> BUFG clocking structure (hold issue?)
154618: 12/12/02: Re: V6 BUFR -> BUFG clocking structure (hold issue?)
154619: 12/12/02: Re: V6 BUFR -> BUFG clocking structure (hold issue?)
154627: 12/12/03: Re: V6 BUFR -> BUFG clocking structure (hold issue?)
154628: 12/12/03: Re: V6 BUFR -> BUFG clocking structure (hold issue?)
154629: 12/12/03: Re: V6 BUFR -> BUFG clocking structure (hold issue?)
154632: 12/12/03: Re: V6 BUFR -> BUFG clocking structure (hold issue?)
mmiodzio:
96054: 06/01/29: 32 bit processor ? Open IP-Core
MMJ:
125663: 07/10/31: Capability of a FPGA device.
125696: 07/11/01: Re: Capability of a FPGA device.
125738: 07/11/02: Re: Capability of a FPGA device.
135625: 08/10/10: Re: Lattice vs Altera (Mico32 / NIOS)....or?
135696: 08/10/13: Re: Lattice vs Altera (Mico32 / NIOS)....or?
135706: 08/10/13: Re: Lattice vs Altera (Mico32 / NIOS)....or?
135710: 08/10/13: Re: Lattice vs Altera (Mico32 / NIOS)....or?
<mmkhajah@gmail.com>:
105969: 06/08/03: Xilinx System Generator crashes repeatedly
105987: 06/08/04: Re: Xilinx System Generator crashes repeatedly
106552: 06/08/15: Bit-Serial Design with Xilinx System Generator
<mmkumar@gmail.com>:
79258: 05/02/16: PLB
79371: 05/02/17: Re: PLB
80979: 05/03/15: PLB_EDK_Simulation
81630: 05/03/29: ISE
mmmniple:
145608: 10/02/15: Searching rod carlson
<mmobcl@hotmail.com>:
16810: 99/06/10: Free Sex Links!! 9209
mmock:
71930: 04/08/03: Need StateCAD 4.11!
72008: 04/08/05: Re: Need StateCAD 4.11!
72027: 04/08/05: Re: Need StateCAD 4.11!
72091: 04/08/08: Re: Need StateCAD 4.11!
72101: 04/08/08: Re: ABEL support for legacy chips
74383: 04/10/09: Re: Need StateCAD 4.11!
<mmoeller@delphi.com>:
551: 94/12/30: Re: PCI with Xilinx XC3100 series
556: 95/01/03: Re: Xilinx and Protel for Windows?
557: 95/01/03: Re: Xchecker programming limits
567: 95/01/05: Re: Xilinx and Protel for Windows?
585: 95/01/11: Re: Backannotating Xilinx pinouts to ViewLogic symbols
628: 95/01/22: Re: ACTEL and EXEMPLAR
MN:
153164: 11/12/21: Equivalence between "XtremeDSP48 slice" and "slices of programmable logic"
153166: 11/12/22: Re: Equivalence between "XtremeDSP48 slice" and "slices of
<mnemo5@163.com>:
97475: 06/02/23: Kalman filters
97567: 06/02/23: Re: Kalman filters
97585: 06/02/24: Re: Kalman filters
mnentwig:
155567: 13/07/20: Verilog: "don't care" in
155573: 13/07/23: Re: Verilog:
156167: 14/01/06: register naming
156168: 14/01/06: register naming
156171: 14/01/06: Re: register naming
156174: 14/01/06: Re: register naming
156191: 14/01/14: Verilog, combinational logic and modules?
156194: 14/01/14: Re: Verilog, combinational logic and modules?
156263: 14/01/29: Programming a Digilent S6 Carrier (Spartan 6
156265: 14/01/29: Re: Programming a Digilent S6 Carrier (Spartan 6
156269: 14/02/01: Verilog (Xilinx): Virtual tristate or muxes?
156276: 14/02/04: Re: Verilog (Xilinx): Virtual tristate or muxes?
156277: 14/02/04: Re: Programming a Digilent S6 Carrier (Spartan 6
156278: 14/02/04: Re: Verilog (Xilinx): Virtual tristate or muxes?
156288: 14/02/06: pipelined algorithm, flow control
156291: 14/02/07: Re: To Xilinx: Regarding the download manager
156292: 14/02/08: Re: pipelined algorithm, flow control
156383: 14/03/24: debug access to memory (JTAG?)
156563: 14/04/30: Lattice MICO32 won't generate?
156564: 14/05/01: Re: Lattice MICO32 won't generate?
156575: 14/05/03: Re: Free alternatives to Xilinx iMPACT?
156578: 14/05/04: Re: Free alternatives to Xilinx iMPACT?
156580: 14/05/04: Re: The USB FPGA?
156621: 14/05/14: Re: Undriven outputs of a module in Quartus II Synthesis
156631: 14/05/16: Re: need coding
156642: 14/05/19: Re: How to reduce
156668: 14/05/31: shift register (invariable size) FIFO = ?
156670: 14/06/01: Re: shift register (invariable size) FIFO = ?
156675: 14/06/02: Re: Zynq devices, boards and suppliers
156722: 14/06/08: Re: HELP: Edge triggering of mode register, Verilog
156726: 14/06/08: Re: HELP: Edge triggering of mode register, Verilog
156787: 14/06/25: Re: A free VHDL simulator
156840: 14/07/08: Re: Using FPGA as dual ported ram
156841: 14/07/08: Re: Using FPGA as dual ported ram
156889: 14/07/22: Re: Generating a desired synthesizable binary pulse train on FPGA using VHDL
156890: 14/07/22: Re: Generating a desired synthesizable binary pulse train on FPGA using VHDL
156900: 14/07/24: Re: Know any good public FPGA projects to contribute to?
156901: 14/07/25: Re: Know any good public FPGA projects to contribute to?
156902: 14/07/25: Re: Know any good public FPGA projects to contribute to?
156903: 14/07/25: Re: Generating a desired synthesizable binary pulse train on FPGA using VHDL
156905: 14/07/26: Re: Generating a desired synthesizable binary pulse train on FPGA using VHDL
156908: 14/07/26: Re: Generating a desired synthesizable binary pulse train on FPGA using VHDL
156912: 14/07/27: Re: Generating a desired synthesizable binary pulse train on FPGA using VHDL
156918: 14/07/28: Re: Primitive debuggable UART interface to a Nios within a multi-Nios system
156923: 14/07/28: Re: Primitive debuggable UART interface to a Nios within a multi-Nios system
156927: 14/07/29: Re: Generating a desired synthesizable binary pulse train on FPGA using VHDL
156936: 14/07/30: Re: Generating a desired synthesizable binary pulse train on FPGA using VHDL
156947: 14/08/01: Re: floating point synthesis on Xilinx FPGAs using ISE Webpack
156950: 14/08/02: Re: Could you give me an example on synthesis techniques?
156967: 14/08/08: Re: Basic question: sequence of execution within FPGAs
157000: 14/08/18: ZPU-based SoC for Numato Saturn board with DRAM
157004: 14/08/23: xc3sprog "instruction capture is 0x3f" (solved)
157005: 14/08/23: Re: xc3sprog
157018: 14/08/29: Re: wrong waveforms in vivado waveform viewer
157019: 14/08/29: xc3sprog: SPI flash access for Spartan 6 LX 25 TFQ256 (Xess Xula 2)
157049: 14/09/13: Re: Free VHDL or Verilog Simulator
157059: 14/09/18: Re: NetCPU or DotNetCPU DB200 anyone?
157081: 14/09/24: Re: Some newbe questions.
157102: 14/10/12: Re: [RFC] METATOR: A look into processor synthesis - What's next?
157107: 14/10/13: Re: Need ideas for FYP
157108: 14/10/13: Re: Need ideas for FYP
157111: 14/10/13: Re: Need ideas for FYP
157144: 14/10/18: Re: Fast and slow clocks
157145: 14/10/18: Re: Fast and slow clocks
157179: 14/10/28: MIPI M-PHY and FPGA?
157211: 14/11/04: Re: practical experience with GPL IP core in commercial product
157260: 14/11/09: Re: Program IO 1.2V
157261: 14/11/09: Re: Program IO 1.2V
157285: 14/11/17: Re: disadvantages of inferring latches
157319: 14/11/21: Re: disadvantages of inferring latches
157325: 14/11/22: Re: disadvantages of inferring latches
157357: 14/11/27: Re: Low-end FPGA mezzanine standard
157367: 14/11/29: Re: Low-end FPGA mezzanine standard
157416: 14/12/03: Re: Which Altera to buy?
157562: 14/12/16: Re: VHDL Synchronization- two stage FF on all inputs?
157582: 14/12/19: Re: MIPI M-PHY and FPGA?
157585: 14/12/19: Re: MIPI M-PHY and FPGA?
157588: 14/12/22: Re: How to automatically allocate multiple bit fields into constant length registers?
157592: 14/12/22: Re: How to automatically allocate multiple bit fields into constant length registers?
157594: 14/12/22: Re: How to automatically allocate multiple bit fields into constant length registers?
157595: 14/12/22: Re: How to automatically allocate multiple bit fields into constant length registers?
157597: 14/12/23: Re: How to automatically allocate multiple bit fields into constant length registers?
157694: 15/02/02: Re: Xilinx XST and initializing block RAMs
157701: 15/02/07: Re: Topics for Projects on FPGA+Computer Archtecture
157762: 15/03/05: Re: DDS
157765: 15/03/06: Re: DDS
157767: 15/03/08: Re: DDS
157778: 15/03/14: Re: DDS
mng:
127235: 07/12/14: Re: FPGA Board design basics
127421: 07/12/21: Re: Routing Vccint on four-layer PCB
129439: 08/02/24: Re: Xilinx DCM for frequency synthesis -- newbie question
129480: 08/02/25: Re: Xilinx DCM for frequency synthesis -- newbie question
130403: 08/03/22: Re: Spartan 3E intefacing for dummies
130604: 08/03/27: Re: Simulink(Matlab)/FPGA serial communication
131494: 08/04/23: Re: Turning off the DLL to run DDR2 at very low frequency
133509: 08/07/01: Re: How do I program an fpga once it has been designed and layout is
133573: 08/07/04: Re: How do I program an fpga once it has been designed and layout is
134241: 08/07/31: Re: Is there a totally command-line driven way to use Xilinx Webpack?
136181: 08/11/04: Re: RS-232 Bus controller design in VHDL
137809: 09/01/29: Re: What software do you use for PCB with FPGA ?
138459: 09/02/23: Re: Spartan 3E Slave Serial problems
138553: 09/02/26: Re: Send data from FPGA to PC via USB
138958: 09/03/16: Re: Send data from FPGA to PC via USB
139274: 09/03/24: Re: Looking for a low-cost development kit
139510: 09/04/01: Re: Digital design references for timing, etc.
139858: 09/04/16: Re: How to constraint the In&Outputs of an ADC in XILINX ISE 9.2
139877: 09/04/17: Re: How to constraint the In&Outputs of an ADC in XILINX ISE 9.2
140159: 09/04/30: Re: FPGA simulator for face recognition
140402: 09/05/12: Re: XCF32P programming via JTAG
140403: 09/05/12: Re: XCF32P programming via JTAG
140446: 09/05/13: Re: XCF32P programming via JTAG
141854: 09/07/13: Re: About configuring FPGAs
142383: 09/08/07: Re: iCore7 vs Core2 simulation & FPGA tool performance?
144855: 10/01/07: Re: university platform cable
MNiegl:
108560: 06/09/13: Clock Source in Low Latency Mode RocketIO
118479: 07/04/27: Problem cascading 2 DCMs
118483: 07/04/27: Re: Problem cascading 2 DCMs
118485: 07/04/27: Re: Problem cascading 2 DCMs
118504: 07/04/28: Re: Problem cascading 2 DCMs
118525: 07/04/29: Re: Problem cascading 2 DCMs
118568: 07/04/30: Re: Problem cascading 2 DCMs
118578: 07/04/30: Re: Problem cascading 2 DCMs
118639: 07/05/01: Re: Problem cascading 2 DCMs
118644: 07/05/01: Re: Problem cascading 2 DCMs
118693: 07/05/02: Re: Problem cascading 2 DCMs
119122: 07/05/12: Re: how to choose the perfect fpga support
119581: 07/05/23: Re: how 33-bit BRAM?
122993: 07/08/13: Design Behavior affected by use of Chipscope
123062: 07/08/15: Re: Design Behavior affected by use of Chipscope
MNQ:
60757: 03/09/22: Re: fpga +cpu + wireless
68252: 04/03/31: Where to source CPLD XC2C256-7TQFP144I
Moadl:
34485: 01/08/27: FPGA : USB in an FPGA, has anyone done it before?
Moazzam:
130875: 08/04/04: Re: "Number of BSCANs: 2 out of 1 200%"
131163: 08/04/13: Re: Spartan3E startup problems
131465: 08/04/21: Re: How to instantiate macro in verilog
131548: 08/04/24: Re: How to instantiate macro in verilog
132222: 08/05/18: Re: System configuration for Xilinx ISE 10.1 - Virtex 5 LX110t or
132430: 08/05/27: Re: Downloading external data file to FPGA
132851: 08/06/09: Re: TI DSP + Virtex-5 using EMIF interface
134509: 08/08/14: Re: Microblaze Projects
136020: 08/10/28: Possibility of Driving FPGA clock from an other FPGA ?
136153: 08/11/04: Re: How to move project files from ISE 7.1 to ISE 10.1
139058: 09/03/19: Exporting AccelDSP generated Fixed Point C-Code to MicroSoft Visual
139280: 09/03/24: Re: Exporting AccelDSP generated Fixed Point C-Code to MicroSoft
139311: 09/03/25: Re: Dynamic reconfiguration in Spartan 3
141127: 09/06/07: Re: Power Estimation for Dynamic Reconfiguration
142372: 09/08/06: Re: Peter Alfke
142702: 09/08/26: Re: error from my own hard macro by FPGA edit
143651: 09/10/20: Re: Handwritten recognition using FPGA
Modellpilot:
132910: 08/06/10: Digital VSB (Vestigial Side Band) Modulator for Analog TV
Modelsim/Synplify/VCS/LDV/FPGA Express/Xilinx/Quar:
37211: 01/12/03: Re: Synplify 7 and Xilinx 4.1 Pair
modelsimmin:
49005: 02/10/29: Re: Modelsim help
modimo:
146490: 10/03/20: Re: Update init data in dualport BRAM without re-run anything?
146783: 10/03/28: Re: XST optimization
moe:
62308: 03/10/25: Modeling hardware in Matlab/Simulink (delay, etc.)?
63081: 03/11/14: Reading back SRAM content via JTAG?
MoellerInc:
273: 94/10/10: Re: Any documentation for Xilinx XNF file format?
286: 94/10/12: Re: Xilinx configuration
305: 94/10/17: Re: SRAM and antifuse for interconnects
328: 94/10/20: Re: XC3000 series FPGA with XAbel
352: 94/10/27: Re: I/O pin currents on Xilinx FPGAs?
mofo:
20: 94/07/29: Re: definition of FPGA
23: 94/07/29: Re: PPR vs NeoCAD (vs. APR)
mogogo:
99153: 06/03/20: Microblaze to My IP-Core connection
moh@speakhard.net:
63101: 03/11/14: Re: Reading back SRAM content via JTAG?
Mohamad Mohamad:
1829: 95/09/07: beginner need help with verilog language
Mohamed:
136154: 08/11/04: GRFPU SDF and simulation VHDL
Mohamed Bakr:
115917: 07/02/25: Bluetooth standard in software defined radio
Mohamed Elnamaky:
72282: 04/08/12: What is the multicycle path? (LeonardoSpectrum - Time Analysis)
72305: 04/08/13: is it possible to time optimize combinational logic ..LeonardoSpectrum.
72818: 04/09/03: Unisim Library
72870: 04/09/06: Re: Unisim Library
72875: 04/09/06: A Typical Design Cycle
77692: 05/01/14: Hard and soft Macro
82457: 05/04/13: MIMO Channel Estimation WCDMA
Mohamed Ismail:
40096: 02/02/27: Re: Power estimation for Virtex-2 device
Mohamed Shiha:
49620: 02/11/18: XC5204 bitstream
<mohamed.benabdeladhim@gmail.com>:
156312: 14/02/16: micro blaze
Mohammad Abbas:
121035: 07/06/23: |!|!|!|!|!|!|!Sparten 3E : !!!USB 2.0 Driver in the
Mohammed A khader:
80971: 05/03/15: Re: Calling netlist module in a design
82947: 05/04/20: Ambigous operator '&'
82951: 05/04/20: Re: Ambigous operator '&'
82954: 05/04/20: Unconstrained ports for synthesis
83461: 05/04/30: Re: Case statement illusions ?
Mohammed khader:
75635: 04/11/11: Internal architecture of lut
77454: 05/01/07: Re: VHDL Test Bench + Help
77455: 05/01/07: Re: Synthesis of more FSMs in one file using DC
Mohammed A Khader:
82481: 05/04/13: LUT in fpga
82958: 05/04/20: Re: Unconstrained ports for synthesis
83231: 05/04/26: Rom Inference
83288: 05/04/27: Re: Rom Inference
83289: 05/04/27: Re: Rom Inference
83301: 05/04/27: Synplify warning CL209
83572: 05/05/03: Negative hold time from Quartus
Mohammed Billoo:
161696: 20/05/05: Passing digitized data to design
161698: 20/05/06: Re: Passing digitized data to design
161701: 20/05/06: Re: Passing digitized data to design
Mohammed Elbadri:
89732: 05/09/23: Re: opb ip master/slave...arbiter problems
Mohammed Hamed:
53926: 03/03/27: Can input rate change internal programming ?
53927: 03/03/27: How can I fix module inputs
53993: 03/03/30: Re: How can I fix module inputs
Mohammed Ishaq:
27122: 00/11/11: Re: CRC, LFSR and scramblers
27135: 00/11/12: Re: CRC, LFSR and scramblers
Mohammed Khalid:
491: 94/12/05: need xnf files for Partitioning93 benchmark circuits
863: 95/03/16: Re: How to partitions the design by ppr ?
977: 95/04/06: Re: pinout changes
1913: 95/09/19: present status of Field Programmable MCMs?
3185: 96/04/21: looking for xnf-to-blif conversion tool
3186: 96/04/21: looking for 'synthesizable' VHDL/Verilog ASIC models
mohan:
63567: 03/11/25: Re: using xilkernel
63568: 03/11/25: Re: running from external memory (microblaze)
63615: 03/11/26: Re: running from external memory (microblaze)
63817: 03/12/04: Re: process table for XMK
63846: 03/12/05: Re: process table for XMK
63912: 03/12/08: Re: process table for XMK
63936: 03/12/09: Re: process table for XMK
64005: 03/12/11: Re: stopping XMK (at microblaze)
64011: 03/12/11: Re: programming with sockets on Xilinx Virtex2Pro
64561: 04/01/07: Re: Generate the first interrupt for MB XMK
100932: 06/04/21: XILINX : IBIS model creation
101498: 06/05/02: Re: help me friend
101500: 06/05/02: Re: LED Driver
118458: 07/04/26: Can i programme non-xilinx fpga through xilinx impact tool & by using xilinx parrellel four cable?
119285: 07/05/16: Unable to scan JTAG chain
119341: 07/05/16: Re: Unable to scan JTAG chain
119343: 07/05/16: can JTAG port of CPLD gets damaged?
119415: 07/05/18: Re: can JTAG port of CPLD gets damaged?
mohankumar:
27473: 00/11/23: Re: Spartan and XC4000 configuration
Mohap:
36523: 01/11/10: 8031 on board Xilinx XC4000XL
37567: 01/12/15: annoying problem
<mohit.tiwari@gmail.com>:
94377: 06/01/10: Software- to- PCI design communication.
mohnkhan:
143705: 09/10/22: Re: Done pin won't go high
Mohsin Riaz:
10779: 98/06/18: Problems with XILINX 1.4
12075: 98/09/27: Faster 32_bit integer multiplier required !!
12107: 98/09/29: Re: strange problem of 4028XL
13274: 98/11/23: Re: VHDL project
13702: 98/12/18: Problems with timing report using Synopsys FPGA compiler!!!
13783: 98/12/26: Problems with FPGA compiler of Synopsys ver1998.O2
moi:
54386: 03/04/09: Quicklogic QL4090
Moikel:
124860: 07/10/08: Neural Coprocessor with Xilinx EDK
131332: 08/04/19: Synthesis Comparison
moindsp:
151890: 11/06/01: FFT using logic gates only
151928: 11/06/07: Re: FFT using logic gates only
Mois?s:
63245: 03/11/18: Problems Configurating MicroBlaze into RC200 board
63323: 03/11/19: Re: Problems Configurating MicroBlaze into RC200 board
64571: 04/01/07: iMPACT error : Done did not go high.
Moises:
91854: 05/11/15: Multiple instantiation in SystemC
Moises Cambra:
56985: 03/06/20: Multiple clock generation and maybe FIFO
MOK:
mok:
25022: 00/08/24: Virtex partial reconfiguration feature (?)
25444: 00/09/12: Re: xilinx web site access
29049: 01/02/03: HELP!!!!
30722: 01/04/26: VHDL coding question.
45643: 02/07/30: Looking for a Virtex-II based video board...
mokhoo:
149052: 10/09/27: Spartan 3 DCM problem
Moky:
47594: 02/09/30: Large Multiplexer
Mole:
63120: 03/11/15: Newbie Question about Block Ram & Xilinx ECS
63122: 03/11/15: Re: Newbie Question about Block Ram & Xilinx ECS
=·MoLe=:
53268: 03/03/09: Motion Control IP Cores , anyone do them ?
53295: 03/03/10: Re: Motion Control IP Cores , anyone do them ?
molecularelectronics@googlegroups.com:
111708: 06/11/08: can you please help me VHDL coding on CSMA and DCF based project of wireless LAN
moleo:
90748: 05/10/20: Re: how to connect my IP-Core to Microblaze in EDK and ISE with IPIF
molka:
152700: 11/10/04: macro
153300: 12/01/29: =?ISO-8859-1?Q?Post=2Dsynth=E8se_simulation?=
momo:
48421: 02/10/17: How assingment of IOE by Quratus Ver2.1
Monib Khan:
58905: 03/08/04: Multiple clock generations
Monica:
87617: 05/07/27: QuartusII 4.2 problem
87822: 05/08/02: AVNET Xilinx Spartan3 board, example problem
87836: 05/08/02: Re: AVNET Xilinx Spartan3 board, example problem
87841: 05/08/02: Xilinx libraries missing,j83a/c modulator IP core
87876: 05/08/03: How to import EDIF netlist into ISE webpack 7.1
87881: 05/08/03: Re: How to import EDIF netlist into ISE webpack 7.1
88100: 05/08/09: MPEG-2 links please
88142: 05/08/10: Re: MPEG-2 links please
88143: 05/08/10: Re: FPGA Programming using Block Design Files or Graphic Design Files
88362: 05/08/16: Altera NIOSII IDE problem???
90069: 05/10/04: Altera NIOS PIO interrupt problem
92342: 05/11/28: Altera Pin not used in Quartus project but drives logic
93060: 05/12/13: xilinx constraint
93065: 05/12/13: Re: xilinx constraint
93069: 05/12/13: Re: xilinx constraint
93133: 05/12/14: Re: xilinx constraint
93984: 06/01/04: DCM spartan 3 variable frequency divider
93989: 06/01/04: Re: DCM spartan 3 variable frequency divider
93995: 06/01/04: Re: DCM spartan 3 variable frequency divider
94008: 06/01/04: Re: DCM spartan 3 variable frequency divider
94012: 06/01/04: Re: DCM spartan 3 variable frequency divider
94011: 06/01/04: Re: ISE Evaluation version
94009: 06/01/04: Re: VHDL FF Question
Monica Schnitger:
14039: 99/01/08: Field Applications Engineers: ASIC/Field Programable Gate Arrays
14116: 99/01/14: We need a Mentor Expert!
Monnerie:
6875: 97/07/04: Re: Altera archiving
Monsieur Le Maire:
42283: 02/04/19: FPGA books and tutorials ....
montaro:
149863: 10/11/29: Re: open all blocked sites free now without any effort
Monte Dalrymple:
21023: 00/03/03: Re: SpartanXL route and place
75734: 04/11/13: Re: Obsolete processors resurected in FPGAs
75747: 04/11/14: Re: Obsolete processors resurected in FPGAs
75748: 04/11/14: Re: Obsolete processors resurected in FPGAs
75752: 04/11/14: Re: Obsolete processors resurected in FPGAs
75754: 04/11/14: Re: Obsolete processors resurected in FPGAs
75759: 04/11/14: Re: Obsolete processors resurected in FPGAs
93512: 05/12/23: Re: RTL for Z8000 series CPU?
93523: 05/12/23: Re: RTL for Z8000 series CPU?
93562: 05/12/24: Re: RTL for Z8000 series CPU?
Monty H. Brekke:
516: 94/12/16: Re: Any Way to Download a XNF to FPGA?
monurlu:
142144: 09/07/26: tri-state port in edk
142150: 09/07/27: Re: tri-state port in edk
143253: 09/09/28: Xilinx xps interrupt controller
<monurlu@gmail.com>:
138578: 09/02/28: xilinx-microblaze interrupt controller
139753: 09/04/11: Microblaze GPIO API functions
139763: 09/04/12: Re: Microblaze GPIO API functions
141116: 09/06/06: Microblaze and external block memory
moo:
98882: 06/03/17: where can I find the simulation model of the sram, ISSI61LV25616?
98968: 06/03/18: Re: where can I find the simulation model of the sram, ISSI61LV25616?
MooCow:
46579: 02/09/04: Re: Hardware Code Morphing?
52297: 03/02/06: Re: clock ditribution tree
moogyd:
145006: 10/01/19: Xilinx ISE 8.2 Issue: Pin Name N1, N2...
145280: 10/02/04: Re: Xilinx ISE 8.2 Issue: Pin Name N1, N2...
<moogyd@yahoo.co.uk>:
96411: 06/02/03: Re: How will synthesizers handle these statements?
99698: 06/03/28: Specifying top level generics with XST 7.1
109754: 06/10/05: Generate 16MHz from 75MHz using DCM
109850: 06/10/06: Re: Generate 16MHz from 75MHz using DCM
114569: 07/01/19: Series DCM's and total Lock Time
114644: 07/01/21: Re: Series DCM's and total Lock Time
115022: 07/01/29: Xilinx Timing Constraints and failures
118797: 07/05/03: Select pullup, pulldown or none via embedded S/W
118853: 07/05/04: Re: Select pullup, pulldown or none via embedded S/W
118871: 07/05/04: Re: Select pullup, pulldown or none via embedded S/W
119652: 07/05/24: Xilinx 8.2 : Multippass P&R
119668: 07/05/24: Re: Xilinx 8.2 : Multippass P&R
119669: 07/05/24: Re: Xilinx 8.2 : Multippass P&R
119959: 07/05/30: Re: Xilinx 8.2 : Multippass P&R
119960: 07/05/30: Re: Xilinx 8.2 : Multippass P&R
119972: 07/05/30: Re: Xilinx 8.2 : Multippass P&R
122855: 07/08/08: Specifying LVDS I/O's in Xilinx FPGA's
122955: 07/08/12: Re: Specifying LVDS I/O's in Xilinx FPGA's
123021: 07/08/14: Xilinx Spartan FPGA : Strange Errors
123022: 07/08/14: Xilinx Spartan FPGA : Strange Errors
123033: 07/08/14: Re: Xilinx Spartan FPGA : Strange Errors
123172: 07/08/17: Xilinx Constraints Question
123203: 07/08/19: Re: Xilinx Constraints Question
129585: 08/02/28: DCM Simulation : Input Clock Cycle Jitter
130556: 08/03/27: Re: VHDL document generation utilities
154040: 12/07/19: Xilinx UCF: Adding "Virtual Grounds"
154045: 12/07/19: Re: Xilinx UCF: Adding "Virtual Grounds"
Mook Johnson:
80750: 05/03/11: low speed FIR filter in FPGA
80752: 05/03/11: Re: low speed FIR filter in FPGA
moon:
142599: 09/08/19: Multiple Interrupt handling in XPS 8.2i
<moonbirch@163.com>:
137302: 09/01/07: interrupt cannot return
137305: 09/01/08: Re: interrupt cannot return
moonlight721:
144471: 09/12/09: EDK problem
144485: 09/12/09: Re: EDK problem
<moonygals@yahoo.com>:
62611: 03/11/03: synplify Pro 7.3.1
mooo:
139893: 09/04/18: Why is XST optimizing away my registers and how do I stop it?
139895: 09/04/18: Re: Why is XST optimizing away my registers and how do I stop it?
MOOSA IRSHAD:
156415: 14/04/02: ip address of fpga
MooseFET:
134782: 08/08/29: Re: Future architectures [was Re: Intel details future Larrabee ...]
142204: 09/07/28: Re: cool chart
147807: 10/05/25: Re: Software bloat (Larkin was right)
moox:
69169: 04/04/28: Re: VHDL / Verilog circuits work in 1-V still correct?
<mop13851@mail.telepac.pt>:
8052: 97/11/12: $$FREE TO START - $000s PER MONTH $$
mopra:
138965: 09/03/17: How to load an image onto system ace compact flash embedded on virtex
138967: 09/03/17: Re: How to load an image onto system ace compact flash embedded on
139211: 09/03/23: Using Floating Point Unit in Virtex 2 pro
139327: 09/03/26: Sysace_fread syntax probleme
139334: 09/03/26: Accessing data from flash memory
Moran:
154392: 12/10/22: Re: Actel Designer: how to compile VHDL top & EDIF submodule together?
more:
81135: 05/03/18: About the usb access in board ML310!
81495: 05/03/25: Thanks a lot!
81496: 05/03/25: About the socket in ML310
81497: 05/03/25: About the ethernet access on the ML310 board!
81798: 05/04/01: About Xilnet and LWIP library access on board ML310!
Morgan:
113109: 06/12/06: help with Xilinx LVDS syntax
Morgan Colmer:
19616: 00/01/04: Re: CIC Filters in FPGA
Morgan Kaufmann Publishers:
33058: 01/07/16: New Book: Readings in Hardware/Software Co-design
Morgan Smail:
2139: 95/10/19: Re: one-hot encoding for fsm's
Moritz Schmid:
136078: 08/10/30: Re: Xilinx RapidIO 5.1
mormegil231:
155897: 13/10/14: Vivado HLS -> Vivado IDE -> Xilinx SDK toolflow integration issue
155905: 13/10/15: Re: Vivado HLS -> Vivado IDE -> Xilinx SDK toolflow integration issue
155958: 13/10/25: Implementation ingnoring custom IP made with HLS
morp:
142624: 09/08/22: Ideas needed for implementing SerDes on low-cost fpga (like
142628: 09/08/22: Need support for LVDS to Tmds translation on altera device
morpheous:
151726: 11/05/11: Re: Xilinx MicroBlaze 4.00.a source codes released by Xilinx !?
morpheus:
79797: 05/02/24: Synchronous design
80032: 05/02/28: modelling Bi-directional address/data multiplexed bus
80056: 05/02/28: Re: modelling Bi-directional address/data multiplexed bus
80124: 05/03/01: Help with XST warnings (2)
80188: 05/03/02: Re: Help with XST warnings (2)
80509: 05/03/07: Hierarchical Synchronous Design
80799: 05/03/11: Re: Hierarchical Synchronous Design
80947: 05/03/14: Post-Trasnlation Simulation using ModelSim in XST
81094: 05/03/17: Bit-Rounding Algorithm
81245: 05/03/19: Re: Bit-Rounding Algorithm
81843: 05/04/01: DPSK Receiver in Vertex-4
82138: 05/04/07: Re: DPSK Receiver in Vertex-4
82334: 05/04/11: DC component removal in FPGA
82376: 05/04/11: Re: DC component removal in FPGA
82431: 05/04/12: Re: DC component removal in FPGA
82433: 05/04/12: Re: DC component removal in FPGA
82444: 05/04/12: Re: DC component removal in FPGA
83367: 05/04/28: Formal verification tool?
86238: 05/06/23: Re: How about signed adder?
86239: 05/06/23: Re: DC Offset removal in FPGA
87812: 05/08/01: Conversion of Schematic to Verilog/VHDL
90226: 05/10/06: Re: Altera Gate Delay Simulation
91166: 05/10/31: Quartus II Simulation
91202: 05/11/01: Re: Quartus II Simulation
94794: 06/01/17: Re: Migrating Project from Xilinx ISE 4.1 to 8.1?
94793: 06/01/17: Re: Getting Gate Counts from Quartus
96102: 06/01/30: TI Technical screening phone interview
97895: 06/03/01: Pulse Shape in a functional simulation
97906: 06/03/01: Re: Pulse Shape in a functional simulation
97909: 06/03/01: Re: Pulse Shape in a functional simulation
100630: 06/04/13: ARM Emulator
107827: 06/09/01: Re: easics - crc equations
108455: 06/09/11: Re: Functional and Post-Synthesis Simulation
115390: 07/02/08: Digital AM/FM Receiver
116203: 07/03/04: Re: Digital AM/FM Receiver
117030: 07/03/21: Digital AM/FM Receiver - Systemic Question
117031: 07/03/21: Re: Looking for resources on timing analysis
117390: 07/03/29: Complex Baseband
117395: 07/03/29: Re: Complex Baseband
117398: 07/03/29: Re: Complex Baseband
117414: 07/03/30: Re: Complex Baseband
117424: 07/03/30: Re: Complex Baseband
117585: 07/04/04: Digital Receiver chip suggestion
117620: 07/04/04: Re: Digital Receiver chip suggestion
117621: 07/04/04: Re: Gray code in asynchronous FIFO design
117634: 07/04/05: Re: Gray code in asynchronous FIFO design
117726: 07/04/08: Re: Digital Receiver chip suggestion
morphiend:
120170: 07/06/02: Re: How to execute application code out of external memory using EDK?
120171: 07/06/02: LocalLink TEMAC Data Corruption
120172: 07/06/02: Xilinx OPB External Memory Controller
120183: 07/06/02: Re: Xilinx OPB External Memory Controller
120196: 07/06/03: Re: LocalLink TEMAC Data Corruption
120266: 07/06/04: Re: Xilinx OPB External Memory Controller
120724: 07/06/14: Re: problems with FSL and Microblaze
120766: 07/06/15: V4FX and Microblaze 5.00.c hard multiplier not working
120770: 07/06/15: V4FX60, hard temac, MPMC2 and SoDIMM
121171: 07/06/27: Re: regarding the montavista linux preview kit
121367: 07/07/03: Re: Microblaze and software interrupts?
121419: 07/07/03: Re: A strange error during PAR process in EDK, could anyone in xilinx help me?
122337: 07/07/25: Re: EDK Microblaze project without OPB?
122372: 07/07/26: Re: Why is Xilinx XPS 8.2i so slow?
122374: 07/07/26: Re: XMD crashes on EDK 9.1i
122808: 07/08/07: Re: TEMAC Performance Issues with Virtex 4FX
123347: 07/08/24: Re: xilinx usb cable question
124816: 07/10/05: Re: Best way to export XPS project to ISE?
124907: 07/10/10: Re: Timing Constraint Question
125002: 07/10/15: Re: Xilinx OCM memory use limitations ?
125126: 07/10/16: Re: FPGA quiz2: spartan3A return Virtex JTAGID. Also prizes for quiz1 and quiz2
125134: 07/10/16: Re: FPGA quiz2: spartan3A return Virtex JTAGID. Also prizes for quiz1 and quiz2
125191: 07/10/17: Re: IPs in MHS file
125614: 07/10/30: Re: Is it possible to check how cache memories are mapped to FPGA block rams?
125656: 07/10/31: Re: Is it possible to debug a vhdl design over jtag?
125739: 07/11/02: Re: code hang after loading through gdb
125790: 07/11/05: Re: Linux (not uClinux) on Microblaze 7.0 w/MMU?
125798: 07/11/05: Re: FPGA I/O Selection in UCF
125832: 07/11/06: Re: ERROR:MDT - transparent bus interface connector
128898: 08/02/08: Re: Timing Constraint not met
128995: 08/02/12: Virtex4FX over-voltage
129003: 08/02/12: Re: Virtex4FX over-voltage
129016: 08/02/12: Re: Timing Constraint not met
129199: 08/02/18: V4FX100 PowerPC PLB issues (and EDK 9.2)
129205: 08/02/18: Re: V4FX100 PowerPC PLB issues (and EDK 9.2)
129239: 08/02/19: Re: Which Linux Distro to use for Xilinx tools
129427: 08/02/23: Re: Xilinx DCM for frequency synthesis -- newbie question
129831: 08/03/06: Re: I could run my program at DDR Sdram.
130222: 08/03/18: Re: SGMII, xps_ll_temac and MDIO / MCD
130440: 08/03/24: Re: using mpmc ddr2 controller with an other processor
130581: 08/03/27: Re: Xilinx ISE 9.2i out of memory
130720: 08/03/31: Re: increase memory of microblaze
130721: 08/03/31: Re: After reset, the PC register of PPC is not back to 0Xfffffffc
130978: 08/04/07: Re: Xilinx xilfatfs and systemACE speed issue
131203: 08/04/15: Re: HiTech Global Eval boards?
131850: 08/05/04: Re: FPGA Processor for Signal Processing ?
132233: 08/05/19: Re: System configuration for Xilinx ISE 10.1 - Virtex 5 LX110t or
132235: 08/05/19: Re: XILINX Ethernet MAC (URGENT...)
132236: 08/05/19: Re: Problem with Scheduler in Xilkernel.
132310: 08/05/21: Re: XILINX Ethernet MAC (URGENT...)
132368: 08/05/23: Re: XILINX Ethernet MAC (URGENT...)
132406: 08/05/26: Re: EDK 10.1 Map Error
132440: 08/05/27: Re: EDK 10.1 Map Error
132441: 08/05/27: Re: impact / encrypted bitstream
132611: 08/06/03: Re: Interrupt handler for Xilinx EMAC- URGENT!!
132790: 08/06/06: Re: FPGA to FLASH and back?
133051: 08/06/16: Re: Will Modelsim XE 6.3c (Win32) run in Linux/WINE?
134007: 08/07/21: Linux on V4FX100
134301: 08/08/05: Re: RGMII with Xilinx ML405 Board
134570: 08/08/19: Re: More work, less posts
134595: 08/08/20: Re: ML403 PPC and ISE tools: timestamp and <sysace_stdio.h>
134795: 08/09/01: Re: ED 9.2 too new cygwin error
134803: 08/09/01: Re: ED 9.2 too new cygwin error
135179: 08/09/19: Re: What software do use big organizations for Logic Synthesis from
135544: 08/10/07: Re: Looking for an FPGA board with large memory and high speed
135597: 08/10/09: Re: Reading files from CF (microblaze 7 and plb)
135740: 08/10/14: Re: Microblaze and PowerPC405/440
138203: 09/02/09: Re: REWARD $$$ Xilinx USB Platform Cable problems
morppheu:
144874: 10/01/11: E1 clock problem...
Morppheu:
144873: 10/01/11: E1 clock problem with Spartan3e...
144885: 10/01/12: Re: E1 clock problem with Spartan3e...
145117: 10/01/28: Re: E1 clock problem with Spartan3e...
Morris Dovey:
56513: 03/06/07: Re: Logical analyzer via USB or printer port
56514: 03/06/07: Re: Logical analyzer via USB or printer port
56525: 03/06/07: Re: Logical analyzer via USB or printer port
Morris Ho:
68776: 04/04/17: Microblaze Sub-Module Adventure
68862: 04/04/20: Re: Microblaze Sub-Module Adventure
68990: 04/04/23: Re: Microblaze Sub-Module Adventure
Morris Jones:
2589: 96/01/09: Re: [q][Reverse Engineering Protection]
Morten L. Haugen:
11766: 98/09/08: Re: Assigning IOE on Altera's FLEX10k
Morten Leikvoll:
57143: 03/06/24: Xilinx par at max effort
57144: 03/06/24: Re: Programmable Delay (not clock driven)
57148: 03/06/24: Re: Transfer between clock domains at 350 MHz
57150: 03/06/24: Re: FPGA GPU (Spartan IIe 300K)
57163: 03/06/24: Re: FPGA GPU (Spartan IIe 300K)
57250: 03/06/26: Re: Low-power FPGA
57893: 03/07/09: cascaded DLL's in VirtexE, routing problems
57984: 03/07/11: From one clock domain to another
58021: 03/07/12: Re: From one clock domain to another
58118: 03/07/15: Re: CLKDLLE CLK2X180 Outpu doesn't work
61495: 03/10/06: Timing from 1x to 2x and back
61499: 03/10/06: Re: Digesting runs of ones or zeros "well"
61510: 03/10/06: Re: Timing from 1x to 2x and back
61681: 03/10/09: Placing FF's Relative to RAMB4s (xilinx)
62478: 03/10/30: comparison of FPGA tools?
62745: 03/11/06: Crossing/muxing clocks thru TBUF mux (w/DLL "stunts")
62855: 03/11/10: Unconstrained net to DLL's
62936: 03/11/11: Re: XILINX Foundation Series 3_1i Problem with installation...
63003: 03/11/12: Putting TNM on a FF inside vhdl
63005: 03/11/12: Re: Implementing a very fast counterin VirtexII
63478: 03/11/22: Re: 400 Mb/s ADC
65608: 04/02/03: Re: Xilinx Spartan3 Timing Problems - Whats about the chips
70738: 04/06/25: Large fast FIFO?
92398: 05/11/29: ISE 6.3 equivalent_register_removal off
92541: 05/12/01: Re: ISE 6.3 equivalent_register_removal off
93014: 05/12/12: Re: Adding "super-LUTs" to FPGA, good idea ?
93406: 05/12/21: 8 in clock mux
94251: 06/01/09: Re: Xilinx DCM
94252: 06/01/09: Re: Do you name your FPGA?
94141: 06/01/06: Spartan3 DFS jitter reduction
94272: 06/01/09: Easier initializing of blockram (spartan3)
94298: 06/01/09: Re: Easier initializing of blockram (spartan3)
94307: 06/01/09: Re: Easier initializing of blockram (spartan3)
99200: 06/03/21: Got the XST (ISE8.1) EQUIVALENT_REGISTER_REMOVAL blues
99202: 06/03/21: Re: Got the XST (ISE8.1) EQUIVALENT_REGISTER_REMOVAL blues
99283: 06/03/22: Going from CLK1X to CLK2X.. really safe?
100130: 06/04/04: How fast is YOUR ise8.1?
100131: 06/04/04: Re: How fast is YOUR ise8.1?
100138: 06/04/04: Re: How fast is YOUR ise8.1?
100916: 06/04/21: Editing Spartan3 DCM in FPGA(8.1.03) editor
100934: 06/04/21: Re: Editing Spartan3 DCM in FPGA(8.1.03) editor
102325: 06/05/15: Make a signal free for glitches?
102421: 06/05/16: Re: Make a signal free for glitches?
102422: 06/05/16: Re: Make a signal free for glitches?
102694: 06/05/19: Re: Make a signal free for glitches?
104110: 06/06/19: xst:What happened here?
104151: 06/06/20: Re: xst:What happened here?
104191: 06/06/21: xst can, but vcomp can't
104255: 06/06/22: Re: xst can, but vcomp can't
104586: 06/06/30: Missing ISE HTML online help (pdf sucks!)
110793: 06/10/23: Re: Spartan 3 Configuration Questions
118580: 07/04/30: ise9.1i regid not working on x64
119207: 07/05/15: reading IDCODE from parallel bus?
130052: 08/03/14: DDR3 speed, Altera vs Xilinx
130147: 08/03/17: Re: DDR3 speed, Altera vs Xilinx
130225: 08/03/18: Re: Altera vs Xilinx
130465: 08/03/25: Re: dual clock fifo
130715: 08/03/31: Re: ISE 10.1 - Initial experience
130879: 08/04/04: Re: Conterfeit parts guidance
143265: 09/09/29: Searching for cost effective PCI express x1 core..
143268: 09/09/29: Re: Searching for cost effective PCI express x1 core..
144039: 09/11/09: Re: Searching for cost effective PCI express x1 core..
144184: 09/11/18: Fast stratix3 JTAG programming?
144210: 09/11/20: Re: Fast stratix3 JTAG programming?
144443: 09/12/08: Re: Design a delay line from 10ns to 0.1s
145469: 10/02/11: Re: To get higher clock frequencies at output using propagation delays.
145494: 10/02/12: QDRII on StratixIII pinout strangeness
148334: 10/07/08: Re: xilinx leadtimes
148413: 10/07/20: Re: Xilinx License BS
148752: 10/08/19: Re: CE compliance testing
148753: 10/08/19: Altera blasters missing ESD protection
148770: 10/08/20: Re: CE compliance testing
149080: 10/09/29: Re: SDRAM for specific use - performance and timing questions
149115: 10/10/02: Re: FPGA design not working!
149127: 10/10/04: Re: FPGA design not working!
149155: 10/10/05: Re: Actel bought by Microsemi
149261: 10/10/12: Re: JTAG stops working!
149779: 10/11/24: Re: Spartan3 device with long availability
150224: 11/01/03: Re: Error in Clock Divider!
150230: 11/01/04: Re: Error in Clock Divider!
150258: 11/01/07: Re: Error in Clock Divider!
150261: 11/01/07: Re: Detecting cold reset on flash FPGA
150262: 11/01/07: Re: Detecting cold reset on flash FPGA
150266: 11/01/07: Re: Detecting cold reset on flash FPGA
150318: 11/01/10: Re: Error in Clock Divider!
150345: 11/01/11: Re: Error in Clock Divider!
150656: 11/02/01: Re: Can't program Spartan3A with JTAG
150668: 11/02/02: Re: Can't program Spartan3A with JTAG
150704: 11/02/04: Re: Trivia: Where are you on the HDL Map?
150774: 11/02/10: Re: Trivia: Where are you on the HDL Map?
150780: 11/02/10: Re: Trivia: Where are you on the HDL Map?
150829: 11/02/15: Re: Xilinx USB programming cable.
150841: 11/02/16: Re: Xilinx USB programming cable.
150906: 11/02/21: Re: Mathematical definition of an FPGA
150943: 11/02/24: Simulating mutiplication of 'X' with '0'
150945: 11/02/24: Re: Simulating mutiplication of 'X' with '0'
150946: 11/02/24: Re: Simulating mutiplication of 'X' with '0'
150963: 11/02/24: Re: Simulating mutiplication of 'X' with '0'
150966: 11/02/25: Re: Simulating mutiplication of 'X' with '0'
150973: 11/02/25: Re: Simulating mutiplication of 'X' with '0'
151002: 11/02/28: Re: Simulating mutiplication of 'X' with '0'
151118: 11/03/08: Re: Does anyone have current contact details for Jerry D. Harthcock?
151504: 11/04/15: Re: Altium Limited closing up shop - Altium Designer NOT discontinued
151508: 11/04/15: Oscilloscope recommendations Ghz range?
151531: 11/04/18: Re: Oscilloscope recommendations Ghz range?
151536: 11/04/18: Re: Oscilloscope recommendations Ghz range?
151542: 11/04/18: Re: Oscilloscope recommendations Ghz range?
151553: 11/04/19: Re: Oscilloscope recommendations Ghz range?
151960: 11/06/15: Re: What is the advantage of source-syncronization (in SDRAMs)?
152203: 11/07/20: Re: FPGA not getting programmed
152220: 11/07/22: Re: source synchronous DDR bus with non-continuous clock
152245: 11/07/26: Re: Question on PCI-express verssus Standard PCI performance
152406: 11/08/19: Re: Spartan6 PCB debugging: how badly do you have to screw up for JTAG to not shift?
152443: 11/08/23: vhdl:passing generic sized arrays to functions?
152445: 11/08/23: Re: vhdl:passing generic sized arrays to functions?
152448: 11/08/23: Re: vhdl:passing generic sized arrays to functions?
152589: 11/09/16: Re: LFSR in xilinx 13.2
152628: 11/09/19: Re: How to digitize the VGA output using FPGA?
152634: 11/09/19: Re: Xilinx Tin Whiskers ?
153065: 11/11/25: Re: XC7V2000T, the perfect Thanksgiving gift
153066: 11/11/25: Re: XC7V2000T, the perfect Thanksgiving gift
153106: 11/12/01: Re: Compatible Xilinx USB Cables: worth to bother?
153161: 11/12/19: High-bandwidth Digital Content (HDCP) keys with FPGA?
153229: 12/01/13: Re: balancing IIR filter (after adding extra registers)
153278: 12/01/25: slow edge on clk inputs
153282: 12/01/26: Re: slow edge on clk inputs
153387: 12/02/15: Re: Anybody here got a Xilinx ML605?
153388: 12/02/15: Re: Anybody here got a Xilinx ML605?
153414: 12/02/20: Re: problem with Global Clock pin and normal IO pin as Clock input
153421: 12/02/22: Re: gigabit ethernet problem
153423: 12/02/22: Re: gigabit ethernet problem
153425: 12/02/22: Re: gigabit ethernet problem
153509: 12/03/20: Re: Record type <-> std_logic_vector conversion - Python script
153511: 12/03/20: Re: Record type <-> std_logic_vector conversion - Python script
153544: 12/03/27: Re: FPGA communication with a PC (Windows)
153564: 12/03/28: Re: FPGA communication with a PC (Windows)
154047: 12/07/20: FPGA basic devtool options and prices?
154123: 12/08/15: "Decimals" word in binary space
154124: 12/08/15: Re: My Spartan3 video
154126: 12/08/15: Re: "Decimals" word in binary space
154132: 12/08/16: Re: "Decimals" word in binary space
154133: 12/08/16: Re: "Decimals" word in binary space
154138: 12/08/20: Re: "Decimals" word in binary space
154139: 12/08/20: Re: My Spartan3 video
154175: 12/08/28: fractional radix agnostic calculator tool?
154193: 12/09/03: Re: Delay in Verilog for Asics design which is synthesizable
154195: 12/09/03: Re: Delay in Verilog for Asics design which is synthesizable
154196: 12/09/03: Re: Delay in Verilog for Asics design which is synthesizable
154199: 12/09/07: Re: Verilog file operations
155117: 13/04/23: Re: FPGA for large HDMI switch
Morten Reistad:
145689: 10/02/18: Re: using an FPGA to emulate a vintage computer
Morteza:
45792: 02/08/05: Qn: Low Level Design
Morteza Saheb Zamani:
3292: 96/05/10: Xilinx Placement and Routing Tools
3379: 96/05/23: Xilinx Floorplanner
moshe moalem:
14763: 99/02/16: orcad
Moshe Zalcberg:
4318: 96/10/14: LPM standard support?
Moss Ben:
51955: 03/01/27: Carry Logic propagation delay
51970: 03/01/27: Re: Carry Logic propagation delay
51988: 03/01/28: Installing 2 versions of Xilinx software in the same machine
52415: 03/02/08: estimate area/speed effect
52416: 03/02/08: estimate the area/speed effect
52498: 03/02/11: estimation of area/speed
Mostafa Halas:
25458: 00/09/12: CPLD: Basic informations
25459: 00/09/12: Re: CPLD: Basic informations
Mostafa Kassem:
73337: 04/09/20: Re: Virtex-4 development boards
Mot:
40970: 02/03/19: DDS in an FPGA
41932: 02/04/11: How can I devide bit_vectors?
Moti:
76514: 04/12/05: Re: how to speed up my accumulator ??
76515: 04/12/05: Re: how to speed up my accumulator ??
76521: 04/12/05: Re: how to speed up my accumulator ??
76523: 04/12/05: Re: how to speed up my accumulator ??
76529: 04/12/05: Re: how to speed up my accumulator ??
76556: 04/12/06: Re: how to speed up my accumulator ??
76567: 04/12/06: Re: how to speed up my accumulator ??
76588: 04/12/06: Re: how to speed up my accumulator ??
76589: 04/12/06: Re: how to speed up my accumulator ??
76606: 04/12/07: Re: adding signals to chipscope pro debugging
76607: 04/12/07: Re: adding signals to chipscope pro debugging
77154: 04/12/26: recommendations for a FIFO..
77210: 04/12/30: Re: Multipliers implementation (xilinx)
77211: 04/12/30: Re: recommendations for a FIFO..
77212: 04/12/30: Re: PicoBlaze implementation
77786: 05/01/17: Creating a pyramid of shift registers
77826: 05/01/18: Re: Creating a pyramid of shift registers
77839: 05/01/18: Re: Creating a pyramid of shift registers
78065: 05/01/24: Re: imported ip
78066: 05/01/24: Re: imported ip
78121: 05/01/25: Re: bi-dimensional array
78125: 05/01/25: Re: imported ip
78202: 05/01/26: Re: Creating a pyramid of shift registers
78210: 05/01/26: looking for the opb_core_ssp0_ref
78222: 05/01/26: Re: looking for the opb_core_ssp0_ref
78274: 05/01/27: Re: looking for the opb_core_ssp0_ref
78408: 05/01/31: Re: Init of BRAMs with ISE flow.
78693: 05/02/06: Re: EDK+IPIF: Customizing wizard result
78699: 05/02/06: Debug module and bufg in Xilinx EDK
78738: 05/02/07: Re: warning messages,NgdBuild:454,DesignRules:331
78960: 05/02/10: Re: XMD/GBD problems
78963: 05/02/10: Re: XMD/GBD problems
79389: 05/02/18: Question about microblaze C complier
79460: 05/02/19: Re: Question about microblaze C complier
79588: 05/02/21: Re: BACK to FPGA
79768: 05/02/24: Re: How to synthesize the xilinx ip core?
80155: 05/03/02: Re: Error on launch the Simulator
80275: 05/03/03: Re: IBUFG as ? component
80291: 05/03/03: Re: IBUFG as ? component
80450: 05/03/06: Re: XST block ram init in include files
80454: 05/03/06: Re: State Machine Trouble
80643: 05/03/09: Re: RS232 VHDL-core
80871: 05/03/13: Re: Newb: FSM in no valid state?
80872: 05/03/13: Re: vhdl netlist synthesized
135487: 08/10/04: Video processing in FPGA
Moti Barkan:
9177: 98/02/27: Re: Correlation implementation...
Moti Cohen:
70985: 04/07/04: crc32 vhdl implementation (4 bit data)
70997: 04/07/05: Re: crc32 vhdl implementation (4 bit data)
71200: 04/07/12: Ethernet packet..
71251: 04/07/13: Re: Ethernet packet..
72207: 04/08/11: xilinx SW state machines enumeration
72253: 04/08/12: xilinx Synthesis report - please help..
74970: 04/10/22: Re: unstable fpga design
74997: 04/10/23: Re: unstable fpga design
75030: 04/10/25: Re: unstable fpga design
75044: 04/10/25: Re: VCXO Emulation
75093: 04/10/26: Re: ISE and Clocks
75184: 04/10/28: Re: unstable fpga design
74124: 04/10/04: Re: XST - undeterministic synthesis
74841: 04/10/20: unstable fpga design
75476: 04/11/07: Re: minimum module name length in 6.3i?
75782: 04/11/15: Electronica 2004 - munich - Altera ???
75824: 04/11/16: Re: Electronica 2004 - munich - Altera ???
76510: 04/12/05: how to speed up my accumulator ??
79685: 05/02/23: re:C compiler for Picoblaze
81879: 05/04/03: Re: IPIF Signals
81880: 05/04/03: Re: EDK:Question regarding opb_uart
82984: 05/04/21: CAM for FPGA ...
83003: 05/04/21: Re: CAM for FPGA ...
84580: 05/05/21: Re: How to make a 1.44MHz clock?
93831: 06/01/01: Microbalze program initialization ...
93846: 06/01/02: Re: Microbalze program initialization ...
113577: 06/12/17: Re: PowerPC_EDK to ISE
Moti Litochevski:
132678: 08/06/05: Re: UART master core
141174: 09/06/10: Re: IF board for fpga?
142543: 09/08/16: Re: Soft Processor IP core report
153661: 12/04/10: Re: CPU Design in Xilinx Spartan 3E
motiw:
119600: 07/05/23: Re: M-RAM allocation in Stratix EPS125B672C6
<motiwe@gmail.com>:
119316: 07/05/16: Re: DVI over fiber
MotM:
115931: 07/02/26: Xilinx platform cable USB API?
<mottoblatto@yahoo.com>:
93457: 05/12/22: Re: More beginner's verilog questions
93458: 05/12/22: Re: More beginner's verilog questions
93463: 05/12/22: Re: More beginner's verilog questions
motty:
90814: 05/10/21: Internal Loading in Spartan3
91665: 05/11/10: Signal timing problem
91669: 05/11/10: Re: Signal timing problem
91739: 05/11/11: Re: Signal timing problem
91989: 05/11/18: Xilinx routing details
93468: 05/12/22: Synplicity and the EDK
93653: 05/12/27: Using Synplicity to synthesize EDK user IP's
93713: 05/12/28: Re: Using Synplicity to synthesize EDK user IP's
93721: 05/12/28: Re: Using Synplicity to synthesize EDK user IP's
94082: 06/01/05: Synplify Pro batch mode
94131: 06/01/05: NGDBuild Error 604
94230: 06/01/08: Re: Asynch. signal
94169: 06/01/06: Re: Chipscope Pro
94229: 06/01/08: Synthesis and EDIF gurus.....
95618: 06/01/24: Re: Newbie: xilinx vs arm
96758: 06/02/09: Simulation of MicroBlaze embedded system
96787: 06/02/10: Re: Simulation of MicroBlaze embedded system
96799: 06/02/10: Re: Simulation of MicroBlaze embedded system
96937: 06/02/13: EDK Simulation
98224: 06/03/07: Re: Internal pull down on the FPGA.....
98226: 06/03/07: Re: Internal Signals in OPB EMC In XIlinx PLatform studio
98227: 06/03/07: Re: Simulating a ppc working with external memory
99997: 06/03/31: Re: Concatenate String in Verilog?
99998: 06/03/31: KEEP_HIERARCHY
100038: 06/04/01: Re: KEEP_HIERARCHY
100403: 06/04/07: Re: Help needed
100431: 06/04/08: Re: Help needed
100478: 06/04/10: Re: unused pins
100712: 06/04/16: DCM Question
100979: 06/04/22: Re: Microblaze & Linux tools. (repost)
101415: 06/04/30: OPB Clocking Question
101422: 06/04/30: Re: Microblaze GPIO (basic) question
101706: 06/05/04: OPB clocking question
101734: 06/05/05: Xilinx document timing diagrams?
102770: 06/05/19: Re: PLB clocking
103417: 06/06/01: Re: Using version control for Xilinx 8.1i ISE projects and source files
105341: 06/07/20: Re: tutorial searching
108123: 06/09/05: Serial I/O Question
108126: 06/09/05: Re: Serial I/O Question
108139: 06/09/05: Re: Serial I/O Question
108232: 06/09/06: BUFR in timing sim not working
108674: 06/09/14: Unwanted clock on output pin....
108701: 06/09/15: Re: Unwanted clock on output pin....
109363: 06/09/25: Translate fails in ISE 8.1
109366: 06/09/25: Re: Translate fails in ISE 8.1
109374: 06/09/25: Re: Translate fails in ISE 8.1
109707: 06/10/03: Input signal problem...
109733: 06/10/04: Re: Input signal problem...
111541: 06/11/05: Re: chipscope
111854: 06/11/11: Re: tri0 GSR = glbl.GSR;
111855: 06/11/11: EDK post 7.1 Opinions
111862: 06/11/11: Re: Xilinx Chipscope and EDK
113094: 06/12/06: EDK 8.2, MDM, and ChipScope....
113110: 06/12/06: Re: EDK 8.2, MDM, and ChipScope....
113114: 06/12/06: Re: EDK 8.2, MDM, and ChipScope....
113681: 06/12/19: Re: Frequency divider ?
113686: 06/12/19: Re: Frequency divider ?
113814: 06/12/22: Re: timing?
114266: 07/01/09: Is the FSL a good approach for this...?
114382: 07/01/13: IDELAY and whether pigs can fly...
114386: 07/01/13: Re: IDELAY and whether pigs can fly...
114419: 07/01/15: Re: IDELAY and whether pigs can fly...
114458: 07/01/16: Re: four phase clock using DCM with xilinx FPGA
114464: 07/01/16: Re: four phase clock using DCM with xilinx FPGA
114488: 07/01/17: Re: four phase clock using DCM with xilinx FPGA
114548: 07/01/18: Timing Delay Definitions
114571: 07/01/19: Re: Series DCM's and total Lock Time
114573: 07/01/19: Re: Phasse Detector
114574: 07/01/19: Re: Timing Delay Definitions
114958: 07/01/27: Re: Timing analyzer with Virtex 4
114988: 07/01/28: Re: Problem with verilog program
115093: 07/01/30: Re: Problem with verilog program
115387: 07/02/08: FSL Questions
115452: 07/02/11: Re: chipscope + mdm with microblaze ..
115491: 07/02/12: Re: chipscope + mdm with microblaze ..
115572: 07/02/13: IP to OPB FIFO
115575: 07/02/13: Re: IP to OPB FIFO
115624: 07/02/15: EDK Simulation on NCSIM
115638: 07/02/15: Re: EDK Simulation on NCSIM
115650: 07/02/15: ModelSim EDK Sim Problem
115677: 07/02/16: Re: ModelSim EDK Sim Problem
115819: 07/02/21: Re: up down lfsr
116590: 07/03/13: Xilinx SRL's and sync flip flops
116716: 07/03/15: DCM Autoconfiguration??
116717: 07/03/15: Re: DCM Autoconfiguration??
116718: 07/03/15: Re: DCM Autoconfiguration??
116793: 07/03/18: Re: DCM Autoconfiguration??
117497: 07/04/02: MGT Digital Receiver Oversampling
117509: 07/04/02: Re: Compiling simulation libraries of EDK 8.1.02i under Linux
117813: 07/04/10: Xilinx WebCase support
117848: 07/04/11: Re: Xilinx WebCase support
118124: 07/04/17: ModelSim Waveform naming question
118139: 07/04/18: Re: ModelSim Waveform naming question
118454: 07/04/26: Re: Question about the simulation library in EDK
118488: 07/04/27: Re: Question about the simulation library in EDK
119408: 07/05/17: Xilinx Timing Constraint Questions
119434: 07/05/18: Re: Xilinx Timing Constraint Questions
120213: 07/06/03: Re: ngdbuild error : multiple drivers and driving non buffer primitives
120282: 07/06/04: Re: ngdbuild error : multiple drivers and driving non buffer primitives
120491: 07/06/07: EDK Simulation Problem
120538: 07/06/08: Re: EDK Simulation Problem
120539: 07/06/08: Another EDK Sim question...
120594: 07/06/11: EDK Sim: BRAM won't init
120602: 07/06/11: Re: EDK Sim: BRAM won't init
120631: 07/06/12: Re: EDK Simulation Problem
120698: 07/06/13: Re: custom peripheral registers
120699: 07/06/13: Re: custom peripheral registers
120710: 07/06/14: Re: problems with FSL and Microblaze
120825: 07/06/18: Re: how to assert PSEN for DCM
120846: 07/06/18: V5 GTP Sim Problem
120847: 07/06/18: Re: Help needed regarding addition of Custom IP core to EDK
120848: 07/06/18: Re: want to pay for DCM active phase shift controller.
120893: 07/06/19: Re: V5 GTP Sim Problem
120894: 07/06/19: Re: want to pay for DCM active phase shift controller.
120899: 07/06/19: Re: Help needed regarding addition of Custom IP core to EDK
121013: 07/06/21: Re: Virtex 5 Rocketio
121025: 07/06/22: Re: How to deal with unavoidable setup time violation in CoolRunner II cpld?
121269: 07/06/29: Re: How to snoop an inout signal in EDK?
121333: 07/07/02: Re: Can I use chipscoe to look at V5 GTPoutputs
121378: 07/07/03: DIFF_TERM Question
121379: 07/07/03: Re: DIFF_TERM Question
121413: 07/07/03: Re: DIFF_TERM Question
122176: 07/07/22: FIFO Full logix - V4
122183: 07/07/23: Re: FIFO Full logix - V4
122510: 07/07/29: Re: Odelay usage in virtex5
122542: 07/07/30: Re: Odelay usage in virtex5
123262: 07/08/21: Re: MicroBlaze and ChipScope
123915: 07/09/06: DDR Simulation via MIG
123947: 07/09/07: Re: DDR Simulation via MIG
124597: 07/09/27: PowerPC Simulation
124599: 07/09/27: Re: Xilinx upgrade
124698: 07/09/30: Re: PowerPC Simulation
124890: 07/10/09: Timing Constraint Question
125031: 07/10/15: Xilinx FIFO Flag Question
125402: 07/10/24: MPMC2 NPI Help!
125434: 07/10/25: Re: MPMC2 NPI Help!
125443: 07/10/25: Re: MPMC2 NPI Help!
125484: 07/10/26: Re: MPMC2 NPI Help!
125517: 07/10/26: How to use an internal signal in a testbench...
125535: 07/10/27: Re: How to use an internal signal in a testbench...
126700: 07/11/29: EDK 9.2 Woes
126714: 07/11/29: Re: EDK 9.2 Woes
126829: 07/12/03: Power PC ISOCM Simulation
127101: 07/12/11: Initializing Micron DDR2 Memory
127124: 07/12/12: Re: Initializing Micron DDR2 Memory
128412: 08/01/24: Re: problem simulating in modelsim - swiftpli_mti.dll
Mouarf:
76119: 04/11/25: how to evaluate the needed number of gate?
76155: 04/11/26: Re: how to evaluate the needed number of gate?
76158: 04/11/26: Re: how to evaluate the needed number of gate?
78718: 05/02/07: GND and VCC pins
78722: 05/02/07: Re: GND and VCC pins
78758: 05/02/07: Re: GND and VCC pins
78931: 05/02/10: Re: Writing IP-Cores while sleeping ;)
78934: 05/02/10: Re: Writing IP-Cores while sleeping ;)
78935: 05/02/10: Re: Writing IP-Cores while sleeping ;)
78937: 05/02/10: Re: Writing IP-Cores while sleeping ;)
78940: 05/02/10: Re: Writing IP-Cores while sleeping ;)
79309: 05/02/17: 3.3V device programmable with 5V?
79384: 05/02/18: Re: 3.3V device programmable with 5V?
80377: 05/03/04: Re: Newby Getting started with FPGA
80772: 05/03/11: Re: Xilinx eagle package (PQ208)
83369: 05/04/28: Flexray ip core
83372: 05/04/28: Re: Flexray ip core
83751: 05/05/06: FPGA choice advice needed
83755: 05/05/06: Re: FPGA choice advice needed
83758: 05/05/06: Re: FPGA choice advice needed
83840: 05/05/07: Re: FPGA choice advice needed
83843: 05/05/08: Re: FPGA choice advice needed
84008: 05/05/11: Re: An FPGA eval board at $49!!
84010: 05/05/11: Re: An FPGA eval board at $49!!
85978: 05/06/19: Xilinx LPT programmer help
moudud:
152001: 11/06/21: ucf file for 32 bit counter spartan 3e S500E -4
moukai:
53498: 03/03/14: NIOS problem
54738: 03/04/16: About NIOS sdram
Mouli:
36735: 01/11/18: fft instantiation in foundation tools
mouna:
156656: 14/05/27: FSL Bus Problem
Mounard le Fougueux:
84831: 05/05/29: Re: VHDL vs. Schematic Capture
85924: 05/06/18: SystemC comments
85925: 05/06/18: Re: Lean Ethernet on Digilent board?
85941: 05/06/18: Re: SystemC comments
109474: 06/09/27: Simlex in VHDL/FPGA
134387: 08/08/08: need analog ntsc - ccir 656 core
Mounard Le Fougueux:
114179: 07/01/06: Problem with unused pin on Spartan 2E
114184: 07/01/06: Re: Problem with unused pin on Spartan 2E
114248: 07/01/08: Re: Problem with unused pin on Spartan 2E
115117: 07/01/31: DDR FPGA Design
Mounard le Fougueuxt:
75815: 04/11/15: OpenCore USB 2.0
mounther:
35749: 01/10/16: 1024 point non-complex FFT on a SPARTAN2
Mourad Aberbour:
6139: 97/04/16: Exponential function architecture
Mourad Khediri:
9069: 98/02/18: crossbar switch
Moussa A. Ba:
18200: 99/10/07: External Cloking of Altera MAX 7000S
18289: 99/10/12: Re: ALTERA design ---> XILINX
Moussa Ba:
18212: 99/10/07: Re: External Cloking of Altera MAX 7000S
18240: 99/10/08: Re: External Cloking of Altera MAX 7000S
18269: 99/10/11: CLOCK assignment in MAXPLUS2
18270: 99/10/11: ALTERA design ---> XILINX
19216: 99/12/06: TIme Delay 1us-100ms
mousy:
25698: 00/09/18: Re: Xilinx Student Edition 2.1 where?
move:
130682: 08/03/30: Synthesisable Timer in VHDL
mowa:
131670: 08/04/28: Re: how can i recover my unencrypted bitstream starting from
mozilla:
119979: 07/05/30: Nexys by Digilen xbd file
120277: 07/06/04: Re: Nexys by Digilen xbd file
127047: 07/12/10: Xilinx ise 9.2i clean up project files
127115: 07/12/12: Re: Xilinx ise 9.2i clean up project files
127116: 07/12/12: Re: Xilinx ise 9.2i clean up project files
132372: 08/05/23: Xilinx EDK inferred dual port BRAM unconnected clkb
133327: 08/06/24: edk peripheral communication
mozimo:
26976: 00/11/06: Re: cryptography/Block ciphers
26977: 00/11/06: Re: cryptography/Block ciphers
26978: 00/11/06: Re: cryptography/Block ciphers
<mozur@my-dejanews.com>:
11440: 98/08/13: Problem configuring 10K30ATC144 w/ EPC1
MP:
mpbetts:
54665: 03/04/15: Re: Hardware acceleration for raytracing purposes
<mpeattie@my-deja.com>:
26224: 00/10/09: Re: programm Xilinx FPGAs via JTAG // so far, so good
<mpercy@planetall.com>:
9702: 98/03/31: Re: New radix-4 CORDIC for computing sine and cosine
mpierrotb:
105702: 06/07/28: large data access to SDRAM at fixed frequency
MPJB:
60270: 03/09/09: Re: AWGN in VHDL
mpthompson:
136885: 08/12/10: Adding 128Kx8 SRAM to Spartan 3E FPGA
136900: 08/12/11: Re: Adding 128Kx8 SRAM to Spartan 3E FPGA
mpthompson@gmail.com:
113004: 06/12/04: Xilinx EDK/XPS 8.2 freezes XP desktop when launching XMD
MPU:
17604: 99/08/13: Re: PCI core
MPU Mike:
11697: 98/09/01: Re: (req)I'm looking for foundation
MR:
47824: 02/10/04: Re: Low power design
47923: 02/10/07: Re: .13 micron - what does it indicate
52323: 03/02/06: Re: clock ditribution tree
Mr B:
115224: 07/02/03: Re: Xilinx Interconnects/Routing
115226: 07/02/03: Re: Xilinx Interconnects/Routing
115234: 07/02/04: Reconfiguration
115236: 07/02/04: Re: Xilinx Interconnects/Routing
115241: 07/02/04: Re: Xilinx Interconnects/Routing
115960: 07/02/26: Redundancy
116185: 07/03/03: CUDD
116186: 07/03/03: Re: CUDD
Mr Barry Tso:
7901: 97/10/28: Looking for FAE for Asia Pacific region
7920: 97/10/30: Pin compatible
Mr J A Restrepo:
1500: 95/07/03: Re: Understanding Lattice equations
Mr M:
78044: 05/01/23: Re: How to get 1.8432 MHz out of 24 MHz with Sparten-3?
78562: 05/02/03: Help, i'm geting warnings :-(
78575: 05/02/03: Re: Help, i'm geting warnings :-(
Mr Tisdale:
15065: 99/03/04: A few questions - beginner
Mr. Ken:
103314: 06/05/31: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
103321: 06/05/31: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
103322: 06/05/31: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
103328: 06/05/31: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
103375: 06/06/01: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
103376: 06/06/01: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
103383: 06/06/01: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
105734: 06/07/31: In a function, how to I do bit-extension on temp variables:
105742: 06/07/31: Re: In a function, how to I do bit-extension on temp variables:
105743: 06/07/31: How do I create a clock with random starting phase?
105859: 06/08/02: How do I pass on an integer to a task and compare with an integer in the task?
105860: 06/08/02: Re: How do I pass on an integer to a task and compare with an integer in the task?
105926: 06/08/03: Re: How do I pass on an integer to a task and compare with an integer in the task?
105940: 06/08/03: In NCVerilog, how do I suppress "$readmem warning: words less than that given by address bounds"?
106044: 06/08/07: How do I treat "default" case which is useless?
106051: 06/08/07: Re: How do I treat "default" case which is useless?
Mr.B:
113006: 06/12/04: Re: LUT input order
Mr.CRC:
151143: 11/03/10: Re: Nanosecond pulse generator using Spartan-3E
151438: 11/04/08: Do people do this by hand?
151741: 11/05/13: Counter clocks on both edges sometimes, but not when different IO
151748: 11/05/14: Re: Counter clocks on both edges sometimes, but not when different
151749: 11/05/14: Re: Counter clocks on both edges sometimes, but not when different
151757: 11/05/14: Re: Counter clocks on both edges sometimes, but not when different
151764: 11/05/15: Re: Counter clocks on both edges sometimes, but not when different
151765: 11/05/15: Re: Counter clocks on both edges sometimes, but not when different
151766: 11/05/15: Re: Counter clocks on both edges sometimes, but not when different
151773: 11/05/16: Scoping a glitch
151778: 11/05/17: Re: Scoping a glitch
151779: 11/05/17: Re: Counter clocks on both edges sometimes, but not when different
151783: 11/05/18: Re: Scoping a glitch
151804: 11/05/18: Re: Scoping a glitch
151805: 11/05/18: Re: Counter clocks on both edges sometimes, but not when different
151811: 11/05/19: Re: Scoping a glitch
151819: 11/05/20: Re: Scoping a glitch
151820: 11/05/20: Can a glitch-free mux be designed in an FPGA?
151875: 11/05/26: Re: Scoping a glitch
151983: 11/06/17: Re: FFT using logic gates only
151984: 11/06/17: Re: Choosing a scope
152737: 11/10/15: Doulos training courses at Xilinx
152738: 11/10/15: Synapticad BugHunter and VeriloggerExtreme
152745: 11/10/17: Re: Doulos training courses at Xilinx
152786: 11/10/22: Re: Doulos training courses at Xilinx
153485: 12/03/08: Back from Xilinx trainings
mr16:
143374: 09/10/07: image scalar in Spartan 3E
143391: 09/10/08: Re: image scalar in Spartan 3E
Mr_chips:
102948: 06/05/23: Re: sending multiple char on RS232
<mr_donk@hotmail.com>:
49396: 02/11/11: FPGA Size?
49440: 02/11/12: Re: FPGA Size?
<mr_dsp@myrealbox.com>:
100960: 06/04/21: Re: Xilinx DCI resistor placement guidelines
<mr_reznat@yahoo.com>:
91117: 05/10/29: Re: Why are there two patents with same title
91130: 05/10/30: Re: Why are there two patents with same title
93320: 05/12/19: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
93607: 05/12/26: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
93610: 05/12/26: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
93625: 05/12/26: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
mralboro:
65484: 04/01/30: DLL board level lock feedback
<mrand@my-deja.com>:
24727: 00/08/17: Re: Distributor attitude !!
<mrandelzhofer@my-deja.com>:
28847: 01/01/26: Re: Foundation FPGA Editor hard macros in VHDL
<mrauf@nova-eng.com>:
18302: 99/10/13: Re: Announcement: VHDL/FPGA Development Boards (up to 400.000 Gates) (Corrected Links, More Boards)
20683: 00/02/17: Re: RECONFIGURABLE board for image processign
<mriely@cstp.umkc.edu>:
17400: 99/07/24: GET FRESHLY GROUND COFFEE ONLINE 50923
<mrizwan@rocketmail.com>:
11614: 98/08/27: Digital PLL
<mrmikehicks@earthlink.net>:
45633: 02/07/30: Dual Port Block RAM
45660: 02/07/31: Re: Dual Port Block RAM
45680: 02/08/01: Re: Dual Port Block RAM
<mrmoosavi@gmail.com>:
126934: 07/12/06: Re: How to simulate these example CORDIC code?
127039: 07/12/10: Re: How to simulate these example CORDIC code?
<mroberds@att.net>:
155799: 13/09/08: Re: FPGA temperature measurement
156096: 13/11/22: Re: microZed adventures
156228: 14/01/19: Re: my first microZed board
<mrtwisterz@020.co.uk>:
25370: 00/09/08: Mr Twisterz needs you
MS:
58447: 03/07/23: Pricing question....
58617: 03/07/29: Re: Pricing question....
63927: 03/12/09: Re: Floorplanning techniques
63928: 03/12/09: Embedded Powerpc in xilinx
64305: 03/12/26: EDK oddity
68663: 04/04/13: VirtexII : XC2V2000 Design
69168: 04/04/28: Xilinx edk/modelsim/ VHDL question
69192: 04/04/29: Re: Xilinx edk/modelsim/ VHDL question
69722: 04/05/18: opb_gpio with interrupt- v2pro
70146: 04/06/04: Re: how to random generate packet for Ethernet MAC(802.3) with verilog in testbench ?
70808: 04/06/28: Re: Communication FPGA & MII
71960: 04/08/04: Virtex 2 Pro OCM question
73138: 04/09/14: EDK OPB Uart 16550
75595: 04/11/10: Xilinx Tshirts in football package.....
<msauer@gmx.net>:
40371: 02/03/06: FPGA which supports LVDS
<mschaap@my-dejanews.com>:
15009: 99/03/03: Looking for Xilinx component XC 4020 XLA 09 PQ 208 C
msd:
76278: 04/11/29: OPB PS2 Controller
80952: 05/03/15: 100baseTX MAC/PHY daughterboard
81016: 05/03/16: Cheap 100mbit/s ethernet MAC/PHY daughterboard ?
msegura:
145607: 10/02/15: rocketio TX delay between sata0 and sata1
msfarooq87@gmail.com:
135394: 08/09/30: Interfacing DDR RAM
135436: 08/10/02: Re: Interfacing DDR RAM
135437: 08/10/02: Re: Interfacing DDR RAM
135438: 08/10/02: Re: Interfacing DDR RAM
msg:
115683: 07/02/16: Re: Building Coaxial transmission line on PCB?
116165: 07/03/02: Sources (products) for Cannibalizing FPGAs, PLDs, etc.
116170: 07/03/02: Re: Sources (products) for Cannibalizing FPGAs, PLDs, etc.
116235: 07/03/05: Re: Sources (products) for Cannibalizing FPGAs, PLDs, etc.
116237: 07/03/05: Re: Ideas for Masters Project.
116239: 07/03/05: Re: Sources (products) for Cannibalizing FPGAs, PLDs, etc.
116240: 07/03/05: Re: Sources (products) for Cannibalizing FPGAs, PLDs, etc.
116890: 07/03/20: Re: FPGA with 5V and PLCC package
125472: 07/10/26: Re: Changing refresh rate for DRAM while in operation?
130351: 08/03/20: Re: A Challenge for serialized processor design and implementation
MSI Consulting:
7783: 97/10/14: Digital Contract Jobs in Portland
<msimon@tefbbs.com>:
8946: 98/02/08: Re: Free FPGA tools???
9766: 98/04/04: Re: XactStep6 - The cure for a dongle
9743: 98/04/03: Re: Choosing the right FPGA tools...
9808: 98/04/07: Re: Effects of IC production
10132: 98/04/28: Re: [Q] Cheap Xilinx Proto Boards
10167: 98/04/30: Re: Q: XILINX Foundation
10170: 98/04/30: Re: Q: XILINX Foundation
10278: 98/05/09: Re: Low power FPGA design
10413: 98/05/17: Re: Minimal ALU instruction set.
10882: 98/06/27: Re: I squared C on an FPGA
10930: 98/07/04: Re: Consultants
10989: 98/07/08: Re: Speed Vs Accuracy
11613: 98/08/26: Re: CPLD/FPGA software
11662: 98/08/29: Re: Digital PLL
11746: 98/09/07: Re: 22V10 programming
11754: 98/09/07: Re: 22V10 programming
11853: 98/09/14: Re: ASIC -> FPGA async issues
11877: 98/09/16: Re: measuring junction temperature
11879: 98/09/16: Re: NEED: ideas on small project
11898: 98/09/17: Re: Help a confused teacher
11899: 98/09/17: Re: Help a confused teacher
11900: 98/09/17: Re: sync or async SRAM?
11906: 98/09/18: Re: sync or async SRAM?
12023: 98/09/24: Re: shareware
12081: 98/09/28: Design Your Own Microprocessor(tm)
12140: 98/10/01: Re: Simple programmable device suggestions please?
12196: 98/10/04: Re: Anyone used the Altera 74297 PLL function ?
12200: 98/10/04: Re: Anyone used the Altera 74297 PLL function ?
12204: 98/10/05: Re: info requested for design course
12228: 98/10/06: Re: Power estimation of XILINX XV series
12306: 98/10/08: Re: Xilinx Foundation Base
12320: 98/10/08: Re: FPGA core design
12331: 98/10/09: Re: clock divider chips
12333: 98/10/09: Re: FPGA core design
12367: 98/10/10: Re: Xilinx may not support schematics for Virtex?????
12562: 98/10/16: Re: Digital Sine Generator
12563: 98/10/16: Re: Digital Sine Generator
12585: 98/10/18: Re: ABEL vs. VHDL
12671: 98/10/22: Re: Schematic entry?
12672: 98/10/22: Re: Schematic entry?
12718: 98/10/25: Re: Looking for Love in ALL the Wrong Places???
12746: 98/10/27: Re: New free FPGA CPU
12747: 98/10/27: Re: Virtex PCI Board.
12769: 98/10/29: Re: !Recommendation wanted! Which CAD for shematic entry of Xilinx FPGA'based devices choose
12821: 98/10/30: Design Your Own Processor(tm)
12824: 98/10/30: Re: New free FPGA CPU
12845: 98/11/01: Re: New free FPGA CPU
12872: 98/11/03: Re: New free FPGA CPU
12874: 98/11/03: Re: New free FPGA CPU
12875: 98/11/03: Re: New free FPGA CPU
12852: 98/11/02: Re: Q: 3.3 V regulators suitable for XILINX - ?
12863: 98/11/03: Re: Q: 3.3 V regulators suitable for XILINX - ?
13088: 98/11/15: Re: Board for FPGA ?
13103: 98/11/16: Re: Example of clock circuit needed !
13256: 98/11/22: Combining busses Xilinx
13264: 98/11/22: Re: Combining busses Xilinx
13265: 98/11/22: Re: Combining busses Xilinx
msj:
13133: 98/11/17: Motorola MPA Latchup?
<msn444@gmail.com>:
119995: 07/05/30: Virtex4 Configuration Problem
119996: 07/05/30: Virtex4 Configuration Problem
128009: 08/01/12: Virtex4 burn-in failure
128025: 08/01/13: Re: Virtex4 burn-in failure
131731: 08/04/30: Virtex4 DCM doesn't work unless freezing cold
131770: 08/05/01: Re: Virtex4 DCM doesn't work unless freezing cold
<mspiegels@gmail.com>:
131405: 08/04/21: DCM configuration in Virtex-4 FPGA
131516: 08/04/24: Re: DCM configuration in Virtex-4 FPGA
132175: 08/05/16: Vref IO problems with DDR SDRAM memory controller on a Virtex 4 LX25,
mstanisz:
140191: 09/05/02: Spartan3E Starter Kit MISO and Flash pin shared
140193: 09/05/02: Re: Spartan3E Starter Kit MISO and Flash pin shared
140200: 09/05/03: Re: Spartan3E Starter Kit MISO and Flash pin shared
140231: 09/05/05: Re: Spartan3E Starter Kit MISO and Flash pin shared
140247: 09/05/05: Re: Spartan3E Starter Kit MISO and Flash pin shared
140249: 09/05/05: Code blocks to realize this in VHDL
140250: 09/05/05: Re: Spartan3E Starter Kit MISO and Flash pin shared
mstricker:
151545: 11/04/18: F.S. Xilinx ML403 evaluation board
<mstricker@embarqmail.com>:
135679: 08/10/12: F.S. Xilinx Evaluation boards
mstrug:
92203: 05/11/23: XC2000
92236: 05/11/24: Re: XC2000
112867: 06/11/30: Question: TMED Algorithm
<mstrzalka@my-dejanews.com>:
10632: 98/06/08: ViewDraw Info
mswlogo:
106654: 06/08/16: Re: Quartus and source control (continued)
MT:
97793: 06/02/27: System crashes when configuring altera stratix pci board
97797: 06/02/27: Moreover, the fpga hangs even when I configure a very simple design too...
mta:
16345: 99/05/17: Looking for VHDL Phase Locked Loop design
mte01:
89532: 05/09/18: Using BRAMs in VHDL on Virtex II FPGAs
<mtmason@ix.netcom.com>:
9761: 98/04/03: Re: Choosing the right tools and company....
10486: 98/05/23: XC6200
<mtom199@gmail.com>:
140932: 09/05/29: Re: I don't like xilinx (again)
Mtootell:
16191: 99/05/08: Anyone in the UK looking for FPGA/CPLD support ?
MTootell:
16851: 99/06/14: Re: PCI + I2O in a FPGA.... has anyone done it?
<mtsukanov@gmail.com>:
116052: 07/02/28: what does a 'blank check' do exactly
116084: 07/03/01: Re: what does a 'blank check' do exactly
116093: 07/03/01: Re: what does a 'blank check' do exactly
116098: 07/03/01: Re: what does a 'blank check' do exactly
116116: 07/03/01: Re: what does a 'blank check' do exactly
116119: 07/03/01: Re: what does a 'blank check' do exactly
116878: 07/03/20: prog_b held low?
116880: 07/03/20: Re: prog_b held low?
116957: 07/03/21: CPLD erase??
116965: 07/03/21: Re: prog_b held low?
116998: 07/03/21: Re: prog_b held low?
117055: 07/03/22: Re: CPLD erase??
118350: 07/04/24: Re: XTREME DSP Development Kit2 JTAG Problem
mtx:
75780: 04/11/15: Re: Digital LP filter in multiplier free FPGA
Mu Young Lee:
51633: 03/01/17: Lecroy Research Systems - what happened?
51653: 03/01/17: Re: Lecroy Research Systems - what happened?
<mu0lia0ni@my-deja.com>:
19999: 00/01/22: Transmeta CM & Conf. Comp?
mucikas:
81404: 05/03/22: Re: How to readback a BRAM
mud:
9019: 98/02/14: Re: Development Board for ARM/FPGA
mueller at scs dot ch:
52839: 03/02/24: Re: spartan III what is it?
muffinews:
32463: 01/06/27: Using Altera-ByteBlaster under Linux
mughat:
91514: 05/11/08: What does the IP in IPCORE stand for?
91559: 05/11/09: Re: What does the IP in IPCORE stand for?
91710: 05/11/11: Re: SDRAM controller.
94532: 06/01/13: bandpass filter design for ACTEL FPGA
97075: 06/02/16: CPLD-SPI_flash configuration system problem.
97137: 06/02/17: Re: CPLD-SPI_flash configuration system problem.
97456: 06/02/22: JTAG problem
97580: 06/02/24: Re: JTAG problem
99935: 06/03/31: JTAG program failed
100086: 06/04/03: Problem erasing EEPROM XCF08P
100115: 06/04/04: Re: Problem erasing EEPROM XCF08P
100116: 06/04/04: Re: Problem erasing EEPROM XCF08P
Muhammad Hamid:
7065: 97/07/28: Giga Ops g900 board
8632: 98/01/14: Re: VHDL to GigaOps
Muhammad Khan:
52827: 03/02/24: fe_shell.exe needed
56568: 03/06/09: Xilinx's Device Pin Configuration
56570: 03/06/09: Writing from FPGA to SRAM then to PC
56669: 03/06/11: PAR REPORT SUGGESTED BY PHILIP
56670: 03/06/11: Re: Xilinx's Device Pin Configuration
56672: 03/06/11: ERROR:NgdBuild:755
56755: 03/06/13: Contraint File Problem
56799: 03/06/16: How to Tristate!!! when not reading
56887: 03/06/18: Tristate
57911: 03/07/09: how can I use a signal defined in one Architecture to another Architecture
58110: 03/07/15: Re: problems on using CLKDLL in Xilinx ISE
59056: 03/08/07: Xilinx Error Msg- Help Required
muhammad_umer:
148574: 10/08/03: Xilinx EasyPath Pricing
148599: 10/08/05: Re: Xilinx EasyPath Pricing
148994: 10/09/20: Cant launch ModelSim from Xilin ISE 12.1
Mujtaba Hamid:
25634: 00/09/15: Re: Simulation problem
25850: 00/09/22: Re: Is correct code?
26884: 00/11/02: Re: Block Ram
27101: 00/11/10: Re: Non routable design
27530: 00/11/27: Re: how do i?
Mukesh:
71926: 04/08/03: Matlab/Simulink - System Generator HDL Co-Simulation
72787: 04/09/01: Xpower - Clock Power
Mukesh Chugh:
72837: 04/09/03: Xilinx Xpower Issues - Help from xilinx team please
73149: 04/09/14: Re: Xpower - Clock Power
73151: 04/09/14: Re: Xilinx Xpower Issues - Help from xilinx team please
<mukesh.chugh@gmail.com>:
84466: 05/05/19: Re: Silicon Valley FPGA position
muliani:
3989: 96/08/29: WTB: Configurable computer??
4004: 96/09/02: Address of ALTERA & XILINX
4029: 96/09/04: What is the REAL address of XOILINX and ALTERA?
mulligan:
104840: 06/07/07: Re: DDR Controller problems
<mulmon@hotmail.com>:
9864: 98/04/09: max7000
10363: 98/05/14: vga gen
10404: 98/05/16: Re: vga gen
mulp:
33484: 01/07/28: Re: Book Recommendation (bit different)
33783: 01/08/05: Re: finite defect statistics
munch:
95851: 06/01/26: PPC Memory Management
97288: 06/02/20: PPC LUT inputs/outputs
97984: 06/03/02: PPC LUTS registers
mungam:
98318: 06/03/08: can bus protocol on fpga
98324: 06/03/08: Re: can bus protocol on fpga
98438: 06/03/10: Re: can bus protocol on fpga
98448: 06/03/10: Re: can bus protocol on fpga
munishkumar86:
156757: 14/06/18: NAND flash interface through FPGA
mur KSpi:
60360: 03/09/11: Reading and processing input from graphics cards (DVI)?
Murali:
112026: 06/11/14: Microblaze store
112088: 06/11/15: Re: Microblaze store
112861: 06/11/30: Prefetch buffer in microblaze
113150: 06/12/07: Microblaze LMB bus
113168: 06/12/07: Re: Microblaze LMB bus
Murali Jayapala:
37702: 01/12/19: Re: MIPS or MOPS?
37707: 01/12/19: Re: MIPS or MOPS?
37711: 01/12/19: Re: MIPS or MOPS?
Murali K Warier:
48564: 02/10/20: Webpack download problem
48621: 02/10/21: Re: Webpack download problem
Muralidaran Vijayaraghavan:
112112: 06/11/16: Re: Microblaze store
113195: 06/12/07: Re: Microblaze LMB bus
113199: 06/12/07: Re: Microblaze LMB bus
Murat Çakýrođlu:
68923: 04/04/22: Re: FPGA within demonstration
Murdo Mckissock:
241: 94/09/30: Re: XC1765DPD8C
Murdo McKissock:
1434: 95/06/22: Re: Xilinx PLDMAP usage. Pro's and Cons?
1445: 95/06/23: Re: Inter-Chip Delay vs. CLB Delay
1485: 95/06/28: Re: Xilinx PLDMAP usage. Pro's and Cons?
1819: 95/09/06: Re: WWW Site about Synthesis for FPGAs
1858: 95/09/11: Re: WWW Site about Synthesis for FPGAs
1877: 95/09/14: Re: Fast FPGA's?
murlary@gmail.com:
138269: 09/02/11: Share: SATA HDD Simulation Model
138270: 09/02/11: Re: Share: SATA HDD Simulation Model
138369: 09/02/17: share: PCIE-PCIX simluation model
138430: 09/02/22: share: IDE/PATA HDD simluation model
138552: 09/02/26: why is the bottom 5 lsb all zero of ingress_start_addr/egress_start_addr[27:6]
138582: 09/02/28: Re: why is the bottom 5 lsb all zero of ingress_start_addr/egress_start_addr[27:6]
138758: 09/03/09: PATA-SATA simulation model
139689: 09/04/09: The data cann't written into DDR2 when DMA burst > 64bytes at ML505
142742: 09/08/29: Re: usb3.0 PHY wrapper for Xilinx V5/V6 device
142759: 09/08/30: Re: usb3.0 PHY wrapper for Xilinx V5/V6 device
142775: 09/08/31: Re: usb3.0 PHY wrapper for Xilinx V5/V6 device
142796: 09/09/01: Re: usb3.0 PHY wrapper for Xilinx V5/V6 device
142797: 09/09/01: Re: usb3.0 PHY wrapper for Xilinx V5/V6 device
142828: 09/09/02: Re: usb3.0 PHY wrapper for Xilinx V5/V6 device
Murray:
7171: 97/08/09: Programmable Logic News Website
7474: 97/09/15: Programmable Logic News Site Update
7483: 97/09/16: Re: Programmable Logic News Site Update
7910: 97/10/29: Programmable Logic News & Views
8333: 97/12/09: Programmable Logic News Update
9008: 98/02/13: Programmable Logic News & Views
Murray Newlands:
15033: 99/03/03: Embedded jobs - Ipswich/Cambridge - UK
murselonder:
109714: 06/10/04: ADC card selection for C6713
muruganandam.m@gmail.com:
120849: 07/06/18: Re: V5 GTP Sim Problem
muse_ee:
141810: 09/07/10: Xilinx Spartan 3 DCM no output!
141830: 09/07/11: Re: Xilinx Spartan 3 DCM no output!
141845: 09/07/13: Re: Xilinx Spartan 3 DCM no output!
141847: 09/07/13: Re: Xilinx Spartan 3 DCM no output!
141864: 09/07/14: Re: Xilinx Spartan 3 DCM no output!
mush:
2284: 95/11/17: Re: BP Micro and CUPL -- a good start?
2514: 95/12/22: Re: Floor Planning for Xilinx
Mustafa:
70883: 04/06/30: Re: Nios II and eCos
Mustafa Dagtekin:
10560: 98/05/29: XGA timings
Muthu:
38695: 02/01/22: Re: CRC-32 48bit(width)
38720: 02/01/23: Re: CRC-32 48bit(width)
38722: 02/01/23: Handling the events below in verilog coding??
40655: 02/03/12: powerpc in virtex2pro
41794: 02/04/08: Asynchronous FIFO from xilinx's Core Generator??
43611: 02/05/27: Why there is no clear signal in BRAM?
44483: 02/06/20: Xilinx's 4.1i's Lastest webpack
44484: 02/06/20: Retiming option in synplify pro
46266: 02/08/23: Re: FPGA speed level
46661: 02/09/04: Xilinx's ISE 5.1i
46671: 02/09/05: Modular Design
46958: 02/09/12: Re: Xilinx TBUFs
47010: 02/09/14: Re: Xilinx TBUFs
47334: 02/09/24: Re: MAP problem: Trivial RPM fails
47737: 02/10/02: Re: Large Multiplexer
47885: 02/10/07: writing STAMP file for Synplify Synthesis
47901: 02/10/07: STAMP Model for Coregen Outputs
47902: 02/10/07: Re: FIFO Simulation problem
47933: 02/10/07: Re: .13 micron - what does it indicate
48105: 02/10/10: How do i Know, which service pack i am using?
49537: 02/11/14: Re: EDIF generation from XST of ISE 5.1i
49731: 02/11/19: State Machine Coding....
49887: 02/11/23: Re: An Virtex FPGA architecture question
49888: 02/11/23: Re: Why do post-synthesis simulation result fall into unknow output state 'X' or "XX..."?
49911: 02/11/25: Virtex-II Place and Route...
49967: 02/11/26: How to instantiate a Hard-Macro in a design?
49974: 02/11/27: HardMacro (from FPGA Editor) Instantiation
50006: 02/11/27: Re: HardMacro (from FPGA Editor) Instantiation
50045: 02/11/29: Re: System Generator and 18x18 multipliers
50046: 02/11/29: Re: programmable FSM
50100: 02/12/02: MetaStability Issue on BRAMs
50135: 02/12/03: Parameterising the Core-gen Macro.....!!!
50136: 02/12/03: Re: register OR latch ?
50211: 02/12/04: Re: FPGA Actual Power Measurement
50217: 02/12/05: Re: HowTo 'freeze' a placement
50242: 02/12/06: Re: HowTo 'freeze' a placement
50277: 02/12/07: Re: HowTo 'freeze' a placement
50397: 02/12/10: Area contrain for a Module
50541: 02/12/12: RPM Using ISE5.1i FloorPlanner
50544: 02/12/12: Re: Two clocks for the same module
50573: 02/12/12: Re: RPM Using ISE5.1i FloorPlanner
50780: 02/12/19: Multi cycle Paths..
50813: 02/12/19: Re: Multi cycle Paths..
50825: 02/12/20: Re: Multi cycle Paths..
50966: 02/12/24: Floor Planning DCM
50994: 02/12/25: Re: Floor Planning DCM
51014: 02/12/26: RPM Portability?
51019: 02/12/26: FIFO FULL
52091: 03/01/31: Xilinx Design Softwares?
52116: 03/02/01: Re: Xilinx Design Softwares?
55724: 03/05/17: Re: test cases for testing PCI core
56057: 03/05/27: FIFO Controller
56194: 03/05/29: Gate arrays
56222: 03/05/31: FSM Coding Style
56273: 03/06/02: Parallel_case Synthesis directive
56321: 03/06/02: Re: Parallel_case Synthesis directive
56330: 03/06/03: Mealy FSM
56337: 03/06/03: For Loop Synthesis
56344: 03/06/03: XST :738 Warning
56427: 03/06/04: defparam (Synthesizable or Not?)
56428: 03/06/04: Xilinx Block RAM
56935: 03/06/18: Re: XST verilog problem
56973: 03/06/19: Re: XST verilog problem
57412: 03/06/30: Asynchronous RESET?
57555: 03/07/02: Combining Distributed RAM and Block RAM
59240: 03/08/12: Re: async flip-flop reset by a signal from a different clock domain
59727: 03/08/27: PCI Clock Issue
61806: 03/10/12: XST Timing report
62802: 03/11/07: PCI - X Boot up
62848: 03/11/10: Re: ISE 5.2 to 6.1
62990: 03/11/12: Re: XST Timing report
63432: 03/11/21: Re: regarding clock routing
63634: 03/11/26: Xilinx FPGA Clock Skew
63636: 03/11/26: Re: what is the fastest speed that FPGA deals with CPU?
63638: 03/11/26: Re: Reverse engineering an EDIF file?
63828: 03/12/04: Re: Design analyse methods
63829: 03/12/04: XILINX FPGA: DCM locked Signal
63830: 03/12/04: Re: Hold violation and PLL
63841: 03/12/05: Re: Floorplanning techniques
63900: 03/12/08: Finding Multicyle Paths in a Design
64132: 03/12/17: Re: Xilinx .ucf
64178: 03/12/18: Re: Using FPGA Editor to introduce PULLUP and PULLDOWN
64270: 03/12/23: Re: pcix core in XC2VP7
64271: 03/12/23: Re: Net name convention for Xilinx UCF files.
68251: 04/03/30: Metastablility
68739: 04/04/16: PLL and DLL
71162: 04/07/10: Do i need to use DCM ?
71262: 04/07/13: Re: Do i need to use DCM ?
71263: 04/07/13: Hazard Analysis ???
72597: 04/08/26: X propagation in Timing Simulation
72634: 04/08/26: Re: X propagation in Timing Simulation
72675: 04/08/28: SOC and ASIC ?
72915: 04/09/07: Re: SOC and ASIC ?
72916: 04/09/07: Re: A Typical Design Cycle
72968: 04/09/09: Memory access time?
74214: 04/10/06: Crossing clock domain issue at Functional Simulation
75990: 04/11/21: VLSI professional at NASA
143966: 09/11/05: Re: problem fpga aera optimization
<muthusnv@gmail.com>:
102636: 06/05/18: OFFSET constraints with derived clocks - Xilinx FPGA
128762: 08/02/05: ML505 with Petalinux
129131: 08/02/15: Re: i need ur help
129132: 08/02/15: Re: Xilinx GTP_DUAL: wizard or code ?
129195: 08/02/18: Re: ML505 with Petalinux
129366: 08/02/21: Re: Interview questions
129976: 08/03/11: Design complexity in Logic cells - Virtex-5 FPGA
132664: 08/06/04: UART master core
132676: 08/06/05: Anyone used HiTech global boards?
133304: 08/06/24: Cycle-based or Event-based simulation?
133343: 08/06/25: Xilinx tools in Windows or Linux - Suggestions
134653: 08/08/24: Problem in simulating Xilinx MPMC in VCSMX
135841: 08/10/17: Xilinx: FDR and FD inference in Synplify_pro
140029: 09/04/24: FPGA evaluation board for SD/SDHC Host controller
<muthusnv@rediffmail.com>:
78414: 05/01/31: Active HIGH / Active LOW
87111: 05/07/15: Compilation error with Synplify attribute
<muyihwah@gmail.com>:
157612: 15/01/06: Parallel execution of Systemc code
157615: 15/01/06: Re: Parallel execution of Systemc code
157621: 15/01/07: Re: Parallel execution of Systemc code
Muzaffer Kal:
22900: 00/05/30: Re: Implement LMS
23190: 00/06/16: spartan and virtex on the same board ?
23195: 00/06/16: Re: spartan and virtex on the same board ?
23388: 00/06/23: Re: What tools do people use for Xilinx FPGAs?
23669: 00/07/05: Spartan II PCI32 suggestions ?
23815: 00/07/10: Re: phase lock different frequencies
23824: 00/07/11: Re: Timing Simulation for Alter FPGAs
23917: 00/07/14: Re: Dual Port RAM
23930: 00/07/15: jtag connections for Spartan II on PCI ?
24293: 00/08/02: GPIO board for Avnet Virtex Development system ?
24296: 00/08/03: GPIO board for Avnet Virtex Development system ?
24758: 00/08/17: Re: Clock recovery in FPGA
25258: 00/09/02: Re: Xilinx block Ram Verilog model
25259: 00/09/02: Re: Xilinx block Ram Verilog model
25641: 00/09/16: Re: Physical Interpretation
25718: 00/09/18: Re: Looking for an Altera APEX eval board
25975: 00/09/28: Re: Synplicity vs Xilinx FPGA Express
25994: 00/09/29: Re: Xilinx Logicore Generator
26017: 00/10/01: Re: FPGA Express strikes again! Xilinx response
26022: 00/10/01: Re: multi-input adders in virtex ?
26018: 00/10/01: multi-input adders in virtex ?
26028: 00/10/01: Re: multi-input adders in virtex ?
26048: 00/10/01: Re: GPIO on AVNET Xilinx FPGA board? any cables?!?
26295: 00/10/11: Re: Modular Exponentiation
26393: 00/10/14: Re: 5V compatible Virtex
26475: 00/10/17: Re: VHDL vs Verilog
26479: 00/10/18: Re: VHDL vs Verilog
26585: 00/10/21: xilinx floor planner issues
26645: 00/10/23: Re: xilinx floor planner issues
26708: 00/10/25: ROC (reset on configuration) on Virtex ?
26756: 00/10/27: Re: Lazio Promises End to Long Island FPGA Crisis
26775: 00/10/28: death of rloc ?
26943: 00/11/04: Re: Group behaviour (was: Alliance under Linux)
26942: 00/11/04: Re: Alliance under Linux?
26867: 00/11/01: Re: death of rloc ?
27015: 00/11/07: Re: unique serial nr
27027: 00/11/08: Re: 'event synthesis question
27047: 00/11/08: Re: PLL vs DLL
27203: 00/11/15: Re: Clear AND Preset Pins
27350: 00/11/19: Re: Synthesizable VHDL
27390: 00/11/20: Re: initialization of ROM contents in COREGEN part
27426: 00/11/21: Re: What is the fundamental limitation factor for FPGA clock rate
27454: 00/11/22: Re: Clock Skew : Does Xilinx know what they're doing?
27542: 00/11/28: Re: hard or soft core for FPGA?
27544: 00/11/28: Re: hard or soft core for FPGA?
27595: 00/11/29: Re: question on initial states of FFs and GSR in Virtex
27599: 00/11/29: Re: Synplify Benchmarks
27679: 00/12/02: Re: Hey there anybody!!
27692: 00/12/03: Re: Issues with Spartan II
27708: 00/12/04: Re: Issues with Spartan II
27714: 00/12/04: Re: Issues with Spartan II
27730: 00/12/05: Re: Route/Logic delay ratio
27775: 00/12/07: Re: Test Bench
27939: 00/12/15: Re: kalman filter
27947: 00/12/16: Re: FPGA to ASIC conversion
28173: 00/12/24: Re: Question about programming xcv100
28550: 01/01/17: Re: Synplicity newsgroup?
28679: 01/01/20: Re: Synplicity newsgroup?
28880: 01/01/26: Re: XtremeDSP seminar comments -- Virtex-II 4xPowerPC chip
29000: 01/02/01: Re: It's time to make a little dance
29172: 01/02/08: parallel PRBS ?
29228: 01/02/10: Re: double precision floating point arithmetic
29325: 01/02/14: Re: Problem with pipelined divider in Virtex
29335: 01/02/15: Re: Virtex XCV2000E-6 BG560C - Orcad capture symbol
29371: 01/02/16: DSPIA Inc. becomes Xilinx XPERTS Partner
29405: 01/02/19: Re: ALtera CPLD
29454: 01/02/22: Re: Virtex USB solution
29532: 01/02/25: Re: Is anybody using Quicklogic PCI/FPGA devices?
29599: 01/02/28: Re: Virtex ambit support
29601: 01/02/28: Re: Virtex ambit support
29627: 01/03/02: Re: Interfacing Xilinx 4003 to an IDE Hard Disk interface.
29656: 01/03/04: Re: Metastability
30211: 01/03/28: Re: P4 vs Athlon
30984: 01/05/08: Re: Licensing PB in Synplify_pro 6.2
31049: 01/05/10: Re: Shannon Capacity
31153: 01/05/13: Re: Avnet Virtex-E Development Kit
31161: 01/05/14: Re: Avnet Virtex-E Development Kit
31220: 01/05/15: Re: Leonardo Spectrum Level 1 vs Level 3
31383: 01/05/21: Re: Synplicity newsgroup?
31404: 01/05/22: Re: Xilinx PCI JTAG programming
31484: 01/05/27: Re: RLocs on Inferred registers??
31492: 01/05/28: RLOC_RANGE problem with Virtex-II ?
32058: 01/06/12: Re: Doing Ethernet in a Virtex ?
32624: 01/07/03: Re: poor man's floating point...
32776: 01/07/09: Re: Need some help using Synplify ... and also considering Xilinx Modular Flow
32983: 01/07/13: Re: Design entry
33123: 01/07/17: Re: Fibre Channel info?
33171: 01/07/18: Re: Athlon 1.4 vs Pentium 4 1.7 for Foundation ISE/ModelSim?
33630: 01/08/01: Re: Spanning the heirarchy
33659: 01/08/01: Re: What way for Xilinx to ASIC migration ?
34370: 01/08/22: Re: Logic Emulation
34488: 01/08/27: Re: FPGA to ASIC conversion?
34527: 01/08/28: Re: FPGA : USB in an FPGA, has anyone done it before?
34532: 01/08/28: Re: Level sensitive latches in Xilinx Virtex
34583: 01/08/29: sharing a PROM between configuration and the FPGA
34880: 01/09/12: Re: Fixed or Floating point for MP3 algorithim?
35288: 01/09/27: Re: Programming flash connected to CPLD via JTAG
36656: 01/11/14: Re: ASRC (asynchronus sample rate conversion)
36872: 01/11/22: Re: How do I.......
37628: 01/12/18: Re: division 64
37650: 01/12/18: Re: division 64
37655: 01/12/18: Re: Kindergarten Stuff
37908: 01/12/24: Re: availability of VirtexII production silicon
38105: 02/01/05: Re: ASIC faster than VirtexII FPGA?
38106: 02/01/05: Re: ASIC faster than VirtexII FPGA?
38111: 02/01/05: Re: full custom design
38892: 02/01/28: Re: 18bit counter
39470: 02/02/11: Altera's new family Stratix
39907: 02/02/21: Re: Problems : INOUT not allowed, alternatives
40127: 02/02/28: Re: Simulation Question
40226: 02/03/02: Re: Altera Excalibur
40357: 02/03/05: Re: Writing Synosys library for FPGA using LUT.
40368: 02/03/06: Re: exceeding 2GB limits in xilinx
40449: 02/03/07: Re: high active and low active reset signal mixed in a design
40912: 02/03/18: Re: Lies, damn lies and Synplicity
40913: 02/03/18: Re: Clock buffer and Reset example.
40914: 02/03/18: Re: How do I simulate two separate designs simutaneously in ModelSim XE?
41171: 02/03/22: Re: Interconnect system for multiple FPGA's ?
41172: 02/03/22: Re: Working modulo exponent routine?
42435: 02/04/24: sharing SDRAM between processor and VirtexII?
43617: 02/05/27: Re: Why there is no clear signal in BRAM?
44115: 02/06/12: Re: Visual SourceSafe and VHDL files
44393: 02/06/19: Re: beginer's question: what does tran means in verilog
44726: 02/06/28: Re: 5V tolerance
45105: 02/07/12: Re: FPGA CPU?
45177: 02/07/15: Re: Sensitivity list (VHDL) & FPGA pin assignment
45715: 02/08/02: Re: vcs synplify
46224: 02/08/22: Re: Huge discrepanzcy between gate-array and standard cell synthesis
47118: 02/09/18: Re: Feasibility of 100 tap adaptive FIR design on FPGA
47198: 02/09/20: Re: Multiple divide by 10
47290: 02/09/22: Re: Timing accuracy with Modelsim
47535: 02/09/27: Re: Dual Port RAM
48196: 02/10/14: Re: where can I find the FAQs for this news group???
48565: 02/10/21: Re: Ms-DOS formatting in an CompactFlash card?
49007: 02/10/29: Re: Quartus Run Time Error
49138: 02/11/01: Re: How important is simulation?
49168: 02/11/04: Re: Learner ? - Open Collector in Verilog
49301: 02/11/08: Re: LU-decomposition
49364: 02/11/11: Re: FPGA convert to ASIC
49416: 02/11/12: Re: LU-decomposition
49701: 02/11/19: Re: What combinational logic will produce a falling edge only.
49733: 02/11/20: Re: State Machine Coding....
49879: 02/11/23: Re: Why do post-synthesis simulation result fall into unknow output state 'X' or "XX..."?
50477: 02/12/11: Re: Hold violation in synthesis but not fitting
50814: 02/12/20: Re: Multi cycle Paths..
50961: 02/12/24: Re: Combinatorial clock source question
51238: 03/01/08: Re: USB OPENCORE IP usage
51564: 03/01/16: Re: HSPICE simulator
51870: 03/01/24: Re: VHDL or Verilog?
52004: 03/01/28: Re: 1024bit Adder
52840: 03/02/24: Re: HELP WANTED
52867: 03/02/25: Re: Delay element in Virtex2
53041: 03/03/01: Re: SDA FIR Filter...
53281: 03/03/10: Re: Timing Simulation Glitches
53386: 03/03/12: Re: DRC/ LVS
53777: 03/03/22: Re: how to implement the bidir in Altera AHDL?
53980: 03/03/29: microblaze gnu tool info ?
54007: 03/03/31: Re: microblaze gnu tool info ?
54148: 03/04/03: Re: Gatecount in which basic gate
54379: 03/04/09: Re: prelayout and post layout frequencies
55632: 03/05/14: Re: VitalGlitch
55723: 03/05/17: Re: what and how encrypted VHDL code work
56123: 03/05/29: Re: need help on sending 500Mbit/s data through 100 feet of cable, Giga-Ethernet?
56124: 03/05/29: 20 to 5 encoder optimization?
56324: 03/06/03: Re: Parallel_case Synthesis directive
56382: 03/06/04: Re: Spartan-3 questions?
57426: 03/06/30: Re: Asynchronous RESET?
59048: 03/08/07: Re: Confusing Xilinx Webpack warning
59729: 03/08/27: Re: Thinking out loud about metastability
61096: 03/09/28: Re: Implementing Bidirectional pins
61146: 03/09/29: Re: Implementing Bidirectional pins
61199: 03/09/30: Re: Bit error rate
64449: 04/01/05: Re: is this a good idea
65931: 04/02/10: Re: negative hold time
130849: 08/04/03: Re: async clk input, clock glitches
130871: 08/04/04: Re: problem with synthesis
130940: 08/04/05: Re: problem with synthesis of a state machine
130942: 08/04/05: Re: problem with synthesis of a state machine
131211: 08/04/15: Re: Pre and Post Synthesis Simulation mismatch
131249: 08/04/17: Re: asic gate count
131507: 08/04/23: Re: Verilog state machines, latches, syntax and a bet!
131508: 08/04/23: Re: Verilog state machines, latches, syntax and a bet!
131529: 08/04/24: Re: Verilog state machines, latches, syntax and a bet!
132029: 08/05/10: Re: Anyway to secure a Xilinx NGC file ?
132185: 08/05/16: Re: What could be the problem?
132544: 08/05/30: Re: asic gate count
132907: 08/06/10: Re: how to track down an optimised away signal
133143: 08/06/18: Re: which commercial HDL-Simulator for FPGA?
133207: 08/06/20: Re: virtex 5 security / embedded key memory
133238: 08/06/21: Re: Newbie Verilog Question / ModelSim
133508: 08/07/01: Re: How do I program an fpga once it has been designed and layout is complete
133693: 08/07/09: oversampling serializer?
133759: 08/07/13: Re: Mismatch simulation & post sythese results
133792: 08/07/15: xilinx v5 ddr2 controller
133876: 08/07/18: Re: verilog code
133877: 08/07/18: Re: verilog code
133927: 08/07/19: Re: instantiation in verilog
134019: 08/07/22: Re: help me improve this simple function
134623: 08/08/21: Re: Workaround for installing EDK on Vista x64?
134638: 08/08/22: Re: missing Xilinx virtual machine Centos password
134643: 08/08/22: Re: missing Xilinx virtual machine Centos password
134920: 08/09/07: Re: Are Xilinx tools that bad, or am I missing something?
135241: 08/09/23: Re: duty cycle significance
135349: 08/09/27: Re: Is it possible to get an RTL netlist from Xilinx tools?
135360: 08/09/28: Re: 50 Ohm Analog Output of FPGA
135835: 08/10/16: Re: Literature on 100Base-TX request
135853: 08/10/17: Re: Literature on 100Base-TX request
135867: 08/10/18: Re: Literature on 100Base-TX request
135923: 08/10/21: Re: Literature on 100Base-TX request
136151: 08/11/03: Re: Why does Nios cannot pass make?
136173: 08/11/04: Re: Critical Path
136176: 08/11/04: Re: Critical Path
136644: 08/11/27: Re: help! how to pipeline a non-restoring divider in verilog
136720: 08/12/02: Re: Hold Time Requirement
137115: 08/12/23: Re: DFFR using DFF (only, may be extra gates)
137116: 08/12/23: Re: DFFR using DFF (only, may be extra gates)
137118: 08/12/23: Re: DFFR using DFF (only, may be extra gates)
137120: 08/12/23: Re: DFFR using DFF (only, may be extra gates)
137145: 08/12/28: Re: FPGA > ASIC
137217: 09/01/03: Re: time limited netlist generation
137231: 09/01/05: Re: time limited netlist generation
137493: 09/01/20: Re: Where can I find the matlab file:gmsk_mod.mdl on Xilinx website
137701: 09/01/27: Re: XST Makes Odd Choice
137737: 09/01/28: Re: XST Makes Odd Choice
137840: 09/01/31: Re: how can we connect the two buses of different width
137919: 09/02/02: Re: fpga reset
138117: 09/02/06: Re: Experiencing problems when moving an FPGA-based implementation to an ASIC
138131: 09/02/06: Re: Experiencing problems when moving an FPGA-based implementation to an ASIC
138144: 09/02/07: Re: clk synchronization of reset signal
138147: 09/02/07: Re: PLDShell Plus V5.1
138178: 09/02/08: Re: Is this phase accumulator trick well-known???
138190: 09/02/08: Re: Is this phase accumulator trick well-known???
138194: 09/02/09: Re: pulser problem
138197: 09/02/09: Re: Learning backend stuff
138362: 09/02/17: Re: Troubleshooting fpga design
138404: 09/02/19: GTKWave 3.2.0 for Windows is available
138671: 09/03/03: 32x32 -> 64 multiplier in virtex-5
138687: 09/03/04: Re: 32x32 -> 64 multiplier in virtex-5
138717: 09/03/05: Re: make ise take ngc as source
138739: 09/03/06: Re: make ise take ngc as source
138957: 09/03/16: Re: Zero operand CPUs
139256: 09/03/24: Re: Flow Control
139299: 09/03/25: Re: USB PHY
139314: 09/03/26: virtex-5 lvds termination issue?
139321: 09/03/26: Re: virtex-5 lvds termination issue?
139419: 09/03/28: Re: USB port on FPGA - How is data transmitted?
139453: 09/03/30: Re: USB port on FPGA - How is data transmitted?
139640: 09/04/08: Re: Two stage synchroniser,how does it work?
139665: 09/04/08: Re: Two stage synchroniser,how does it work?
139669: 09/04/08: Re: Two stage synchroniser,how does it work?
139670: 09/04/08: Re: About DSP48 used for 24bit * 18bit
139747: 09/04/11: Re: Avnet spartan 3A design issue
139752: 09/04/11: Re: Decimation clock
139756: 09/04/11: Re: Microblaze GPIO API functions
139765: 09/04/12: Re: Programming Digilent Nexys 2 from Linux
139974: 09/04/21: Re: Why is XST optimizing away my registers and how do I stop it?
140110: 09/04/28: Re: a basics question: using input pins, pullup, short to ground vs driven signal.
140111: 09/04/28: Re: a basics question: using input pins, pullup, short to ground vs driven signal.
140115: 09/04/28: Re: a basics question: using input pins, pullup, short to ground vs driven signal.
140131: 09/04/29: Re: Quartus Timing
140133: 09/04/29: Re: ASIC from working FPGA design
140228: 09/05/04: Re: FIFO that latches data asynchronic manner
140391: 09/05/12: Re: [newbie asking] I don't like Xilinx
140438: 09/05/13: Re: I don't like Xilinx
140439: 09/05/13: Re: How to improve maximum operating frequency of a design using DSP 48E?
140548: 09/05/16: Re: Virtex 5 clocking
140552: 09/05/16: Re: Virtex 5 clocking
140638: 09/05/20: GTKWave 3.2.1 for Windows is available
140717: 09/05/22: Re: Muli-Cycle Path Constrains in RTL
140728: 09/05/22: Re: INFO:Xst:738 - HDL ADVISOR - 256 flip-flops were inferred .... Warning. Should I care?
140810: 09/05/26: Re: INFO:Xst:738 - HDL ADVISOR - 256 flip-flops were inferred .... Warning. Should I care?
140815: 09/05/26: Re: I don't like Xilinx
140824: 09/05/26: Re: Core 2 Duo E8500 vs. Core i7 920?
140856: 09/05/27: Re: phase locking a slow (2Mhz) signal.
140886: 09/05/28: Re: simulating a program inside a soft core with systemc
141050: 09/06/03: Re: Secure netlist
141234: 09/06/11: Re: Safe margin in FPGA static timing analysis
141287: 09/06/15: Re: About Altera patent application "Logic Cell Supporting Addition of Three Binary Words"
141350: 09/06/19: Re: set dont touch in Xilinx Xst
141372: 09/06/21: Re: Subtleties of Booth's Algorithm Implementation
141375: 09/06/22: Re: Subtleties of Booth's Algorithm Implementation
141382: 09/06/22: Re: Question on FPGA driver
141387: 09/06/22: Re: Subtleties of Booth's Algorithm Implementation
141390: 09/06/22: Re: Question on FPGA driver
141439: 09/06/24: Re: True dual-port RAM in VHDL: XST question
141444: 09/06/24: Re: True dual-port RAM in VHDL: XST question
141484: 09/06/25: Re: True dual-port RAM in VHDL: XST question
141696: 09/07/03: Re: Math Integral operation in FPGA
141869: 09/07/14: Re: Minimal size 1-bit adder....
142062: 09/07/23: Re: FPGA development tools for FreeBSD?
142137: 09/07/26: Re: iCore7 vs Core2 simulation & FPGA tool performance?
142406: 09/08/09: Re: Spartan-6 Boards - Your Wish List
142442: 09/08/11: Re: algorithm implementation in IC
142443: 09/08/11: Re: algorithm implementation in IC
142445: 09/08/11: Re: algorithm implementation in IC
142531: 09/08/15: GTKWave 3.2.2 for Windows is available
142548: 09/08/16: Re: Virtex 4 package code
142620: 09/08/21: Re: Emulation of highly complex superscaler processor using FPGAs
142815: 09/09/02: Re: Virtex-5 clock input is excessively loading SERDES recovered clock
142949: 09/09/09: Re: Xilinx TCL and Cygwin
143007: 09/09/14: Re: Everything in single clock cycle.
143011: 09/09/14: Re: Everything in single clock cycle.
143013: 09/09/14: Re: 8 phase clock output
143033: 09/09/15: Re: 8 phase clock output
143112: 09/09/21: Re: timing simulation performance
143114: 09/09/21: Re: timing simulation performance
144171: 09/11/16: Re: who have a usb3.0 pipe3 wrapper for xilinx V5/V6 FPGA?
144331: 09/11/26: Re: Going mad trying to solve PLL setup/hold timing violation issues in Quartus
144337: 09/11/27: Re: Going mad trying to solve PLL setup/hold timing violation issues in Quartus
144338: 09/11/27: Re: Going mad trying to solve PLL setup/hold timing violation issues in Quartus
144340: 09/11/27: Re: Going mad trying to solve PLL setup/hold timing violation issues in Quartus
144346: 09/11/28: Re: Going mad trying to solve PLL setup/hold timing violation issues in Quartus
144522: 09/12/12: Re: post route simulation
144532: 09/12/13: Re: Does a 1-bit mux glitch if only one input is known to change at one time?
144590: 09/12/17: GTKWave 3.3.0 for Windows is available
144708: 09/12/26: Re: Xilinx and Multi-port memories
144727: 09/12/29: Re: fsm coding question
145064: 10/01/24: Re: Post route simulation warning
145242: 10/02/02: Re: Help Please - Xilinx message
145600: 10/02/15: Re: How relevant is the Residue Number System (RNS)?
145707: 10/02/19: Re: rocketio TX delay between sata0 and sata1
145922: 10/02/27: Re: Frustration with Vendors!
145933: 10/02/28: Re: Frustration with Vendors!
146103: 10/03/05: Re: using an FPGA to emulate a vintage computer
146199: 10/03/08: Re: Some Active-HDL questions
146328: 10/03/11: Re: Comparing FPGA with ASIC implementations
146469: 10/03/19: Re: Xilinx Spartan6 Virtex6 Rollout
146566: 10/03/22: Re: Standard cell library help
146682: 10/03/25: Re: Newbie Coding Question
146813: 10/03/29: Re: XST optimization
146844: 10/03/30: Re: XST optimization
146889: 10/03/31: Re: Spartan 6 PLL - Why such a strict input jitter requirement?
147150: 10/04/15: Re: I'd rather switch than fight!
147316: 10/04/22: Re: I'd rather switch than fight!
147347: 10/04/23: Re: I'd rather switch than fight!
147370: 10/04/23: Re: I'd rather switch than fight!
147387: 10/04/25: Re: Craignell2-48 - 48 Pin FPGA DIL Module
147488: 10/04/28: Re: xilinx arm finally announced
147503: 10/04/28: Re: xilinx arm finally announced
147571: 10/05/04: Re: Unecessary simulation paths
147580: 10/05/04: Re: FIFO Depth Calculation
147581: 10/05/04: Re: FIFO Depth Calculation
147704: 10/05/17: Re: Xilinx Synthesis Tool generates clock signals from combinatorial logic
147886: 10/05/29: Re: Last Xilinx Webpack that was big-brother free?
148087: 10/06/19: GTKWave 3.3.7 for Windows is available
148395: 10/07/17: Re: Another Xilinx webpack download rant
148403: 10/07/18: Re: I2C Master Start stop generation
148975: 10/09/17: Re: Preventing timing warnings
148990: 10/09/19: Re: Stack Exchange site for programmable logic and FPGA design
149003: 10/09/20: Re: Xilinx XST and a State Machine - A Mystery
149046: 10/09/23: Re: Virtex6 quote
149105: 10/10/01: Re: FPGA design not working!
149119: 10/10/03: Re: Another Xilinx webpack download rant
149417: 10/10/22: Re: Need help with powering FPGA
149436: 10/10/25: Re: Need help with powering FPGA
149519: 10/11/01: Re: Xilinx ConstraintSystem:59
149632: 10/11/12: Re: cool BGA pattern
149827: 10/11/25: Re: Synthesis/place and route with Solid-State Drives
149841: 10/11/26: Re: Multiple clock domains
149854: 10/11/28: Re: 1653 - At least one timing constraint is impossible to meet
149866: 10/11/29: Re: Multiple clock domains
150075: 10/12/09: Re: Multiple clock domains
150268: 11/01/07: Re: Low slewrate, abnormal current consumption.
150269: 11/01/07: Re: spartan 3 xc3s1000 not getting programmed
150295: 11/01/08: Re: spartan 3 xc3s1000 not getting programmed
150299: 11/01/08: Re: OT: Fast Circuits
150436: 11/01/20: Re: Overview for non-technicals.
150615: 11/01/27: Re: V6 SerDes simulation
150721: 11/02/06: Re: Looking for off-the-shelf 3.3 <--> 5v level shifter
150722: 11/02/06: Re: Looking for off-the-shelf 3.3 <--> 5v level shifter
150724: 11/02/06: Re: Looking for off-the-shelf 3.3 <--> 5v level shifter
150894: 11/02/19: Re: Mathematical definition of an FPGA
150922: 11/02/21: Re: timing issues at high speed
150931: 11/02/22: Re: timing issues at high speed
151315: 11/03/22: Re: SRL as a synchroniser
151523: 11/04/17: GTKWave 3.3.20 for Windows is available
<muzaffer.kal@gmail.com>:
154873: 13/01/24: Re: implementation of 8051 ip core on fpga
154908: 13/02/12: Re: Vivado - Pack I/O Registers?
154939: 13/02/25: Re: about the always block in verilog
155098: 13/04/13: Re: XILINX Artix-7
155390: 13/06/25: Re: Pure HDL Xilinx Zynq Arm Instantiation
155616: 13/07/30: Re: seperate high speed rules for HDL?
155868: 13/10/08: Re: Granularity of components for FPGA synthesis?
157321: 14/11/21: Re: Program IO 1.2V
<muzaffer@dspia.com>:
29639: 01/03/03: Re: Interfacing Xilinx 4003 to an IDE Hard Disk interface.
30082: 01/03/22: frequency measurement?
30090: 01/03/23: Re: TBUFs in Virtex and later chips, going out of fashion, what instead
31065: 01/05/10: Re: Spartan Annoyances
31575: 01/05/30: RLOC'in Virtex-II FDCs???
<muzaffer@kal.st>:
36996: 01/11/28: Re: What is a difference?
muzo:
1667: 95/08/13: verilog to fpga ?
1801: 95/09/05: looking for fpga burn and PCB design house in BA
2648: 96/01/19: good interview questions ?
3093: 96/03/30: Re: Sq. Roots and Languages
3119: 96/04/07: ISA Plug & Plug models ?
6861: 97/07/03: Altera MaxPlus2 verilog HIERARCHICAL writer ?
7123: 97/08/03: pin placement in Max+plus2 ?
7703: 97/10/04: Altera MAX+PLUS 2 timing backannotation problem
7949: 97/11/01: Synopsys FPGA Express and Altera 10K design
8402: 97/12/12: bus design in Altera 10K, how to increase speed
8531: 98/01/06: Synopsys FPGA Express vs Exemplar Leonardo
8853: 98/02/02: ISA bus vectors
9426: 98/03/13: Altera Flex10K register initialization confusion
9586: 98/03/25: Re: USB bus interface (12 mbit/sec) in an FPGA - how difficult?
9945: 98/04/15: Re: Synplicity
11615: 98/08/26: OLE automation access to WorkViewOffice or ViewDraw ?
11633: 98/08/27: Re: SYNTHESIS TOOLS
11639: 98/08/27: Re: FPGA Manufacturer's gate counts
11756: 98/09/07: Re: Altera 10K20 Register File Implementation??
12254: 98/10/06: Re: FIR Filter Design
12177: 98/10/02: Re: Verilog Simulators
12272: 98/10/07: Re: Verilog Simulators
12623: 98/10/20: Re: Schematic entry?
12631: 98/10/20: Re: gray code counter in a Xilinx fpga???
12717: 98/10/24: Re: Looking for Love in ALL the Wrong Places???
12957: 98/11/06: Re: FPGA on ASIC (Was: Re: New free FPGA CPU)
12961: 98/11/07: Re: FPGA on ASIC (Was: Re: New free FPGA CPU)
12968: 98/11/08: Re: FPGA on ASIC (Was: Re: New free FPGA CPU)
13116: 98/11/16: Re: Big-Endian vs Little-Endian
13250: 98/11/21: Re: Big-Endian vs Little-Endian
14805: 99/02/17: virtex vs apex ?
15238: 99/03/15: Re: How can I improve an adder?
15884: 99/04/18: Re: How to write BIDIR IO in MAXPLUS2 VHDL ?
16089: 99/05/01: 10KE dual port RAM help ?
16120: 99/05/04: Re: 10KE dual port RAM help ?
16131: 99/05/05: Re: 10KE dual port RAM help ?
16471: 99/05/24: virtex vs apex20k family comparison for DSP ?
16789: 99/06/08: Re: ALtera 20KE LVDS IO
17156: 99/07/05: Re: Q: Floating point on fpga?
17432: 99/07/27: Re: NRZ Deserializing in Virtex
17516: 99/08/04: ECL IO to Virtex or APEX ?
17666: 99/08/21: synthesis comparion between Synplify and FPGA express
17707: 99/08/25: Re: Parallel in Serial out
17866: 99/09/14: Re: Opinions Wanted
18237: 99/10/08: Re: Capacity metrics for Virtex
18555: 99/10/30: which Xilinx package for Virtex ?
19231: 99/12/07: Re: TIme Delay 1us-100ms
19913: 00/01/17: Re: Viterbi decoder in FPGA
21012: 00/03/02: Re: New name: DLLs, PLLs and videotape...
21038: 00/03/03: Re: EDA tools
21559: 00/03/24: Re: No- FPGA openness
21560: 00/03/24: Re: FPGA openness
21615: 00/03/26: Re: FPGA openness
21616: 00/03/26: Re: FPGA openness
muzok:
5153: 97/01/27: FPGAs with internal Tri-state busses ?
MV:
<mvaria@gmail.com>:
116475: 07/03/09: Re: Altera PowerPlay Power estimation
<mvarman@gmail.com>:
122718: 07/08/04: Xilinx XC4VLX40-10FFG1148C - Available New
mvetromille:
88447: 05/08/18: Two microblaze in EDK
90052: 05/10/03: Problems in simulating EDK system
90972: 05/10/26: SDRAM in EDK
90979: 05/10/26: Re: SDRAM in EDK
<mvjijuaie@gmail.com>:
130455: 08/03/24: AWGN in vhdl
mw:
14868: 99/02/22: Re: Eval Activ-VHDL only for 30 day :(
<mwiesbock@gmail.com>:
87649: 05/07/27: wishbone core with ethernet, hierarchy / architecture
113837: 06/12/24: Signal <foo> is assigned but never used. XST Warning help
117083: 07/03/22: Xilinx Virtex-4 Embedded Ethernet Wrapper IP Core - HELP with UCF
117084: 07/03/22: Re: Xilinx Virtex-4 Embedded Ethernet Wrapper IP Core - HELP with UCF
117279: 07/03/27: Re: Xilinx Virtex-4 Embedded Ethernet Wrapper IP Core - HELP with UCF
117281: 07/03/27: Re: Xilinx Virtex-4 Embedded Ethernet Wrapper IP Core - HELP with UCF
mwrew:
72094: 04/08/08: Xilinx Student Edition 6.x?
mx:
70935: 04/07/02: Re: *RANT* Ridiculous EDA software "user license agreements"?
MX:
<mx3000@my-deja.com>:
17617: 99/08/15: VHDL/Verilog? - Can of Worms
<mxrpwx@starmedia.com>:
15627: 99/04/04: DO YOU BELIEVE IN REINCARNATION? 9284
My Name:
138448: 09/02/23: Fm digital baseband demodulation
138501: 09/02/25: Re: Fm digital baseband demodulation
138510: 09/02/25: Re: Fm digital baseband demodulation
<1209@my-deja.com>:
21030: 00/03/03: Re: BEHAVIOURAL VHDL
21029: 00/03/03: Synplicity for sale
my.king:
99174: 06/03/21: Ace file for design with dual ppc405
99426: 06/03/24: Re: Ace file for design with dual ppc405
99843: 06/03/29: Re: Ace file for design with dual ppc405
104516: 06/06/29: EDK: Using DCR bus on ML310-based project
104688: 06/07/04: Re: EDK: Using DCR bus on ML310-based project
<myemail@any.where.com>:
7849: 97/10/23: Work at Home
11962: 98/09/21: The Ultimate Southpark CD-ROM
mygenie:
29489: 01/02/23: Help : Question about Synopsis
myke hats:
24147: 00/07/27: 2 bios
Mykola Kyrylenko:
32298: 01/06/22: Xilinx WebPack schematic capture - OBUFE8 fault
mynewlifever@yahoo.com.cn:
100080: 06/04/03: =?iso-8859-1?q?Re:_how_to_read_this_book=AB_Digital_integrated_circuits.a_design_perspective(Second_Edition)=BB?=
116723: 07/03/16: How to generate sgmii interface?
117768: 07/04/10: Why I cannot use the XAUI core(generated by xilinx)
127210: 07/12/14: xilinx v5 configeration problem
130011: 08/03/12: Using xilinx XAUI core in Ethernet design. What is the exact frame
136288: 08/11/09: How to handle the problem "timing constraint not met"?
136312: 08/11/10: Re: How to handle the problem "timing constraint not met"?
136313: 08/11/10: Re: How to handle the problem "timing constraint not met"?
<mynewlifever@yahoo.com.cn>:
99824: 06/03/29: =?iso-8859-1?q?how_to_read_this_book=AB_Digital_integrated_circuits.a_design_perspective(Second_Edition)=BB?=
myren:
67430: 04/03/11: where to start for going high bandwidth [was: next learning platform]
68441: 04/04/05: minimum software for virtex II pro
myren, lord:
69581: 04/05/14: Re: virtex dev board?
myself:
18840: 99/11/18: analog capabilities?
19065: 99/11/26: Re: Analog
19795: 00/01/12: hc11 core & fpga or cpld
20921: 00/02/28: atmel fpga starter kit
20936: 00/02/29: Re: atmel fpga starter kit
21836: 00/04/03: Xilinx student edition, version 1.5
21854: 00/04/04: Re: Xilinx student edition, version 1.5
22440: 00/05/09: Xilinx fpga board schematics?
22570: 00/05/12: Re: Xilinx fpga board schematics?
22583: 00/05/12: Re: Future of FPGAs?
22789: 00/05/24: Simple 256k Dram tester code?
22949: 00/06/05: 3.3V I/O TO 5V LOGIC?
22965: 00/06/06: Re: 3.3V I/O TO 5V LOGIC?
23330: 00/06/22: Re: Looking for 'FREE' FPGA software
23369: 00/06/23: What tools do people use for Xilinx FPGAs?
<myusenetacct@gmail.com>:
91474: 05/11/07: What does @ mean in EDIF?
<myx2@gmx.de>:
131263: 08/04/17: DMA in PLB custom core (XilinxV4)
mz:
11844: 98/09/13: Re: 16 bit CRC
MZurlo4054:
13028: 98/11/12: Re: Problem with the ABEL to Macro convertion in XILINX FB1.3
Márcio Longaray:
21372: 00/03/20: Re: Beginner's Guide
22165: 00/04/28: DSP (FPGA) description
24018: 00/07/23: Need MP3 decoder souce
29388: 01/02/18: Samll quantities ordering
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