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Hi, I'm trying to script a hardware co-sim design in Matlab (m-code). I'm using locable shared memories throughout for reading and writing. My co-sim wrapper reads a frame, feeds it to a wishbone-compliant core, and write back results. The API examples included in SysGen don't use locable memories. It is not clear also what should the cosim sequence be in this case and what functions to use. The LocableSharedMemory class documentation towards the end of SysGen reference guide describes the mex interface but not the Matlab one. I'm a bit confused and not exactly sure about the locable case. For instance, the m-code Shmem class has a method _release()_ in addition to the default constructor. The mex class, on the other hand, has _acquireLock()_ and releaseLock()_ which I'd initially thought to be the way for sequencing the operation. I would be most grateful for any input on this, -MArticle: 140401
"HT-Lab" <hans64@ht-lab.com> wrote in message news:3NSNl.25634$i%2.21137@newsfe15.ams2... > We used military grade Actel A1010, A1020 and 1280 and they all worked > great but then again we launched into a quite a "mild" radiation orbit > (LEO,800KM), > Hans While I'm not directly involved in building space circuits (I'm a systems guy), our company (BAE Systems) does a lot of radiation-hard space electronics. It's a tricky business. In fact, Actel has stopped making the space-qualified 1280 and instead our foundry now makes a fully rad-hard version called the RH1280 under an Actel license. If I'm not mistaken, most of those Actel parts are program-once (PROM-based) FPGAs, not flash or EEPROM. Very stable usually, though there was an issue about 5 years ago where some of the "blown" fuses started conducting again and changed the program...very scary for $$$ space programs. I don't know if it affected launched parts or was found in a few non-flight samples that were stress tested. Anyway, regarding the OP's question, it depends greatly on whether you can deal with an SEU (Single Event Upset) smoothly (e.g., detect a fault, scrub the program, and restart) and whether the underlying circuits are latchup-resistant. I'm fairly sure that quite a few of the non-QV Virtex family parts have been flown in short LEO missions, but I don't know the details (Austin has posted regarding these questions in the past). NASA runs a lot of conferences etc. that can help provide data...IIRC klabs.org (maybe without the s) is a site they sponsor. Good luck, MartyArticle: 140402
On May 12, 1:34=A0pm, Dave <dhsch...@gmail.com> wrote: > I have an ML403 devkit and am attempting to program the XCF32P by bit- > banging the JTAG interface from a microcontroller devboard. My problem > is that the FPGA does not want to configure with from the PROM when I > load it this way. I have tried to troubleshoot the issue and found the > following: > > 1. If I program the flash using iMPACT, erase Revision 0 (the only one > I'm using), and then program Revision 0 from the microcontroller, the > FPGA will configure successfully. When performing this test, I do > verify that Revision 0 was successfully erased before I re-program it. > > 2. If I erase the entire flash, program the relevant registers (DATA- > BTC, DATA-CCB, DATA-SUCR, and DONE), and then program Revision 0, the > FPGA will NOT configure successfully. I have read out the > configuration data as well as the non-data registers to verify they > are identical to what is programmed via iMPACT. > > I can use iMPACT in my development environment but the final system > will not have external access to the JTAG pins and so I need to find a > way to program the flash from an initially blank state. Does anyone > have any ideas why Method 2 is not working or other troubleshooting > measures I can take? Is there a specific instruction sequence or > timing restriction that must be adhered to even though all the > registers and data seem correct? I suggest you try writing DONE after writing the PROM data. You may also want to generate an SVF using iMPACT and compare the command sequences. Good luck, MikeArticle: 140403
On May 13, 12:47=A0am, mng <michael.jh...@gmail.com> wrote: > On May 12, 1:34=A0pm, Dave <dhsch...@gmail.com> wrote: > > > > > I have an ML403 devkit and am attempting to program the XCF32P by bit- > > banging the JTAG interface from a microcontroller devboard. My problem > > is that the FPGA does not want to configure with from the PROM when I > > load it this way. I have tried to troubleshoot the issue and found the > > following: > > > 1. If I program the flash using iMPACT, erase Revision 0 (the only one > > I'm using), and then program Revision 0 from the microcontroller, the > > FPGA will configure successfully. When performing this test, I do > > verify that Revision 0 was successfully erased before I re-program it. > > > 2. If I erase the entire flash, program the relevant registers (DATA- > > BTC, DATA-CCB, DATA-SUCR, and DONE), and then program Revision 0, the > > FPGA will NOT configure successfully. I have read out the > > configuration data as well as the non-data registers to verify they > > are identical to what is programmed via iMPACT. > > > I can use iMPACT in my development environment but the final system > > will not have external access to the JTAG pins and so I need to find a > > way to program the flash from an initially blank state. Does anyone > > have any ideas why Method 2 is not working or other troubleshooting > > measures I can take? Is there a specific instruction sequence or > > timing restriction that must be adhered to even though all the > > registers and data seem correct? > > I suggest you try writing DONE after writing the PROM data. You may > also want to generate an SVF using iMPACT and compare the command > sequences. > > Good luck, > Mike Actually, I take that back. How do you generate a file to program the PROM? I don't use the ML403, but have board with XCF08P and XCF32P which are programmed with emulated JTAG. I use the dialog to generate an MCS _using revisioning_, even though only rev 0 is used. Cheers, MikeArticle: 140404
On May 11, 4:29=A0pm, pe...@xilinx.com wrote:
> On May 11, 12:43=A0pm, Mark <m...@cacurry.net> wrote:
>
>
>
> > I know I'm a little late on this thread, but offer my two cents,
> > on what we use, and a warning as well.
>
> > We use dual-port RAMS (same clock) with inference, and don't have
> > trouble. =A0It's in verilog, and it's READ_FIRST. =A0So two strikes
> > against it for what you're looking for Rick. =A0(you want VHDL, and
> > WRITE_FIRST, I beleive). =A0We call this our "mem2rw1clk" module.
>
> > But here's what we do (minus header/etc):
>
> > always @( posedge clk )
> > begin
> > =A0 if( en0 )
> > =A0 begin
> > =A0 =A0 if( wren0 )
> > =A0 =A0 =A0 mem[ addr0 ] <=3D wdata0;
> > =A0 =A0 rdata0 <=3D mem[ addr0 ];
> > =A0 end
> > end
>
> > always @( posedge clk )
> > begin
> > =A0 if( en1 )
> > =A0 begin
> > =A0 =A0 if( wren1 )
> > =A0 =A0 =A0 mem[ addr1 ] <=3D wdata1;
> > =A0 =A0 rdata1 <=3D mem[ addr1 ];
> > =A0 end
> > end
>
> > So, two almost identical always blocks, operating on the same RAM.
> > Since we use non-blocking assignments, the READ_FIRST is implied
> > (correctly by XST).
>
> > Works, and we've been using it for many designs no trouble.
>
> > Now the warning:
>
> > We use almost the EXACT same structure for implementing a pseudo
> > dual port - i.e. an independant READ port, and a WRITE port
> > (same clock) "mem1r1w1clk". =A0 =A0I.e. the type of memory you'd
> > use for a synchronous fifo. =A0The logic is again clearly coded for
> > READ_FIRST.
>
> > Well, XST was (sometimes) inferring WRITE_FIRST. =A0So, simulation
> > vs implementation mismatch. =A0It only mattered in a few places
> > we were specifically ALWAYS reading the same location as we
> > were writing in the same cycle. You get quite different results.
> > Spent 2-3 weeks on the bench figuring out this one.
>
> > So - check the XST report to make sure it's inferring the
> > correct READ_FIRST vs. WRITE_FIRST behaviour. =A0XST can get things
> > wrong here.
>
> > Regards,
>
> > Mark
>
> I am surprised about the interest in write_first vs read_first.
> The read output during a write operation came really about as an
> afterthought. ("It's easy, the port is already there, so it costs
> nothing").
> But why do you want to read from the same location that you are
> writing to?
> Especially when you are reading what you already know, since you
> simultaneously are writing it (which was the original mode).
> Then we found that read-before-write was an easy modification, and
> more valuable.
> But still: why do you read from the write address, when you have a
> separate read port with its own dedicated addressing available?
>
> But, judging from the interest in this thread, it seems to be
> valuable.
> Peter Alfke
That's easy. In my case I am using the ram as a stack, two actually.
Each port has to read whatever was last written because it does *not*
have an independent read port and the read data has to reflect the top
of the stack at all times. The ram is shared as two stacks to save
space since the entire depth of the block ram is not needed.
Thinking that the read port does not need to reflect the last written
data is a very limited perspective. *I* may know what was written,
but whatever is connected to the read port does not know it unless the
read port reflects it.
Rick
Article: 140405On May 12, 11:13=A0pm, lolita.tang...@gmail.com wrote: > i tried a description of RAM but i can't syntesize it and i have > the following error: > > ERROR:Pack:18 - The design is too large for the given device and > package. > > i think i will be to use the external SRAM FPGA's board, but i don't > know if i can use it without EDK and how i can read and write in this > SRAM. it's easy to read or write sram using fpgaArticle: 140406
Hi, I want to implement 100 Mbps ethernet MAC with a 1000/100/10 PHY capable PHY that is by default set to 1000Mbps. I have connected the RGMII interface and MDIO interface but i dont know how to put this PHY into auto negotiation mode or force it to run on 100 Mbps. Please guide in this regard. i.e. (which MDIO register i should write to control this thing). AitezazArticle: 140407
On 12 Mai, 17:13, lolita.tang...@gmail.com wrote: > i tried a description of RAM but i can't syntesize it and i have > the following error: > > ERROR:Pack:18 - The design is too large for the given device and > package. > > i think i will be to use the external SRAM FPGA's board, but i don't > know if i can use it without EDK and how i can read and write in this > SRAM. Hi lolita, You didn't tell us how much RAM you need and which FPGA you are about to use. Generally, RAM inside an FPGA is quite limited. Take a look at the datasheet how much BlockRAM and distributed RAM are available in your chosen device and keep in mind, that distributed RAM consumes LUTs so minimizes the ressources for the rest of your design. Do these calculations before you implement anything. On using external SRAM: If you have an ordinary design, you don't need EDK to use SRAM. Simply connect your address lines of your design to the FPGA pins where the SRAM adresses are, and do the same for data and control lines. that's it You will find that information in the board documentation if you buy some board "of the shelf". If you are doing some MicroBlaze design, you are using EDK anyway and for the microblaze EDK comes with an IP-Core to connect MB and SRAM. Still you need to update your UCF file to connect to the right pins. Have a nice synthesis EilertArticle: 140408
On May 13, 7:46=A0am, aitezaz....@gmail.com wrote: > Hi, > I want to implement 100 Mbps ethernet MAC with a 1000/100/10 PHY > capable PHY that is by default set to 1000Mbps. I have connected the > RGMII interface and MDIO interface but i dont know how to put this PHY > into auto negotiation mode or force it to run on 100 Mbps. Please > guide in this regard. i.e. (which MDIO register i should write to > control this thing). > > Aitezaz Aitezaz, What about reading the datasheet of your phy? Anyway, for the 100/10 Phy the clause 22 of the 802.3 standard does require the register 0 bit 13 set the speed, (10 or 100) bit 12 enable/disable autonegotiation bit 8 set the duplex mode For your 1000/100/10 phy but please read the datasheet SandroArticle: 140409
Hi! Anyone here worked with these asynchronous FPGAs already? I wonder what the prices are. It doesn't look like the tool-flow will be for free, since they use Synplify Pro or Precision for synthesis. But I'd love to see the performance of one of our designs on the their FPGAs.. If only have of the promises are true this would be really great! MatthiasArticle: 140410
Wanted to say: If only half of the promises are true this would be really great!Article: 140411
On May 12, 5:21 pm, Muzaffer Kal <k...@dspia.com> wrote: > By looking at your name of the pad (and assuming there is a clk200_p) > I'm assuming you want differential IO. If that's the case you need to > add a property to your UCF file marking them so ie LVPECL etc. All, thank you for your answers. Yes, I'm using differential clock signals. I've checked also the pins once more, they're correct. I incline to thinking that there's an important constraint in the UCF file missing. The problem is I don't know the constraint which needs to be added (I'm not very familiar with Xilinx yet). In the UCF file I have specified the NET-LOC constraints as well as IOSTANDARD definition. For clock inputs I used LVPECL_25: NET "clk200_n" IOSTANDARD = LVPECL_25; Then, I added DIFF_TERM (please, don't ask why, I've found in Google): NET "clk200_n" IOSTANDARD = LVPECL_25 | DIFF_TERM = TRUE; The result is the same as before (identical error message). If it can help, the Target Device is xc5vsx95t (Virtex-5 family). MR :/Article: 140412
On May 13, 11:31=A0am, Sandro <sdro...@netscape.net> wrote: > On May 13, 7:46=A0am, aitezaz....@gmail.com wrote: > > > Hi, > > I want to implement 100 Mbps ethernet MAC with a 1000/100/10 PHY > > capable PHY that is by default set to 1000Mbps. I have connected the > > RGMII interface and MDIO interface but i dont know how to put this PHY > > into auto negotiation mode or force it to run on 100 Mbps. Please > > guide in this regard. i.e. (which MDIO register i should write to > > control this thing). > > > Aitezaz > > Aitezaz, > What about reading the datasheet of your phy? > Anyway, for the 100/10 Phy the clause 22 of the 802.3 standard > does require the register 0 > =A0 bit 13 set the speed, (10 or 100) > =A0 bit 12 enable/disable autonegotiation > =A0 bit 8 set the duplex mode > For your 1000/100/10 phy but please read the datasheet > > Sandro Thanks Sandro for help. The board is using BCM5464SR (on NETFPGA) whose datasheet doesn't tell anything about it. But as you written the standard name, I have found the registers in the standard. Thank you again AitezazArticle: 140413
Hi, I am trying to run 100 Mbps PHY on NETFPGA card. The NETFPGA card uses BCM5464SR PHY and gives us the control of its registers using MDIO. The changes I have made to make it work are as follows. i). I am using the rgmii_20_if.v rgmii version 2.0 verilog file generated by Xilinx. ii). I am using a transmit clock of 25 MHz instead of 125 MHz. But I am unable to make it run on 100 Mbps. I have tried both the Autonegotiation mode and speed setting but to no avail. Any ideas if i'm missing something Thanks for your time AitezazArticle: 140414
Did you add the correct buffer from the Xilinx Unisim library to your HDL code? As you are using a differential signal/LVPECL standard you should add the ibufgds_lvpecl_25 to the HDL code and connect it to the clk_200 signals. Devas -- devas ------------------------------------------------------------------------ devas's Profile: http://www.fpgacentral.com/group/member.php?userid=84 View this thread: http://www.fpgacentral.com/group/showthread.php?t=90004Article: 140415
lolita.tangier@gmail.com writes: > i tried a description of RAM but i can't syntesize it and i have > the following error: > > ERROR:Pack:18 - The design is too large for the given device and > package. > > i think i will be to use the external SRAM FPGA's board, but i don't > know if i can use it without EDK and how i can read and write in this > SRAM. You'll have to put an external memory interface into your design. You may or may not realise, so I'll point it out - XPS won't magically take your large RAM and put some of it into external memory, you'll have two RAM elements (assuming you keep a smaller version of your current memory) and you'll have to use the software linker file to allocate different parts of your data to those blocks. And if you want to put code or initialised data in the external SRAM you'll need a bootloader system to pull the initialisation data out of your configuration device (or somewhere else non-volatile). Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 140416
Hi we have a problem, namly Xilinx driver will DIE on ASSERT if fiber is not connected at boot time this happens inside the Xilinx driver init code, what does never return in such case, while maybe not a real bug as such, it is annoying and unacceptable way, any problem during init should return some error so our toplevel code could retry the init at later time. is the only workaround to go patch and fix Xilinx drivers again? the code is from 10.1, we do not want to upgrade to 11.1 after all the pain of upgrade to 10.1 AnttiArticle: 140417
I'm looking at a possible application and trying to figure the relative costs of FPGA/CPLD versus MCU. I can do it with a microcontroller, but the only MCUs with the hardware I need (TFT LCD controller) tend to come with lots of other stuff (ethernet, large flash, USB etc.) which I don't need. As it can be hard to get 'real' prices of FPGAs without talking to all the distis etc. I wonder if anyone can suggest parts to look at . Rough reqiurement is : Cheapest in 100x qtys for total solution inc. config and power supply ( from 3.3v supply), below about GBP5(US$7.5) Not BGA Readly available : ex-stock or sensible leadtimes (2 weeks) A couple of RAM blocks, around 1K byte each about 60 IOs, all 3.3v 30MHz clock Logic equivalent to around 100 CPLD macrocells Free or low cost (<$500) design software The Xilinx S3A/AN-50 is the cheapest I've found so far, but is a a bit over-specced. CPLDs seem to get expensive above 72 cells and don't tend to have RAMArticle: 140418
On May 13, 1:23=A0pm, Mike Harrison <m...@whitewing.co.uk> wrote: > I'm looking at a possible application and trying to figure the relative c= osts of FPGA/CPLD versus > MCU. > I can do it with a microcontroller, but the only MCUs with the hardware I= need (TFT LCD controller) > tend to come with lots of other stuff (ethernet, large flash, USB etc.) w= hich I don't need. > > As it can be hard to get 'real' prices of FPGAs without talking to all th= e distis etc. I =A0wonder if > anyone can suggest parts to look at . > > Rough reqiurement is : > > Cheapest in 100x qtys for total solution inc. config and power supply ( f= rom 3.3v supply), below > about GBP5(US$7.5) > Not BGA > Readly available : ex-stock or sensible leadtimes (2 weeks) > A couple of RAM blocks, around 1K byte each > about 60 IOs, all 3.3v > 30MHz clock > Logic equivalent to around 100 CPLD macrocells > Free or low cost (<$500) design software > > The Xilinx S3A/AN-50 is the cheapest I've found so far, but is a a bit ov= er-specced. > CPLDs seem to get expensive above 72 cells and don't tend to have RAM the IC you need is always the one that doesnt exist ;) S3-50AN prices do go below 4$ but not at 100x qty. in 100x qty, it proabably more than your target price 7.5 (depend how good you deal..) Xilinx disties say: leadtime 12 weeks, call for order Digikey has 4 pcs in stock if you can deal with 2 KB RAM, then lattice EC1 is 6.1$ online price available in stock, need spi flash, but it still cheap total price but here XC3S50A would be better at about same price Lattice XP3 is too expensive with online pricing.. $10, stock YES, this is the IC that needs NO Externals, no flash, no LDO, just 3.3V ! Actel A3P060, is cheap, but again 2K RAM only all the above have free tools Altera doesnt seem to have devices that come to your desired price range hm.. call lattice disti, say you would like XP3-VQ100, but your BOM limit is 7.5$ see what they say !! if price doesnt come down, place xc3s50a-vq100 order on digikey, to secure your devices before those are gone too (disties have no stock. leadt=3D12w) AnttiArticle: 140419
Mike Harrison <mike@whitewing.co.uk> writes: > The Xilinx S3A/AN-50 is the cheapest I've found so far, but is a a bit over-specced. > CPLDs seem to get expensive above 72 cells and don't tend to have RAM I've used the Altera MAX-II a couple years ago and seem to remember that they were pretty cheap. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 140420
I've encoutered the aforementioned error while compiling not my own code, but code obtained from Core Generator, in which I made some modifications... The code seems to use the unisim library. MRArticle: 140421
On 2009-05-09, Richard Pennington <rich@pennware.com> wrote: >> I'm wondering whether to use 10/100 Ethernet and CAN controller chips >> (two of each) in a new design or just put cores from OpenCores inside >> an FPGA (which we will need in both cases). I'm (still) new to FPGA's >> and have never used cores from OpenCores. Has anybody used these cores? >> Are they reliable and ready for production use? > > Whose FPGA are you using? We are going to use Altera Cyclone III (if possible, since we have used these chips before). -jmArticle: 140422
On May 13, 6:23=A0am, Mike Harrison <m...@whitewing.co.uk> wrote: > The Xilinx S3A/AN-50 is the cheapest I've found so far, but is a a bit ov= er-specced. > CPLDs seem to get expensive above 72 cells and don't tend to have RAM You might want to take a look at the following devices: Lattice Semi - MachXO Lattice Semi - Lattice XP / XP2 Altera - Cyclone II / III Xilinx - Spartan 3A/AN Silicon Blue - iCE 65 The MachXO looks to be exactly what you are after, although I don't know what they cost. The Lattice tools come with an Synplify OEM bundled, but I don't know what they cost or if older versions are available for free. Hope that helpsArticle: 140423
Hi, I used VIRTEX-5 DSP48E slice in order to implement a high speed logic design which involves 3 parallel multiply-add logic.I need to operate the design in to about 500MHz. When using single multiply-add unit, i got the required frequency. But the issue is when using multiple multiply-add unit. Also when i gave inputs directly without using I/O pads(ie hard coding input values), i got maximum operating frequency as 500 MHz.So any one please suggest an idea to avoid this issue and to get maximum operating frequency. Thanxs in advanceArticle: 140424
Hi, Please help in connecting two bidirectional pins (A,B)of an FPGA. The data lines should connect A to B when write enable is low. The data lines should connect B to A when read enable is low. let me know your inputs.
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