Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
On Wed, 13 May 2009 12:36:26 -0700 (PDT), rickman <gnuarm@gmail.com> wrote: >On May 13, 1:45 pm, Mike Harrison <m...@whitewing.co.uk> wrote: >> On Wed, 13 May 2009 03:58:40 -0700 (PDT), "Antti.Luk...@googlemail.com" >> >> >> >> <Antti.Luk...@googlemail.com> wrote: >> >On May 13, 1:23 pm, Mike Harrison <m...@whitewing.co.uk> wrote: >> >> I'm looking at a possible application and trying to figure the relative costs of FPGA/CPLD versus >> >> MCU. >> >> I can do it with a microcontroller, but the only MCUs with the hardware I need (TFT LCD controller) >> >> tend to come with lots of other stuff (ethernet, large flash, USB etc.) which I don't need. >> >> >> As it can be hard to get 'real' prices of FPGAs without talking to all the distis etc. I wonder if >> >> anyone can suggest parts to look at . >> >> >> Rough reqiurement is : >> >> >> Cheapest in 100x qtys for total solution inc. config and power supply ( from 3.3v supply), below >> >> about GBP5(US$7.5) >> >> Not BGA >> >> Readly available : ex-stock or sensible leadtimes (2 weeks) >> >> A couple of RAM blocks, around 1K byte each >> >> about 60 IOs, all 3.3v >> >> 30MHz clock >> >> Logic equivalent to around 100 CPLD macrocells >> >> Free or low cost (<$500) design software >> >> >> The Xilinx S3A/AN-50 is the cheapest I've found so far, but is a a bit over-specced. >> >> CPLDs seem to get expensive above 72 cells and don't tend to have RAM >> >> >the IC you need is always the one that doesnt exist ;) >> >> >S3-50AN prices do go below 4$ but not at 100x qty. >> >in 100x qty, it proabably more than your target price 7.5 (depend how >> >good you deal..) >> >> >Xilinx disties say: leadtime 12 weeks, call for order >> >Digikey has 4 pcs in stock >> >> >if you can deal with 2 KB RAM, then lattice EC1 is 6.1$ online price >> >available in stock, need spi flash, but it still cheap total price >> >> >but here XC3S50A would be better at about same price >> >> >Lattice XP3 is too expensive with online pricing.. $10, stock YES, >> >this is the IC that needs NO Externals, no flash, no LDO, just 3.3V ! >> >> >Actel A3P060, is cheap, but again 2K RAM only >> >> >all the above have free tools >> >Altera doesnt seem to have devices that come to your desired price >> >range >> >> >hm.. call lattice disti, say you would like XP3-VQ100, but your BOM >> >limit is 7.5$ see what they say !! >> >> >if price doesnt come down, place xc3s50a-vq100 order on digikey, to >> >secure your devices before those are gone too (disties have no stock. >> >leadt=12w) >> >> >Antti >> >> Thanks for the suggestions - the Lattice EC1 looks a pretty good fit on all counts - RAM is 'only >> just' enough, but means I'm not paying for stuff I don't need. >> >> I even found a cheap eval board for it :http://www.msc-toolguide.com/latticeec-low-cost-evaluation-board.html > >I had to do this same search last year and I found very little that >would suit my needs... in fact, I found exactly one part that really >was suited to the job. The problem you will find with most parts is >not actually the price of the part itself, but rather the price of the >package. The FPGA vendors will attest to the fact that the pricing of >these parts at the low end is mostly governed by testing which is in >tern dominated by the cost of testing the I/Os. So the lower the pin >count, the cheaper the part. And nobody seems to do low pin-count FPGAs, and CPLDs seem to have a big price jump above 72 macrocells which I've never quite understood - there appears to be a gaping hole between the $2 CPLD and the $8ish FPGA. > I remember that some ram based FPGA vendors would jump up and down and >insist that ram was the only way to go when considering the advantages >of die size and how it would impact the cost. I guess that really is >not the whole picture is it? Well the pricing of S3A+SPI flash compared to S3AN seems to support this... Single-chip and single-supply are nice, but not if the additional cost is several times that of external regulator/flash! >The only issue may be availability, but then I have never found *any* >FPGA that they maintain significant amounts of stock at all times. >Mouser sells Lattice, but the inventory is mostly at Lattice and is >drop shipped. Farnell also list several Lattice devices, so availability appears to at least be better than Xilinx.Article: 140451
On May 13, 10:23=A0pm, Mike Harrison <m...@whitewing.co.uk> wrote: > I'm looking at a possible application and trying to figure the relative c= osts of FPGA/CPLD versus > MCU. > I can do it with a microcontroller, but the only MCUs with the hardware I= need (TFT LCD controller) > tend to come with lots of other stuff (ethernet, large flash, USB etc.) w= hich I don't need. If you can find a chip that does the task, that's normally going to be cheaper than a FPGA. (even with unused bits ) Or, find a uC that is close, and add a smaller Prog Logic device to stretch the peripherals. Streaming SPI-CPLD can add quite smart 'external peripherals'. The uC have Code-flash built in, as well as Analog features. > > As it can be hard to get 'real' prices of FPGAs without talking to all th= e distis etc. I =A0wonder if > anyone can suggest parts to look at . > > Rough reqiurement is : > > Cheapest in 100x qtys for total solution inc. config and power supply ( f= rom 3.3v supply), below > about GBP5(US$7.5) > Not BGA > Readly available : ex-stock or sensible leadtimes (2 weeks) > A couple of RAM blocks, around 1K byte each > about 60 IOs, all 3.3v > 30MHz clock > Logic equivalent to around 100 CPLD macrocells > Free or low cost (<$500) design software > > The Xilinx S3A/AN-50 is the cheapest I've found so far, but is a a bit ov= er-specced. > CPLDs seem to get expensive above 72 cells and don't tend to have RAM The two choices do not really seem to overlap here ? - you have a quite small logic block, and no mention of any processor on the 2nd choice ? 100 macrocells is viable in CPLD (384/512 tend to not stack up), and a device like ATF1508RE (128MC 3.3V SingleSupply) is $3.90/100+ at Digikey. You may be able to add SPI RAM - 32Kx8 is $1.09/100+Article: 140452
Hi, I'm trying to find an open source processor as a basis for a research, preferably it is in VHDL and implements a 5-stage RISC pipeline with bypassing (exceptions are not a concern), of course if you know of any processor with a clean 5-stage pipeline with bypassing, please let me know. It would be awesome if it implements the MIPS ISA. I've tried the open cores website, and have looked at 2 MIPS ISA implementations: Plasma and miniMIPS. Problem is Plasma does not deal with bypassing and is not a 5-stage pipeline, and miniMIPS is rather weird, it process instructions every other cycle, so it would process, then it would pause everything on the next cycle. So I'm wondering maybe there would be someone out there on the internets that know about this, please help me out :) Thanks! Regards, David.Article: 140453
On May 14, 3:29=A0am, DH <dh1...@gmail.com> wrote: > Hi, > > I'm trying to find an open source processor as a basis for a research, > preferably it is in VHDL and implements a 5-stage RISC pipeline with > bypassing (exceptions are not a concern), of course if you know of any > processor with a clean 5-stage pipeline with bypassing, please let me > know. It would be awesome if it implements the MIPS ISA. > > I've tried the open cores website, and have looked at 2 MIPS ISA > implementations: Plasma and miniMIPS. > Problem is Plasma does not deal with bypassing and is not a 5-stage > pipeline, and miniMIPS is rather weird, it process instructions every > other cycle, so it would process, then it would pause everything on > the next cycle. > > So I'm wondering maybe there would be someone out there on the > internets that know about this, please help me out :) Thanks! > > Regards, > David. try also http://yari.thorn.ws/YARI/Introduction.html it is now useable for Xilinx too, (prev versions only compiled with quartus) AnttiArticle: 140454
On 2009-05-14, acd <acd4usenet@lycos.de> wrote: > I think this second step should be easily doable with XSLT if the > netlist is represented as XML. > I wonder if there are existing formats and tools to do this. I would look at the kind of formats that commercial synthesis tools output. This is most likely going to be some sort of EDIF based format. I know that Precision outputs EDIF files when synthesizing to Xilinx and I guess that other vendors' backend tools can handle EDIF inputs as well. Another choice if you are targetting Xilinx is XDL, although that is a bit more low level (you will have to map LUTs into slices before you can use XDL). /AndreasArticle: 140455
>jayantbala <jayantbala@gmail.com> wrote:
>(snip)
>
>< but for this purpose i dont want to implement TCP/IP
>< .i just simply want to send and receive MAC Packets i.e
>< preamble+Destination Address+source address+type+data+FCS
>
>For type X'0800' that will be hard on many systems.
>
>If you don't need or want TCP, can you use UDP?
>It is a very simple header to add and then send it out.
>
>Receivers can ignore the header, if that is easier, though
>they should probably verify the IP address.
>
>-- glen
>
thank you glen.
I am using XP with intel machine .glen the thing is that i even dont
want
UDP also. cant i write few lines of code in any supportive s/w
language
which can read and write MAC packet over ethernet bcoz my
application
is point 2 point connection.
i just want to make it simple.
also i am not very much familiar with TCP/IP. so can u suggest me the
S/W language and some gud tutorial for implementing TCP/IP if needed.
Article: 140456On May 13, 9:36=A0pm, Rob Gaddi <rga...@technologyhighland.com> wrote: > On Wed, 13 May 2009 01:31:31 -0700 (PDT) > > > > aitezaz....@gmail.com wrote: > > On May 13, 11:31=A0am, Sandro <sdro...@netscape.net> wrote: > > > On May 13, 7:46=A0am, aitezaz....@gmail.com wrote: > > > > > Hi, > > > > I want to implement 100 Mbps ethernet MAC with a 1000/100/10 PHY > > > > capable PHY that is by default set to 1000Mbps. I have connected > > > > the RGMII interface and MDIO interface but i dont know how to put > > > > this PHY into auto negotiation mode or force it to run on 100 > > > > Mbps. Please guide in this regard. i.e. (which MDIO register i > > > > should write to control this thing). > > > > > Aitezaz > > > > Aitezaz, > > > What about reading the datasheet of your phy? > > > Anyway, for the 100/10 Phy the clause 22 of the 802.3 standard > > > does require the register 0 > > > =A0 bit 13 set the speed, (10 or 100) > > > =A0 bit 12 enable/disable autonegotiation > > > =A0 bit 8 set the duplex mode > > > For your 1000/100/10 phy but please read the datasheet > > > > Sandro > > > Thanks Sandro for help. The board is using BCM5464SR (on NETFPGA) > > whose datasheet doesn't tell anything about it. But as you written the > > standard name, I have found the registers in the standard. > > Thank you again > > > Aitezaz > > What, a Broadcom PHY with bad/nonexistant/unavailable documentation? > Such a thing has never before in all of history occurred. > > -- > Rob Gaddi, Highland Technology > Email address is currently out of order Yeah at least that is what I have found. Even the authors of NETFPGA directed towards BROADCOM documentation but all that I have found about it is this little product brief. http://www.broadcom.com/products/Enterprise-Networking/Gigabit-Ethernet-Tra= nsceivers/BCM5464SR Even I tried to download the datasheet from other websites but everywhere it is the same two page document. The information I gathered is from an Intel Transceiver chip LXT972A. Since, the register I am using is not manufacturer dependant and is dictated by the standard, I am using this document to configure the BROADCOM PHY.Article: 140457
Hi, I am currently working on a circuit generator problem, which I also want to target to FPGAs. However, I want to make my tools somewhat technology/vendor independent by generating a netlist of LUT's and FlipFlops. This means my tool would be configured with the available LUT sizes and area costs. A second step should then translate the netlist into a technology- specific form. I think this second step should be easily doable with XSLT if the netlist is represented as XML. I wonder if there are existing formats and tools to do this. I have found individual academic projects that do something similar, but none seemed to have reached a wider scope. Is there a wide-spread approach? Currently I target ASIC technologies and generate VHDL. If I give this VHDL for instance to ISE, it runs for hours and I am not convinced that the result is close to what I intend. The reason is that this VHDL shares signals on a gate level. So the FPGA mapper has a hard time to figure out which gates need to be replicated and put together with other gates into a LUT. Regards, AndreasArticle: 140458
hi all,
i have installed EDK 10.1 ,but not getting start saying that
fileset.txt can not be opened in $XILINX directory .
the content of the same file is
Thu May 14 11:33:02 TZ 2009:: product=EDK
Thu May 14 11:33:02 TZ 2009:: configuration=
Thu May 14 11:33:02 TZ 2009:: version=10.1
Thu May 14 11:33:02 TZ 2009:: Registration_ID=1AYJAMRTAGR8SA948A5K407AF
Thu May 14 11:33:02 TZ 2009:: summary=Location: C:\xilinx\10.1\EDK
Thu May 14 11:33:02 TZ 2009:: summary=Platform Studio Tool and Processor
IP
Thu May 14 11:40:47 TZ 2009:: summary=backup 10.1
Thu May 14 11:40:47 TZ 2009:: version=10.1.03
i have doubt that configuration in second row must be needing some info.
bcoz when i checked the same file for chipScope it has
Configuration=pro,for ISE
it has foundation and so on.
so plz help.
Article: 140459Bert_Paris <do_not_spam@me.com> writes: > I would consider the Igloo nano. > The Max II doesn't have embedded Ram. That's true, but it has a quite a few registers (240-2k+ LE's). I see from some of the later posts that 2K RAM is a minimin requirement which will rule out the Max-II unless an external RAM is used. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 140460
Dave <dhschetz@gmail.com> writes: > documentation were better on this. I also wish the iMPACT SVF player > were faster - it takes hours (no exaggeration) to play out an svf file > for a XC4VLX25! Wow! How big is the SVF file? Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 140461
On May 14, 10:36=A0am, Petter Gustad <newsmailco...@gustad.com> wrote: > Dave <dhsch...@gmail.com> writes: > > documentation were better on this. I also wish the iMPACT SVF player > > were faster - it takes hours (no exaggeration) to play out an svf file > > for a XC4VLX25! > > Wow! =A0How big is the SVF file? > > Petter > -- > A: Because it messes up the order in which people normally read text. > Q: Why is top-posting such a bad thing? > A: Top-posting. > Q: What is the most annoying thing on usenet and in e-mail? 23MByte orsoArticle: 140462
On Wed, 13 May 2009 23:14:41 -0700 (PDT), acd <acd4usenet@lycos.de> wrote: >Hi, > >I am currently working on a circuit generator problem, which I also >want to target to FPGAs. >However, I want to make my tools somewhat technology/vendor >independent by generating a netlist of LUT's and >FlipFlops. This means my tool would be configured with the available >LUT sizes and area costs. >A second step should then translate the netlist into a technology- >specific form. ... >Currently I target ASIC technologies and generate VHDL. >If I give this VHDL for instance to ISE, it runs for hours and I am >not convinced that the result is close to what I intend. >The reason is that this VHDL shares signals on a gate level. So the >FPGA mapper has a hard time to figure out which gates need to be >replicated and put together with other gates into a LUT. It sounds as if your tool has a good idea what to replicate and how to optimally map it. You could consider adding this information to the VHDL in the form of attributes - e.g. "keep" and "RLOC" when targetting Xilinx; others for other technologies; probably at the second tech-specific stage. Search online for "Death of the RLOC?" to see this in action. Be prepared for a tussle with ISE to overcome its optimisations... - BrianArticle: 140463
On Wed, 13 May 2009 16:45:05 -0700 (PDT), -jg <Jim.Granville@gmail.com> wrote: >On May 13, 10:23 pm, Mike Harrison <m...@whitewing.co.uk> wrote: >> I'm looking at a possible application and trying to figure the relative costs of FPGA/CPLD versus >> MCU. >> I can do it with a microcontroller, but the only MCUs with the hardware I need (TFT LCD controller) >> tend to come with lots of other stuff (ethernet, large flash, USB etc.) which I don't need. > >If you can find a chip that does the task, that's normally going to be >cheaper than a FPGA. >(even with unused bits ) In many cases I'd agree that this is true, but in this particular one, almost all the other parts of the MCU, including most of the 512K of flash, ethernet,USB,CAN,SD etc. etc. and a lot of pins aren't needed. >Or, find a uC that is close, and add a smaller Prog Logic device to >stretch the peripherals. >Streaming SPI-CPLD can add quite smart 'external peripherals'. >The uC have Code-flash built in, as well as Analog features. Again in many cases this would be a good solution but probably not here. What I'm looking at is the cheapest way to drive a large number (potentially hundreds) of distributed TFT (PSP) displays with local SDRAM and/or NAND flash storage for a few tens to hundreds of frames, with a relatively a low bandwidth network of some sort to update content in non-realtime, and switch the display between stored frames realtime. The aim is to minimise the cost per node as much as possible. The NXP LPC2478's LCD controller is fine, but the memory bus will be a bit of a bottleneck, especially with the NAND flash option, as data needs to pass over the bus 3 times. Unfortunately for reasons I can't fathom, NXP forgot to put a SPI flash load option in the bootloader of the flashless 2470 version - it would in principle to load it using the ISP interface at startup but it's a bit messy. And it would still be more expensive than the Lattice EC1 option. At some point I may look at the NXP ARM9 LCD part which can load from SPI but it's in a BGA package and this project is still at a small-scale speculative proof-of-concept stage so prototyping costs need to be minimised. The problem for both NAND and SDRAM is getting a contiguous stream of data to the LCD between the hsyncs- NAND's 25uS page read time, and the SDRAM page sizes are problems which can be solved easily once you have enough RAM for a 1-line FIFO buffer in an FPGA. It also makes it more potentially viable to drive 2 displays per controller, which would slash the per-node cost. The FPGA also provides more flexibility on the interface between units - e.g. faster SPI or UART rates than the MCU could handle. If there are enough spare pins to commit an IO bank, even fast LVDS between nodes could be an option, >> The Xilinx S3A/AN-50 is the cheapest I've found so far, but is a a bit over-specced. >> CPLDs seem to get expensive above 72 cells and don't tend to have RAM > >The two choices do not really seem to overlap here ? - you have a >quite small logic block, and no >mention of any processor on the 2nd choice ? This was more of a general comment than one specific to this app. there is a big cost jump above 72 MC's that makes them not much cheaper than FPGAs. I did start looking at whether a CPLD solution would be viable, hiding flash read/SDRAM setup inside the line syncs but the timings & addressing don't quite look like they would work, and you'd need too many macrocells to add an external SRAM. >100 macrocells is viable in CPLD (384/512 tend to not stack up), and a >device like >ATF1508RE (128MC 3.3V SingleSupply) is $3.90/100+ at Digikey. >You may be able to add SPI RAM - 32Kx8 is $1.09/100+ Interesting - I'd not noticed that one - I've used Atmel CPLDs in the distant past but had sort of forgotten that they still did them as they don't seem promote them very much these days..!Article: 140464
Hi, I'm using EMACS vhdl-mode to generate a makefile for simulation. My problem is that I don't know how to tell EMACS to rescan the source code folders before re-generating the makefile. If it doesn't rescan then it doesn't find new files I have added or new dependencies. My workaround is to close down emacs. Delete the emacs cache file. Reopen emacs, and then regenerate the makefile. Is there a simple way to force emacs to rescan the source code folders? Cheers AndrewArticle: 140465
Hi, I have some basic questions on sync and async reset schemes. I would be thankful if any design experts clarify them for me. 1. Most of the chips that use async reset schemes, tend to process these resets using clocks. Now doesn't this result on depending on clock being present, which is quoted as one of the main disadvantage of sync clocks. 2. While normally the async reset input is processed inside the chips to ensure that assertion is async but deassertion is synchronous, I have seen some cases where the async reset is first synchronized and then used throughout the design. So what is the advantage of synchronizing async resets inside the chips 3. In case of sync resets, how is the reset generated by the system (which is outside the chip) since the reset should have a defined relation wrt the clock that uses this reset. Also, in case the chip uses multiple clock domains, it means that the reset should also be different and properly synchronized with the corresponding clock. How is this ensured. Is it that the system generally generates a wide reset and the reset circuitry inside the chip synchronizes per clock domain and fans out the reset? 4. Also, sync resets directly go to input of the data input of the flop. Does not this have an impact on the max frequency of the circuit since one level of logic will get added due to this input? RegardsArticle: 140466
The MAX II is a nice device, but the lack of RAM does let it down some. The on board slow flash gives 1K EEPROM but this is not large enough for many designs. SRAM chips are quite cheap for small capacities, but there needs to be a pin budget of around 20+ pins to interface to them. RAM is the only thing 'missing' from the MAX IIZ. The smaller die size argument is a bit silly, 1/4 of the macrocell area could be replaced by a reasonable self refresh DRAM, with single ported access. cheers jackoArticle: 140467
Jacko <jackokring@gmail.com> writes: > capacities, but there needs to be a pin budget of around 20+ pins to Not so if a serial RAM fits your bandwidth and latency requirements: http://ww1.microchip.com/downloads/en/DeviceDoc/22127a.pdf Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 140468
On 14 May, 01:29, DH <dh1...@gmail.com> wrote: > Hi, > > I'm trying to find an open source processor as a basis for a research, > preferably it is in VHDL and implements a 5-stage RISC pipeline with > bypassing (exceptions are not a concern), of course if you know of any > processor with a clean 5-stage pipeline with bypassing, please let me > know. It would be awesome if it implements the MIPS ISA. > > I've tried the open cores website, and have looked at 2 MIPS ISA > implementations: Plasma and miniMIPS. > Problem is Plasma does not deal with bypassing and is not a 5-stage > pipeline, and miniMIPS is rather weird, it process instructions every > other cycle, so it would process, then it would pause everything on > the next cycle. > > So I'm wondering maybe there would be someone out there on the > internets that know about this, please help me out :) Thanks! > > Regards, > David. Have a look at Lattice Mico32. It's in verilog rather than VHDL, and not MIPS, but is quite similar and is pipelined with bypassing. http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/index.cfm Cheers, JonArticle: 140469
how? in GUI can just add many UCF files they are all used but in the cmd log only one of them is displayed? must be some magic? I do not want to create .ISE files, need just script file to spec multiple UCFs AnttiArticle: 140470
On Thu, 2009-05-14 at 05:20 -0700, Antti wrote:
> how?
>
> in GUI can just add many UCF files they are all used
> but in the cmd log only one of them is displayed?
>
> must be some magic? I do not want to create .ISE files, need just
> script file to spec multiple UCFs
Hi Antti,
I found no ise solution for that. So my solution was:
"find <src-dir> -name '*.ucf' -exec cat {} >> merged.ucf \;"
For some projects I define a variable with all ucf files
and merged these into one file. Depends on your project tree.
cheers
ben
Article: 140471
On May 14, 3:36=A0pm, Benjamin Krill <b...@codiert.org> wrote:
> On Thu, 2009-05-14 at 05:20 -0700, Antti wrote:
> > how?
>
> > in GUI can just add many UCF files they are all used
> > but in the cmd log only one of them is displayed?
>
> > must be some magic? I do not want to create .ISE files, need just
> > script file to spec multiple UCFs
>
> Hi Antti,
>
> I found no ise solution for that. So my solution was:
>
> "find <src-dir> -name '*.ucf' -exec cat {} >> merged.ucf \;"
>
> For some projects I define a variable with all ucf files
> and merged these into one file. Depends on your project tree.
>
> cheers
> =A0ben
but this !?
when it works with ISE GUI,
it should also work from commandline???
Antti
Article: 140472hi.. i am presently doing one project, in that i need to convert a 128 bit plain text to a 4X4 matrix, each element in the matrix is of 8bit length...how to write a vhdl code for this....can u please help me in this regard...... thanks in advance.....Article: 140473
On 14 mayo, 15:52, "renuka" <renukasd...@gmail.com> wrote: > hi.. > i am presently doing one project, in that i need =A0to convert a =A0128 b= it > plain text to a 4X4 matrix, each element in the matrix is of 8bit > length...how to write a vhdl code for this....can u please help me in thi= s > regard...... > =A0 thanks in advance..... How do u get those 128 bits? Is it for a synth circuit or just for simulation purpose?Article: 140474
On May 13, 7:29=A0pm, DH <dh1...@gmail.com> wrote: > Hi, > > I'm trying to find an open source processor as a basis for a research, > preferably it is in VHDL and implements a 5-stage RISC pipeline with > bypassing (exceptions are not a concern), of course if you know of any > processor with a clean 5-stage pipeline with bypassing, please let me > know. It would be awesome if it implements the MIPS ISA. > > I've tried the open cores website, and have looked at 2 MIPS ISA > implementations: Plasma and miniMIPS. > Problem is Plasma does not deal with bypassing and is not a 5-stage > pipeline, and miniMIPS is rather weird, it process instructions every > other cycle, so it would process, then it would pause everything on > the next cycle. > > So I'm wondering maybe there would be someone out there on the > internets that know about this, please help me out :) Thanks! > > Regards, > David. Why the specific requirements? What is the research focusing on?
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z