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Hello, I'm designing several Xilinx FPGAs and CPLDs and I was wondering if there is a way to set the way ISE encodes state machines other than in project navigator? I'd like to be able to set it in the VHDL file or in the UCF. It's really a quality control problem. As the project is touched by many people and as it's upgraded to newer versions of ISE software the encoding method seems to get changed. I want to be able to guarantee that it's set to what I want it to be set to. Thanks in advance for the help. DaleArticle: 136226
Hello all,
I am having some issues with this piece of code, which is supposed to
work correctly with the spartan 3 leds.
I am trying to display a 16 bit count to the led display; however, the
value on the leddisplay produces duplicate values across all 4 leds.
Is there something I am doing wrong with the code ?
Please help,
Uchenna Anyanwu
always @ ( posedge done or posedge reset)
begin
if(reset)
leddisp <= 0;
else
leddisp[15:0] <= numcounter1 - numcounter2;
go = 1;
end
always @ (posedge go)
begin
if(go)
difcount1={leddisp[3], leddisp[2], leddisp[1],leddisp[0]};
end
always @ (posedge go)
begin
if(go)
difcount2={leddisp[7], leddisp[6], leddisp[5], leddisp[4]};
end
always @ (posedge go)
begin
if(go)
difcount3={leddisp[11], leddisp[10], leddisp[9], leddisp[8]};
end
always @ (posedge go)
begin
if (go)
difcount4={leddisp[15], leddisp[14], leddisp[13], leddisp[12]};
end
led u3 (difcount1,s0, s1, s2, s3, s4, s5, s6);
led u4 (difcount2,s7, s8, s9, s10, s11, s12, s13);
led u5 (difcount3,s14, s15, s16, s17, s18, s19,s20);
led u6 (difcount4,s21, s22, s23, s24, s25, s26, s27);
LED_MUX u7 (/*clkbuf*/ clk_50Mhz, reset, {s6, s5, s4, s3, s2, s1, s0},
{s13,s12,s11,s10,s9,s8,s7}, {s20,s19,s18,s17,s16,s15,s14},
{s27,s26,s25,s24,s23,s22,s21}, LEDOUT, LEDSEL );
endmodule
module led(number, s0, s1, s2, s3, s4, s5, s6);
output s0, s1, s2, s3, s4, s5, s6;
input [3:0] number;
reg s0, s1, s2, s3, s4, s5, s6;
always @ (number)
begin // BCD to 7-segment decoding
case (number) // s0 ? s6 are active low
4'b0000: begin s0=0; s1=0; s2=0; s3=1; s4=0; s5=0; s6=0; end
4'b0001: begin s0=1; s1=0; s2=1; s3=1; s4=0; s5=1; s6=1; end
4'b0010: begin s0=0; s1=1; s2=0; s3=0; s4=0; s5=1; s6=0; end
4'b0011: begin s0=0; s1=0; s2=1; s3=0; s4=0; s5=1; s6=0; end
4'b0100: begin s0=1; s1=0; s2=1; s3=0; s4=0; s5=0; s6=1; end
4'b0101: begin s0=0; s1=0; s2=1; s3=0; s4=1; s5=0; s6=0; end
4'b0110: begin s0=0; s1=0; s2=0; s3=0; s4=1; s5=0; s6=0; end
4'b0111: begin s0=1; s1=0; s2=1; s3=1; s4=0; s5=1; s6=0; end
4'b1000: begin s0=0; s1=0; s2=0; s3=0; s4=0; s5=0; s6=0; end
4'b1001: begin s0=0; s1=0; s2=1; s3=0; s4=0; s5=0; s6=0; end
default: begin s0=1; s1=1; s2=1; s3=1; s4=1; s5=1; s6=1; end
endcase
end
endmodule // end led
module LED_MUX (clk, rst, LED0, LED1, LED2, LED3, LEDOUT, LEDSEL);
input clk, rst;
input [7:0] LED0, LED1, LED2, LED3;
output[3:0] LEDSEL;
reg [3:0] LEDSEL;
output[6:0] LEDOUT;
reg [6:0] LEDOUT;
reg [1:0] index;
always @(posedge clk)
begin
if(rst)
index = 0;
else
index = index + 1;
end
always @(index or LED0 or LED1 or LED2 or LED3)
begin
case(index)
0: begin
LEDSEL = 4'b1110;
LEDOUT = LED0;
end
1: begin
LEDSEL = 4'b1101;
LEDOUT = LED1;
end
2: begin
LEDSEL = 4'b1011;
LEDOUT = LED2;
end
3: begin
LEDSEL = 4'b0111;
LEDOUT = LED3;
end
default: begin
LEDSEL = 0; LEDOUT = 0;
end
endcase
end
endmodule
Article: 136227Hi All, A newly added feature of the TimingAnalyzer is the ability to read .vcd files. These files can be generated by logic simulators or tools like Xilinx chipscope, or test equipment like logic analyzers. So, you can easily make annotated timing diagrams from simulation or test equipment outputs. Would it be possible to email any .vcd files samples that you might have, that are not proprietary, so I can test this feature with .vcd files from as many sources as possible? tiiminganalyzer@gmail.com support@timing-diagrams.com Thank you in advance, Dan www.timing-diagrams.comArticle: 136228
mentari wrote: > What are your views on http://scratchpad.wikia.com/wiki/TileraMulticore > as a replacement for FPGA's ? http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/99a7f70929b2f1e2 Last I checked there was little info about price or availability. -JeffArticle: 136229
On 7 Nov, 10:25, mentari <Stephan...@gmail.com> wrote: > What are your views onhttp://scratchpad.wikia.com/wiki/TileraMulticore > as a replacement for FPGA's ? > > http://www.tilera.com/solutions/digital_baseband.php > > The current architecture for base stations fall short of delivering > the performance, the low latency and the flexibility customers need. > To meet the requirements, wireless equipment providers design complex > systems with FPGA, ASIC, DSP and processors with each component > requiring special tools in a customized development environment. This > leads to a long development cycle, sometimes years, before > applications can be productized. Changes in standards also impact > providers because such systems are inflexible-upgrades can be a slow > and expensive process. > > What providers seek is an uncomplicated, well-designed, architecture > that yields good performance. Tilera's processors provide a low > latency single solution that integrates many functions seamlessly in a > single processor and uses C/C++ to program their applications with > industry standard tools. The familiar tools enable customers to > preserve their software investments, replace a number of disparate > programming methodologies with one standard programming environment, > and gain the flexibility they need to support evolving protocols and > ever-increasing demands for service XMOS chips are intended to replace FPGAs in many applications, and are available now: http://www.xmos.com LeonArticle: 136230
Dale wrote: > Hello, > I'm designing several Xilinx FPGAs and CPLDs and I was wondering if > there is a way to set the way ISE encodes state machines other than in > project navigator? I'd like to be able to set it in the VHDL file or > in the UCF. It's really a quality control problem. As the project is > touched by many people and as it's upgraded to newer versions of ISE > software the encoding method seems to get changed. I want to be able > to guarantee that it's set to what I want it to be set to. > Thanks in advance for the help. > > Dale type state_type is (foo, bar, ...); attribute syn_enum_encoding of state_type: type is "onehot"; signal state: state_type; -JeffArticle: 136231
On 7 nov, 05:25, mentari <Stephan...@gmail.com> wrote: > What are your views onhttp://scratchpad.wikia.com/wiki/TileraMulticore > as a replacement for FPGA's ? > > http://www.tilera.com/solutions/digital_baseband.php > > The current architecture for base stations fall short of delivering > the performance, the low latency and the flexibility customers need. > To meet the requirements, wireless equipment providers design complex > systems with FPGA, ASIC, DSP and processors with each component > requiring special tools in a customized development environment. This > leads to a long development cycle, sometimes years, before > applications can be productized. Changes in standards also impact > providers because such systems are inflexible-upgrades can be a slow > and expensive process. > > What providers seek is an uncomplicated, well-designed, architecture > that yields good performance. Tilera's processors provide a low > latency single solution that integrates many functions seamlessly in a > single processor and uses C/C++ to program their applications with > industry standard tools. The familiar tools enable customers to > preserve their software investments, replace a number of disparate > programming methodologies with one standard programming environment, > and gain the flexibility they need to support evolving protocols and > ever-increasing demands for service It seems to be similar to XMOS devices. I suppose that it could replace FPGAs in some applications. However, it's still a much coarser architecture than an FPGA. There's still only 64 processing units, while a Virtex-5 can have about 20 000 slices and a couple of PPC processors. In the end, I think that since FPGAs are much more flexible, they have the upper hand. Plus with tools like system generator, AccelDSP and Simulink, low-level HDL coding can be skipped, and the engineer can focus more on applications and less on the "bit- level" of things. Plus I suppose that with a high-capacity FPGA, one could emulate a Tilera-like device with 64 processing units. Maybe the future's there, take the Tilera (or Xmos) concept and implement it in a FPGA. My 2 centsArticle: 136232
On Nov 7, 11:04=A0am, Jeff Cunningham <j...@sover.net> wrote: > Dale wrote: > > Hello, > > I'm designing several Xilinx FPGAs and CPLDs and I was wondering if > > there is a way to set the way ISE encodes state machines other than in > > project navigator? =A0I'd like to be able to set it in the VHDL file or > > in the UCF. =A0It's really a quality control problem. =A0As the project= is > > touched by many people and as it's upgraded to newer versions of ISE > > software the encoding method seems to get changed. =A0I want to be able > > to guarantee that it's set to what I want it to be set to. > > Thanks in advance for the help. > > > Dale > > type state_type is (foo, bar, ...); > attribute syn_enum_encoding of state_type: type is "onehot"; > signal state: state_type; > > -Jeff Jeff, thanks for the help. When I do that I get the following error. ERROR:HDLParsers:3312 - "C:/Projects/HAL/Hardware/FPGA_B/trunk/ ADC_Audio.vhd" Line 51. Undefined symbol 'syn_enum_encoding'. Do I need to include a library or something? Thanks.Article: 136233
Hi, > > type state_type is (foo, bar, ...); attribute syn_enum_encoding: string; > > attribute syn_enum_encoding of state_type: type is "onehot"; > > signal state: state_type; cheers benArticle: 136234
On 7 nov, 11:01, Leon <leon...@btinternet.com> wrote: > On 7 Nov, 10:25, mentari <Stephan...@gmail.com> wrote: > > > > > What are your views onhttp://scratchpad.wikia.com/wiki/TileraMulticore > > as a replacement for FPGA's ? > > >http://www.tilera.com/solutions/digital_baseband.php > > > The current architecture for base stations fall short of delivering > > the performance, the low latency and the flexibility customers need. > > To meet the requirements, wireless equipment providers design complex > > systems with FPGA, ASIC, DSP and processors with each component > > requiring special tools in a customized development environment. This > > leads to a long development cycle, sometimes years, before > > applications can be productized. Changes in standards also impact > > providers because such systems are inflexible-upgrades can be a slow > > and expensive process. > > > What providers seek is an uncomplicated, well-designed, architecture > > that yields good performance. Tilera's processors provide a low > > latency single solution that integrates many functions seamlessly in a > > single processor and uses C/C++ to program their applications with > > industry standard tools. The familiar tools enable customers to > > preserve their software investments, replace a number of disparate > > programming methodologies with one standard programming environment, > > and gain the flexibility they need to support evolving protocols and > > ever-increasing demands for service > > XMOS chips are intended to replace FPGAs in many applications, and are > available now: > > http://www.xmos.com > > Leon So Leon, what's your impression of the xmos devices so far?Article: 136235
On Nov 7, 9:14 am, Dale <dale.prat...@gmail.com> wrote: > On Nov 7, 11:04 am, Jeff Cunningham <j...@sover.net> wrote: > > > > > Dale wrote: > > > Hello, > > > I'm designing several Xilinx FPGAs and CPLDs and I was wondering if > > > there is a way to set the way ISE encodes state machines other than in > > > project navigator? I'd like to be able to set it in the VHDL file or > > > in the UCF. It's really a quality control problem. As the project is > > > touched by many people and as it's upgraded to newer versions of ISE > > > software the encoding method seems to get changed. I want to be able > > > to guarantee that it's set to what I want it to be set to. > > > Thanks in advance for the help. > > > > Dale > > > type state_type is (foo, bar, ...); > > attribute syn_enum_encoding of state_type: type is "onehot"; > > signal state: state_type; > > > -Jeff > > Jeff, thanks for the help. When I do that I get the following error. > > ERROR:HDLParsers:3312 - "C:/Projects/HAL/Hardware/FPGA_B/trunk/ > ADC_Audio.vhd" Line 51. Undefined symbol 'syn_enum_encoding'. > > Do I need to include a library or something? > > Thanks. Typo; try this: attribute SYN_ENCODING of state_type: type is "onehot"; -or- attribute type_encoding_style of state_type: type is "onehot"; One of those should work, AlexArticle: 136236
On 7 Nov, 16:26, Benjamin Couillard <benjamin.couill...@gmail.com> wrote: > On 7 nov, 11:01, Leon <leon...@btinternet.com> wrote: > > > > > On 7 Nov, 10:25, mentari <Stephan...@gmail.com> wrote: > > > > What are your views onhttp://scratchpad.wikia.com/wiki/TileraMulticore > > > as a replacement for FPGA's ? > > > >http://www.tilera.com/solutions/digital_baseband.php > > > > The current architecture for base stations fall short of delivering > > > the performance, the low latency and the flexibility customers need. > > > To meet the requirements, wireless equipment providers design complex > > > systems with FPGA, ASIC, DSP and processors with each component > > > requiring special tools in a customized development environment. This > > > leads to a long development cycle, sometimes years, before > > > applications can be productized. Changes in standards also impact > > > providers because such systems are inflexible-upgrades can be a slow > > > and expensive process. > > > > What providers seek is an uncomplicated, well-designed, architecture > > > that yields good performance. Tilera's processors provide a low > > > latency single solution that integrates many functions seamlessly in a > > > single processor and uses C/C++ to program their applications with > > > industry standard tools. The familiar tools enable customers to > > > preserve their software investments, replace a number of disparate > > > programming methodologies with one standard programming environment, > > > and gain the flexibility they need to support evolving protocols and > > > ever-increasing demands for service > > > XMOS chips are intended to replace FPGAs in many applications, and are > > available now: > > >http://www.xmos.com > > > Leon > > So Leon, what's your impression of the xmos devices so far? I'm very impressed. The $99 XC-1 kit is very good value, and the (open source) tools are good. The tools have a few bugs, but they aren't serious. I don't think the silicon has any problems. Support is excellent. The chips are made using a conservative 90nm process, when they move to something more advanced they should be able to push the speed up and get more cores on a chip; they have said that they probably won't go over eight cores, though. LeonArticle: 136237
Thanks for all your input. I'm still not sure if I am where I need to be. I have the following and it synthesizes. type State_Machine is (S0,S1,S2,S3,S4,S5,S6,S7); attribute syn_enum_encoding: string; attribute syn_enum_encoding of State_Machine: type is "onehot"; signal FSM_0 : State_Machine; Then I changed the "onehot" to "jibberish" for an experiment. It sill synthesizes. So, what effect does the above syntax really have? Does it do anything?Article: 136238
On 7 Nov, 16:11, Benjamin Couillard <benjamin.couill...@gmail.com> wrote: > On 7 nov, 05:25, mentari <Stephan...@gmail.com> wrote: > > > > > What are your views onhttp://scratchpad.wikia.com/wiki/TileraMulticore > > as a replacement for FPGA's ? > > >http://www.tilera.com/solutions/digital_baseband.php > > > The current architecture for base stations fall short of delivering > > the performance, the low latency and the flexibility customers need. > > To meet the requirements, wireless equipment providers design complex > > systems with FPGA, ASIC, DSP and processors with each component > > requiring special tools in a customized development environment. This > > leads to a long development cycle, sometimes years, before > > applications can be productized. Changes in standards also impact > > providers because such systems are inflexible-upgrades can be a slow > > and expensive process. > > > What providers seek is an uncomplicated, well-designed, architecture > > that yields good performance. Tilera's processors provide a low > > latency single solution that integrates many functions seamlessly in a > > single processor and uses C/C++ to program their applications with > > industry standard tools. The familiar tools enable customers to > > preserve their software investments, replace a number of disparate > > programming methodologies with one standard programming environment, > > and gain the flexibility they need to support evolving protocols and > > ever-increasing demands for service > > It seems to be similar to XMOS devices. I suppose that it could > replace FPGAs in some applications. However, it's still a much coarser > architecture than an FPGA. =A0There's still only 64 processing units, > while a Virtex-5 can have about 20 000 slices and a couple of PPC > processors. In the end, I think that since FPGAs are much more > flexible, they have the upper hand. Plus with tools like system > generator, AccelDSP and Simulink, low-level HDL coding can be skipped, > and the engineer can focus more on applications and less on the "bit- > level" of things. > > Plus I suppose that with a high-capacity FPGA, one could emulate a > Tilera-like device with 64 processing units. Maybe the future's there, > take the Tilera (or Xmos) concept and implement it in a FPGA. > > My 2 cents They will cost more, be much harder to use, use a lot more power and won't be any faster. LeonArticle: 136239
Dale wrote:
> I'm designing several Xilinx FPGAs and CPLDs and I was wondering if
> there is a way to set the way ISE encodes state machines other than in
> project navigator? I'd like to be able to set it in the VHDL file or
> in the UCF. It's really a quality control problem.
It is possible to write synthesis code
such that the encoding selection
does not affect the fpga operation.
-- Mike Treseler
Article: 136240
On Fri, 7 Nov 2008 07:38:55 -0800 (PST), uraniumore238@gmail.com
wrote:
>Hello all,
>
>I am having some issues with this piece of code, which is supposed to
>work correctly with the spartan 3 leds.
>I am trying to display a 16 bit count to the led display; however, the
>value on the leddisplay produces duplicate values across all 4 leds.
>Is there something I am doing wrong with the code ?
>
>Please help,
>Uchenna Anyanwu
>
>always @ ( posedge done or posedge reset)
>begin
>if(reset)
>leddisp <= 0;
>else
>leddisp[15:0] <= numcounter1 - numcounter2;
>go = 1;
>end
>
>always @ (posedge go)
>begin
>if(go)
>difcount1={leddisp[3], leddisp[2], leddisp[1],leddisp[0]};
>end
>
>always @ (posedge go)
>begin
>if(go)
>difcount2={leddisp[7], leddisp[6], leddisp[5], leddisp[4]};
>end
>
>always @ (posedge go)
>begin
>if(go)
>difcount3={leddisp[11], leddisp[10], leddisp[9], leddisp[8]};
>end
>
>always @ (posedge go)
>begin
>if (go)
>difcount4={leddisp[15], leddisp[14], leddisp[13], leddisp[12]};
>end
>
>led u3 (difcount1,s0, s1, s2, s3, s4, s5, s6);
>led u4 (difcount2,s7, s8, s9, s10, s11, s12, s13);
>led u5 (difcount3,s14, s15, s16, s17, s18, s19,s20);
>led u6 (difcount4,s21, s22, s23, s24, s25, s26, s27);
>
>LED_MUX u7 (/*clkbuf*/ clk_50Mhz, reset, {s6, s5, s4, s3, s2, s1, s0},
>{s13,s12,s11,s10,s9,s8,s7}, {s20,s19,s18,s17,s16,s15,s14},
>{s27,s26,s25,s24,s23,s22,s21}, LEDOUT, LEDSEL );
>
>endmodule
>
>module led(number, s0, s1, s2, s3, s4, s5, s6);
>output s0, s1, s2, s3, s4, s5, s6;
>input [3:0] number;
>reg s0, s1, s2, s3, s4, s5, s6;
>always @ (number)
>begin // BCD to 7-segment decoding
>case (number) // s0 ? s6 are active low
>4'b0000: begin s0=0; s1=0; s2=0; s3=1; s4=0; s5=0; s6=0; end
>4'b0001: begin s0=1; s1=0; s2=1; s3=1; s4=0; s5=1; s6=1; end
>4'b0010: begin s0=0; s1=1; s2=0; s3=0; s4=0; s5=1; s6=0; end
>4'b0011: begin s0=0; s1=0; s2=1; s3=0; s4=0; s5=1; s6=0; end
>4'b0100: begin s0=1; s1=0; s2=1; s3=0; s4=0; s5=0; s6=1; end
>4'b0101: begin s0=0; s1=0; s2=1; s3=0; s4=1; s5=0; s6=0; end
>4'b0110: begin s0=0; s1=0; s2=0; s3=0; s4=1; s5=0; s6=0; end
>4'b0111: begin s0=1; s1=0; s2=1; s3=1; s4=0; s5=1; s6=0; end
>4'b1000: begin s0=0; s1=0; s2=0; s3=0; s4=0; s5=0; s6=0; end
>4'b1001: begin s0=0; s1=0; s2=1; s3=0; s4=0; s5=0; s6=0; end
>default: begin s0=1; s1=1; s2=1; s3=1; s4=1; s5=1; s6=1; end
>endcase
>end
>endmodule // end led
>
>module LED_MUX (clk, rst, LED0, LED1, LED2, LED3, LEDOUT, LEDSEL);
>input clk, rst;
>input [7:0] LED0, LED1, LED2, LED3;
>output[3:0] LEDSEL;
>reg [3:0] LEDSEL;
>output[6:0] LEDOUT;
>reg [6:0] LEDOUT;
>reg [1:0] index;
>always @(posedge clk)
>begin
>if(rst)
>index = 0;
>else
>index = index + 1;
>end
>always @(index or LED0 or LED1 or LED2 or LED3)
>begin
>case(index)
>0: begin
>LEDSEL = 4'b1110;
>LEDOUT = LED0;
>end
>1: begin
>LEDSEL = 4'b1101;
>LEDOUT = LED1;
>end
>2: begin
>LEDSEL = 4'b1011;
>LEDOUT = LED2;
>end
>3: begin
>LEDSEL = 4'b0111;
>LEDOUT = LED3;
>end
>default: begin
>LEDSEL = 0; LEDOUT = 0;
>end
>endcase
>end
>endmodule
I'm not a verilog guy, but as far as I can tell, "go" goes HI only
once - it never changes.
-Dave Pollum
From rgaddi@technologyhighland.com Fri Nov 07 09:49:19 2008
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Newsgroups: comp.arch.fpga
Subject: Re: Setting FSM encoding in VHDL or in UCF for Xilinx
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On Fri, 7 Nov 2008 08:45:59 -0800 (PST)
Dale <dale.prather@gmail.com> wrote:
> Thanks for all your input. I'm still not sure if I am where I need to
> be.
>
> I have the following and it synthesizes.
>
> type State_Machine is (S0,S1,S2,S3,S4,S5,S6,S7);
> attribute syn_enum_encoding: string;
> attribute syn_enum_encoding of State_Machine: type is
> "onehot"; signal FSM_0 : State_Machine;
>
> Then I changed the "onehot" to "jibberish" for an experiment. It sill
> synthesizes. So, what effect does the above syntax really have? Does
> it do anything?
Then that might not be the right attribute. Thing to remember about
passing attributes to the synthesizer is that (far too) many of them
are synthesizer specific. I didn't see you mention what synthesis
tool your're using, but if you're using XST, then you want:
type State_Machine is (S0,S1,S2,S3,S4,S5,S6,S7);
signal FSM_0 : State_Machine;
attribute fsm_encoding : string;
attribute fsm_encoding of FSM_0 : signal is "one-hot";
Note that not only is the attribute name different, but for some
unfathomable reason it's applied to the signal, rather than to the type.
--
Rob Gaddi, Highland Technology
Email address is currently out of order
Article: 136241On Nov 7, 6:11 pm, Benjamin Couillard <benjamin.couill...@gmail.com> wrote: > It seems to be similar to XMOS devices. I suppose that it could > replace FPGAs in some applications. However, it's still a much coarser > architecture than an FPGA. There's still only 64 processing units, > while a Virtex-5 can have about 20 000 slices and a couple of PPC > processors. In the end, I think that since FPGAs are much more > flexible, they have the upper hand. Plus with tools like system > generator, AccelDSP and Simulink, low-level HDL coding can be skipped, > and the engineer can focus more on applications and less on the "bit- > level" of things. How complicated is it to do Viterbi, Reed-Solomon on an FPGA for a Wimax transmitter on say 2.4ghz implementing OFDM? My understanding is that that Tilera will provide us with a pure C++ environment and speed up the development cycle which with FPGA could be a few years for a full fledged base station.Article: 136242
On 6 nov, 18:30, John_H <newsgr...@johnhandwork.com> wrote: > 1stderivat...@gmail.com wrote: > > Hey, > > Why FPGA based face recognition? MATLAB is fine too right. Is it for > > the Power or Reconfigurability or .. ? > > > Cheers > > For an application like Face Recognition, FPGAs would often be used > because of the speed of parallelism afforded by the ability to tailor > the logic to the task. > > The next faster step in speed but much faster in development is a DSP > based approach, allowing the high algorithmic speed with the ease of > higher level software languages. > > The slower option is to use a generic PC running software designed to > accommodate a huge breadth of numerical processing such as MATLAB. > > But isn't MATLAB much slower and less effective than a human observer? > > Different applications call for different needs. =A0A human observer > can't recognize faces from an enormous database. =A0An FPGA takes a long > development time for such a high-level algorithm to get the speed into > the system. Well I think that designing a face-recognition system in VHDL (or Verilog) would be a huge waste of time and it would be really hard to do. There are tools for that, to automate conversion from Matlab to HDL (AccelDSP, system generator). I'm pretty sure that there are FPGA- neutral tools too for Matlab (that would work on both Altera and Xilinx)Article: 136243
Yes, I'm using XST. I'm using a Spartan 3. I took your suggestion, Rob and again replaced "onehot" with garbage and it still synthesized. Any chance that attribute is invalid with a spartan 3? I "think" I read that somewhere. Thanks.Article: 136244
On 7 nov, 11:47, Leon <leon...@btinternet.com> wrote: > On 7 Nov, 16:11, Benjamin Couillard <benjamin.couill...@gmail.com> > wrote: > > > > > On 7 nov, 05:25, mentari <Stephan...@gmail.com> wrote: > > > > What are your views onhttp://scratchpad.wikia.com/wiki/TileraMulticor= e > > > as a replacement for FPGA's ? > > > >http://www.tilera.com/solutions/digital_baseband.php > > > > The current architecture for base stations fall short of delivering > > > the performance, the low latency and the flexibility customers need. > > > To meet the requirements, wireless equipment providers design complex > > > systems with FPGA, ASIC, DSP and processors with each component > > > requiring special tools in a customized development environment. This > > > leads to a long development cycle, sometimes years, before > > > applications can be productized. Changes in standards also impact > > > providers because such systems are inflexible-upgrades can be a slow > > > and expensive process. > > > > What providers seek is an uncomplicated, well-designed, architecture > > > that yields good performance. Tilera's processors provide a low > > > latency single solution that integrates many functions seamlessly in = a > > > single processor and uses C/C++ to program their applications with > > > industry standard tools. The familiar tools enable customers to > > > preserve their software investments, replace a number of disparate > > > programming methodologies with one standard programming environment, > > > and gain the flexibility they need to support evolving protocols and > > > ever-increasing demands for service > > > It seems to be similar to XMOS devices. I suppose that it could > > replace FPGAs in some applications. However, it's still a much coarser > > architecture than an FPGA. =A0There's still only 64 processing units, > > while a Virtex-5 can have about 20 000 slices and a couple of PPC > > processors. In the end, I think that since FPGAs are much more > > flexible, they have the upper hand. Plus with tools like system > > generator, AccelDSP and Simulink, low-level HDL coding can be skipped, > > and the engineer can focus more on applications and less on the "bit- > > level" of things. > > > Plus I suppose that with a high-capacity FPGA, one could emulate a > > Tilera-like device with 64 processing units. Maybe the future's there, > > take the Tilera (or Xmos) concept and implement it in a FPGA. > > > My 2 cents > > They will cost more, be much harder to use, use a lot more power and > won't be any faster. > > Leon THe point is not that it will be faster, is that it'll be much more versatile since you won't be stuck with a fixed architecture From rgaddi@technologyhighland.com Fri Nov 07 10:10:56 2008 Path: flpi142.ffdc.sbc.com!flpi088.ffdc.sbc.com!prodigy.com!flpi089.ffdc.sbc.com!prodigy.net!bigfeed.bellsouth.net!bigfeed2.bellsouth.net!news.bellsouth.net!border2.nntp.dca.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local02.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Fri, 07 Nov 2008 12:10:56 -0600 Date: Fri, 7 Nov 2008 10:10:56 -0800 From: Rob Gaddi <rgaddi@technologyhighland.com> Newsgroups: comp.arch.fpga Subject: Re: Setting FSM encoding in VHDL or in UCF for Xilinx Message-Id: <20081107101056.13942f3e.rgaddi@technologyhighland.com> References: <9dad5c4a-dfc1-4037-819d-20b76308bac4@z6g2000pre.googlegroups.com> <491466c0$0$30444$4d3efbfe@news.sover.net> <6e607519-fc53-4563-9c2d-425096afd27e@1g2000prd.googlegroups.com> <8049b128-56d5-4fa1-98fd-4b4d43272e0e@a29g2000pra.googlegroups.com> <1f16773c-817b-4aba-acc8-a29779a4c96d@35g2000pry.googlegroups.com> <20081107094919.3256ac78.rgaddi@technologyhighland.com> <a5dce98b-9a87-4174-83e7-6854f1e5a878@a29g2000pra.googlegroups.com> Organization: Highland Technology, Inc. X-Newsreader: Sylpheed 2.5.0 (GTK+ 2.10.14; i686-pc-mingw32) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Lines: 32 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 66.117.134.49 X-Trace: sv3-F8YdsEtj/9MFrOfINre0NubNz4x+e1KpNcrfk2QGHUQjvWGuZ8FCMsK7XEx+p+As1cvzOl1kE/5oyhT!mHJW3x5pqhv93mtIBZV18+U76J7Ck35h6hJq/7uYOQEzUUsakUekVBMrkskGLJR2fHIAk8FR5mA9!JBackDyfIiSMeIaKVkI= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Bytes: 2848 X-Original-Bytes: 2784 Xref: prodigy.net comp.arch.fpga:149126 X-Received-Date: Fri, 07 Nov 2008 13:10:57 EST (flpi142.ffdc.sbc.com) On Fri, 7 Nov 2008 10:00:36 -0800 (PST) Dale <dale.prather@gmail.com> wrote: > Yes, I'm using XST. I'm using a Spartan 3. I took your suggestion, > Rob and again replaced "onehot" with garbage and it still synthesized. > Any chance that attribute is invalid with a spartan 3? I "think" I > read that somewhere. > Thanks. Not at all. I use Spartan 3s, and have successfully used that attribute to force the encoding. One thing is that "onehot" is just as much garbage as "asdfhalksdjfh"; XST wants "one-hot". In the 10.1 documentation, FSM_ENCODING is covered in xst.pdf, page 370, with a full list of what options it supports. I'm not 100% sure that, if you specify an invalid encoding type, that it will throw an error rather than just assume "auto" and keep right on going. What you should try is asking it for "one-hot" and for one of the other defined types, then looking through the synthesis report file and seeing how it got encoded. There'll be a block of text beginning with the phrase Found finite state machine down in the HDL synthesis section, and it'll tell you the encoding style that it used. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 136245
" Found finite state machine down in the HDL synthesis section, and it'll tell you the encoding style that it used. " Great idea. That's solid proof. I'm on it.Article: 136246
Thanks for all of your help. The reference to the xst.pdf was helpful also. I confirmed that if I put garbage in as the string, xst just defaults it to auto. I don't like that at all. If I make a typo, there's no way of knowing that my FSM is not as I want it without going through the report and confirming each one. Oh well, I'll just have to make sure I don't make a typo. Another useful attribute I found in the xst.pdf was the fsm_extract. Using this I can turn off FSM encoding/extracting altogether. Thanks for all of your help.Article: 136247
On Nov 7, 10:31=A0am, Dale <dale.prat...@gmail.com> wrote: > I was wondering if there is a way to set the way ISE encodes state machin= es > other than in project navigator? I'd like to be able to set it in the VH= DL file or > in the UCF. =A0It's really a quality control problem. =A0 I can't see how this could ever be a 'quality control problem'. > As the project is > touched by many people and as it's upgraded to newer versions of ISE > software the encoding method seems to get changed. =A0 Unless the newer versions address some particular issue that your project is having you shouldn't be changing versions of your tools when you get anywhere near the point where your deploying the design. Doing that frequently is more of a 'quality control' problem in itself. > I want to be able > to guarantee that it's set to what I want it to be set to. If the code is using enumerated types, then you haven't set the encoding to be anything so there is nothing to guarantee. If you have a need for a specific encoding then the logic in the VHDL code should directly reflect that. The path that the rest of this thread has gone down for trying to 'guarantee' an encoding based on synthesis tool settings will not guarantee anything since it is tool dependent and as you're already seeing doesn't always do what you want either. The other question to answer is why you "want to be able to guarantee that it's set to what I want it to be set to" in the first place? A valid reason might be because you've found that, for a particular hunk- o-code you get dismal clock performance. If you do have such a valid reason, then you should rewrite that particular hunk-o-code a bit to reflect just that (it's not that difficult). Doing so will directly solve your issue and will actually be guaranteed as well as portable to other tools/versions of tools. If you don't have such a valid reason and are just trying to lock things down out of paranoia then you should either - Relax and let the synthesis tools do their job - Eliminate all enumeration types from your code and come back to them when you are ready to let the synthesis tool take care of that encoding task for you. Kevin JenningsArticle: 136248
On Nov 7, 1:40=A0pm, Dale <dale.prat...@gmail.com> wrote: > I confirmed that if I put garbage in as the string, xst just defaults > it to auto. =A0I don't like that at all. =A0If I make a typo, there's no > way of knowing that my FSM is not as I want it without going through > the report and confirming each one. =A0Oh well, I'll just have to make > sure I don't make a typo. > Or don't use non-portable, uncheckable synthesis attributes for something that should be explicit in the design code (see my other reply off of your original posting). KJArticle: 136249
On 7 Nov, 18:00, Benjamin Couillard <benjamin.couill...@gmail.com> wrote: > On 7 nov, 11:47, Leon <leon...@btinternet.com> wrote: > > > > > On 7 Nov, 16:11, Benjamin Couillard <benjamin.couill...@gmail.com> > > wrote: > > > > On 7 nov, 05:25, mentari <Stephan...@gmail.com> wrote: > > > > > What are your views onhttp://scratchpad.wikia.com/wiki/TileraMultic= ore > > > > as a replacement for FPGA's ? > > > > >http://www.tilera.com/solutions/digital_baseband.php > > > > > The current architecture for base stations fall short of delivering > > > > the performance, the low latency and the flexibility customers need= . > > > > To meet the requirements, wireless equipment providers design compl= ex > > > > systems with FPGA, ASIC, DSP and processors with each component > > > > requiring special tools in a customized development environment. Th= is > > > > leads to a long development cycle, sometimes years, before > > > > applications can be productized. Changes in standards also impact > > > > providers because such systems are inflexible-upgrades can be a slo= w > > > > and expensive process. > > > > > What providers seek is an uncomplicated, well-designed, architectur= e > > > > that yields good performance. Tilera's processors provide a low > > > > latency single solution that integrates many functions seamlessly i= n a > > > > single processor and uses C/C++ to program their applications with > > > > industry standard tools. The familiar tools enable customers to > > > > preserve their software investments, replace a number of disparate > > > > programming methodologies with one standard programming environment= , > > > > and gain the flexibility they need to support evolving protocols an= d > > > > ever-increasing demands for service > > > > It seems to be similar to XMOS devices. I suppose that it could > > > replace FPGAs in some applications. However, it's still a much coarse= r > > > architecture than an FPGA. =A0There's still only 64 processing units, > > > while a Virtex-5 can have about 20 000 slices and a couple of PPC > > > processors. In the end, I think that since FPGAs are much more > > > flexible, they have the upper hand. Plus with tools like system > > > generator, AccelDSP and Simulink, low-level HDL coding can be skipped= , > > > and the engineer can focus more on applications and less on the "bit- > > > level" of things. > > > > Plus I suppose that with a high-capacity FPGA, one could emulate a > > > Tilera-like device with 64 processing units. Maybe the future's there= , > > > take the Tilera (or Xmos) concept and implement it in a FPGA. > > > > My 2 cents > > > They will cost more, be much harder to use, use a lot more power and > > won't be any faster. > > > Leon > > THe point is not that it will be faster, is that it'll be much more > versatile since you won't be stuck with a fixed architecture You won't have 64k per core, and what about stuff like 100 MHz I/Os, hardware threads switching in one cycle, and 3.2 Gb/s full duplex links between cores? Leon
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