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Hello everyone. Now I need to convert MATLAB file(m-file) to VHDL. I've heard that there are some of automatic converting tools like Simulink and Acceldsp. But I have to do manually. My matlab code has many matrix operations like transpose,reshape, squeeze and so on. So is there anyone who can give me an advice fot this?Article: 135726
I am using a Spartan 3 Starter board from Digilent... I am feeding a square wave to my D9 pin (I/O pin) and my board counts the square wave, displaying the max count on the LED. However, when I turn off the square wave and simply touch the output of the D9, the FPGA counts be itself. Is there some touch sensitive stuff that I am not aware about with the I/O pins ? How do I really know that the FPGA is counting signals from the input or if the FPGA is just picking out some external pulses...I feel that it really isn't counting the square wave pulses...please help me with this occurance. UcehnnaArticle: 135727
On Oct 14, 1:31=A0am, Joerg <notthisjoerg...@removethispacbell.net> wrote: > > There was nothing innovative about the design of the Transputer. The > > device as it was supposed to be (i.e. separate comms and execution > > planes), rather than the crippled one they shipped, was similar to > > designs several people in the UK (and presumably elsewhere) were > > toying with at that time. The others did not proceed because the > > economics looked so wrong. > > Toying means nothing in our industry, it's all about rolling out actual > product. That is what Inmos did. But: > > The economics didn't have to look wrong. They were wrong because IMHO a > cardinal mistake had been made: Entering the market with very high price > tags. That was bound to fail and cause me to turn away. Same thing > happened with S/C filter chips. > > Next, they should have lined up an early licensing deal with a major > semiconductor manufacturer, one that engineers trust. This is extremely > important. Nobody in their right mind would design in a single-source > part from a tiny manufacturer without a serious business track record. > My guess is that a few more business-thinkers could have potentially > saved the bacon at Inmos. Going to market with an impractical product is much worse than toying and figuring out its impractical before you spend the big bucks. I remember when the Inmos people kept trying to sell their filter chip into a board I was doing. The board's BOM target was about 130 pounds (more or less met in the end), while their chip in 100k volume was something like 800 pounds. I guess the salesman had few other leads to follow if he kept wasting his time on us. Regards, SteveArticle: 135728
Someone wrote: >>> micro-SD adapter for PMOD extension slot (http://www.microdream-1.com/ >>> Pmod-B.html). I wrote: >> You mean there's actually a way to purchase those? Antti wrote: > http://www.trenz-electronic.de/ > Trenz electronic has them in stock and several Xilinx kits are > shipping with them as bundled package from Trenz webshop They're remarkably well hidden. Even with that URL I can't find them. Have you considered putting a link on the microdream-1 page to a page where they can actually be purchased? EricArticle: 135729
steveu@coppice.org wrote: > On Oct 14, 1:31 am, Joerg <notthisjoerg...@removethispacbell.net> > wrote: >>> There was nothing innovative about the design of the Transputer. The >>> device as it was supposed to be (i.e. separate comms and execution >>> planes), rather than the crippled one they shipped, was similar to >>> designs several people in the UK (and presumably elsewhere) were >>> toying with at that time. The others did not proceed because the >>> economics looked so wrong. >> Toying means nothing in our industry, it's all about rolling out actual >> product. That is what Inmos did. But: >> >> The economics didn't have to look wrong. They were wrong because IMHO a >> cardinal mistake had been made: Entering the market with very high price >> tags. That was bound to fail and cause me to turn away. Same thing >> happened with S/C filter chips. >> >> Next, they should have lined up an early licensing deal with a major >> semiconductor manufacturer, one that engineers trust. This is extremely >> important. Nobody in their right mind would design in a single-source >> part from a tiny manufacturer without a serious business track record. >> My guess is that a few more business-thinkers could have potentially >> saved the bacon at Inmos. > > Going to market with an impractical product is much worse than toying > and figuring out its impractical before you spend the big bucks. I > remember when the Inmos people kept trying to sell their filter chip > into a board I was doing. The board's BOM target was about 130 pounds > (more or less met in the end), while their chip in 100k volume was > something like 800 pounds. I guess the salesman had few other leads to > follow if he kept wasting his time on us. > That's exactly the cardinal mistake I mentioned above. Coming into the market with a totally unrealistic price is bound to fail. And it did. Usually that happens after spending big bucks in NRE, it's all way behind schedule and the investors demand a rather quick and unrealistic ROI. Seen it many times, failed every single time. You should have seen some of the faces here when high-faluting chips were presented and then I told them that my discrete solution costs a buck fifty. -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM.Article: 135730
Floating CMOS inputs do exactly what you just saw. It's not a function of the FPGA, it's a function of CMOS architecture. I would suggest either ensuring that the input is always driven or pulling the input to a deterministic state. Xilinx FPGAs all have programmable pull-up and pull-down resistors for input/output buffers. You can insert one easily in the UFC file by adding a PULLUP or PULLDOWN constraint to the pin. - Nathan On Oct 13, 4:42=A0pm, uraniumore...@gmail.com wrote: > I am using a Spartan 3 Starter board from Digilent... > > I am feeding a square wave to my D9 pin (I/O pin) and my board counts > the square wave, displaying the max count on the LED. However, when I > turn off the square wave and simply touch the output of the D9, the > FPGA counts be itself. Is there some touch sensitive stuff that I am > not aware about with the I/O pins ? How do I really know that the FPGA > is counting signals from the input or if the FPGA is just picking out > some external pulses...I feel that it really isn't counting the square > wave pulses...please help me with this occurance. > > UcehnnaArticle: 135731
uraniumore238@gmail.com wrote: > I am using a Spartan 3 Starter board from Digilent... > > I am feeding a square wave to my D9 pin (I/O pin) and my board counts > the square wave, displaying the max count on the LED. However, when I > turn off the square wave and simply touch the output of the D9, the > FPGA counts be itself. Is there some touch sensitive stuff that I am > not aware about with the I/O pins ? How do I really know that the FPGA > is counting signals from the input or if the FPGA is just picking out > some external pulses...I feel that it really isn't counting the square > wave pulses...please help me with this occurance. > > Ucehnna There are concepts such as stored charge and static electricity that can affect inputs - particularly floating inputs - and may damage your device if you're not careful! Inputs are intended to be driven by ground-referenced signals within a defined voltage range. If you have a low impedance pull-up or pull-down on your input, you will *typically* not see the signal change by touching the signal pin PROVIDED THAT you have discharged your body to ground first. If you don't discharge to ground - perhaps through a grounding strap worn for static protection - you can damage sensitive electronics!Article: 135732
"KJ" <lkjrsy@gmail.com> wrote in message
news:fb5d4c29-f122-43ae-9e1f-06886d9bd7c2@a3g2000prm.googlegroups.com...
> Hello everyone.
>
> Now I need to convert MATLAB file(m-file) to VHDL.
> I've heard that there are some of automatic converting tools like
> Simulink and Acceldsp.
> But I have to do manually. My matlab code has many matrix operations
> like transpose,reshape, squeeze and so on.
>
> So is there anyone who can give me an advice fot this?
Well, this isn't quite MATLAB-to-VHDL recipes, but I would say that there's
quite a lot of steps to manually create VHDL for a bunch of "simple" array
operations, especially if any of your dimensions are dynamic. VHDL for
DSP/array math is much more akin to data flow programming versus the
procedural structure of MATLAB algorithms. That's why many of the
"MATLAB-to-VHDL" processes really work best as "Simulink-to-VHDL" processes.
It was easier for me to go straight from a dataflow picture of my DSP
processing to a VHDL implementation than to try to bend Matlab/Simulink to
fit. Others have had positive results with these tools, especially if you
can leverage a lot of library blocks. You could see if your major steps can
be broken down into a pipeline of blocks that then could be implemented
using vendor or third-party IP blocks.
I would suggest you seriously investigate an alternative like the current
fad of "GPU acceleration." For instance, even the basic MMX Pentium
instructions can be leveraged to make your PC a faster array processor.
Intel and a few others have built (even free!) tools and libraries for doing
this from C and/or Fortran. Going further, that high-end Nvidia chip running
your display can instead be "repurposed" as an even hotter array processor.
A couple of our programs are getting good results this way, and the
performance/{watt,cu. in.} is pretty impressive.
There is a company that is selling a "Matlab accellerator" products. Since
the Matlab processing for one task we had was more I/O bound than anything,
this didn't meet our needs but it could meet yours. You may want to check it
out: http://www.agilityds.com/
Good luck,
Marty
Article: 135733On Oct 13, 5:53=A0pm, John_H <newsgr...@johnhandwork.com> wrote: > uraniumore...@gmail.com wrote: > > I am using a Spartan 3 Starter board from Digilent... > > > I am feeding a square wave to my D9 pin (I/O pin) and my board counts > > the square wave, displaying the max count on the LED. However, when I > > turn off the square wave and simply touch the output of the D9, the > > FPGA counts be itself. Is there some touch sensitive stuff that I am > > not aware about with the I/O pins ? How do I really know that the FPGA > > is counting signals from the input or if the FPGA is just picking out > > some external pulses...I feel that it really isn't counting the square > > wave pulses...please help me with this occurance. > > > Ucehnna > > There are concepts such as stored charge and static electricity that can > affect inputs - particularly floating inputs - and may damage your > device if you're not careful! > > Inputs are intended to be driven by ground-referenced signals within a > defined voltage range. =A0If you have a low impedance pull-up or pull-dow= n > on your input, you will *typically* not see the signal change by > touching the signal pin PROVIDED THAT you have discharged your body to > ground first. =A0If you don't discharge to ground - perhaps through a > grounding strap worn for static protection - you can damage sensitive > electronics! Hi Guys! Thanks for the help. So, I can insure myself that the FPGA is counting as long as the FPGA is always driven by some input square wave and not floting to some external squivering ? How would I verify that it is actually counting (despite the fact that the count value got to the max) ? Any ideas ?Article: 135734
On 13 Oct, 16:06, pfri...@yahoo.co.uk wrote: > Hello! > > I would like to write image files (*.bmp, ...) to micro-SD card. > I am using Spartan 3e starter kit with microblaze soft processor and a > micro-SD adapter for PMOD extension slot (http://www.microdream-1.com/ > Pmod-B.html). > The general idea is to write files in FAT16 file system to micro-SD > card and then later transfer them to PC. > Does anybody have an idea (or reference design) how to do this? Is it > possible to use DOSFS? > > Thanks! Do you need a file system whilst doing FPGA accesses? If you put the sd card in the pc, delete every file, then create a single file which is the size of the available space you will find that all the fat blocks are sequential. The fpga can use the memory as a single block which then needs simple sorting out back in the PC. I've done this with no problem. ColinArticle: 135735
I am reading this forum for quite some time now. Quite often, the use of softcores in FPGAs is discussed here. I do see almost no mentioning of the embedded hard cores PowerPC405/440 that are available in some Xilinx devices. Are they used in any real world designs at all? Or are there just no issued that need to be discussed? My impression is that the hardcores are really valuable because of their performance and the tight integration into the fabric, especially with the PowerPC APU. I also think that the co-simulation possibilities between the hardware design and the PowerPC software is a bonus. Is anyone using the APU interface for anything else then a custom FPU? I am aware that there are severe drawbacks associated with the hardcores: the devices are high-end (and expensive) and you have to trade of flexible slice resources vs. a fixed hardcore. I am curios on you opinions. MarkusArticle: 135736
Hi, The above link (http://help.xilant.com/Xilinx:Configuration:CRC) is not valid anymore. Would some one who has a copy of the CRC calculation algorithm for Virtex 4 send me a copy please. Thanks in advance. ShahramArticle: 135737
Thanks everybody for really useful ideas. I think the best solution for me would be DOSFS with SPI core because I need to write multiple image files to micro-SD card and later make them available to PC users. Link to Trenz Electronic where you can purchase Micro-SD Adapter for Xilinx PMOD Extension Slot: http://shop.trenz-electronic.de/catalog/product_info.php?cPath=1_65&products_id=348 (Online Shop -> FPGA/CPLD Boards -> Industrial Modules)Article: 135738
On Oct 13, 10:36=A0pm, uraniumore...@gmail.com wrote: > How would I verify that it is > actually counting (despite the fact that the count value got to the > max) ? Any ideas ? > Same way you would verify any function, give it a known stimulus and check the result. In your case... 1. Give it 10 (as an example) things to count and verify that you get a count of 10. 2. Repeat step #1 a few times verifying that you get 10 counts every time. 3. Repeat steps #1 and 2 but change '10' to be 'max - 1' (as another example). KJArticle: 135739
Where can I find information on PRBS generator of Aurora cores for Xilinx devices. I have been searching the aurora core documentation but havent found anything yet.Article: 135740
On Oct 14, 4:07=A0am, Markus <n...@nowhere.org> wrote: > I am reading this forum for quite some time now. Quite often, the use of > softcores in FPGAs is discussed here. I do see almost no mentioning of th= e > embedded hard cores PowerPC405/440 that are available in some Xilinx devi= ces. > > Are they used in any real world designs at all? > > Or are there just no issued that need to be discussed? > > My impression is that the hardcores are really valuable because of their > performance and the tight integration into the fabric, especially with th= e > PowerPC APU. I also think that the co-simulation possibilities between th= e > hardware design and the PowerPC software is a bonus. > > Is anyone using the APU interface for anything else then a custom FPU? > > I am aware that there are severe drawbacks associated with the hardcores: > the devices are high-end (and expensive) and you have to trade of flexibl= e > slice resources vs. a fixed hardcore. > > I am curios on you opinions. > > Markus Oh there have been a few posts about the use of the hardcore processors. I know I've posted some myself. The problem with those entities is that they are generally found in more expensive development boards and many people tend to stick to the cheaper boards for learning. It's during the initial learning phase that most of the posts about the processors usually show up. The 405 has been making a bit more of a comeback because the Xilinx XUPV2 boards are being used more in the classrooms for embedded teaching/research. The issue with these is that for most cases, the users do not deviate from the check-box configuration provided by the EDK tools. Out-of-the-box, the boards and their system work fine and now they're onto debugging their software. With the Microblaze, it has more FPGA/ BIG (macro?) microcontroller uses that things like the Picoblaze cannot provide. It also has less overhead for instantiating some interfaces where as the PPC's have a few requirements just to have a basic 405 system. I'd also say that we see more Microblaze questions because it can be used in more places. The 405/440 are only available in the Virtex2-Pro, V4FX, and the V5FXT parts, where are the Microblaze can be used on anything from the Virtex2,4,5, and even some of the Spartan 3's. -- MikeArticle: 135741
I have the IEEE standard 802.3 documents but find they're not the most readable in the world. I find they confuse issues by having many standards in one document. Is there a more readable document around which is specifically related to 100Base-TX? Does any one know of example waveforms I could include in a test bench, so I can check the scrambling and descrambling of data? I am aware of a very good site for 10Base-T not for for fast ethernet. I'm trying to send an Ethernet packet direct from a FPGA though a suitable line driver.Article: 135742
On 13 Oct, 20:42, Eric Smith <e...@brouhaha.com> wrote: > Bob wrote about XMOS: > > > They seem far too fixated on doing everything in software, things like > > ethernet where there is no point shoveling bytes in software if > > hardware can take care of it. > Leon wrote: > > They are supplying free libraries for all the usual peripheral > > functions. Doing stuff like that in software is much cheaper than > > using hardware, and easier in many ways. > > Been there, done that, and it's not cheaper or easier when you > consider the overall system cost impact, not just the "benefit" of > leaving out the hardware block. =A0That was the path Scenix/Ubicom went > down, calling it "virtual peripherals", and it was not very > successful. =A0Ubicom has since added hardware for Ethernet, USB, > etc. to their most recent parts. =A0The reality is that a hardware > Ethernet MAC costs less than the total system cost impact of the > software alternative. > > Eric Not if you have four 400 MIPS cores on the chip, each with 64 bits of I/O, 64k of RAM, with 3.2 Gbit/s comms links between cores and 32 threads per core, with switching between threads in one clock. If the software is free, it is a very cost-effective solution, especially as the chips will be very cheap. LeonArticle: 135743
In the Core Generator there are 2 separate Aurora IPs: "GTP Aurora 2.8" and "Virtex-5 Aurora 3.0". Both work with Virtex 5 LXTs so which one is the best to use? Presumably the "Virtex 5" version, is this right? What's the difference anyway? In my project several dual tiles will be used, clocked via the GTP Dedicated Clock Routing from 2 sources. How is the clock routing set-up? Once set it'll never be changed. Do the RefClk_Sel0,1,2 and ClkNorth, ClkSouth bits have to be set using the DRP?! or is there a simpler way? TIA Roger.Article: 135744
In article <3d4b6f41-b742-405d-87bd- 47e2fb75ac1d@8g2000hse.googlegroups.com>, leon355@btinternet.com says... > On 13 Oct, 20:42, Eric Smith <e...@brouhaha.com> wrote: > > Bob wrote about XMOS: > > > > > They seem far too fixated on doing everything in software, things lik= e > > > ethernet where there is no point shoveling bytes in software if > > > hardware can take care of it. > > Leon wrote: > > > They are supplying free libraries for all the usual peripheral > > > functions. Doing stuff like that in software is much cheaper than > > > using hardware, and easier in many ways. > > > > Been there, done that, and it's not cheaper or easier when you > > consider the overall system cost impact, not just the "benefit" of > > leaving out the hardware block. =A0That was the path Scenix/Ubicom went > > down, calling it "virtual peripherals", and it was not very > > successful. =A0Ubicom has since added hardware for Ethernet, USB, > > etc. to their most recent parts. =A0The reality is that a hardware > > Ethernet MAC costs less than the total system cost impact of the > > software alternative. > > > > Eric >=20 > Not if you have four 400 MIPS cores on the chip, each with 64 bits of > I/O, 64k of RAM, with 3.2 Gbit/s comms links between cores and 32 > threads per core, with switching between threads in one clock. If the > software is free, it is a very cost-effective solution, especially as > the chips will be very cheap. The PC market solution to determinisity - =09"If in doubt put bigger processor(s) and=20 =09 lots more memory to solve the 'problem'" Having seen how easily screwed even software UARTs can get, and when something goes wrong all other activity is screwed. The PC example is dodgy CD inserted, nothing else can work until the upto 30 seconds of lockout. Lots of other examples exist. This sort of software emulation of hardware ONLY is useful for cheap and nasty commodity products that assume that unusability is always solved by a reset (for some products that means host PC AS WELL!). This means for the VAST majority of my applications it is useless. --=20 Paul Carpenter | paul@pcserviceselectronics.co.uk <http://www.pcserviceselectronics.co.uk/> PC Services <http://www.pcserviceselectronics.co.uk/fonts/> Timing Diagram Font <http://www.gnuh8.org.uk/> GNU H8 - compiler & Renesas H8/H8S/H8 Tiny <http://www.badweb.org.uk/> For those web sites you hateArticle: 135745
In article=20 <3d4b6f41-b742-405d-87bd-47e2fb75ac1d@8g2000hse.googlegroups.com>,=20 leon355@btinternet.com says... > On 13 Oct, 20:42, Eric Smith <e...@brouhaha.com> wrote: > > Bob wrote about XMOS: > > > > > They seem far too fixated on doing everything in software, things lik= e > > > ethernet where there is no point shoveling bytes in software if > > > hardware can take care of it. > > Leon wrote: > > > They are supplying free libraries for all the usual peripheral > > > functions. Doing stuff like that in software is much cheaper than > > > using hardware, and easier in many ways. > > > > Been there, done that, and it's not cheaper or easier when you > > consider the overall system cost impact, not just the "benefit" of > > leaving out the hardware block. =A0That was the path Scenix/Ubicom went > > down, calling it "virtual peripherals", and it was not very > > successful. =A0Ubicom has since added hardware for Ethernet, USB, > > etc. to their most recent parts. =A0The reality is that a hardware > > Ethernet MAC costs less than the total system cost impact of the > > software alternative. > > > > Eric >=20 > Not if you have four 400 MIPS cores on the chip, each with 64 bits of > I/O, 64k of RAM, with 3.2 Gbit/s comms links between cores and 32 > threads per core, with switching between threads in one clock. If the > software is free, it is a very cost-effective solution, especially as > the chips will be very cheap. The PC market solution to determinisity - =09"If in doubt put bigger processor(s) and=20 =09 lots more memory to solve the 'problem'" Having seen how easily screwed even software UARTs can get, and when something goes wrong all other activity is screwed. The PC example is dodgy CD inserted, nothing else can work until the upto 30 seconds of lockout. Lots of other examples exist. This sort of software emulation of hardware ONLY is useful for cheap and nasty commodity products that assume that unusability is always solved by a reset (for some products that means host PC AS WELL!). This means for the VAST majority of *my* applications it is useless. --=20 Paul Carpenter | paul@pcserviceselectronics.co.uk <http://www.pcserviceselectronics.co.uk/> PC Services <http://www.pcserviceselectronics.co.uk/fonts/> Timing Diagram Font <http://www.gnuh8.org.uk/> GNU H8 - compiler & Renesas H8/H8S/H8 Tiny <http://www.badweb.org.uk/> For those web sites you hateArticle: 135746
On 12 oct, 15:52, Equinox <soham...@gmail.com> wrote: > Hi All, > > Can somebody suggest me a technical report/paper/case study of > implementation of Complex Event Processing in FPGA. > > Basically, I want to know how to implement CEP in FPGA. I am trying to > build a high volume high speed data stream handling device[hint: think > trading!] and I need that initial 'handle' to start developing/getting > started in implementation of CEP in FPGA. > > Your suggestions, comments are most welcome > > Soham CHeck out http://www.impulsec.com/ THey have a "C-To-FPGA" environment that allows people to design C software and then accelerate it in Hardware (i.e. an FPGA). One of the application they mention is "Financial feed handling". I've never used the product though, YMMVArticle: 135747
Where can I find this kind of parameters? I have heared that the Xilinx's clock scenario is not good. Is that right?Article: 135748
Hello everyone,
I am very new in VHDL programming. For my work I am using ISE 10.1 and
ModelSim XE III 6.3c. I am facing some problems in programming a simple
code. the code is as follows:
------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test is
port(
clk: in std_logic;
in_i1: in std_logic_vector(7 downto 0);
out_i1: out std_logic_vector(7 downto 0)
);
end test;
architecture a of test is
signal signed_out_i1: signed(7 downto 0);
begin
process(clk)
begin
if (clk'event and clk = '1') then
signed_out_i1 <= -signed(in_i1);
end if;
end process;
out_i1 <= std_logic_vector(signed_out_i1);
end a;
----------------------------------------
Problem # 1:
I want "signed_out_i1" will be changed to negative of "in_i1" at each
clock change to 1. the behavioral (functional) simulation works alright and
shows the expected result. But the in the Post-translate simulation the
output is not as expected. I used the following testbench code:
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test_tb is
end test_tb;
architecture test_tb_arch of test_tb is
component test
port(
clk: in std_logic;
in_i1: in std_logic_vector(7 downto 0);
out_i1: out std_logic_vector(7 downto 0)
);
end component;
signal clk: std_logic;
signal in_i1,out_i1: std_logic_vector(7 downto 0);
begin
aaaa: test port map(clk,in_i1,out_i1);
process
begin
clk<='0';
in_i1<="11111111";
wait for 50 ns;
clk<='1';
in_i1<="00000001";
wait for 50 ns;
clk<='0';
in_i1<="00000001";
wait for 50 ns;
clk<='1';
in_i1<="11111111";
wait for 50 ns;
end process;
end test_tb_arch;
configuration AOA of test_tb is
for test_tb_arch
end for;
end AOA;
-----------------------------------------------------------
the expected output should be either "00000001" or "11111111". But in the
output it shows "11001001" and "00110111". Can anyone explain what is the
problem?
Problem # 2:
Another problem is that when I run Post-map Simulation or Post-route
simulation in ISE 10.1 the simulation output is not shown in Modelsim. It
shows the following ERROR in ModelSim:
# ** Warning: Design size of 12274 statements or 0 non-Xilinx leaf
instances exceeds ModelSim XE-Starter recommended capacity.
# Expect performance to be quite adversely affected.
# ** Error: (vsim-SDF-3250) netgen/map/test_map.sdf(0): Failed to find
INSTANCE '/UUT'.
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./test_tb.mdo PAUSED at line 8
How to solve the problem?
I will be very greatful if anyone can help me to solve the problems.
Thanks and best regards,
Pantho
Article: 135749"samliu" <china.ruiliu@gmail.com> wrote in message news:yr2dneRkw_eBR2nVnZ2dnUVZ_h6dnZ2d@giganews.com... > Where can I find this kind of parameters? Read the datasheet. > I have heared that the Xilinx's clock scenario is not good. Is that > right? No, what you have heard is wrong. Bob -- == All google group posts are automatically deleted due to spam ==
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