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> No idea why, though. In my experience this phrase often accompanies the Xilinx constraint system! ;-) FYI: In my design I put a TNM_NET on the internal clock signals after they are buffered, which works well. I'm just guessing here, but your first attempt may not have worked because you are using TNM_NET rather than TNM, these two constraints behave differently for IO pins.Article: 135876
At the start of the year, there were suggestions that WebPack 10.1 would support Windows x64, but this has turned out not to be the case. Is there any newer news on when an x64-supporting WebPack will come out? I don't care about WebPack being a 32-bit application or 64-bit; the 32-bit version of WebPack works fine (if as slow as molassas) on XP x64 (and Vista x64) except for iMPACT. Has Xilinx intentionally prevented the 32-bit iMPACT from using the 64-bit USB drivers (which install fine), or is it simply a case of poor software engineering tying the USB driver bitness to the application layer bitness? Currently, I'm using a spare machine that does nothing except run 32-bit XP solely for ISE to upload designs to the board, but with summer coming here in Australia, I'd like to get rid of the extra heat source. -- Michael Brown Add michael@ to emboss.co.nz ---+--- My inbox is always openArticle: 135877
On Oct 19, 2:45=A0pm, Jukka Marin <jma...@pyy.embedtronics.fi> wrote: > > I would try putting the RAM stuff inside one always block, but it seems a > bit difficult to do.. (or, I still can't think FPGA - my brain always > seems to enter software mode when opening a text editor). > > I'd appreciate pointers or examples which would get me unstuck. ;-) > Start around page 13 http://www.altera.com/literature/hb/qts/qts_qii51007.pdf KJArticle: 135878
Hi newsgroup, I am curious about the Xilinx paper WP335. Are there VHDL examples available illustrating the different EBR usage areas described in the paper ? Best regards, AluPinArticle: 135879
Hi, guys I learned fpga and vhdl years ago in university, built a toy cpu and something like that. Not much. Now I want to pick up and do some hobby project, but I have no idea what board in the market is for people like me. It has to be robust and cheap. Any recommendation? thanks a lot. chaojiArticle: 135880
Because of all the feedback we got in response to the initial open- source release of Genode FX in August, here comes a follow-up about our progress since then. Genode FX is a combination of hardware and software for creating GUIs on FPGA platforms. The initial release relied on the Spartan-3A Starter Kit as reference platform. Since then, we enhanced the range of supported platforms to the following FPGA boards: - Spartan-3A/3AN/3E Starter Kits using the Microblaze softcore - Virtex-4-based ML405 evaluation platform using the PowerPC 405 - Virtex-5-based ML507 evaluation platform using the PowerPC 440 For those boards, there exist ready-to-use example EDK projects. Furthermore, we thoroughly documented the process of incorporating Genode FX into a custom EDK project by the example of supporting the ML405 board: https://sourceforge.net/docman/display_doc.php?docid=132123&group_id=237260 You can find the latest source code and binary demonstrations for all the supported platforms at our project site at Sourceforge: https://sourceforge.net/projects/genode-fx/ Special thanks to Tamas Szabo for adding the Spartan-3AN support and Ales Gorkic for adding the Spartan-3E support! Regards NormanArticle: 135881
Hi, I would like to connect an external clk source (i.e. signal generator) to my virtex 2 pro board (xupv2p) The thing is that I didn't really unterstand the concept of differential clocks. Can I just connect one clk source to one input or do i have to have an input for both EXTERNAL_CLOCK_P and EXTERNAL_CLOCK_N. Whats the difference between those. Thanks for your help. SebastianArticle: 135882
Michael, I'm in a similar situation. I don't know why Xilinx do what they do. I'd have thought they'd have gone for 64 bit whole-heartedly - shame they haven't. Sorry I can't shed any more light on the situation. Rog. "Michael Brown" <see@signature.below> wrote in message news:48fc54df$0$18427$afc38c87@news.optusnet.com.au... > At the start of the year, there were suggestions that WebPack 10.1 would > support Windows x64, but this has turned out not to be the case. Is there > any newer news on when an x64-supporting WebPack will come out? I don't > care about WebPack being a 32-bit application or 64-bit; the 32-bit > version of WebPack works fine (if as slow as molassas) on XP x64 (and > Vista x64) except for iMPACT. Has Xilinx intentionally prevented the > 32-bit iMPACT from using the 64-bit USB drivers (which install fine), or > is it simply a case of poor software engineering tying the USB driver > bitness to the application layer bitness? > > Currently, I'm using a spare machine that does nothing except run 32-bit > XP solely for ISE to upload designs to the board, but with summer coming > here in Australia, I'd like to get rid of the extra heat source. > > -- > Michael Brown > Add michael@ to emboss.co.nz ---+--- My inbox is always openArticle: 135883
On 2008-10-20, KJ <kkjennings@sbcglobal.net> wrote:
> Start around page 13
> http://www.altera.com/literature/hb/qts/qts_qii51007.pdf
Thanks. I have read this document before, but I noticed something new on
the second time - but still no go. Here are some fragments of my Verilog
source:
`define RXRAMSIZE 16'd2048
`define RXRAMBITS 16'd9
reg [31:0] rx1 [0:`RXRAMSIZE-1] /* synthesis ramstyle = "M9K, no_rw_check" */;
...
reg [`RXRAMBITS-1:0] rx1rptr;
reg [1:0] rx1rbank;
reg [15:0] rx1rlen;
reg [`RXRAMBITS+1:0] rx1b;
reg [`RXRAMBITS+1:0] rx1i;
always @(negedge rd) begin // MCU bus read
if ((cs == 0)) begin
case (a << 2)
...
`REG_RX1LEN: begin
if (rx1rptr == 0) begin
// start a read if data available
rx1rlen = rx1[rx1b][15:0];
if (rx1rlen != 0) begin
rx1rptr = 1;
end
end
dout = rx1rlen;
end
`REG_RX1DATA: begin
if (rx1rptr != 0) begin
// read operation in progress
dout = rx1[rx1i];
rx1rptr = rx1rptr + 1'b1;
if (rx1rptr > rx1rlen) begin
// end of data, move to next bank
rx1rptr = 0;
rx1rbank = rx1rbank + 2'b1;
end
rx1b = rx1rbank << `RXRAMBITS;
rx1i = {rx1rbank, rx1rptr};
end else begin
// no more data
dout = 0;
end
end
endcase
end
end
....
reg [`RXRAMBITS-1:0] rx1wptr;
reg [1:0] rx1wbank;
reg [55:0] fbrx1_flag;
reg [32:0] fbrx1_shifter;
reg [15:0] fbrx1_wordcount;
always @(posedge fbrxc or posedge softreset) begin
if (softreset) begin
rx1wptr = 0;
rx1wbank = 0;
fbrx1_flag = 0;
end else begin
if (fbrx1_wordcount == 0) begin
// searching for start flag
fbrx1_flag = {fbrx1_flag[54:0], fbrxd};
if (fbrx1_flag[55:24] == `FIBER_FLAG) begin
fbrx1_wordcount = fbrx1_flag[15:0];
fbrx1_flag = 0;
fbrx1_shifter = 33'b1;
rx1wptr = 1;
rx1[rx1wbank << `RXRAMBITS] = 0;
end
end else begin
fbrx1_shifter = {fbrx1_shifter[31:0], fbrxd};
if (fbrx1_shifter[32] == 1) begin
rx1[{rx1wbank,rx1wptr}] = fbrx1_shifter[31:0];
fbrx1_shifter = 33'b1;
rx1wptr = rx1wptr + 1'b1;
if (rx1wptr > fbrx1_wordcount) begin
rx1[rx1wbank << `RXRAMBITS] = fbrx1_wordcount;
fbrx1_wordcount = 0;
rx1wbank = rx1wbank + 2'b1;
end
end
end
end
end
I'm trying to receive 32-bit words (bits clocked in on the rising edge of
fbrxc and stored in a 33-bit shift register) and store the data in rx1[],
rx1[0] is supposed to hold the frame length (received after the start flag).
There are four fixed banks in the rx1 buffer, the banks are accessed by
the rx1wbank register.
The first always@() block is part of the MCU bus interface; the MCU reads
the frame length from the REG_RX1LEN register and data from REG_RX1DATA.
The code is not finished yet, I'd like to make it compile before putting
more effort in it.
This is my very first FPGA project, so I may be doing something in the
completely wrong way. I have been working on hardware and software for
more than 20 years, but I'm afraid I haven't learned how to think the
FPGA way yet. I wish I had someone to teach me Verilog and FPGA, but
the "local" Altera FAE has only been using VHDL and hasn't been able to
help too much.
So, is there anything correct in my code? ;-) Thanks!
-jm
Article: 135884Have a look at our Drigmorn1 product http://www.enterpoint.co.uk/component_replacements/drigmorn1.html. It's one of the lowest cost FPGA boards out there. There will also be a new low cost CPLD product available in a few weeks that will have a fun element for the hobby and student market. I'll release more details on the newsgroup that when we have stock ready to ship. Alternatively you can sign up for our newsletter to receivve product release announcements - go http://www.enterpoint.co.uk/signup.html to join that distribution. John Adair Enterpoint Ltd. On 20 Oct, 14:56, licha...@gmail.com wrote: > Hi, guys > > I learned fpga and vhdl years ago in university, built a toy cpu and > something like that. Not much. > > Now I want to pick up and do some hobby project, but I have no idea what > board in the market is for people like me. It has to be robust and > cheap. > > Any recommendation? > > thanks a lot. > > chaojiArticle: 135885
Hi Sebastian differential pins need LVDS standards i.e. both pins should be connected to the appropriate differential signal . At the code level, you only use the (p) pin to identify the clock. However, I believe many of these pins may also accept LVTTL standards and others, so check that and then you can connect your signal to the p pin and ground the n pin if required. Regards kadhiemArticle: 135886
cid wrote:
> I have a B.S.E.E. with basic vhdl/verilog knowledge and currently
> unemployed. I'm trying to break into the industry and need advice
> getting/looking for an entry-level fpga job.
At small companies, fpga work is rarely a full time job.
There, you would need to have experience designing
and turning on a circuit board with an fpga on it.
Large companies might have positions focused on
the fpga design process. You would likely start
verifying an existing design in this case.
> I'm considering taking some fpga classes from xilinx to give me an
> edge, but not sure if the material covered will be worth the cost.
I would pick a language and get a simulator and start by working
on my own. Learn the language and the simulator inside and out to start
with.
Vendor seminars will focus on devices and "free" cores
rather than vhdl or verilog synthesis using your own code.
These can be good for meeting people from nearby companies however.
> I was also thinking of working on my own fpga projects to have my resume/
> skillset stand out.
That is a good idea.
> Does anyone have some advice breaking into the fpga engineering
> industry?
Start doing the work on your own
so that you have something interesting to talk about
Start hanging out with kindred spirits
at classes or seminars.
> Also, it seems like plenty of entry level engineering/programming jobs
> are being outsourced to India/China. Is this true for fpga jobs as
> well?
Not in my experience.
> as far as working on my own fpga projects I am interested in:
>
> cell phone technology
> wireless technology
> video/audio processing
> sonar/radar
Pick one and just do it.
-- Mike Treseler
Article: 135887
Jan wrote:
> Dear all,
>
> What are the smartest way to make a solo FPGA project capable of field
> updates? I'm very new in the FPGA world so I don't much about the
> practical use of them. Normally when I uses microcontrollers I make them
> updateble via USB, serial or SD cards.
That's the way to do it.
Save multiple images in flash.
The uP handles networking and
loading images to flash and fpga.
> What techniques are possible when I want to avoid having a uP in the
> project.
You could put the project
on a pci[e] card and have
the host pc do the updates.
-- Mike Treseler
Article: 135888
> On 2008-10-20, KJ <kkjennings@sbcglobal.net> wrote:
>> Start around page 13
>> http://www.altera.com/literature/hb/qts/qts_qii51007.pdf
That is a nice reference.
Jukka Marin wrote:
> The code is not finished yet, I'd like to make it compile before putting
> more effort in it.
Most designers would use a simulator to debug this code.
A simulator will help with the syntax errors *and*
with logical problems.
> So, is there anything correct in my code? ;-) Thanks!
The only way to find out is to add a module interface
and run a sim. When I get stuck, I go back and start
with a related, working example (maybe from the reference above)
> I have been working on hardware and software for
> more than 20 years, but I'm afraid I haven't learned how to think the
> FPGA way yet.
Here's a hint. The execution environment
for verilog and vhdl code is a simulator.
-- Mike Treseler
Article: 135889On Oct 20, 6:56 am, licha...@gmail.com wrote: > Hi, guys > > I learned fpga and vhdl years ago in university, built a toy cpu and > something like that. Not much. > > Now I want to pick up and do some hobby project, but I have no idea what > board in the market is for people like me. It has to be robust and > cheap. > > Any recommendation? > > thanks a lot. > > chaoji Two options I would consider: 1) Look at the MFG web site (Altera/Xilinx) and buy an entry level board. $150~$200 will get you a lot of gates and a bunch of I/O. 2) Buy a 'previous generation' board off of an auction site. Verify tool-chain support with the current "web pack" before bidding. Good Luck, AlexArticle: 135890
On 20 Oct, 14:56, licha...@gmail.com wrote: > Hi, guys > > I learned fpga and vhdl years ago in university, built a toy cpu and > something like that. Not much. > > Now I want to pick up and do some hobby project, but I have no idea what > board in the market is for people like me. It has to be robust and > cheap. > > Any recommendation? In addition to other suggestions you may want to check out http://www.digilentinc.com/ -- JamesArticle: 135891
On Oct 20, 9:12 am, "sebastian.schuep...@gmail.com" <sebastian.schuep...@googlemail.com> wrote: > Hi, > > I would like to connect an external clk source (i.e. signal generator) > to my virtex 2 pro board (xupv2p) > The thing is that I didn't really unterstand the concept of > differential clocks. Can I just connect one clk source to one input or > do i have to have an input for both EXTERNAL_CLOCK_P and > EXTERNAL_CLOCK_N. Whats the difference between those. > > Thanks for your help. > Sebastian The differential clock input circuitry of the FPGA measures the voltage difference between the two inputs, not their absolute voltage level with respect to a common reference (e.g. ground). The advantage of differential clocks is greater noise immunity. If the differential pair is routed correctly, then a noise source will couple into both inputs, affecting the common mode voltage but not the voltage difference. Also, differential pairs cancel out self noise because each signal of the pair emits an EM field that is of opposite phase with respect to the other. There's plenty of info on the web if you want more detail. Darol KlawetterArticle: 135892
On Oct 13, 6:59=A0am, General Schvantzkopf <schvantzk...@yahoo.com> wrote: > On Wed, 08 Oct 2008 07:35:44 -0700, Pratap wrote: > > Hi, > > I want to synthesize a delay of around 10 ns in Xilinx Virtex2 Pro. So = I > > put around 200 inverters in series and get the desired delay. So I did > > port map the BASIC cell "INV" according to the XST settings. But when i > > place and route I guess the optimizer removes all the intermediate > > buffers and I get very less delay when I do a post route simulation. > > How can I get rid of this problem? > > Thanks in advance. > > -Pratap > > Do you need a delay or can you accomplish your task with a phase shifted > clock? If you can use a phase shifted clock from the DCM that's a much > better way of doing it because it's stable over temperature and process > and because it won't change when the tools change. > > If you must build a delay line from buffers you will have to directly > place them because the routing delays are much more important then the LU= T > delays. Also you should use an XOR instead of an inverter. Tie one side o= f > the XOR to a flop which presets to 1 on reset and then clocks a zero into > the data input. This will be enough to fool XST and PAR into leaving the > components alone.Article: 135893
Hi, Can you please send me some good material on DCM? I actually require to generating delays around 0 ps by having a passive delay of around 1 period and then increasing and decreasing the input frequency slightly.Can DCM help me in that case? On Oct 13, 6:59=A0am, General Schvantzkopf <schvantzk...@yahoo.com> wrote: > On Wed, 08 Oct 2008 07:35:44 -0700, Pratap wrote: > > Hi, > > I want to synthesize a delay of around 10 ns in Xilinx Virtex2 Pro. So = I > > put around 200 inverters in series and get the desired delay. So I did > > port map the BASIC cell "INV" according to the XST settings. But when i > > place and route I guess the optimizer removes all the intermediate > > buffers and I get very less delay when I do a post route simulation. > > How can I get rid of this problem? > > Thanks in advance. > > -Pratap > > Do you need a delay or can you accomplish your task with a phase shifted > clock? If you can use a phase shifted clock from the DCM that's a much > better way of doing it because it's stable over temperature and process > and because it won't change when the tools change. > > If you must build a delay line from buffers you will have to directly > place them because the routing delays are much more important then the LU= T > delays. Also you should use an XOR instead of an inverter. Tie one side o= f > the XOR to a flop which presets to 1 on reset and then clocks a zero into > the data input. This will be enough to fool XST and PAR into leaving the > components alone.Article: 135894
On Oct 13, 6:59=A0am, General Schvantzkopf <schvantzk...@yahoo.com> wrote: > On Wed, 08 Oct 2008 07:35:44 -0700, Pratap wrote: > > Hi, > > I want to synthesize a delay of around 10 ns in Xilinx Virtex2 Pro. So = I > > put around 200 inverters in series and get the desired delay. So I did > > port map the BASIC cell "INV" according to the XST settings. But when i > > place and route I guess the optimizer removes all the intermediate > > buffers and I get very less delay when I do a post route simulation. > > How can I get rid of this problem? Hi, Can you please send me some good material on DCM? I actually require to generating delays around 0 ps by having a passive delay of around 1 period and then increasing and decreasing the input frequency slightly.Can DCM help me in that case? -pratap > > Thanks in advance. > > -Pratap > > Do you need a delay or can you accomplish your task with a phase shifted > clock? If you can use a phase shifted clock from the DCM that's a much > better way of doing it because it's stable over temperature and process > and because it won't change when the tools change. > > If you must build a delay line from buffers you will have to directly > place them because the routing delays are much more important then the LU= T > delays. Also you should use an XOR instead of an inverter. Tie one side o= f > the XOR to a flop which presets to 1 on reset and then clocks a zero into > the data input. This will be enough to fool XST and PAR into leaving the > components alone.Article: 135895
On Oct 20, 10:44=A0am, Mike Treseler <mtrese...@gmail.com> wrote: > > as far as working on my own fpga projects I am interested in: > > > cell phone technology > > wireless technology > > video/audio processing > > sonar/radar > > Pick one and just do it. > > -- Mike Treseler Thanks for the advice. I think the biggest problem when trying to learn on your own is finding good resources. For example: In America TV stations will start broadcasting digital signals to replace analog signals. Most digital TV receivers that have been produce so far have average video/audio quality. I'm interested in creating my own digital receiver with high video/ audio quality, however, don't know where to get information on the TV signal's encoding type, data bit length, channel information...etc. Also, I'm not sure whether or not working on this is legal without permission. I haven't found any information about this online, but I'm assuming that broadcasting stations have license agreements with digital TV receiver manufacturers; and that is how they are able to decode the signals.Article: 135896
cid wrote:
> I think the biggest problem when trying to learn on your own is
> finding good resources.
Get started with google.
Sometimes you have to buy a book or a spec.
> For example: In America TV stations will start broadcasting digital
> signals to replace analog signals.
This has already happened.
> Most digital TV receivers that have
> been produce so far have average video/audio quality.
I don't agree, but what's the point?
This has all been done.
> I'm interested in creating my own digital receiver
If your goal is to learn vhdl/verilog,
step one is simulation.
-- Mike Treseler
Article: 135897On Mon, 20 Oct 2008 15:30:49 -0700, Pratap wrote: > On Oct 13, 6:59 am, General Schvantzkopf <schvantzk...@yahoo.com> wrote: >> On Wed, 08 Oct 2008 07:35:44 -0700, Pratap wrote: >> > Hi, >> > I want to synthesize a delay of around 10 ns in Xilinx Virtex2 Pro. >> > So I put around 200 inverters in series and get the desired delay. So >> > I did port map the BASIC cell "INV" according to the XST settings. >> > But when i place and route I guess the optimizer removes all the >> > intermediate buffers and I get very less delay when I do a post route >> > simulation. How can I get rid of this problem? > Hi, > Can you please send me some good material on DCM? I actually require to > generating delays around 0 ps by having a passive > delay of around 1 period and then increasing and decreasing the input > frequency slightly.Can DCM help me in that case? -pratap > > >> > Thanks in advance. >> > -Pratap >> >> Do you need a delay or can you accomplish your task with a phase >> shifted clock? If you can use a phase shifted clock from the DCM that's >> a much better way of doing it because it's stable over temperature and >> process and because it won't change when the tools change. >> >> If you must build a delay line from buffers you will have to directly >> place them because the routing delays are much more important then the >> LUT delays. Also you should use an XOR instead of an inverter. Tie one >> side of the XOR to a flop which presets to 1 on reset and then clocks a >> zero into the data input. This will be enough to fool XST and PAR into >> leaving the components alone. Just read the Users Guide for the V2PArticle: 135898
I think the MultiBoot feature available in Xilinx FPGAs is especially useful for field updates. MultiBoot allows you to update the FPGA while maintaining a failsafe image. Avnet has an example application note showing how to do this, updating the secondary image in serial Flash with a new image arriving over ethernet. "S3A1800DSP Serial Flash Bistream Update over Ethernet" at https://www.em.avnet.com/common/filetree/0%2C2740%2CRID%3D&CID%3D42106&CCD%= 3DUSA&SID%3D32214&DID%3DDF2&SRT%3D1&LID%3D32232&PRT%3D0&PVW%3D&PNT%3D&BID%3= DDF2&CTP%3DEVK%2C00.html?ACD=3D3 Bryan On Oct 19, 9:25=A0am, Jan <1...@2.3> wrote: > Dear all, > > What are the smartest way to make a solo FPGA project capable of field > updates? I'm very new in the FPGA world so I don't much about the > practical use of them. Normally when I uses microcontrollers I make them > updateble via USB, serial or SD cards. > > What techniques are possible when I want to avoid having a uP in the > project. > > My target is a Xilinx Spartan 3A or 3AN > > Regards > =A0 =A0 JanArticle: 135899
On Oct 20, 3:30=A0pm, Pratap <pratap.i...@gmail.com> wrote: > On Oct 13, 6:59=A0am, General Schvantzkopf <schvantzk...@yahoo.com> > wrote:> On Wed, 08 Oct 2008 07:35:44 -0700, Pratap wrote: > > > Hi, > > > I want to synthesize a delay of around 10 ns in Xilinx Virtex2 Pro. S= o I > > > put around 200 inverters in series and get the desired delay. So I di= d > > > port map the BASIC cell "INV" according to the XST settings. But when= i > > > place and route I guess the optimizer removes all the intermediate > > > buffers and I get very less delay when I do a post route simulation. > > > How can I get rid of this problem? > > Hi, > Can you please send me some good material on DCM? > I actually require to generating delays around 0 ps by having a > passive > delay of around 1 period and then increasing and decreasing the input > frequency slightly.Can DCM help me in that case? > -pratap > > > > Thanks in advance. > > > -Pratap > > > Do you need a delay or can you accomplish your task with a phase shifte= d > > clock? If you can use a phase shifted clock from the DCM that's a much > > better way of doing it because it's stable over temperature and process > > and because it won't change when the tools change. > > > If you must build a delay line from buffers you will have to directly > > place them because the routing delays are much more important then the = LUT > > delays. Also you should use an XOR instead of an inverter. Tie one side= of > > the XOR to a flop which presets to 1 on reset and then clocks a zero in= to > > the data input. This will be enough to fool XST and PAR into leaving th= e > > components alone. The important question is: Who decides when to start your delay. If you can wait until an oscillator has a rising edge, then there are many high-quality solutions, especially when you know the delay value well beforehand. With the help of frequency synthesis and PLLs, you can generate a delay with very fine resolution, even below a picosecond. (Of course you lose that accuracy as you propagate through more logic.) If, however, you need to be the master of starting the delay, then you are much more constrained, and your best bet is what Virtex-4 and later did by cascading analog delay elements, and servo-controlling their composite delay. And the inherent accuracy will be not perfect, with an error of a nanosecond, unless you get really creative. Peter Alfke, lurking from home...
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