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On 2008-12-14, Nico Coesel <nico@puntnl.niks> wrote: > IMHO there are 2 seperate things to consider: F_MAX and flip-flop to > flip-flop delays. F_MAX is a property of the clock tree. Even if the > flip-flop to flip-flop delay allows for higher clock speeds, the > maximum frequency of the clock tree is the limit. In other words, you > can reduce the number of pipeline stages so the flip-flop to flip-flop > delay increases because more logic is in between. > That would be my interpretation as well. However, I am very surprised that trce doesn't warn about exceeding the maximum clock tree speed. (Or rather print an error.) Perhaps the maximum speed of the clock tree depends on the load in some way, so that for a Virtex-4 with very little logic the maximum speed of the clock tree is way faster than 500 MHz whereas the maximum speed of the clock tree when every flip-flop in the device is used (and a big ugly cooling solution is used, not to mention the power supply... :)) is around 500 MHz. If trce would know about this then it makes sense that it doesn't warn about a small design. I might also add that Quartus does warn about exceeding the maximum speed of the clock net. (Although I had to read the datasheet to figure out why it said that F_max was restricted to XXX MHz (don't remember XXX off the top of my head now).) /AndreasArticle: 136926
On Dec 13, 9:28=A0pm, googler <pinaki_...@yahoo.com> wrote: > Hi all, > I need some advice from FPGA experts and users. I am a front-end ASIC > designer with very little experience in FPGA. Recently I have been > thinking if I could buy an FPGA board and try and learn certain things > in the field of digital design that I don't know very well yet. For > example, > (1) I would like to understand the backend flow better and be able to > perform synthesis and STA. > (2) I would also like to do something related to DFT. I need some > hands-on experience to understand it better. > (3) Besides, any other interesting design stuff will be fun to do. > > So, my questions are: > * My basic assumption is whatever I learn on the FPGA platform will > more or less translate into ASIC domain too. Is that right? I can't say much about this as I don't know much about ASIC design. I believe the back end tools are all different from FPGAs. The front end should be the same with the only real difference being the setting for ASIC vs. FPGA. The tool should then produce the appropriate synthesized design for the target. Certainly the same design principals apply. > * Which board(s) can you recommend for this? My budget is $100 to > $200. Anything else I need to buy (for example, peripherals)? If you want inexpensive, Avnet sells a Spartan 3 board for $40. It has two types of Flash memory and a USB interface. If you want more peripherals, you will want a different board. What peripherals are you interested in? > * Do I need to purchase tools for synthesis, STA etc separately, or do > they come as a package with the board? The above board comes with the free Webpack version of the Xilinx tools. This includes everything you need, front end, back end, timing analysis and download tools. > * Can you suggest some website that has interesting FPGA projects, > especially on the topics I mentioned above? I don't know about projects, but there are lots of code for various functions at opencores.org. One project, ZPU, is a CPU that is fairly small and is supported by the GNU C compiler. In fact, the ZPU was designed with an instruction set optimized for code generation by the GNU C compiler. Static timing analysis is not really something to base a project on nor is design for test. Do you have any ideas on what you would want to use an FPGA for? RickArticle: 136927
If you have come from ASIC land the jump to FPGA shouldn't be too difficult. There are free tools from both Xilinx and Altera. Just watch for the cut off point for devices. The bigger, usually more expensive, parts are not supported in the free tool versions. From our own stable have a look at out Raggedstone1 http://www.enterpoint.co.uk/moelbryn/raggedstone1.html, Drigmorn1 http://www.enterpoint.co.uk/component_replacements/drigmorn1.html and Polmaddie1 http://www.enterpoint.co.uk/cpld_boards/polmaddie1.html products as they meet your pricing. If you want to do different things the Raggedstone1 has a wide range of supporting modules. some are listed http://www.enterpoint.co.uk/moelbryn/modules/modules.html. Some useful stuff http://www.enterpoint.co.uk/techitips/techitips.html and here http://www.enterpoint.co.uk/techitips/techitips_useful_things.html. We do have some labs coming for the Polmaddie range of boards. There are 4 more members of this family in progress and we will be releasing those hopefully early next year. John Adair Enterpoint Ltd. On 14 Dec, 02:28, googler <pinaki_...@yahoo.com> wrote: > Hi all, > I need some advice from FPGA experts and users. I am a front-end ASIC > designer with very little experience in FPGA. Recently I have been > thinking if I could buy an FPGA board and try and learn certain things > in the field of digital design that I don't know very well yet. For > example, > (1) I would like to understand the backend flow better and be able to > perform synthesis and STA. > (2) I would also like to do something related to DFT. I need some > hands-on experience to understand it better. > (3) Besides, any other interesting design stuff will be fun to do. > > So, my questions are: > * My basic assumption is whatever I learn on the FPGA platform will > more or less translate into ASIC domain too. Is that right? > * Which board(s) can you recommend for this? My budget is $100 to > $200. Anything else I need to buy (for example, peripherals)? > * Do I need to purchase tools for synthesis, STA etc separately, or do > they come as a package with the board? > * Can you suggest some website that has interesting FPGA projects, > especially on the topics I mentioned above? > > Thanks in advance for any advice on this.Article: 136928
Hi, I have to make a fifo with a minimum size of 512 KB. Is necessary an external Memory type SRAM, SRDAM, DDRAM, ZBT. What type of memory is recommended ? The maximum speed is 27 MHz. Should use as Xilinx "MIG", but how to use it ? Someone has an some code, VHDL ? Kappa.Article: 136929
On Dec 14, 7:39=A0am, secure...@gmail.com wrote: > Hi, > > I have to make a fifo with a minimum size of 512 KB. Is necessary an > external Memory type SRAM, SRDAM, DDRAM, ZBT. > > What type of memory is recommended ? The maximum speed is 27 MHz. > > Should use as Xilinx "MIG", but how to use it ? > > Someone has an some code, VHDL ? > > Kappa. If you need more memory than available in the internal BlockRAM, I would use an external SRAM (of 4 Mbits, pretty small) and build inside the FPGA the two address counters for read and write locations, plus a "2-stroke" state machine that alternates between read and write, running at double your speed of 27 MHz. Since this is all synchronous, the usual difficulty of detecting Full and Empty is reduced to a synchronous identity comparator. Your slow data rate makes this design quite simple. At 300 MHz it would be much more difficult... Peter Alfke, Xilinx, occasionally watching the NG.Article: 136930
I have a code for transferring the data serially to SDA line as:
when data_tx=>
if(bit_cnt<8) then
if(SCL'event and SCL='0') then
if(temp='0') then
SDA<=data_register(7);
temp:='1';
bit_cnt:=bit_cnt+1;
else
data_register<=data_register(6 downto 0) & '0';
SDA<=data_register(7);
bit_cnt:=bit_cnt+1;
end if;
end if;
end if;
in above code, i want to change the data on SDA line at every falling
edge of SCL but iam confusing that
on changing data on SDA line at exact falling edge of the SCL, does
SDA get correct data what i want? or
there is same data on SDA line as just before the falling of
SCL.........................
more particularly, i hav a confusion on this line:
data_register<=data_register(6 downto 0) & '0';.....
here, i have used two clocks: one is SCL and other is system clock
which is ten times faster than SCL. and this
"data_register<=data_register(6 downto 0) &
'0';data_register<=data_register(6 downto 0) & '0';" signal assignment
is synchronous with SCL...........
Article: 136931On Dec 14, 3:59=A0pm, GrIsH <girish_thesi...@hotmail.com> wrote: > I have a code for transferring the data serially to SDA line as: > when data_tx=3D> > =A0 =A0 =A0if(bit_cnt<8) then > =A0 =A0 =A0 =A0 =A0 =A0 if(SCL'event and SCL=3D'0') then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if(temp=3D'0') then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0SDA<=3Ddata_register(7); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0temp:=3D'1'; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0bit_cnt:=3Dbit_cnt+1; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0else > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 data_register<=3Ddata_register(6 = downto 0) & '0'; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 SDA<=3Ddata_register(7); > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 bit_cnt:=3Dbit_cnt+1; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 end if; > in above code, i want to change the data on SDA line at every falling > edge of SCL but iam confusing that > on changing data on SDA line at exact falling edge of the SCL, does > SDA get correct data what i want? or > there is same data on SDA line as just before the falling of > SCL......................... > > more particularly, i hav a confusion on this line: > data_register<=3Ddata_register(6 downto 0) & '0';..... > > here, i have used two clocks: one is SCL and other is system clock > which is ten times faster than SCL. and this > "data_register<=3Ddata_register(6 downto 0) & > '0';data_register<=3Ddata_register(6 downto 0) & '0';" signal assignment > is synchronous with SCL........... You didn't show any code running on the system clock. The code you posted should take the value of data_register(7) just before the falling edge of SCL and assign it to SDA. If this is a master I2c interface then you should be generating SCL yourself. If that is the case why not run everything on your system clock. Another thing to look at is the i2c bus specification. Although you probably don't need to add extra delay to SDA, to go by the spec, SDA needs to have a guaranteed hold time (it may be zero) after the fall of SCL. So if you are driving both, the variance in driver delay due to large capacitive loads could cause this hold time to require more delay inside you FPGA. When I do i2c logic I generally run everything on the high speed clock and use edge detectors (delay SCL inputs and look for change) instead of clocking with the logic using SCL. If SCL is generated externally you may have problems using it as a clock due to low slew rate causing noise-induced clock glitches as the signal slowly transitions through the logic threshold region. Most true i2c parts have significant input hysteresis to deal with the slow slew rates. Regards, GaborArticle: 136932
On Dec 14, 1:04=A0pm, Peter Alfke <al...@sbcglobal.net> wrote: > On Dec 14, 7:39=A0am, secure...@gmail.com wrote: > > > Hi, > > > I have to make a fifo with a minimum size of 512 KB. Is necessary an > > external Memory type SRAM, SRDAM, DDRAM, ZBT. > > > What type of memory is recommended ? The maximum speed is 27 MHz. > > > Should use as Xilinx "MIG", but how to use it ? > > > Someone has an some code, VHDL ? > > > Kappa. > > If you need more memory than available in the internal BlockRAM, I > would use an external SRAM (of 4 Mbits, pretty small) and build inside > the FPGA the two address counters for read and write locations, plus a > "2-stroke" state machine that alternates between read and write, > running at double your speed of 27 MHz. Since this is all synchronous, > the usual difficulty of detecting Full and Empty is reduced to a > synchronous identity comparator. > Your slow data rate makes this design quite simple. At 300 MHz it > would be much more difficult... > Peter Alfke, Xilinx, occasionally watching the NG. When I need to go off-chip to deepen a FIFO, I generally use a short FIFO before and after the external memory-based FIFO to simplify the internal interfaces to the remainder of the design. Then it doesn't matter so much what kind of memory you use unless you need low latency. Generally deep FIFO's and low latency are not needed at the same time. The Xilinx MIG interfaces are already FIFO-like, but they would be easier to use if you set the minimum FIFO unit to be one burst size at the SDRAM interface. While the FIFO before and after the interface can help to deal with this, you may need to create some sort of short-circuiting logic to bypass the external memory if you need to completely empty the FIFOs when less than a burst is sitting at the input FIFO. Regards, Gabor PS - Nice to see Peter A is still with us:)Article: 136933
>When I need to go off-chip to deepen a FIFO, I generally use a >short FIFO before and after the external memory-based FIFO >to simplify the internal interfaces to the remainder of the >design. Then it doesn't matter so much what kind of memory >you use unless you need low latency. Generally deep >FIFO's and low latency are not needed at the same time. > >The Xilinx MIG interfaces are already FIFO-like, but they would >be easier to use if you set the minimum FIFO unit to be one >burst size at the SDRAM interface. While the FIFO before >and after the interface can help to deal with this, you may need >to create some sort of short-circuiting logic to bypass the >external memory if you need to completely empty the FIFOs >when less than a burst is sitting at the input FIFO. Is there a simple/clean way to push a partial burst through the FIFO? For example, if the burst size is 8 bytes and a packet is N bursts plus 5 bytes, how do you get the last 5 bytes through the FIFO? (without waiting for another packet to come along) -- These are my opinions, not necessarily my employer's. I hate spam.Article: 136934
On Dec 14, 4:06=A0pm, hal-use...@ip-64-139-1-69.sjc.megapath.net (Hal Murray) wrote: > >When I need to =A0go off-chip to deepen a FIFO, I generally use a > >short FIFO before and after the external memory-based FIFO > >to simplify the internal interfaces to the remainder of the > >design. =A0Then it doesn't matter so much what kind of memory > >you use unless you need low latency. =A0Generally deep > >FIFO's and low latency are not needed at the same time. > > >The Xilinx MIG interfaces are already FIFO-like, but they would > >be easier to use if you set the minimum FIFO unit to be one > >burst size at the SDRAM interface. =A0While the FIFO before > >and after the interface can help to deal with this, you may need > >to create some sort of short-circuiting logic to bypass the > >external memory if you need to completely empty the FIFOs > >when less than a burst is sitting at the input FIFO. > > Is there a simple/clean way to push a partial burst through > the FIFO? > > For example, if the burst size is 8 bytes and a packet is > N bursts plus 5 bytes, how do you get the last 5 bytes > through the FIFO? =A0(without waiting for another packet > to come along) > > -- > These are my opinions, not necessarily my employer's. =A0I hate spam. While I stuck my head out: At 27 (or 54) MHz, I see no reason for such "elegant complexity". Just a single read register plus a write register (if necessary) and a small state machine that alternates between read and write. Yes, there are a million ways to make it more elegant and give it more performance. Are reads and writes controlled by the same free-running clock? Peter Alfke (on a cold and rainy day in California. But that still beats New England weather...)Article: 136935
In article <0175ee87-79f7-4c40-8b19-e4171a248b2d@e1g2000pra.googlegroups.com>, Peter Alfke <alfke@sbcglobal.net> writes: >[snip] >While I stuck my head out: >At 27 (or 54) MHz, I see no reason for such "elegant complexity". Just >a single read register plus a write register (if necessary) and a >small state machine that alternates between read and write. >Yes, there are a million ways to make it more elegant and give it more >performance. Yes. I don't think there is any problem with slow clocks, especially with SRAM. I was thinking of the case where you needed DRAMs for size or the clock was fast enough so that the overhead of leaving a dead (turn around) cycle on a SRAM meant you needed to use short bursts. >Are reads and writes controlled by the same free-running clock? I assumed so. If not, put a small FIFO on the input/write side so you can reduce the problem to a simpler one-clock problem when you get near the external RAM. >Peter Alfke (on a cold and rainy day in California. But that still >beats New England weather...) It was nice enough this morning in Menlo Park that I could walk down to the farmer's market. A few drops on the way back. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 136936
Hi GrIsh, What are you running? What are you trying to do? I'm not sure having a nested clock like you have will synthesize correctly. But it might. Does the when statement have a another clock above it? Where is the clock coming from? What is your sensitivity list? Is this a master or slave interface? I think your data flow is OK. You could just mux it in: case bit_cnt is when "000" => sda <= i2c_data(7) ; when "001" => sda <= i2c_data(6) ; when "010" => sda <= i2c_data(5) ; when "011" => sda <= i2c_data(4) ; when "100" => sda <= i2c_data(3) ; when "101" => sda <= i2c_data(2) ; when "110" => sda <= i2c_data(1) ; when "111" => sda <= i2c_data(0) ; when others => null ; but what you have should work. Brad Smallridge AiVisionArticle: 136937
Hi all, I am writing a Test case for a requirement. My query is that i made a full test case (normal test case) with the initial setup inputs like: por_n = 0 dsp_clock=100MHz,50% duty cycle fpga_clk=50MHz, 50% duty cycle,.., and looking the output change on output line (dsp_data), so the thing is this test case consists many registers which internally having operation on receive end. So my doubt is if i want to change the duty cycle to 40% and 60% (robustness test case)then does it effects on internal registers or just i have to look output change on data line? Here duty cycle change is with respect to the fpga_clk. If this query is not in clear then i can provide the some more details regarding to this,...please anyone who had experience on this kind of issues suggest me to go forward. Thanks, Sreenivas, Moog,IncArticle: 136938
In a conventional design (single clock, distributed over global clock nets, all flip-flops triggered on the same, usually rising, clock edge, clock frequency not at the max data-sheet limit) duty cycle is irrelevant, as long as you do not violate any clock-High or clock-Low timing. More exotic designs that use both clock edges or use latches instead of flip-flops, are (or might be) sensitive to clock duty cycle. Distributing clocks on non-global lines can seriously affect duty cycle, and also cause uncontrolled clock skew and other bad problems. Don't do that! Peter AlfkeArticle: 136939
Hi all, can anyone give the techniques on "Impact on output by Reducing Clock Frequency" If the logic contains internal register than what kind of things to take care. Let say i have a clok called fpga_clk = 50 MHz, with 50% duty cycle and by reducing it to 10 or 5 MHz with fixed duty cycle. Thanks J.Sreeni, Moog,IncArticle: 136940
Hello Friends, The question is interesting. I did not want to arouse so much interest. But I am happy. I agree with you all. Using a SRAM that is simple, yet easier with a ZBT. With a DRAM it is a bit complicated, a first fifo to offset the expected reading of writing. But I would like more details regarding the practical side. Where to start to implement the project, perhaps on an SRAM, which is simpler ? Some VHDL example ? Thanks to all. Kappa.Article: 136941
ooze3d@gmail.com skrev: > Hi all, > > I'm working on a project to create a basic FPGA based digital > cinema camera. The FPGA would have to capture a 1920x1080 progressive > frames at speeds from 1 to 60 frames/second from a Kodak CCD we've > already chosen, convert the stream to a DNG sequence (separate Adobe > DNG files, you can find the SDK at www.adobe.com) and store them in an > internal SATA SSD disk. > > The FPGA also needs to control every single feature in the sensor > with a basic user interface, enable a DVI out for monitoring and a USB > in/out so the files can be downloaded to a computer. > > This is of course a paid job. Isn't this something that exists already, or should it be able to do something special ? Are you looking for a 1 or 3-CCD solution ? Regards, Finn DenmarkArticle: 136942
>Isn't this something that exists already, or should it be able to do >something special ? > >Regards, > >Finn >Denmark ********************** But it is competetion Finn not research, most of design work is already done...that shouldn't stop us from having a share in the market. kadhiemArticle: 136943
Hi everybody, Why the operation of programming FPGA through JTAG (using SVF file) takes a lot of time ??!! The elapsed time shown by IMPACT cmd window is about 17 sec !!!!! i would like to know how to reduce this time ?Article: 136944
Hi, I am reading through the manual for ISE in order to find out if it is possible to extract gate level netlist and SDF for a part of a design only. I have a wrapper around some legacy code and a testbench for that wrapper. There is a long logic chain somewhere inside that wrapper and I need to verify it by simulation before I change it. It would take me too long time to do SDF simulation on the whole design so I am looking for a way to get a netlist and SDF for that wrapper alone that I can provide to Modelsim (using VHDL). From the documentation it is not quite clear if this is possible or not. I can generate several vhd and sdf files with an option in ISE, but that requires a custom do file and a KEEP_HIERARCHY attribute in my source code. Maybe somebody here have more experience on how to achieve modular SDF simulation with Xilinx and Modelsim. -- SvennArticle: 136945
"dajjou": > Why the operation of programming FPGA through JTAG (using SVF file) > takes a lot of time ??!! > The elapsed time shown by IMPACT cmd window is about 17 sec !!!!! > i would like to know how to reduce this time ? Are you using a parallelport cable? This cable more or less directly conntexs the JTAG-lines to the PC's LPT port. X86 PCs normally use x86 IO instructions to ptogramm the LPT port, and such IO instructions traditionally take about one microsecond. A full JTAG one bit shift operation takes at least 3 such instructions (or even some more, if the JTAG line drivers are conntext through long wires to the lpt port). So don't expect any more than 100..300 kBit/s. Gruss Jan BrunsArticle: 136946
On Dec 15, 11:59=A0am, Svenn Are Bjerkem <svenn.bjer...@googlemail.com> wrote: > > Maybe somebody here have more experience on how to achieve modular SDF > simulation with Xilinx and Modelsim. By accident I found an answer on www.xilinx.com support question #17693 that covers how to do this. Some differences to ISE 10.1 but I hope it will work. -- SvennArticle: 136947
Thank you for your prompt response Jan Bruns, Indeed I am using the XILINX platform cable USB II, normally the configuration operation should be more speed than using parallel port. Moreover why the configuration with the .bit file takes at most 4 sec. (whearas as I mentioned before, it takes at least 17 sec for SVF file)Article: 136948
dajjou <swissiyoussef@gmail.com> wrote: > Thank you for your prompt response Jan Bruns, > Indeed I am using the XILINX platform cable USB II, normally the > configuration operation should be more speed than using parallel port. > Moreover why the configuration with the .bit file takes at most 4 sec. > (whearas as I mentioned before, it takes at least 17 sec for SVF file) SVF programming has many overhead... Impact direct can shift in the Bitfile in one single sequence -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 136949
Uwe Bonnes, Thank you, So there is no way to reduce this time ? by modifiying or removing some JTAG instructions ?
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