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Hi Raph, My advice is to try to use fewer global clocks. Consider using a single fast clock with clock enables for your slower clocked FFs, BlockRAMs etc. HTH., Syms. "raph" <rponsard@gmail.com> wrote in message news:2a5fa95f-259a-401e-88a9-0263d9453274@d42g2000prb.googlegroups.com... > while synthetising (with is10.1) leon3 processor for xilinx 3adsp1800 > starter kit, I got this error : > > > Place:848 - Automatic clock placement failed.Article: 136951
Hi, I'm looking for synthesizable 4DDR Infiniband core, allowing to connect a Virtex/Stratix FPGA directly to Infiniband net. There is nothing like this on OpenCores. Maybe there are also other people interested in development of such solution? Maybe someone has some useful hints regarding its implementation? -- TIA & Regards, Wojciech Zabolotny wzab@mail.cern.chArticle: 136952
Hi Raph, I suggest checking your Leon3 configuration. It is likely that you have a ASIC configuration with clock-gating. When targeting an FPGA, I believe you should get a single clock per core. - gaelArticle: 136953
wzab wrote: > I'm looking for synthesizable 4DDR Infiniband core, allowing to > connect a Virtex/Stratix FPGA directly to Infiniband net. There is > nothing like this on OpenCores. > Maybe there are also other people interested in development of such > solution? > Maybe someone has some useful hints regarding its implementation? Talk to the folks at Polybus (http://www.polybus.com/), they specialize in Infiniband. -- Dave TweedArticle: 136954
On Dec 15, 7:50=A0am, dajjou <swissiyous...@gmail.com> wrote: > Uwe Bonnes, > > =A0Thank you, > > So there is no way to reduce this time ? by modifiying or removing > some JTAG instructions ? SVF files are intended for embedded programming. They are written without hardware feedback. That is, if you are programming a device that can tell you it is finished programming using a busy signal, you should be able to program the device at maximum speed by waiting for the busy signal to go inactive. With the SVF file, there is no busy feedback, so you must always wait for the maximum programming time. Time delays are programmed into the SVF format, and usually handled in the embedded processor using program loops for small delays and perhaps system timing like sleep for longer delays. When you run SVF files from a PC, the system timing is used for all delays, as program loops are not deterministic in modern pipelined, multithreaded, etc. processors. Your SCF file may have delay times in the order of microseconds for the JTAG signal toggling. Using even the minimum Sleep delays in Windows generally produces delays of milliseconds. So this can slow down the whole process dramatically. You could try to edit the svf text file to remove the small delays. Any reason you are using SVF rather than the bit file when you run iMpact? Normally you would only do this to test the SVF file, not as a production programming method.Article: 136955
On Dec 15, 2:57=A0am, Gabor <ga...@alacron.com> wrote: > On Dec 14, 3:59=A0pm, GrIsH <girish_thesi...@hotmail.com> wrote: > > > > > I have a code for transferring the data serially to SDA line as: > > when data_tx=3D> > > =A0 =A0 =A0if(bit_cnt<8) then > > =A0 =A0 =A0 =A0 =A0 =A0 if(SCL'event and SCL=3D'0') then > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if(temp=3D'0') then > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0SDA<=3Ddata_register(7); > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0temp:=3D'1'; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0bit_cnt:=3Dbit_cnt+1; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0else > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 data_register<=3Ddata_register(= 6 downto 0) & '0'; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 SDA<=3Ddata_register(7); > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 bit_cnt:=3Dbit_cnt+1; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if; > > =A0 =A0 =A0 =A0 =A0 =A0 end if; > > =A0 =A0 =A0 end if; > > in above code, i want to change the data on SDA line at every falling > > edge of SCL but iam confusing that > > on changing data on SDA line at exact falling edge of the SCL, does > > SDA get correct data what i want? or > > there is same data on SDA line as just before the falling of > > SCL......................... > > > more particularly, i hav a confusion on this line: > > data_register<=3Ddata_register(6 downto 0) & '0';..... > > > here, i have used two clocks: one is SCL and other is system clock > > which is ten times faster than SCL. and this > > "data_register<=3Ddata_register(6 downto 0) & > > '0';data_register<=3Ddata_register(6 downto 0) & '0';" signal assignmen= t > > is synchronous with SCL........... > > You didn't show any code running on the system clock. > The code you posted should take the value of data_register(7) > just before the falling edge of SCL and assign it to SDA. According to above statements you said that the value of data_register (7) is assigned to SDA just before the falling edge of SCL... but here in this code ""data_register<=3Ddata_register(6 downto 0) & '0';"" on the falling edge of SCL, there is two actions taking place one after another immediately as shifting of data_register itself first and assigning it to SDA immediately after shifting............so how does this works on the falling edge of SCL?.......i mean SDA takes value of data_register(7) just before the falling edge of SCL: but what about the data shifting of data_register? > > If this is a master I2c interface then you should be generating > SCL yourself. =A0If that is the case why not run everything on > your system clock. =A0Another thing to look at is the i2c bus > specification. =A0Although you probably don't need to add > extra delay to SDA, to go by the spec, SDA needs to have > a guaranteed hold time (it may be zero) after the fall of > SCL. =A0So if you are driving both, the variance in driver delay > due to large capacitive loads could cause this hold time to > require more delay inside you FPGA. > yes...i have master i2c interface.and iam using i2c protocol for interfacing camera c3038......and it can transfer the data at the rate of 400kbit/sec maximum. so i could not use fast system clock as SCL.. > When I do i2c logic I generally run everything on the high > speed clock and use edge detectors (delay SCL inputs and > look for change) instead of clocking with the logic using SCL. > If SCL is generated externally you may have problems using > it as a clock due to low slew rate causing noise-induced > clock glitches as the signal slowly transitions through the > logic threshold region. =A0Most true i2c parts have significant > input hysteresis to deal with the slow slew rates. > > Regards, > GaborArticle: 136956
On Dec 15, 6:46=A0am, "Brad Smallridge" <bradsmallri...@dslextreme.com>
wrote:
> Hi GrIsh,
>
> What are you running? What are you trying to do?
>
iam using i2c protocol for interfacing c3038 camera having
omniVision's CMOS image sensor ov6630....
combinational:process( pr_state, SCL, start_signal, load) is
----------------------------------------
begin
----------------------------------------------
--------------------------------------------
when data_tx=3D>
if(bit_cnt<8) then
if(SCL'event and SCL=3D'0') then
if(temp=3D'0') then
SDA<=3Ddata_register(7);
temp:=3D'1';
bit_cnt:=3Dbit_cnt+1;
else
data_register<=3Ddata_register(6 downto 0) & '0';
SDA<=3Ddata_register(7);
bit_cnt:=3Dbit_cnt+1;
end if;
end if;
------------------------------------------------------------------
-------------------------------------------------------------------
i think it is clear from above code that iam using SCL as clock for
this process not the system clock......so i don't think that there is
nested
clock .....................................................................=
.........
> I'm not sure having a nested clock like you have
> will synthesize correctly. But it might. Does the
> when statement have a another clock above it?
> Where is the clock coming from? What is your
> sensitivity list? Is this a master or slave interface?
i have i2c master interface,and iam presented here my code with
sensitivity list.............
>
> I think your data flow is OK. You could just mux it in:
> case bit_cnt is
> =A0when "000" =3D> sda <=3D i2c_data(7) ;
> =A0when "001" =3D> sda <=3D i2c_data(6) ;
> =A0when "010" =3D> sda <=3D i2c_data(5) ;
> =A0when "011" =3D> sda <=3D i2c_data(4) ;
> =A0when "100" =3D> sda <=3D i2c_data(3) ;
> =A0when "101" =3D> sda <=3D i2c_data(2) ;
> =A0when "110" =3D> sda <=3D i2c_data(1) ;
> =A0when "111" =3D> sda <=3D i2c_data(0) ;
> =A0when others =3D> null ;
> but what you have should work.
>
> Brad Smallridge
> AiVision
Article: 136957thanks for your replies but it is not that... if you are interested see : http://tech.groups.yahoo.com/group/leon_sparc/message/14447 On Dec 15, 3:55=A0pm, Gael Paul <gael.p...@gmail.com> wrote: > Hi Raph, > > I suggest checking your Leon3 configuration. It is likely that you > have a ASIC configuration with clock-gating. When targeting an FPGA, I > believe you should get a single clock per core. > > =A0- gaelArticle: 136958
"GrIsH" <girish_thesingh@hotmail.com> wrote in message
news:a18780ee-7b53-4612-bc66-5295e19679fc@r10g2000prf.googlegroups.com...
>I have a code for transferring the data serially to SDA line as:
> when data_tx=>
> if(bit_cnt<8) then
> if(SCL'event and SCL='0') then
> if(temp='0') then
> SDA<=data_register(7);
> temp:='1';
> bit_cnt:=bit_cnt+1;
> else
> data_register<=data_register(6 downto 0) & '0';
> SDA<=data_register(7);
> bit_cnt:=bit_cnt+1;
> end if;
> end if;
> end if;
> in above code, i want to change the data on SDA line at every falling
> edge of SCL but iam confusing that
The code you've written is not synthesizable. To detect the falling edge of
SCL you'll need to delay it by one system clock and then check to see if the
current state is '0' and the previous state is '1'. The only time you can
use X'event is on the outermost 'if' statement of a clocked process
Example: process(Clock)
begin
if rising_edge(Clock) then
-- Do synchronous assignment here
Scl_Dlyd <= Scl; -- Assuming that Scl is synced to Clock, if not then
-- proper clock domain crossing techniques
need
-- to be followed first.
if (Scl = '0') and (Scl_Dlyd = '1') then
-- Put stuff here that you only want to do on the 'falling' edge of
Scl
end if;
end if;
end process Example;
> on changing data on SDA line at exact falling edge of the SCL, does
> SDA get correct data what i want?
You need to look at the setup and hold time requirements of the devices that
you're talking to and go from there.
> or
> there is same data on SDA line as just before the falling of
> SCL.........................
>
See previous regarding timing requirements.
> more particularly, i hav a confusion on this line:
> data_register<=data_register(6 downto 0) & '0';.....
>
What is the confusion?
> here, i have used two clocks: one is SCL and other is system clock
Should we just assume that the system clock is enveloping the whole thing?
> which is ten times faster than SCL. and this
> "data_register<=data_register(6 downto 0) &
> '0';data_register<=data_register(6 downto 0) & '0';" signal assignment
> is synchronous with SCL...........
Is there a question here?
Kevin Jennings
Article: 136959On Nov 30, 4:18=A0am, "H. Peter Anvin" <h...@zytor.com> wrote: > Hello, > > I am in the process of porting a project of mine from the Cyclone Nios > Development Kit to the Terasic DE1 board. =A0The main reason for this is > to be able to run on less expensive hardware and thus make the project > available to more people (hence "get a better board" is not really an > easy answer.) =A0My interest is mostly in computing projects, so my views > are certainly biased in that direction. > > Unfortunately, I have run into a few issues with the DE1 board. =A0I > thought I'd post them here (and please let me know if there is a better > place to send this) in the hope that a future board (Cyclone III-based, > maybe?) might address these. =A0Please don't get me wrong - this is a > great board at a great price; I think, however, that a few things would > make it even better. > > 1. The SD card slot only connects a handful of signals. =A0In particular, > it does not connect the two switch pins on the socket (card detect and > write protect.) =A0This makes it much harder than it needs to be to handl= e > card removal and insertion. > > 2. Similarly, the serial port doesn't connect more than the transmit and > receive signals, even though there is a 2/2 transceiver on the board. > Having at least DTR/DCD or RTS/CTS would have been a plus; a "real" > serial port with 3/5 signals would of course be even better. > > 3. While I'm dreaming, I would *love* to see a USB-A or -AB connector > and/or an Ethernet PHY (not a fullblown Ethernet controller) connected > to the FPGA. > > That would make the DE1 a dream board in my book. > > =A0 =A0 =A0 =A0 -hpa The DE1 is a subset of the DE2, which uses almost every single I/O pin on the FPGA. My guess is that they simply deleted portions of the schematic and rerouted the board - which explains some of the oddities you noticed. The upside, however; is that if you ported to the DE2, it should be almost trivial if necessary at all.Article: 136960
On Dec 16, 10:11=A0am, "KJ" <kkjenni...@sbcglobal.net> wrote: > "GrIsH" <girish_thesi...@hotmail.com> wrote in message > > news:a18780ee-7b53-4612-bc66-5295e19679fc@r10g2000prf.googlegroups.com... > > > > >I have a code for transferring the data serially to SDA line as: > > when data_tx=3D> > > =A0 =A0 if(bit_cnt<8) then > > =A0 =A0 =A0 =A0 =A0 =A0if(SCL'event and SCL=3D'0') then > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if(temp=3D'0') then > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 SDA<=3Ddata_register(7); > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 temp:=3D'1'; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 bit_cnt:=3Dbit_cnt+1; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 else > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0data_register<=3Ddata_register(6= downto 0) & '0'; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0SDA<=3Ddata_register(7); > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0bit_cnt:=3Dbit_cnt+1; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0end if; > > =A0 =A0 =A0 =A0 =A0 =A0end if; > > =A0 =A0 =A0end if; > > in above code, i want to change the data on SDA line at every falling > > edge of SCL but iam confusing that > > The code you've written is not synthesizable. =A0To detect the falling ed= ge of > SCL you'll need to delay it by one system clock and then check to see if = the > current state is '0' and the previous state is '1'. =A0The only time you = can > use X'event is on the outermost 'if' statement of a clocked process > > Example: process(Clock) > begin > =A0 if rising_edge(Clock) then > =A0 =A0 -- Do synchronous assignment here > =A0 =A0 Scl_Dlyd <=3D Scl; =A0-- Assuming that Scl is synced to Clock, if= not then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- proper= clock domain crossing techniques > need > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- to be = followed first. > =A0 =A0 if (Scl =3D '0') and (Scl_Dlyd =3D '1') then > =A0 =A0 =A0 -- Put stuff here that you only want to do on the 'falling' e= dge of > Scl > =A0 =A0 end if; > =A0 end if; > end process Example; > > > on changing data on SDA line at exact falling edge of the SCL, does > > SDA get correct data what i want? > > You need to look at the setup and hold time requirements of the devices t= hat > you're talking to and go from there. > > > or > > there is same data on SDA line as just before the falling of > > SCL......................... > > See previous regarding timing requirements. > > > more particularly, i hav a confusion on this line: > > data_register<=3Ddata_register(6 downto 0) & '0';..... > > What is the confusion? In above statement, there is two actions are taking place one after another immediately i.e. one is shifting of data_register itself and another is assigning this data to data_register . so these two actions are supposed to be happening on the same falling edge of the SCL( same falling edge).....................So my confusion is HOW THIS STATEMENT WORKS? > > > here, i have used two clocks: one is SCL and other is system clock > > Should we just assume that the system clock is enveloping the whole thing= ? > > > which is ten times faster than SCL. and this > > "data_register<=3Ddata_register(6 downto 0) & > > '0';data_register<=3Ddata_register(6 downto 0) & '0';" signal assignmen= t > > is synchronous with SCL...........> > Is there a question here? There is two processes in the code that i hav, one is sequential which is synchronous with system clock(it is ten times faster than SCL) and another is combinational which is synchronous with SCL......so is there any dependency between these two clocks.... i mean that, does system clock affects the operation of combinational process? be sure, not system clk is in the sensitivity list of combinational process.... > > Kevin JenningsArticle: 136961
Hello, This is not exactly an FPGA question but maybe someone can help. Leonardo Spectrum synthesizer has a ASIC library named scl05u. After synthesizing a design with this library I get a technology schematic with primitive block named: AO2L0, OAI5R0, NR2R0 etc. I understand these are all complex gates (AND-OR-Invert, Or-AND- Invert, etc.) but I cannot find a datasheet or a vhdl/verilog code describing their exact function and IOs connections. Does anyone know if there is such a datasheet or source-code describing these cells or simply understand what their function is? Thank you in advance. Giorgos P.Article: 136962
"Giorgos_P" <giorgos.puiklis@gmail.com> wrote in message news:214ff52c-032b-400e-ad94-824eeea683eb@v39g2000pro.googlegroups.com... > Hello, > > This is not exactly an FPGA question but maybe someone can help. > Leonardo Spectrum synthesizer has a ASIC library named scl05u. After > synthesizing a design with this library I get a technology schematic > with primitive block named: AO2L0, OAI5R0, NR2R0 etc. > > I understand these are all complex gates (AND-OR-Invert, Or-AND- > Invert, etc.) but I cannot find a datasheet or a vhdl/verilog code > describing their exact function and IOs connections. > > Does anyone know if there is such a datasheet or source-code > describing these cells or simply understand what their function is? > > Thank you in advance. > > Giorgos P. You can find the source code in \LS2008a_5\data\modgen\scl05u.vhd Hans www.ht-lab.comArticle: 136963
Hi Guys, Hope someone would be able to help me out here. I am trying to mux 2 data streams into a dual port BRAM (2 streams on each of the ports). In order to speed things I have a register on the output of all muxs on all RAM signals. On the RAM output side I have to mux outputs of 2 BRAMs, this mux also has a register. XST fails to infer a BRAM when the address line mux has a register and gives a error message such as "You are apparently trying to describe a RAM with several write ports for signal <Mram_dp_mem>. This RAM cannot be implemented using distributed resources". When I don't have a register on the address mux output, XST manages to infer a BRAM. Would someone please be able to explain why this happens. Thanks in advance. SudhirArticle: 136964
On Dec 16, 12:24 pm, "HT-Lab" <han...@ht-lab.com> wrote: > "Giorgos_P" <giorgos.puik...@gmail.com> wrote in message > > news:214ff52c-032b-400e-ad94-824eeea683eb@v39g2000pro.googlegroups.com... > > > > > Hello, > > > This is not exactly an FPGA question but maybe someone can help. > > Leonardo Spectrum synthesizer has a ASIC library named scl05u. After > > synthesizing a design with this library I get a technology schematic > > with primitive block named: AO2L0, OAI5R0, NR2R0 etc. > > > I understand these are all complex gates (AND-OR-Invert, Or-AND- > > Invert, etc.) but I cannot find a datasheet or a vhdl/verilog code > > describing their exact function and IOs connections. > > > Does anyone know if there is such a datasheet or source-code > > describing these cells or simply understand what their function is? > > > Thank you in advance. > > > Giorgos P. > > You can find the source code in \LS2008a_5\data\modgen\scl05u.vhd > > Hanswww.ht-lab.com I have looked into this source-code but the cells used in the technology schematics (like the ones quoted below) are not described in the vhdl file. Any ideas? Cell Library References Total Area AN2T0 scl05u 1 x 5 5 gates AO2L0 scl05u 1 x 8 8 gates AO3I0 scl05u 1 x 8 8 gates NR2R0 scl05u 1 x 5 5 gates OAI5R0 scl05u 1 x 11 11 gates Thank you for your help, Regards, Giorgos P.Article: 136965
On Dec 12, 11:19 pm, raph <rpons...@gmail.com> wrote: > while synthetising (with is10.1) leon3 processor for xilinx 3adsp1800 > starter kit, I got this error : > > Place:848 - Automatic clock placement failed. Please attempt to > analyze > the global clocking required for this design and either lock the > clock > placement or area locate the logic driven by the clocks so that > that the > clocks may be placed in such a way that all logic driven by them > may be > routed. The main restriction on clock placement is that only one > clock output > signal for any competing Global / Side pair of clocks may enter any > region. > For further information see the "Quadrant Clock Routing" section in > the > Spartan3adsp Family Datasheet. > > The competing Global / Side clock buffers for this device are as > follows: > BUFGMUX_X2Y1 : BUFGMUX_X0Y2 > BUFGMUX_X2Y0 : BUFGMUX_X0Y3 > BUFGMUX_X1Y1 : BUFGMUX_X0Y4 > BUFGMUX_X1Y0 : BUFGMUX_X0Y5 > BUFGMUX_X2Y11 : BUFGMUX_X0Y6 > BUFGMUX_X2Y10 : BUFGMUX_X0Y7 > BUFGMUX_X1Y11 : BUFGMUX_X0Y8 > BUFGMUX_X1Y10 : BUFGMUX_X0Y9 > BUFGMUX_X2Y1 : BUFGMUX_X3Y2 > BUFGMUX_X2Y0 : BUFGMUX_X3Y3 > BUFGMUX_X1Y1 : BUFGMUX_X3Y4 > BUFGMUX_X1Y0 : BUFGMUX_X3Y5 > BUFGMUX_X2Y11 : BUFGMUX_X3Y6 > BUFGMUX_X2Y10 : BUFGMUX_X3Y7 > BUFGMUX_X1Y11 : BUFGMUX_X3Y8 > BUFGMUX_X1Y10 : BUFGMUX_X3Y9 > > I am new to quadrant clock constraint, can somebody provide help to > manualy place the BUFGMUXes... > > regards Try using a Xplorer script. It helps me when I encounter this problem in EDK.Article: 136966
On 15 Gru, 16:02, David Tweed <dtw...@acm.org> wrote: > Talk to the folks at Polybus (http://www.polybus.com/), they specialize > in Infiniband. > Well, I'll try to contact them. But they seem to provide the closed commercial solution. I'm also interested if there any people interested in cooperation at development of the open source and portable version... -- Regards, WojtekArticle: 136967
"Giorgos_P" <giorgos.puiklis@gmail.com> wrote in message news:0eb14507-79e1-4c28-9535-c893cd74cdb8@f11g2000vbf.googlegroups.com... > On Dec 16, 12:24 pm, "HT-Lab" <han...@ht-lab.com> wrote: >> "Giorgos_P" <giorgos.puik...@gmail.com> wrote in message .. >> > Giorgos P. >> >> You can find the source code in \LS2008a_5\data\modgen\scl05u.vhd >> >> Hanswww.ht-lab.com > > > I have looked into this source-code but the cells used in the > technology schematics (like the ones quoted below) are not described > in the vhdl file. Any ideas? > > Cell Library References Total Area > > AN2T0 scl05u 1 x 5 5 gates > AO2L0 scl05u 1 x 8 8 gates > AO3I0 scl05u 1 x 8 8 gates > NR2R0 scl05u 1 x 5 5 gates > OAI5R0 scl05u 1 x 11 11 gates > > Thank you for your help, > Regards, > > Giorgos P. Hi Giorgos, According to supportnet you need to contact Mentor to get some more info on the primitives, see: http://supportnet.mentor.com/reference/technotes/public/technote.cfm?tn=mg40072 Regards, Hans www.ht-lab.comArticle: 136968
Altera list Windows XP x64 as a supported platform for their development tools. Does anybody know, from experience, if the tool chain is compiled to take advantage of the larger memory space? Sincerely, Derek SimmonsArticle: 136969
I am using Xilinx Coregen and ISE 9.2i and see this peculiar issue with the Multiplier core v10.0. The Xilinx Coregen multiplier has a problem handling signed inputs, particularly when the inputs have greater than 18 bits, the size of the hardware multiplier. For instance, we have an example where a negative 26-bit value is multiplied by a positive 24-bit value. A Coregen core is created to do this arithmetic using four DSP48 cores. The resulting 50-bit output should be negative, but the core produces a positive number. We are using ISE9.2i with all of the SP updates. The Multiplier version inside Coregen is version 10; there does not seem to be any release notes for ISE10.x to say that the new Coregen fixed anything in the Multiplier core. So, has anyone seen or heard of any problem with the Coregen multiplier, particularly for inputs with greater than 18 bits? Thanks, VivekArticle: 136970
On Dec 16, 10:11=A0am, "KJ" <kkjenni...@sbcglobal.net> wrote: > "GrIsH" <girish_thesi...@hotmail.com> wrote in message > > news:a18780ee-7b53-4612-bc66-5295e19679fc@r10g2000prf.googlegroups.com... > > > > > > >I have a code for transferring the data serially to SDA line as: > > when data_tx=3D> > > =A0 =A0 if(bit_cnt<8) then > > =A0 =A0 =A0 =A0 =A0 =A0if(SCL'event and SCL=3D'0') then > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if(temp=3D'0') then > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 SDA<=3Ddata_register(7); > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 temp:=3D'1'; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 bit_cnt:=3Dbit_cnt+1; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 else > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0data_register<=3Ddata_register(6= downto 0) & '0'; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0SDA<=3Ddata_register(7); > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0bit_cnt:=3Dbit_cnt+1; > > =A0 =A0 =A0 =A0 =A0 =A0 =A0end if; > > =A0 =A0 =A0 =A0 =A0 =A0end if; > > =A0 =A0 =A0end if; > > in above code, i want to change the data on SDA line at every falling > > edge of SCL but iam confusing that > > The code you've written is not synthesizable. =A0To detect the falling ed= ge of > SCL you'll need to delay it by one system clock and then check to see if = the > current state is '0' and the previous state is '1'. =A0The only time you = can > use X'event is on the outermost 'if' statement of a clocked process The original poster (OP) has used scl in his process sensitivity list which does not contain system clock. So isn't it possible to use falling_edge(scl) inside this process? although he'd probably have another process with system clock in its sensitivity list. But he's using scl'event in one of the possible conditions under case statement (this seems to the part of the state machine he's trying to design.) So if I am right it must be creating a gated clock of scl which is not good. Using delayed scl and scl to check the falling edge of scl is of course the better solution but is it completely unsynthesizable ? i.e when process (scl, ...) is there (BUT NO say CLK) and using falling_edge(scl) inside this process. Or is it just because of the formation of gated clock when scl is used in some inner if statements? > > Example: process(Clock) > begin > =A0 if rising_edge(Clock) then > =A0 =A0 -- Do synchronous assignment here > =A0 =A0 Scl_Dlyd <=3D Scl; =A0-- Assuming that Scl is synced to Clock, if= not then > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- proper= clock domain crossing techniques > need > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- to be = followed first. > =A0 =A0 if (Scl =3D '0') and (Scl_Dlyd =3D '1') then > =A0 =A0 =A0 -- Put stuff here that you only want to do on the 'falling' e= dge of > Scl > =A0 =A0 end if; > =A0 end if; > end process Example; > > > on changing data on SDA line at exact falling edge of the SCL, does > > SDA get correct data what i want? > > You need to look at the setup and hold time requirements of the devices t= hat > you're talking to and go from there. > > > or > > there is same data on SDA line as just before the falling of > > SCL......................... > > See previous regarding timing requirements. > > > more particularly, i hav a confusion on this line: > > data_register<=3Ddata_register(6 downto 0) & '0';..... > > What is the confusion? > > > here, i have used two clocks: one is SCL and other is system clock > > Should we just assume that the system clock is enveloping the whole thing= ? > > > which is ten times faster than SCL. and this > > "data_register<=3Ddata_register(6 downto 0) & > > '0';data_register<=3Ddata_register(6 downto 0) & '0';" signal assignmen= t > > is synchronous with SCL........... > > Is there a question here? > > Kevin Jennings- Hide quoted text - > > - Show quoted text -Article: 136971
On Dec 16, 4:46=A0am, Sudhir.Si...@email.com wrote: > Hi Guys, > > Hope someone would be able to help me out here. I am trying to mux 2 > data streams into a dual port BRAM (2 streams on each of the ports). > In order to speed things I have a register on the output of all muxs > on all RAM signals. On the RAM output side I have to mux outputs of 2 > BRAMs, this mux also has a register. XST fails to infer a BRAM when > the address line mux has a register and gives a error message such as > "You are apparently trying to describe a RAM with several write ports > for signal <Mram_dp_mem>. This RAM cannot be implemented using > distributed resources". > > When I don't have a register on the address mux output, XST manages to > infer a BRAM. > > Would someone please be able to explain why this happens. > > Thanks in advance. > Sudhir Sudhir: XST can be very finicky when trying to infer BRAMs, and I would suggest encapsulating the BRAM template code in a separate entity, and then wrapping this entity up with your stream/multiplexing logic. This should make it easier for XST to infer the BRAM, as the template should match Xilinx's recommended coding style exactly. -JasonArticle: 136972
On Dec 16, 1:58=A0am, GrIsH <girish_thesi...@hotmail.com> wrote: > In above statement, there is two actions are taking place one after > another immediately i.e. one is shifting of data_register itself and > another is assigning this data to data_register Signal assignments don't get updated until the process has completed. You could reverse the ordering of those two assignments if you wanted and it would work exactly the same because data_register does not change values between those two lines of code. > =A0There is two processes in the code that i hav, one is sequential > which is synchronous with system clock(it is ten times faster than > SCL) Sounds like sampling SCL with the 10x faster system clock would be appropriate and then work in just one clock domain...unless the setup/ hold time requirements of the receiver don't make that feasible, that's how I'd approach it. > and another is combinational which is synchronous with > SCL......so is there any dependency between these two clocks.... SCL is only a clock because you choose to *use* it that way. It is really just an input signal to the device, you make the design choice to use it as a clock or not. As I mentioned, with a system clock that is 10x faster, I would likely not use SCL as a clock input to any register, instead running everything off of the system clock and simply sampling SCL to see when the edges are occurring. Kevin JenningsArticle: 136973
On Dec 16, 10:17=A0am, bish <bishes...@gmail.com> wrote: > > The original poster (OP) has used scl in his process sensitivity list > which does not contain system clock. So isn't it possible to use > falling_edge(scl) inside this process? Most anything is possible, and maybe some tool might accept it and produce a bitstream that can be used to program the device. If there is such a tool though I can guarantee that the design will be flaky on a good day, and just never work at all on a bad day. Hopefully the OP's tools simply produce an error and stop which will save the OP a bit of time in the long run since he will be forced to confront the problem earlier rather than be lulled into thinking the design might actually work. > So if I am right it must be creating a gated clock of scl which is not > good. Hard to tell what the design really is based on the code snippet, but I agree the gated clock is not good and is the source of the problems that the OP will have if he chooses to continue down this path. > Using delayed scl and scl to check the falling edge of scl is of > course the better solution but is it completely unsynthesizable ? i.e > when process (scl, ...) is there (BUT NO say CLK) and using > falling_edge(scl) inside this process. You get rid of scl (and all the other signals) from the sensitivity list and simply use the system clock. The outermost part of the process is where the "if rising_edge(system clock) then..." would be placed, nowhere else would one have XX'event or any such equivalents. See previous post for the basic template. Kevin JenningsArticle: 136974
Vivek Menon wrote: > > So, has anyone seen or heard of any problem with the Coregen > multiplier, particularly for inputs with greater than 18 bits? A more general question: Why are You using coregen for this task? Why not just use vhdl/verilog? Or is it that clock-critical? Then maybe instantiating the DSP-Slices by hand might be quite mor powerfull and better. To split a larger multiplication down to smaller ones have a look at the divide and conquer algorithm. > > Thanks, > Vivek Regards, Lorenz
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