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Gabor <gabor@alacron.com> writes: > How many BRAM devices does your FPGA have? That's easy to answer, the Spartan3 starter the OP mentioned has a XC3S200, so 12 BRAMs. Not quite enough for 32 kB. The answer to the original poster is, create your MicroBlaze design in the EDK using the wizard and leave all settings at their defaults. You'll get a system that actually *works* and you can play with.Article: 145726
bizarrefish wrote:
> I just got quartus II linux web edition operational on my Arch64
> lappy. This involved installing a bunch of libraries, tweaking my /etc/
> issue file to correct something that altera was getting upset about,
> and LD_PRELOADing a library or two.
> All a lot of messing around, but it ended up actually working. JTAG n
> all.
...
> Is there any kind of workaround for this, or am I at the mercy of
> altera to come out with a fix?
If I were using the recommended distro,
I would file a case with Altera
and use windows in the mean time.
-- Mike Treseler
Article: 145727
Giorgos Tzampanakis wrote:
> I'm trying to get Quartus to recognize my state machines. I'm
> using version 9.0. I tried generating a state machine using the
> State Machine Wizard, but after compiling, if I try to look at it
> with the State Machine Viewer I get "This design has no State
> Machine." I tried to copy the Verilog code from the Help file,
> and I still get the same problem.
I would look at the RTL view to
see how the code synthesized.
> Is it possible to get Quartus to understand my state machines?
Yes. The Quartus viewer draws a state diagram when
I update an enumeration using a case statement.
Learn vhdl or verilog and get a simulator.
-- Mike Treseler
Article: 145728"jmfbahciv" <jmfbahciv@aol> wrote in message news:hlm59g2jg9@news4.newsguy.com... > Abby Brown wrote: >> "Eric Chomko" <pne.chomko@comcast.net> wrote in message >> news:badc12c3-cb2b-4ce9-9543-237d60fc22d5@o8g2000vbm.googlegroups.com... >>> Has anyone created a copy machine of an old system using an >>> FPGA? I >>> was wondering if it would be possible to take an entire >>> SWTPC 6800 and >>> compile the schematics and have it run on an FPGA board.? >>> Wouldn't >>> even have to be the latest Xylinx product, I suspect. >> >> Absolutely. There a number of them. This guy has done a >> PDP-4 and PDP-8, >> >> http://homepage.mac.com/dgcx/pdp4x/ >> >> http://homepage.mac.com/dgcx/pdp4x/ >> >> I am in the process of doing a PDP-1. My background is high >> performance computers so it is a high performance design. >> Todays FPGAs and CAD allow a much more agressive >> implementation than the original designers could afford and >> with far less effort. The original PDP-1s sold for about >> $100K in early 1960s' dollars. Mine will cost only a few >> hundred dollars to build. >> >> Those interested in the subject might also be interested in >> the simh group, >> >> http://simh.trailing-edge.com/ >> >> which does simulators for legacy computers. > > Re your background is high performance, what do you like best > about the PDP-1? (Or haven't you got that far?) > > /BAH The best (and worst) is the PDP-1's simplicity. It is easy to implement. For the most part conditionals are decoupled from arithmetic operations. That helps branches, which are always a bottleneck. The single arithmetic register is a bottleneck. Out of order execution, for example, is difficult when almost every instruction accesses the same register. Other the other hand, if you treat memory as registers, which is feasible (there are only 4K words), you can do interesting things with out-of-order. RISC computers, such as ALPHA and MIPS, have compilers that help the hardware by ordering instructions. With legacy software, you cannot do that. For comparison, when I was a DECie, I did the instruction fetch and processing unit for a data flow VAX (never produced, unfortunately). The number and complexity of instructions and the weirdness of a few made high performace difficult. That was one of the reasons DEC developed ALPHA. GaryArticle: 145729
On Feb 20, 11:34=A0pm, Giorgos Tzampanakis <g...@hw.ac.uk> wrote: > I'm trying to get Quartus to recognize my state machines. I'm > using version 9.0. I tried generating a state machine using the > State Machine Wizard, but after compiling, if I try to look at it > with the State Machine Viewer I get "This design has no State > Machine." I tried to copy the Verilog code from the Help file, > and I still get the same problem. > > Is it possible to get Quartus to understand my state machines? Without seeing the code I'm guessing it was optimized out. Quartus defaults to one-hot state machines. In settings (someplace) you need to tell it 'custom' or 'user defined' (I forget which). That might not be enough, you might also have to associate each state with an output signal or it might go poof. For small state machines I'll create a signal and tie it to a pin with an LED.Article: 145730
On Feb 21, 4:53=A0pm, Mike Treseler <mtrese...@gmail.com> wrote: > bizarrefish wrote: > > I just got quartus II linux web edition operational on my Arch64 > > lappy. This involved installing a bunch of libraries, tweaking my /etc/ > > issue file to correct something that altera was getting upset about, > > and LD_PRELOADing a library or two. > > All a lot of messing around, but it ended up actually working. JTAG n > > all. > ... > > Is there any kind of workaround for this, or am I at the mercy of > > altera to come out with a fix? > > If I were using the recommended distro, > I would file a case with Altera > and use windows in the mean time. > > =A0 =A0 =A0 =A0-- Mike Treseler Gah, screwit. I'll stick it in CentOS 5 in virtualbox. hope the performance hit isn't too massive.Article: 145731
On Feb 5, 1:19=A0pm, Eric Chomko <pne.cho...@comcast.net> wrote: > Has anyone created a copy machine of an old system using an FPGA? I > was wondering if it would be possible to take an entire SWTPC 6800 and > compile the schematics and have it run on an FPGA board.? Wouldn't > even have to be the latest Xylinx product, I suspect. In Circuit Cellar's 2009 issue is the article, "Retrocomputing on an FPGA: Reconstructing an '80s-Era Home Computer with Programmable Logic". The author describes his experience of designing a Apple II+ compatiable project. Another project I know of is mentioned at: http://vector-graphic.info/vg_links.aspx This whole website is dedicated to Vector Graphic S-100 computers. The link half way down the page is wrong but the project can be found at: http://opencores.org/project,vg_z80_sbc At this web is 8086 core: http://www.ht-lab.com/freecores/cpu8086/cpu86.html I believe the sample project with the core would be equivalent of a 8086 SBC running DOS. DerekArticle: 145732
I realize what I'm looking for might not be out there anymore but I'm trying to give it my best shot. A couple of years ago I came across a website that somebody put up describing an ultimate RISC or MISC processor they were developing. One of their goals was to be able to run LINUX on it. Was having a conversation with of friend of mine that made me think of this and I wondered if they ever achieved their goal. I think his processor had 16 different instructions and they had implemented it using an FPGA. Does this sound familair to anybody? Thanks, DerekArticle: 145733
On Feb 21, 2:02=A0pm, Derek Simmons <dereks...@gmail.com> wrote: > On Feb 5, 1:19=A0pm, Eric Chomko <pne.cho...@comcast.net> wrote: > > > Has anyone created a copy machine of an old system using an FPGA? I > > was wondering if it would be possible to take an entire SWTPC 6800 and > > compile the schematics and have it run on an FPGA board.? Wouldn't > > even have to be the latest Xylinx product, I suspect. > > In Circuit Cellar's 2009 issue is the article, "Retrocomputing on an > FPGA: Reconstructing an '80s-Era Home Computer with Programmable > Logic". The author describes his experience of designing a Apple II+ > compatiable project. > > Another project I know of is mentioned at: > > http://vector-graphic.info/vg_links.aspx > > This whole website is dedicated to Vector Graphic S-100 computers. The > link half way down the page is wrong but the project can be found at: > > http://opencores.org/project,vg_z80_sbc > > At this web is 8086 core: > > http://www.ht-lab.com/freecores/cpu8086/cpu86.html > > I believe the sample project with the core would be equivalent of a > 8086 SBC running DOS. > > Derek NOT a FPGA but certainly a design I would like to see executed in FPGA and very vintage http://laughtonelectronics.com/arcana/BrideOfSonPg1.html He used a 65C02 and a KIM as his starting point. The 65C02 was chosen because all of its unimplemented instructions became NOPs. If I have it right, he then intercepts the unused op codes and uses them for his own purposes like extending the memory addressing. It is an interesting design in that when you move the microcode off the main processor you can optimize the system for very specific tasks. In his case he used it for running Forth. I guess the argument could be just do the entire thing in VDHL or use the right processor for the job.<grin> Instruction set problems seem to come up fairly often. I *think* some C implementations could use a separate hardware stack for instance. RickArticle: 145734
yes I understand but 500ps is to much for pcb delay, are 15cm. The idia is ti desing an ultra wideband transmiter using the MGT. I'm using BPKS modulation, so the delay between TX1(positive pulse) and TX2(negativo pulse), must be the same. --- frmsrcurl: http://compgroups.net/comp.arch.fpga/rocketio-TX-delay-between-sata0-and-sata1Article: 145735
On Feb 19, 11:58=A0am, Marcelo <u...@compgroups.net/> wrote: > Ed, > So you told me that its no posible to sent two bits using diferent MGT wi= th the same delay? > But how work the comm systems that use several paralle channels? > I'll check the datasheet for my virtex2p. > Marcelo > > --- > frmsrcurl:http://compgroups.net/comp.arch.fpga/rocketio-TX-delay-between-= sata0-... For interfaces that use multiple MGTs, such as PCIe and XAUI, the protocol uses channel bonding that allows the receiver to align the data correctly with multiple (1-40+) bits of skew. The are some standards that want to skimp on the logic resources needed to implement channel bonding and have a tighter requirement on the lane skew, but the protocols that I am aware of still allow for about 1000pS of lane skew. Expecting 0pS of lane skew is not realistic. Ed McGettigan -- Xilinx Inc.Article: 145736
On Feb 22, 1:45=A0pm, Derek Simmons <dereks...@gmail.com> wrote: > I realize what I'm looking for might not be out there anymore but I'm > trying to give it my best shot. > > A couple of years ago I came across a website that somebody put up > describing an ultimate RISC or MISC processor they were developing. > One of their goals was to be able to run LINUX on it. Was having a > conversation with of friend of mine that made me think of this and I > wondered if they ever achieved their goal. > > I think his processor had 16 different instructions and they had > implemented it using an FPGA. > > Does this sound familair to anybody? It sounds a little mangled to me ? ~16 instruction cores have been discussed, but they are at the educational end of the spectrum, rather than Linux capable. Antti may be along shortly to add more ;) -jgArticle: 145737
On 20 Feb., 15:47, suni <sunitara...@gmail.com> wrote: > helo > =A0i am in B.E.-E&TC,doing project on DIGITAL WATER MARKING TECH.. I > need to convert matlab code in to vhdl for downloading,if not then how > to read bmp file in vhdl?..Can u please help me out.. Hi, whatever interface you are going to use, read in the bmp data byte by byte and follow the format instructions to be able to decode the raw pixel data. Remember: VHDL is about hardware design. Have a nice synthesis. EilertArticle: 145738
jozamm <jozamm@gmail.com> writes: > Hi all, > > I am a budding FPGA designer and I am in the process of designing > first system. Until now I have partitioned my system into various > entities, each entity implementing a small part of the system. It is > also easier for implementation. However I have found myself in routing > a lot of signals from one entity to another which increases complexity > in a way. > As others have noted, deciding where to draw the boundaries is a bit of an art. In terms of routing signals around, records can help with that: if you want to push an extra signal down the hierarchy, you just add it to the appropriate record and recompile. However, make sure you package things together sensibly - by function is often good. Not just "all the signals to this entity go in one record" as then you can end up with all the signals in the design in one big record! Splitting things down into "things that are easy to test" is a good boundary in my experience. Here's an example - say you want an image processing system which does an "edge detecting" function, then does a "peak detecting" function on the results of that and then a "assign x,y coordinates to each peak we detected" function. You could stick all of that into one big block of code, but when you get the wrong x coordinates out of the far end, you have no idea which subfunction went wrong. Instead you design three blocks, one for each of the functions, and test them individually. You can get each part right *in isolation*. Then when you wire them all together and test it, and it doesn't work first time (!), you only have to look at the higher-level integration to see what's wrong. It may sound like more work this way (writing testbenches doesn't feel like productive work, especially when you're starting out). But once you get proficient (which means practicing, just like playing your scles on the piano :), you can do the testing very quickly because each individual test is fairly simple. And you can push your design to all the corner cases, which is much more difficult when testing the whole thing all together. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 145739
On 2/22/2010 2:03 AM, marcelo wrote: > yes I understand but 500ps is to much for pcb delay, are 15cm. > The idia is ti desing an ultra wideband transmiter using the MGT. > I'm using BPKS modulation, so the delay between TX1(positive pulse) and TX2(negativo pulse), must be the same. > > > --- > frmsrcurl: http://compgroups.net/comp.arch.fpga/rocketio-TX-delay-between-sata0-and-sata1 Do you remember this reply from a week ago? "What are these two signals? Where do they connect to your FPGA?" Why don't you answer it? Symon.Article: 145740
Am 17.02.2010 08:47, schrieb Ed McGettigan: > On Feb 16, 9:10 pm, Antti <antti.luk...@googlemail.com> wrote: >> On Feb 16, 7:21 pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: >> >> >> >> >> >>> On Feb 15, 11:10 pm, Antti <antti.luk...@googlemail.com> wrote: >> >>>> Hi >> >>>> my co-worker has a problem with EDK (used on w7, 32bit) >>>> OLD project can be built but any new projexcts created stop >>>> during implementation >> >>>> xilinx claims that the following tablehttp://www.xilinx.com/ise/ossupport/index.htm >> >>>> is UPTODATE OS support list for Xilinx tools, in that table win7 is >>>> missing >> >>>> so what is wrong? is there something wrong with the installation, but >>>> hey >>>> why then old projects pass full flow? >> >>>> any ideas? >> >>>> Antti >> >>> Win7 isn't a supported OS for ISE tools and it is not listed in the >>> table. >> >>> The tools may work under some conditions, but they likely will not >>> under all conditions as your co-worker found out. >> >>> Ed McGettigan >>> -- >>> Xilinx Inc. >> >> Hi >> >> and thanks for clarification, I could not belive the table to be >> accurate >> as of today everybody DOES support w7 already ;) ok maybe not >> all companies do, but most other software does run nicely on w7 >> >> Antti- Hide quoted text - >> >> - Show quoted text - > > ISE 11.1 was released in April while Windows 7 wasn't released until > October. > > While smaller companies and academia tend to move faster with Windows > OS upgrades as the tend to use the OS sold with the PC/Laptop larger > companies in constrast don't rapidly upgrade the OS and prefer to stay > with older, stable versions. > > A quick survey of other EDA tools shows > > Synopsys Synplify Pro - Win XP, Win Vista, Linux, Solaris > Mentor ModelSim PE - Win XP, Win Vista (32) > Mentor ModelSim SE - Win XP, Win Vista (32), Linux (32) > Mentor ModelSim DE - Win XP, Win Vista (32/64), Linux (32/64), Solaris > (32/64) > Altera Quatrus II 9.1 - Win XP, Win Vista, Red Hat 4/5, Suse 9/10, > CentOS 4/5 > Lattice ispLever - Win 2K, Win XP, Win Vista (32), Red hat 3/4, Suse > 10, Solaris 2.8/10 > Actel Libero - Win XP, Win Vista, Red Hat WS 4/5.2 > > Ed McGettigan > -- > Xilinx Inc. Hi, since there is no native Win7 support in the 11.x toolchain, will it be in 12.x? If so, could you please give us a rough periode when it will be released? -- Regards, MaikArticle: 145741
On 2/22/2010 10:18 AM, Symon wrote: > On 2/22/2010 2:03 AM, marcelo wrote: >> yes I understand but 500ps is to much for pcb delay, are 15cm. >> The idia is ti desing an ultra wideband transmiter using the MGT. >> I'm using BPKS modulation, so the delay between TX1(positive pulse) >> and TX2(negativo pulse), must be the same. >> >> >> --- >> frmsrcurl: >> http://compgroups.net/comp.arch.fpga/rocketio-TX-delay-between-sata0-and-sata1 >> > > Do you remember this reply from a week ago? > > > "What are these two signals? Where do they connect to your FPGA?" > > > Why don't you answer it? > > Symon. Sorry, ignore that. I thought you were the OP. FWIW, the P and N signals will be aligned to within a few ps. Different lanes will not be. HTH, Syms.Article: 145742
suni <sunitaraul5@gmail.com> writes: > helo > i am in B.E.-E&TC,doing project on DIGITAL WATER MARKING TECH.. I > need to convert matlab code in to vhdl for downloading,if not then how > to read bmp file in vhdl?..Can u please help me out.. I'd attempt to read a simpler format than BMP files - try PGM files: they're a lot easier to read, as the header is simple and there's only two formats to worry about, rather than the many variations that a BMP can hide. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 145743
On 11 Feb, 01:12, van...@sfu.ca (Peter Van Epp) wrote: > Dek <daniele.deq...@gmail.com> writes: > >Hi all, > >as the title says I have to read some information stored in UDP packet > >with an FPGA. Now I'm evaluating 3 options: > >1) Use an external processor and send data to FPGA through dedicated > >lines > >2) Use a microcontroller embedded into the FPGA (i.e. microblaze, > >since I'm working on a Xilinx) > >3) Write an hardware implementation of the IP stack, or at least of he > >part of the stack I need to read those packets > >What are the pros and cons of each solution? Can you suggest me others > >way to do that? > >Thanks all > >Dek > > =A0 =A0 =A0 =A0 How fast is the UDP stream (gig or will 10/100 and low th= roughput do)? > Does your board already have an ethernet PHY or do you need to add one ju= st > for this? If the volume and speed are both low (i.e. 100 or less) there w= as > a spi interfaced PIC 10/100 board referenced here a while back. That may = be > your cheapest solution (the one referenced here is about $20 and Wiznet m= akes > a bunch more that are a little more expensive). I don't think it will do > anywhere near wire speed, but if your traffic is small enough that may be > the easiest solution (someone else does the IP heavy lifting such as it i= s and > worries about things like arp :-)). > > Peter Van Epp Thanks you all for the replies, I'm working on an embedded sistem (NI PXIe) and the FPGA is a Virtex5 mounted on a Flex Rio board. I decided to add an SNTP client on the controller PC (wich runs NI real time software) and then comunicate the time information through the backplane. I think it's the easiest solution. Bye DekArticle: 145744
Hi all, I'm working on a Virtex5 xc5vlx50 and in my design I need to use some block ram. I generated the core with core generator, but when I implement the design I got this warning during mapping: WARNING:Pack:231 - trimming timing constraints from pin hit2/RAM1/BU2/ U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_init.ram/TR UE_DP.SINGLE_PRIM36.TDP of frag REGCLKBL connected to power/ground net hit2/RAM1/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/ v5_init.ram/TR UE_DP.SINGLE_PRIM36.TDP_REGCLKBL_tiesig Does anyone knows what it mean and how can i fix it? I found nothing neither on the xilinx site nor on the web Thanks all Bye DekArticle: 145745
On 10 Feb, 16:31, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > John McCaskill <jhmccask...@gmail.com> wrote: > > (snip) > > > I also have designs that use the FPGA fabric to directly deal with the > > data from the EMAC with out using a processor at all. =A0Those are only > > dealing with UDP and ICMP, and were simple and straight forward. > > What do you do about ARP? > > You won't get the packets unless ARP tells where to send them. > > -- glen I was thinking to follow this implementation: http://www.itee.uq.edu.au/~peters/xsvboard/stack/stack.htm maybe upgrading it to a 10/100Mb Ethernet, but I changed idea. Anyway they says they can handle arp send and arp request properly, but I haven't tested it yet. Bye DekArticle: 145746
Most of what's been posted is good advice. I usually split design into functional blocks which can then be indepentantly functionally tested, these are my entities. When it comes to signal routing I had to pick up a design a while ago that used records all over the place. I found this obscured the functional intent and made it much more difficult to debug so I'm not a big fan, although I have used them in a couple of instances. Keep it all as simple as possible! Nial.Article: 145747
Hi, I am a beginner at FPGA. I had a query that which platform is used for professional digital designs. Is it linux or windows?? --------------------------------------- Posted through http://www.FPGARelated.comArticle: 145748
bizarrefish <leeguy92@googlemail.com> writes: > Gah, screwit. I'll stick it in CentOS 5 in virtualbox. hope the > performance hit isn't too massive. I haven't played with it much, but the Linux Quartus 9.1 beta seemed to have issues running in VirtualBoxed Centos 5 on my laptop. As in crashing problems, when running the fitter for some simple example designs (complex multiplier and FIR filter examples from Altera's site). OTOH, same examples work fine in the laptop's native 64-bit Fedora 12.Article: 145749
>Hi, I am a beginner at FPGA. I had a query that which platform is used for >professional digital designs. Is it linux or windows?? > All the places I have worked at (in UK) have used Windows. Some have also used Unix/Linux. I would be surprised if no Linux-only shops existed. --------------------------------------- Posted through http://www.FPGARelated.com
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z