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On Feb 14, 12:08=C2=A0pm, rickman <gnu...@gmail.com> wrote: <snip> > Is this right? =C2=A01 ns/Ft is the speed of light in a vacuum. =C2=A0In = FR4 it > is approximately half that giving 28 GHz a wavelength of about 2 cm or > about 0.8 inches. I hate it when I goof like this so I hesitate to point out that half of 0.4" is 0.2" rather than 0.8". Propagation delay in a medium with a relative permeability =CE=B5r =E2=89= =88 4 is about c/=E2=88=9A4. (hoping I don't lose formatting)Article: 145576
On Sun, 14 Feb 2010 19:08:07 +0100, Petter Gustad wrote: > General Schvantzkoph <schvantzkoph@yahoo.com> writes: > >> p.s. the reason that I'm trying to do this with a VM is that Quartus >> doesn't run on Fedora, just CentOS. Also I've found that the Altera >> cable driver is pretty much unusable on CentOS so putting a native >> CentOS partition on machine won't solve the problem. I don't have a >> native Windows partition on my laptop so that's not an option either. > > Hmm. I've used the USB blaster almost daily on several gentoo systems > for the last couple years. I even used an old headless PC (running > gentoo) as a JTAG server for some time. However, I tend to use most of > the CLI (quartus_pgm, nios2-download, and gdb) tools except signaltap. > > Long ago when I was running Quartus on Solaris I had an old Windows > Laptop (I think it was even a 486) running Quartus Programmer acting as > a JTAG server. > > > Petter I have an old first generation A64 machine that I'm using as a lab computer. I have both CentOS 5.4 and XP on that system. Under CentOS SignalTap hardly ever sees the USB Blaster, I have to keep power cycling the board or the cable and occasionally SignalTap will find it. Using XP on the same machine there are no problems with SignalTap finding the cable. In a couple of weeks I want to demo something to customer which is why I need to be able to use my laptop. I was hoping to be able to use an XP VM for this purpose but I haven't been able to get the VM to see the cable.Article: 145577
In Uwe Meyer-Baese's Book "Digital Signal Processing with Field Programmable Gate Arrays", I saw quite a lot of references to the (at least for me) obscure Residue Number System. I'm wondering how relevant the RNS is in practice. I've never seen it mentioned anywhere except in scientific publications. Is anyone using RNS in a real FPGA project? Cheers, Guy.Article: 145578
General Schvantzkoph <schvantzkoph@yahoo.com> writes: > why I need to be able to use my laptop. I was hoping to be able to use an > XP VM for this purpose but I haven't been able to get the VM to see the > cable. I understand. Unfortunately I haven't tried that combo. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 145579
Thank you all for your replies. I discussed with my prof regarding the project and this is what I'm supposed to do. I have implemented a counter already. Using the propagation delays for each clock cycle i need to drive a shift register. That is, this shift register will be having a higher input clock(330MHZ) than the counter(25MHz). And it will be cleared for the duration the propagation delay is active for the counter. Before clearing, the value needs to be copied to a priority encoder. So finally, the number of f/fs storing the value times the clock freq in nanoseconds (approx. 3ns in this case) will be the output. Hope I was able to expalin it properly. DO I have to write the shift regiater as a different module? Which type of register to use for this purpose? How to implement the clearing logic for shift register considering the propagation delays of counter? Please help me. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 145580
Pallavi <pallavi_mp@n_o_s_p_a_m.rediffmail.com> wrote: > Thank you all for your replies. I discussed with my prof regarding the > project and this is what I'm supposed to do. I have implemented a counter > already. Using the propagation delays for each clock cycle i need to drive > a shift register. That is, this shift register will be having a higher > input clock(330MHZ) than the counter(25MHz). And it will be cleared for the > duration the propagation delay is active for the counter. Not knowing about your design, it would seem easier to use a wider shift register at a slower clock rate. Maybe that isn't possible, but if it is that is probably a better way. (Though since 330 isn't divisible by 25, maybe I don't know what you are doing at all.) > Before clearing, > the value needs to be copied to a priority encoder. So finally, the number > of f/fs storing the value times the clock freq in nanoseconds (approx. 3ns > in this case) will be the output. Hope I was able to expalin it properly. > DO I have to write the shift regiater as a different module? You pretty much never NEED to write something as a different module, but often it is easier to write (and for someone else to read.) > Which type of > register to use for this purpose? How to implement the clearing logic for > shift register considering the propagation delays of counter? Please help > me. How long is the SR and how wide is the priority encoder? -- glenArticle: 145581
hi all, lets say there is a system in which there are N -inputs and 1 - output. lets say N-100 or 1000 etc. if we want to test it completely we have to give all 2 power N inputs and examine the functionality which will take more time and impossible as N goes high. so my question is how many no of optimum inputs one should give to test the functionality of such system.Article: 145582
chaitanyakurmala@gmail.com <chaitanyakurmala@gmail.com> wrote: > lets say there is a system in which there are N -inputs and 1 - > output. lets say N-100 or 1000 etc. > if we want to test it completely we have to give all 2 power N inputs > and examine the functionality which will take more time and impossible > as N goes high. In general, no, you don't have to test all 2**N combinations. You have to know for each system which need to be tested. > so my question is how many no of optimum inputs one should give to > test the functionality of such system. Say, for example, that the system is a 1000 input XOR gate. If it works with all zeros, and with all combinations of only one input 1, then it likely works for all. (It might depend on the exact implementation for XOR.) For memory arrays, the likely failure modes connect neighboring cells, so the test patterns have to know the way the address decoders work on the chip. -- glenArticle: 145583
On Sun, 2010-02-14 at 17:11 +0000, General Schvantzkoph wrote:
> I have a KVM XP VM running on Fedora 12. I'm trying to run SignalTap on
> the VM however I can't get the VM to see the USB cable. Virt-manager sees
> the cable and I've attached it to the VM but XP doesn't see it. Has
> anyone been able to attach an Altera cable to a KVM VM?
>
> p.s. the reason that I'm trying to do this with a VM is that Quartus
> doesn't run on Fedora, just CentOS. Also I've found that the Altera cable
> driver is pretty much unusable on CentOS so putting a native CentOS
> partition on machine won't solve the problem. I don't have a native
> Windows partition on my laptop so that's not an option either.
Quartus II 9.1sp1 runs under my x86_64 Fedora fine. It was just
necessary to do some small hacking first.
1. Edit the <altera_install_dir>/quartus/adm/qenv.csh file to get rid of
the stupid compatibility mode causing Quartus IDE to freeze. I added
following lines below simlar section related to CentOS:
if ( "$REDHAT_VERSION" =~ *Fedora* ) then
setenv REDHAT_VERSION 5.0rhel
endif
2. Run the Quartus II IDE as well as other tools in 64 bit mode under
x86_64 Fedora. Otherwise the tools do not start complaining about tcl/tk
problems.
quartus --64bit
Second option is to use brand new native Linux GUI based on QT (qgui).
It is in beta but it looks fine.
I hope this helps you to get rid of the VM. I use Quartus 9.1 this way
since SP1 was released.
Jan
Article: 145584On Sun, 2010-02-14 at 17:11 +0000, General Schvantzkoph wrote: > I have a KVM XP VM running on Fedora 12. I'm trying to run SignalTap on > the VM however I can't get the VM to see the USB cable. Virt-manager sees > the cable and I've attached it to the VM but XP doesn't see it. Has > anyone been able to attach an Altera cable to a KVM VM? > > p.s. the reason that I'm trying to do this with a VM is that Quartus > doesn't run on Fedora, just CentOS. Also I've found that the Altera cable > driver is pretty much unusable on CentOS so putting a native CentOS > partition on machine won't solve the problem. I don't have a native > Windows partition on my laptop so that's not an option either. BTW, what is wrong with the JTAG cable driver on CentOS? I use Altera tools on both Fedora and CentOS and I had no problems at all. At least not since the time I managed to setup udev properly and start the jtagd during system startup. JanArticle: 145585
On Feb 14, 3:10 pm, Guy Eschemann <guy.eschem...@gmail.com> wrote: > In Uwe Meyer-Baese's Book "Digital Signal Processing with Field > Programmable Gate Arrays", I saw quite a lot of references to the (at > least for me) obscure Residue Number System. I'm wondering how > relevant the RNS is in practice. I've never seen it mentioned anywhere > except in scientific publications. Is anyone using RNS in a real FPGA > project? > Cheers, Guy. I'm not sure I've even heard of it. It vaguely rings a bell, but I may be thinking of something with a similar name that is otherwise unrelated. Nope, now that I've read a bit about it I can say I've never heard of it. I like the Wikipedia page on RNS. Under Practical Applications they actually say, "...it's particularly popular in hardware implementations"! This shows one of the shortcomings of Wikipedia... unsubstantiated statements as if they were fact. I didn't see a reference for that one. RickArticle: 145586
On Sun, 14 Feb 2010 20:32:19 -0800 (PST), "chaitanyakurmala@gmail.com"
<chaitanyakurmala@gmail.com> wrote:
>hi all,
>
>lets say there is a system in which there are N -inputs and 1 -
>output. lets say N-100 or 1000 etc.
>
>if we want to test it completely we have to give all 2 power N inputs
>and examine the functionality which will take more time and impossible
>as N goes high.
>so my question is how many no of optimum inputs one should give to
>test the functionality of such system.
This is a fascinating academic problem that has been addressed
in many ways over the years.
In a seminal study by Marker and Proff [1] it was shown that
at least one solution exists that will globally maximise the
Grade function [2]. Unfortunately, this function must be
uniquely recalculated for each problem, and is also time-
varying, so the existence of a theoretically achievable
maximum is unhelpful in practice.
An alternative heuristic method, which seems to have been
first used by Slacker and Goodtime [3] in their investigation
of alcohol tolerance in the female population, involves
the application of random inputs. However, this approach
is not guaranteed to find a global maximum of the Grade
function and can exhibit instability, causing the solution
to oscillate around a local minimum instead.
From a practical point of view there appear to be three
productive approaches. The first, and least satisfactory,
is to apply the "envelope" cost function of Wonga and
Moolah [$400]. Although they achieved some success in
their original study, time variability of the Grade
function and its sensitivity to the Ethix constraint [5]
have given it a reputation for lack of repeatability.
The second, originally due to Quitter, is to sidestep the
problem entirely by application of the Corse Transformation -
I'm sorry I don't have a reference for that, but you
should be able to find information in any good Social
Studies library. Finally there is Plagia's method of
duplication [7, 8, 9, 10 et al], which has been used
successfully on innumerable studies.
References:
[1] Marker and Proff: "On the minimization of student
interference in real work", J.Edu.Obfusc. 1953
[2] Grade, A: "A new assessment function", J..zzzzz....
--
Jonathan Bromley
Article: 145587The length of the SR and the width of priority encoder is for me to decide(8-bit should be sufficient, I guess). Can you please suggest what should be the appropiate length. To write a testbench the counter and SR should be in the same module right? Or can we have more than one modules in a single 'Verilog file'? Please let me know how to use the propagation delay of counter output to get the clearing logic for SR. The i/p clk for SR should be a multiple of Counter clk? In that case the clk for SR can be taken as 300Mhz. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 145588
On 2/14/2010 10:02 AM, Jonathan Bromley wrote: > OTOH I really haven't got the first idea what happens > on PCBs at>2GHz frequencies; presumably FR4 won't cut it > any more, and more exotic substrates are required to > avoid excessive loss and dispersion? > It depends how far you want to go. The problem with FR4 is that, as a composite material, the glass fibre weave starts to screw up the signal at microwave frequencies as the Er changes along the signal path. There are a bunch of other fairly cheap and harmless substrates though, before you need to use PTFE. You can even use different layers of substrates in the same stack up, mixing cheap FR4 layers with more expensive Rogers type or even PTFE substrates. http://www.taconic-add.com/pdf/technicalarticles--ptfe-microwave-substrates.pdf It's no big deal to send 11G along an inch or so of FR4, nice fat traces on the surface. The faster you go, the bigger the problem of skin effect, so wide traces and polished copper or even silver plating are the order of the day for 28Gbps, I would suggest. I expect Altera will provide guides for the transitions, as the FPGA vendors do for their existing MGT offerings. > > Ah, now it gets interesting. Nothing in the original > press release said anything about GHz. Are we *sure* that > it's NRZ coding? It must be. I think. Cheers, Syms.Article: 145589
>The length of the SR and the width of priority encoder is for me to >decide(8-bit should be sufficient, I guess). Can you please suggest what >should be the appropiate length. To write a testbench the counter and SR >should be in the same module right? Or can we have more than one modules in >a single 'Verilog file'? Please let me know how to use the propagation >delay of counter output to get the clearing logic for SR. The i/p clk for >SR should be a multiple of Counter clk? In that case the clk for SR can be >taken as 300Mhz. > "Normal industrial practice" is to have 1 module per file. But the tools that you will use (simulator, synthesizer) will probably allow multiple modules in a file. Perhaps you should go through any tutorials that come with the tools - or that you can download from the FPGA vendor's website - before proceeding any further. These should answer your more obvious questions... --------------------------------------- Posted through http://www.FPGARelated.comArticle: 145590
After Symon's pleading to re-post, here it is... >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> I'm about to start the layout on a board which I think needs a 10 layer stack. After the religious wars betwen rickman and Symon on decoupling I'm unsure on the best stack but am veering towards... 1 signal - Top 2 GND plane 3 signal 4 signal 5 PWR plane 6 GND plane 7 signal 8 signal 9 PWR & GND plane 10 signal - Bottom >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> I'll keep the gaps between layers 2 and 9 and the associated signal layers fairly tight. What I didn't say was that this application isn't terribly demanding but it would be good to have a 'useful' stack defined that I know can be built for the future. Answering some of the previous comments... Gabor: > If you're planning a solid plane for the "PWR plane" on > layer 5, I'd probably swap that one with layer 9 so you'd > have a solid plane near the bottom. Otherwise you need > to be careful routing high speed signals across the plane > splits on layers 8 and 10. Understood, but in this application I can fairly easily route any power in where there are not IO signals. Symon: > I've given up on that last thread, but I'm a > glutton for religious wars, because when I win/martyr myself, my > religion promises me a stripper factory and a beer volcano. It's gospel! What's that, Plymouth Bretheren? > you could make clear whether you are > using a 1152 pin package because you want to use all the I/O or the > reason is you need so much logic for your application that you need that > big a package. That's what's in the reqts spec (mix of amount of logic with reasonable number of IO). > Are you gonna use any gigabit stuff to the BGA? If so, what rate? No, fastest outputs are several 200MHz single ended clocks. These will be kept short, source terminated and trace impedance tightly controlled. The biggest concern is clock & PLL useage flexibility (system clock to all PLL inputs) and optimal jitter performance on the 200MHz clock IOs. > What are you connecting the 1152 pin part to? I can't give too many details but it's a number of SDRAMs, FLASH, PCI etc. Nothing madly fast but a few interfaces I'll need to be careful with. > Is the 1152 pin part an FPGA? Yep, Stratix EP3SE100F1152 > How many supplies does the 1152 pin part need? Not that many, I've maneged to keep the number down. > What rise time are you shooting for on the I/O from this BGA? As slow as possible. There are the 200MHz outputs above and a synch ram which might be runat 167MHz but that's it. > Nial, have you ever been in a Turkish prison? Ahem, no comment. > Is this board going to be sold? In a metal box? Does it need CE > approval or somesuch? No, no, no. > How much time/money have you got? Not enough as usual. > Do you do layout yourself? Yes, I've done several BGAs, this is the first that needs 10 layers. I'm using Altium Designer so matching trace lengths etc if easy enough. I'm away back to Belfast tomorrow (it's half term) so might not be able to reply to any comments for a while. NialArticle: 145591
On 15 Feb., 05:32, "chaitanyakurm...@gmail.com" <chaitanyakurm...@gmail.com> wrote: > hi all, > > lets say there is a system in which there are N -inputs and 1 - > output. lets say N-100 or 1000 etc. > > if we want to test it completely we have to give all 2 power N inputs > and examine the functionality which will take more time and impossible > as N goes high. > so my question is how many no of optimum inputs one should give to > test the functionality of such system. You can use formal verification to achieve 100% coverage. The tools are expensive, but they work. Kolja SulimmaArticle: 145592
On Sun, 14 Feb 2010 12:10:21 -0800 (PST), Guy Eschemann <guy.eschemann@gmail.com> wrote: >In Uwe Meyer-Baese's Book "Digital Signal Processing with Field >Programmable Gate Arrays", I saw quite a lot of references to the (at >least for me) obscure Residue Number System. I'm wondering how >relevant the RNS is in practice. I've never seen it mentioned anywhere >except in scientific publications. Is anyone using RNS in a real FPGA >project? >Cheers, Guy. I remember it appearing in signal processing conferences around 1990, (try ISSCC the year it came to Glasgow) as a cute way to perform very fast multiplication because of very short carry chains, but at a huge cost overhead transcoding the inputs and outputs from normal binary to RNS and back again. Potential applications were where the number of multiplications was large enough to make that overhead look small. (Usual suspects: radar signal processing and cryptography). Probably not at all useful in FPGA because the hard wired multipliers and carry chains are so fast compared to random logic in LUTs. Actually I think it was mainly a madcap scheme to win bragging rights on the earliest date in the list of references - one paper had a (possibly bogus) reference in the 2000BC timeframe on the Chinese Remainder Theorem... - BrianArticle: 145593
On Sun, 14 Feb 2010 20:32:19 -0800 (PST), "chaitanyakurmala@gmail.com" <chaitanyakurmala@gmail.com> wrote: >hi all, > >lets say there is a system in which there are N -inputs and 1 - >output. lets say N-100 or 1000 etc. > >if we want to test it completely we have to give all 2 power N inputs >and examine the functionality which will take more time and impossible >as N goes high. >so my question is how many no of optimum inputs one should give to >test the functionality of such system. Enough to cover the state space of the system. Look for "coverage metrics" for more information. Glenn's answer is good, but I'd add: - it is best achieved with intimate knowledge of the system under test (but not necessarily so intimate that the tester shares the designer's blind spots!) - don't stop at just one test strategy (e.g. testing one bit at a time with all others '0') See "Hubble Telescope" for a failure to consider this... - Consider and test for pathological cases - e.g. where an internal counter carries into the next highest bit or rolls over to 0 - test one count either side of such problem areas as well as the problem case itself - sometimes a problem has been hidden by a quick fix! - make at least one test deliberately fail, to prove that a "pass" doesn't mean that reports have been accidentally turned off! - "constrained random" testing may find errors you didn't consider above. - some designs CAN be exhaustively tested in a reasonable time. A 24-bit square root unit can, a 24-bit multiplier (48 inputs) cannot (for a suitable definition of reasonable time) In short, there is no one general answer. - BrianArticle: 145594
On 2/15/2010 4:35 AM, Jonathan Bromley wrote: > On Sun, 14 Feb 2010 20:32:19 -0800 (PST), "chaitanyakurmala@gmail.com" > <chaitanyakurmala@gmail.com> wrote: > >> hi all, >> >> lets say there is a system in which there are N -inputs and 1 - >> output. lets say N-100 or 1000 etc. >> >> if we want to test it completely we have to give all 2 power N inputs >> and examine the functionality which will take more time and impossible >> as N goes high. >> so my question is how many no of optimum inputs one should give to >> test the functionality of such system. > > This is a fascinating academic problem that has been addressed > in many ways over the years. > > In a seminal study by Marker and Proff [1] it was shown that > at least one solution exists that will globally maximise the > Grade function [2]. Unfortunately, this function must be > uniquely recalculated for each problem, and is also time- > varying, so the existence of a theoretically achievable > maximum is unhelpful in practice. > > An alternative heuristic method, which seems to have been > first used by Slacker and Goodtime [3] in their investigation > of alcohol tolerance in the female population, involves > the application of random inputs. However, this approach > is not guaranteed to find a global maximum of the Grade > function and can exhibit instability, causing the solution > to oscillate around a local minimum instead. > > From a practical point of view there appear to be three > productive approaches. The first, and least satisfactory, > is to apply the "envelope" cost function of Wonga and > Moolah [$400]. Although they achieved some success in > their original study, time variability of the Grade > function and its sensitivity to the Ethix constraint [5] > have given it a reputation for lack of repeatability. > The second, originally due to Quitter, is to sidestep the > problem entirely by application of the Corse Transformation - > I'm sorry I don't have a reference for that, but you > should be able to find information in any good Social > Studies library. Finally there is Plagia's method of > duplication [7, 8, 9, 10 et al], which has been used > successfully on innumerable studies. > > References: > [1] Marker and Proff: "On the minimization of student > interference in real work", J.Edu.Obfusc. 1953 > [2] Grade, A: "A new assessment function", J..zzzzz.... > -- > Jonathan Bromley Most illuminating. It brightened my morning to see such an erudite practitioner sharing his knowledge. ChrisArticle: 145595
On Mon, 15 Feb 2010 09:22:13 +0100, Jan Pech wrote: > On Sun, 2010-02-14 at 17:11 +0000, General Schvantzkoph wrote: >> I have a KVM XP VM running on Fedora 12. I'm trying to run SignalTap on >> the VM however I can't get the VM to see the USB cable. Virt-manager >> sees the cable and I've attached it to the VM but XP doesn't see it. >> Has anyone been able to attach an Altera cable to a KVM VM? >> >> p.s. the reason that I'm trying to do this with a VM is that Quartus >> doesn't run on Fedora, just CentOS. Also I've found that the Altera >> cable driver is pretty much unusable on CentOS so putting a native >> CentOS partition on machine won't solve the problem. I don't have a >> native Windows partition on my laptop so that's not an option either. > > > BTW, what is wrong with the JTAG cable driver on CentOS? I use Altera > tools on both Fedora and CentOS and I had no problems at all. At least > not since the time I managed to setup udev properly and start the jtagd > during system startup. > > Jan Two questions, 1) How do you invoke the new beta GUI? 2) What did you do to get udev working? When I tried to use the USB Blaster from CentOS it almost never found the FPGA, on XP on the same machine it worked.Article: 145596
Paul <pault.eg@googlemail.com> writes: > I do use unit tests on occasion for software, but I don't use test > driven development. For VHDL, unit tests would mean I would have to > write self-checking testbenches, and unfortunately I don't tend to get > the time for that. It would be nice however to have a unit test > environment for VHDL. One day I might get the time to use it.... I usually don't have time to *not* write a self-checking testbench :) And on the occasions I think I'll get away without it, I often end up writing one anyway! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 145597
On Feb 14, 3:10 pm, Guy Eschemann <guy.eschem...@gmail.com> wrote: > In Uwe Meyer-Baese's Book "Digital Signal Processing with Field > Programmable Gate Arrays", I saw quite a lot of references to the (at > least for me) obscure Residue Number System. I'm wondering how > relevant the RNS is in practice. I've never seen it mentioned anywhere > except in scientific publications. Is anyone using RNS in a real FPGA > project? Back in the 70's I was designing digital video processing gear. Typically each system we designed had multiple, large FIR filters. This was before the TRW MPY8HJ appeared, so most of the filters had one time programmable taps, each tap (pair) being based on three 1024 x 4 proms, appropriately programmed. We gor four multipliers on a board, so 23-tap filter would take up three boards. Throw in a dozen such filters, and soon you were using a lot of resources. The mathematician associated with the group started thinking about using Peled-Liu or the Chinese Remainder Theorem to change the architecture of some of our filters, and perhaps save some hardware. He concluded that there were no substantial savings to be had for the sorts of filters we were using. I can't remember much detail of his work, but the main hope was to get rid of expensive multipliers. Now that multipliers in FPGAs are dirt cheap, it seems that P-L and CRT would be even less attractive. PeteArticle: 145598
On Mon, 2010-02-15 at 14:49 +0000, General Schvantzkoph wrote:
> On Mon, 15 Feb 2010 09:22:13 +0100, Jan Pech wrote:
>
> > On Sun, 2010-02-14 at 17:11 +0000, General Schvantzkoph wrote:
> >> I have a KVM XP VM running on Fedora 12. I'm trying to run SignalTap on
> >> the VM however I can't get the VM to see the USB cable. Virt-manager
> >> sees the cable and I've attached it to the VM but XP doesn't see it.
> >> Has anyone been able to attach an Altera cable to a KVM VM?
> >>
> >> p.s. the reason that I'm trying to do this with a VM is that Quartus
> >> doesn't run on Fedora, just CentOS. Also I've found that the Altera
> >> cable driver is pretty much unusable on CentOS so putting a native
> >> CentOS partition on machine won't solve the problem. I don't have a
> >> native Windows partition on my laptop so that's not an option either.
> >
> >
> > BTW, what is wrong with the JTAG cable driver on CentOS? I use Altera
> > tools on both Fedora and CentOS and I had no problems at all. At least
> > not since the time I managed to setup udev properly and start the jtagd
> > during system startup.
> >
> > Jan
>
> Two questions,
>
> 1) How do you invoke the new beta GUI?
> 2) What did you do to get udev working?
>
> When I tried to use the USB Blaster from CentOS it almost never found the
> FPGA, on XP on the same machine it worked.
>
1) qgui
2) cat /etc/udev/rules.d/51-usbblaster.rules:
BUS=="usb", SYSFS{idVendor}=="09fb", SYSFS{idProduct}=="6001",
MODE="0666", PROGRAM="/bin/sh -c 'K=%k; K=$${K#usbdev};
printf /proc/bus/usb/%%03i/%%03i$${K%%%%.*} $${K#*.}'", RUN+="/bin/chmod
0666 %c"
Jan
Article: 145599
On Mon, 15 Feb 2010 15:58:56 +0100, Jan Pech wrote:
> On Mon, 2010-02-15 at 14:49 +0000, General Schvantzkoph wrote:
>> On Mon, 15 Feb 2010 09:22:13 +0100, Jan Pech wrote:
>>
>> > On Sun, 2010-02-14 at 17:11 +0000, General Schvantzkoph wrote:
>> >> I have a KVM XP VM running on Fedora 12. I'm trying to run SignalTap
>> >> on the VM however I can't get the VM to see the USB cable.
>> >> Virt-manager sees the cable and I've attached it to the VM but XP
>> >> doesn't see it. Has anyone been able to attach an Altera cable to a
>> >> KVM VM?
>> >>
>> >> p.s. the reason that I'm trying to do this with a VM is that Quartus
>> >> doesn't run on Fedora, just CentOS. Also I've found that the Altera
>> >> cable driver is pretty much unusable on CentOS so putting a native
>> >> CentOS partition on machine won't solve the problem. I don't have a
>> >> native Windows partition on my laptop so that's not an option
>> >> either.
>> >
>> >
>> > BTW, what is wrong with the JTAG cable driver on CentOS? I use Altera
>> > tools on both Fedora and CentOS and I had no problems at all. At
>> > least not since the time I managed to setup udev properly and start
>> > the jtagd during system startup.
>> >
>> > Jan
>>
>> Two questions,
>>
>> 1) How do you invoke the new beta GUI? 2) What did you do to get udev
>> working?
>>
>> When I tried to use the USB Blaster from CentOS it almost never found
>> the FPGA, on XP on the same machine it worked.
>>
>>
> 1) qgui
>
> 2) cat /etc/udev/rules.d/51-usbblaster.rules:
>
> BUS=="usb", SYSFS{idVendor}=="09fb", SYSFS{idProduct}=="6001",
> MODE="0666", PROGRAM="/bin/sh -c 'K=%k; K=$${K#usbdev}; printf
> /proc/bus/usb/%%03i/%%03i$${K%%%%.*} $${K#*.}'", RUN+="/bin/chmod 0666
> %c"
>
> Jan
Thanks, its' all working on Fedora 12. I switch to the beta GUI and I set
up udev as you suggested and I added the following to /etc/rc.local
echo 356 40000 32 32000 > /proc/sys/kernel/sem
/usr/local/tools/Quartus/bin/jtagd
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