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Paul wrote:
> But RTL generally is very different to software, because RTL has the
> extra requirement that things have to happen at explicit times. I'm
> not sure RTL could adopt much from the software world that would make
> RTL quicker/easier.
I could argue that RTL is very similar to software, because the only
difference is that HDLs support time. The information content of such
statements is not very high.
> I can't think of how OO methods would work for RTL coding. For
> testbenches maybe. Although procedural testbenches are probably more
> than adequate for the majority of cases.
>
> Dynamic types of course are also no good for RTL, because signals/
> variables are static. Dynamic languages could be used for testbenches
> but then dynamic languages are slower, possibly not what you want for
> testbenches. Although I guess the speed impact of a dynamic language
> for testbenches would depend on the relative complexity of a testbench
> to the RTL design.
It is "of course" trivial to emulate static objects in dynamic languages:
just don't touch them after creation :-) The principal RTL restriction
lies elsewhere: only a limited subset of types can be implemented
in silicon.
> Agile methods are probably out. Apparently they're good for quickly
> changing code to accommodate quickly changing requirements. But
> because RTL coding is harder than writing software (because of the
> extra requirement that things have to happen happen at specific
> times), quickly changing RTL code isn't really possible.
So what you're saying is that *because* RTL coding is harder,
methodologies that may make it easier are not applicable ???
The logical conclusion would be the opposite.
> And for FPGA
> designs tying specs down to a reasonable level is a lot easier than
> for software engineering, because an FPGA has at least well defined
> requirements in what it has to drive on a circuit board. So just write
> the specs right, or mostly right to start with, and you don't need
> agile.
I don't see how the rapidly evolving FPGA technology can be optimally
used without drastic changes to traditional FPGA design methodology.
> I can't think of how any recent software methods would help RTL. Maybe
> I'm a stick-in-the-mud :-)
I think your a little fast with conclusions.
For an HDL based on a dynamic language, check out MyHDL.
To understand how agile concepts such as unit testing and test driven
development can be used for HDL design, also check out MyHDL.
For an agile VHDL development platform, check out Sigasi HDT.
Jan
--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Python as a HDL: http://www.myhdl.org
VHDL development, the modern way: http://www.sigasi.com
Analog design automation: http://www.mephisto-da.com
World-class digital design: http://www.easics.com
Article: 145551>> Just a slip or Freudian Slip? > >A Freudian slip is when you say one thing, but mean amother. And presumably a (capitalized) Freudian Slip is when you ask for one piece of underwear, but want another? -- Jonathan BromleyArticle: 145552
On Sat, 13 Feb 2010 15:17:09 -0800 (PST), Michael S <already5chosen@yahoo.com> wrote: >On Feb 13, 12:48 pm, Jonathan Bromley wrote: >> >> By contrast, VHDL's limitations in the world of >> testbench writing are so severe that it's amazing >> it gained any traction at all in that space. > >I am assuming the above was intended to read as "By contrast, >Verilog's limitations in the world of testbench writing are so severe >that it's amazing it gained any traction at all in that space." No, I meant what I said. I agree that Verilog pre-2001, with absolutely everything being static, was fairly painful for writing any kind of software. But VHDL pre-2008 (and, because of lack of interest by tool vendors, VHDL even today) lacks cross-module references, which is a show-stopper. SystemVerilog, Vera, 'e' and other dynamic testbench languages (even C++, if you really must) are so much more fit-for-purpose that there is no point in looking back unless you're constrained by lack of availability of the appropriate tools. -- Jonathan BromleyArticle: 145553
On Sat, 13 Feb 2010 21:28:54 -0800 (PST), Patrick Maupin <pmaupin@gmail.com> wrote: >On Feb 13, 2:57 pm, whygee <y...@yg.yg> wrote: >> Symon wrote: >> damnit, the fundamental wavelength of a 28GHz signal >> is smaller than the pin's pitch... or close... > >Well it's late, and I haven't looked at the announcement yet, but >1/28th of a ns should be slightly over a centimeter for light in a >vacuum, probably around half an inch for a signal on a board -- eh? 0.5in==1.27cm; but group velocity on a typical PCB is something around c/2 so surely you meant "under a centimeter". OTOH I really haven't got the first idea what happens on PCBs at >2GHz frequencies; presumably FR4 won't cut it any more, and more exotic substrates are required to avoid excessive loss and dispersion? >exactly how far apart are the pins on this new chip :-) tee hee. Please let's forgive the poor chap his one-order-of-magnitude error. The newspaper I usually read has a nasty habit of telling me that a power station has an output of a few hundred "mw", which is about 1E9 times smaller than I would expect :-) >BTW, if you're talking about the wavelength, you can probably double >that to around an inch, because 28Gbps using 1s and 0s is probably >only a 14 GHz signal, right? Ah, now it gets interesting. Nothing in the original press release said anything about GHz. Are we *sure* that it's NRZ coding? -- Jonathan BromleyArticle: 145554
nico@puntnl.niks (Nico Coesel) writes: > Bottom line is that VHDL is more powerful & complicated than Verilog > but neither are the perfect language. For people with a background in Depends upon which Verilog standard you refer to as Verilog. IEEE-1800 is way more powerful than any of the VHDL standards IMHO. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 145555
On Sun, 14 Feb 2010 01:35:12 +0000, Symon wrote: >OT, but couldn't resist. > >A Freudian slip is when you say one thing, but mean amother. I thought a Freudian slip occurs when you say the embarrassing words that you really mean, instead of the weasel words you were trying to say? When your id slips through your superego's security checks? -- Jonathan BromleyArticle: 145556
On Feb 14, 12:17=A0am, Patrick Maupin <pmau...@gmail.com> wrote: > On Feb 13, 6:21=A0pm, John_H <newsgr...@johnhandwork.com> wrote: > > > The description comes out a little muddy which is why it took me a few > > days to buy in to the whole concept. =A0It's sweet! =A0It just takes so= me > > timing diagrams and head scratching. =A0And it's certainly not set up > > for proper analysis especially in the Xilinx tools where I > > experimented with the phase domain changes. > > It's not just FPGA tools. =A0Many of the high-end chip tools don't > support this very well, and to do it you need a PhD in the tool. The sad thing is it *shouldn't* be difficult. For each stage of latch traversed with an opposite clock edge, one more half cycle is added to the overall timing spec for the path. By analyzing up to each stage, a logic delay short enough to change the input of a latch that's still not transparent starts the timing path fresh from this intermediate latch. It's such a "pretty" cascade of logic delays that I have to research what you mean by "domino logic" to make sure we're not talking about the same thing. It truly would be simple to analyze, no PhD required.Article: 145557
On Feb 14, 5:02=A0am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: <snip> > Ah, now it gets interesting. =A0Nothing in the original > press release said anything about GHz. =A0Are we *sure* that > it's NRZ coding? > -- > Jonathan Bromley Oooooohhh..... QAM? OFDM? I need to find my notes on the Costas loop, don't I?Article: 145558
On Feb 8, 7:51=A0pm, timinganalyzer <timinganaly...@gmail.com> wrote: > Hello serkan, > > The latest version of the TimingAnalyzer now reads VCD files and > automatically converts and saves it as a timing diagram. =A0This is > useful for documenting simulation results for specifications, reviews, > and presentations. > > http://www.timing-diagrams.com/dokuwiki/doku.php?id=3Ddocs:vcd_files > > Dan > > On Feb 5, 5:29=A0pm, "M.Randelzhofer" <techsel...@gmx.de> wrote: > > > "Serkan" <ok...@su.sabanciuniv.edu> schrieb im Newsbeitragnews:382d6281= -244f-48d7-a0ae-ff76e69316db@p24g2000yqm.googlegroups.com... > > > > Any suggestions for a free waveform drawing tool? > > > > inkscape or word alike tools take too much time for edition. > > > some free tools does not let more than 10 clock cycles > > > some free tools does not let more than 5 or 6 signals > > > > kind regards > > > serkan > > >http://www.timing-diagrams.com/doku.php > > > MIKE I am having trouble figuring out other aspects of using this program. I noticed that the author's web site doesn't have a forum for users, so I've started a Yahoo group for users to discuss this program and hopefully provide support to one another. http://tech.groups.yahoo.com/group/TimingAnalyzer/ I am trying to draw a diagram to help me visualize the advantages of replacing registers with latches in designs with tight timing. It seems like an uphill struggle given that I can't tell if the things I try don't work because that isn't the way the tool works or if I'm just not using it right. I'm not finding this tool to be very intuitive. But then maybe I'm just not thinking along the right vein. RickArticle: 145559
On 14 Feb, 09:34, Jan Decaluwe <j...@jandecaluwe.com> wrote: > > So what you're saying is that *because* RTL coding is harder, > methodologies that may make it easier are not applicable ??? > That's not what I said at all!! :-) OK, my point was too narrow, i.e. specs for FPGA designs tend to be pretty well specified and so you don't need agile methodology, which essentially I construe as being geared up to deal with implementing a design that has changing requirements. > To understand how agile concepts such as unit testing and test driven > development can be used for HDL design, also check out MyHDL. I do use unit tests on occasion for software, but I don't use test driven development. For VHDL, unit tests would mean I would have to write self-checking testbenches, and unfortunately I don't tend to get the time for that. It would be nice however to have a unit test environment for VHDL. One day I might get the time to use it.... Regards, Paul.Article: 145560
On Feb 14, 8:32=A0am, John_H <newsgr...@johnhandwork.com> wrote: > On Feb 14, 5:02=A0am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> > wrote: > <snip> > > > Ah, now it gets interesting. =A0Nothing in the original > > press release said anything about GHz. =A0Are we *sure* that > > it's NRZ coding? > > -- > > Jonathan Bromley > > Oooooohhh..... =A0QAM? =A0OFDM? =A0I need to find my notes on the Costas > loop, don't I? The standard marketing gigabits probably comes from the total bandwidth of all transceivers on the part. And if it really means 28 Gbps on a single wire pair, NRZ, then a bit period would represent about .4" of FR4 using the old 1 ns/ft estimate. Still a large pin pitch but no doubt a real pain to work with. I hope the transceiver pins are on the edge of the package, lined up to properly connect to a standard connector / fiber transceiver without any cross-overs. - GLSArticle: 145561
Paul <pault.eg@googlemail.com> writes: > driven development. For VHDL, unit tests would mean I would have to > write self-checking testbenches, and unfortunately I don't tend to get > the time for that. It would be nice however to have a unit test How do you have time *not* to do that :-) Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 145562
Petter Gustad <newsmailcomp6@gustad.com> wrote: >nico@puntnl.niks (Nico Coesel) writes: > >> Bottom line is that VHDL is more powerful & complicated than Verilog >> but neither are the perfect language. For people with a background in > >Depends upon which Verilog standard you refer to as Verilog. IEEE-1800 >is way more powerful than any of the VHDL standards IMHO. I'm talking about the Verilog you can actually use with todays tools. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 145563
On 14 Feb, 16:02, Petter Gustad <newsmailco...@gustad.com> wrote: > > driven development. For VHDL, unit tests would mean I would have to > > write self-checking testbenches, and unfortunately I don't tend to get > > the time for that. It would be nice however to have a unit test > > How do you have time *not* to do that :-) Because I write stimulus only test benches. Which of course only means visual inspection of results. That method I find is the quickest way of getting to a working FPGA design. How do you get the time to do self-checking testbenches? :-) Paul.Article: 145564
Patrick Maupin wrote: > Well it's late, and I haven't looked at the announcement yet, but > 1/28th of a ns should be slightly over a centimeter for light in a > vacuum, probably around half an inch for a signal on a board -- > exactly how far apart are the pins on this new chip :-) hmmm I had a 10 fold error in my rought estimate, but it scares me anyway :-) > BTW, if you're talking about the wavelength, you can probably double > that to around an inch, because 28Gbps using 1s and 0s is probably > only a 14 GHz signal, right? oooopps right, I get caught in this old trap again and again... > Pat yg -- http://ygdes.com / http://yasep.orgArticle: 145565
On Feb 14, 10:43=A0am, Gabor <ga...@alacron.com> wrote: > On Feb 14, 8:32=A0am, John_H <newsgr...@johnhandwork.com> wrote: > > > On Feb 14, 5:02=A0am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> > > wrote: > > <snip> > > > > Ah, now it gets interesting. =A0Nothing in the original > > > press release said anything about GHz. =A0Are we *sure* that > > > it's NRZ coding? > > > -- > > > Jonathan Bromley > > > Oooooohhh..... =A0QAM? =A0OFDM? =A0I need to find my notes on the Costa= s > > loop, don't I? > > The standard marketing gigabits probably comes from the > total bandwidth of all transceivers on the part. =A0And if it > really means 28 Gbps on a single wire pair, NRZ, then > a bit period would represent about .4" of FR4 using the > old 1 ns/ft estimate. =A0Still a large pin pitch but no doubt > a real pain to work with. =A0I hope the transceiver pins are > on the edge of the package, lined up to properly connect > to a standard connector / fiber transceiver without > any cross-overs. > > - GLS Is this right? 1 ns/Ft is the speed of light in a vacuum. In FR4 it is approximately half that giving 28 GHz a wavelength of about 2 cm or about 0.8 inches. As far as I can tell, Patrick was right in his way of estimating the wavelength in a PCB although his round off error is pretty large and in the wrong direction... ;^) Regardless, 28 GHz is pretty fast and will only be used by a very few... mostly the ones who can afford to pay through the nose for it. RickArticle: 145566
I have a KVM XP VM running on Fedora 12. I'm trying to run SignalTap on the VM however I can't get the VM to see the USB cable. Virt-manager sees the cable and I've attached it to the VM but XP doesn't see it. Has anyone been able to attach an Altera cable to a KVM VM? p.s. the reason that I'm trying to do this with a VM is that Quartus doesn't run on Fedora, just CentOS. Also I've found that the Altera cable driver is pretty much unusable on CentOS so putting a native CentOS partition on machine won't solve the problem. I don't have a native Windows partition on my laptop so that's not an option either.Article: 145567
On Feb 14, 11:13=A0am, Paul <pault...@googlemail.com> wrote: > On 14 Feb, 16:02, Petter Gustad <newsmailco...@gustad.com> wrote: > > > > driven development. For VHDL, unit tests would mean I would have to > > > write self-checking testbenches, and unfortunately I don't tend to ge= t > > > the time for that. It would be nice however to have a unit test > > > How do you have time *not* to do that :-) > > Because I write stimulus only test benches. Which of course only means > visual inspection of results. That method I find is the quickest way > of getting to a working FPGA design. > > How do you get the time to do self-checking testbenches? :-) > > Paul. I tend to use self-checking test benches. There is some question as to what is best, but I find that often my design has to be tweaked after I have it working and once I have the test bench working, the tweaked design can be tested very easily. I guess it is a question of whether the test bench is a one time thing or will be "reused". I often find I "reuse" my test benches in both ways, I often run them more than once and I use parts of one test bench in others as I test my way up the integration process. Oh, also, there has been more than once that my test bench was actually another FPGA design that ended up on a test fixture to production test the real board. That can be a fair amount of work, but not as much work as separately testing two FPGA designs. RickArticle: 145568
In article <ec4da9c9-de93-445b-b0b5-71707548cf26@l26g2000yqd.googlegroups.com>, Gabor <gabor@alacron.com> wrote: >On Feb 14, 8:32=A0am, John_H <newsgr...@johnhandwork.com> wrote: >> On Feb 14, 5:02=A0am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> >> wrote: >> <snip> >> >> > Ah, now it gets interesting. =A0Nothing in the original >> > press release said anything about GHz. =A0Are we *sure* that >> > it's NRZ coding? >> >> Oooooohhh..... =A0QAM? =A0OFDM? =A0I need to find my notes on the Costas >> loop, don't I? > >The standard marketing gigabits probably comes from the >total bandwidth of all transceivers on the part. No; at least, they said '11.3 Gbps' for Stratix IV and the parts have up to 24 9.95-to-11.3Gbps transceivers. Given that they're talking about 400Gbit/s networking, I suspect there will be sixteen 20-to-28Gbps transceivers on a big Stratix VI. TomArticle: 145569
On 14 Feb, 17:15, rickman <gnu...@gmail.com> wrote: > > I tend to use self-checking test benches. =A0There is some question as > to what is best, but I find that often my design has to be tweaked > after I have it working and once I have the test bench working, the > tweaked design can be tested very easily. =A0I guess it is a question of > whether the test bench is a one time thing or will be "reused". =A0I > often find I "reuse" my test benches in both ways, I often run them > more than once and I use parts of one test bench in others as I test > my way up the integration process. > > Oh, also, there has been more than once that my test bench was > actually another FPGA design that ended up on a test fixture to > production test the real board. =A0That can be a fair amount of work, > but not as much work as separately testing two FPGA designs. > > Rick I thought non-checking test benches was the most prevalent method used, because that's what I do and almost all engineers I've come across do as well. Hmmmm...... maybe I need to change my mind :-)Article: 145570
nico@puntnl.niks (Nico Coesel) writes: > Petter Gustad <newsmailcomp6@gustad.com> wrote: > >>nico@puntnl.niks (Nico Coesel) writes: >> >>> Bottom line is that VHDL is more powerful & complicated than Verilog >>> but neither are the perfect language. For people with a background in >> >>Depends upon which Verilog standard you refer to as Verilog. IEEE-1800 >>is way more powerful than any of the VHDL standards IMHO. > > I'm talking about the Verilog you can actually use with todays tools. I actually used IEEE-1800 several years ago (VCS and DC). Today it's supported by even more tools, including Quartus. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 145571
General Schvantzkoph <schvantzkoph@yahoo.com> writes: > p.s. the reason that I'm trying to do this with a VM is that Quartus > doesn't run on Fedora, just CentOS. Also I've found that the Altera cable > driver is pretty much unusable on CentOS so putting a native CentOS > partition on machine won't solve the problem. I don't have a native > Windows partition on my laptop so that's not an option either. Hmm. I've used the USB blaster almost daily on several gentoo systems for the last couple years. I even used an old headless PC (running gentoo) as a JTAG server for some time. However, I tend to use most of the CLI (quartus_pgm, nios2-download, and gdb) tools except signaltap. Long ago when I was running Quartus on Solaris I had an old Windows Laptop (I think it was even a 486) running Quartus Programmer acting as a JTAG server. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 145572
Paul <pault.eg@googlemail.com> writes: > visual inspection of results. That method I find is the quickest way > of getting to a working FPGA design. Visual inspection does not scale. If you run the test more a couple times you have probably saved the time it takes to write the self-checking test bench. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 145573
On Feb 14, 11:08=A0am, rickman <gnu...@gmail.com> wrote: > Is this right? =A01 ns/Ft is the speed of light in a vacuum. =A0In FR4 it > is approximately half that giving 28 GHz a wavelength of about 2 cm or > about 0.8 inches. =A0As far as I can tell, Patrick was right in his way > of estimating the wavelength in a PCB although his round off error is > pretty large and in the wrong direction... ;^) Yes. Definitely the wrong direction. Fortunately, I was prescient enough to report (truthfully) that it was late when I was making my observations :-) PatArticle: 145574
On Feb 14, 4:02=A0am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > On Sat, 13 Feb 2010 21:28:54 -0800 (PST), Patrick Maupin > >BTW, if you're talking about the wavelength, you can probably double > >that to around an inch, because 28Gbps using 1s and 0s is probably > >only a 14 GHz signal, right? > > Ah, now it gets interesting. =A0Nothing in the original > press release said anything about GHz. =A0Are we *sure* that > it's NRZ coding? Well, Gabor pointed out that it might be "marketing Gbps", multiplying number of signal pairs on the chip by bandwidth capability per pair. Which is probably the correct interpretation. But if I were building a fancy FPGA, and wanted to make sure I sold more of them by having them talk to each other really, really fast, I might consider building a transceiver that could encode more than 1 bit per symbol over a short link. So, for example, if you could reliably encode and decode 16 levels per bit time, you could transfer 4 bits per symbol, and now you're "only" running the link at 7 G samples/sec =3D=3D 3.5 GHz. Of course, you'd have to build a really fantastic adaptive receiver, training algorithms, etc., but it might still be easier than 14 GHz.
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