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On Sun, 14 Feb 2010 12:10:21 -0800 (PST), Guy Eschemann <guy.eschemann@gmail.com> wrote: >In Uwe Meyer-Baese's Book "Digital Signal Processing with Field >Programmable Gate Arrays", I saw quite a lot of references to the (at >least for me) obscure Residue Number System. I'm wondering how >relevant the RNS is in practice. I've never seen it mentioned anywhere >except in scientific publications. Is anyone using RNS in a real FPGA >project? >Cheers, Guy. RNS is one of the methods which allow you to add without carries. The problem with them is two fold both of which have the same slow solution. One you can't compare them, two there are no RNS peripherals so while things are fast while you're in the RNS domain you have convert IO to a 'normal' number system and also to compare two numbers you have to convert to NNS. The conversion is quite slow as you have to account for the carries during the conversion. These days with all the embedded arithmetic blocks in FPGAs (or high speed/density of logic processes in ASICs) there is no more need for them anymore. If one manages to formulate an adaptive filter solely in RNS domain then there may be renewed interest in their use. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 145601
On Feb 15, 7:34 am, "Nial Stewart" <nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote: > After Symon's pleading to re-post, here it is... > > > > I'm about to start the layout on a board which I think needs > a 10 layer stack. > > After the religious wars betwen rickman and Symon on decoupling I'm > unsure on the best stack but am veering towards... > > 1 signal - Top > 2 GND plane > 3 signal > 4 signal > 5 PWR plane > 6 GND plane > 7 signal > 8 signal > 9 PWR & GND plane > 10 signal - Bottom Rather than have us tell you what we think of your design and ideas (which you actually don't give much of) why not you tell us why you want to do things the way you are doing them. I think it would be much more useful to discuss the rational rather than the result. There are any number of reasons to do something one way or another which may or may not have been stated. Since we can't easily know all the facts, it might be easier for us to critique your thinking rather than your result. > I'll keep the gaps between layers 2 and 9 and the associated signal > layers fairly tight. Here is an example. Why are you concerned about layers 2 and 9 and not 5 and 6? Why are you concerned about spacing rather than coupling or impedance? My point is that the spacing of signal layers to power planes can vary depending on a number of factors including limitations in the stackup total thickness. What is mostly important is the ratio of the spacing to the trace width (which is also how you control impedance). > What I didn't say was that this application isn't terribly > demanding but it would be good to have a 'useful' stack defined > that I know can be built for the future. > > Answering some of the previous comments... > > Gabor: > > > If you're planning a solid plane for the "PWR plane" on > > layer 5, I'd probably swap that one with layer 9 so you'd > > have a solid plane near the bottom. Otherwise you need > > to be careful routing high speed signals across the plane > > splits on layers 8 and 10. > > Understood, but in this application I can fairly easily route > any power in where there are not IO signals. I'm not clear on what you are saying. Are you suggesting that you will be routing power on signal layers? What I'm really curious about is why you want to mix power and ground on one plane. Everything I have learned says that coupled power and ground planes are the same for high speed signals and you will get better coupling if you have more area common between the ground and power planes. So using the entire layer for power should give better coupling and better high speed signal returns. If you don't have good high frequency coupling between power and ground, won't you see a change in impedance if a trace on an adjacent signal layer passes from the ground area to the power area and vice versa? In other words, I don't get why you are mixing ground and power on one plane when you already have two ground planes. > Symon: > > > Are you gonna use any gigabit stuff to the BGA? If so, what rate? > > No, fastest outputs are several 200MHz single ended clocks. These will > be kept short, source terminated and trace impedance tightly controlled. With the stackup shown above I suggest that you keep them off of layers 7, 8 and 10. Potentially poor impedance control depending on the area and spacing of your power planes on layer 9. > The biggest concern is clock & PLL useage flexibility (system clock to > all PLL inputs) and optimal jitter performance on the 200MHz clock IOs. > > > What are you connecting the 1152 pin part to? > > I can't give too many details but it's a number of SDRAMs, FLASH, PCI > etc. Nothing madly fast but a few interfaces I'll need to be careful > with. > > > Is the 1152 pin part an FPGA? > > Yep, Stratix EP3SE100F1152 > > > How many supplies does the 1152 pin part need? > > Not that many, I've maneged to keep the number down. I've heard of primitive number systems that count 1, 2, 3 and "more than 3". But I've not heard of one that used "Not that many". Can you tell us if you are using 1, 2, 3 or "more than 3" power supply voltages? ;^) > > What rise time are you shooting for on the I/O from this BGA? > > As slow as possible. There are the 200MHz outputs above and a > synch ram which might be runat 167MHz but that's it. So how slow is that? With the huge number of I/Os you appear to be using, SSN (simultaneous switching noise) is potentially large. You might want to simulate that to get an idea of the amount of ground bounce you will see. And when you do it, I recommend that you simulate *all* of the components in your PDS, not just one example component... ;^) It has occurred to me that Altera must have done simulations on their parts to be sure that they are usable with a large number of I/Os switching. You might want to ask them for info on their simulations. They may have detailed simulations available complete with recommended stackups and PDS specs. If they have done a worst case design analysis, maybe you won't have to reinvent the wheel. It's worth asking about. RickArticle: 145602
On Feb 14, 12:41=A0pm, Paul <pault...@googlemail.com> wrote: > On 14 Feb, 17:15, rickman <gnu...@gmail.com> wrote: > > > > > > > I tend to use self-checking test benches. =A0There is some question as > > to what is best, but I find that often my design has to be tweaked > > after I have it working and once I have the test bench working, the > > tweaked design can be tested very easily. =A0I guess it is a question o= f > > whether the test bench is a one time thing or will be "reused". =A0I > > often find I "reuse" my test benches in both ways, I often run them > > more than once and I use parts of one test bench in others as I test > > my way up the integration process. > > > Oh, also, there has been more than once that my test bench was > > actually another FPGA design that ended up on a test fixture to > > production test the real board. =A0That can be a fair amount of work, > > but not as much work as separately testing two FPGA designs. > > > Rick > > I thought non-checking test benches was the most prevalent method > used, because that's what I do and almost all engineers I've come > across do as well. Hmmmm...... maybe I need to change my mind :-) I can't say I have worked with that many engineers well enough to know how their test benches work, but I can only think of one designer (I hate to call him an engineer even if he has a degree) who does not use self-checking test benches. But then this guy also doesn't use static timing analysis. He claims a post-route simulation will find timing errors. I actually could not get him to understand why everyone else uses static timing analysis and why the vendors put so much effort into providing the tool! RickArticle: 145603
If its any help I can relate my experience of designing an 8 layer PCI Express card (4 lanes). This consisted of a Virtex 5 with four DDR2 SDRAM components operating at 333 MHz. The stackup I used :- 1. Signal 2. Gnd 3. Signal 4. Pwr (1V8 2V5 1V0(GTP)) 5. Pwr (1V0 0V9 1V2 (GTP)) 6. Signal 7. Pwr (3V3) 8. Signal I tried to keep one continous plane (layers 2 and 7) next to each signal layer for controlled impedance routing. I followed the Xilinx documentation with regard to decoupling caps and power supply requiremnts. I routed the GTP signals on layers 1 and 8 next to the continuous planes. The DDR2 signals were kept as short as possible (about 50mm max). I have no external termination on the tracks; I use the Xilinx DCI which works very well. I did do some simulations using Hyperlynx before starting the board to verify there would be no problem. I have to say that the board has worked perfectly from the start of testing so I guess I must have done something right. Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 145604
Hi Nial, OK, I understand your reticence to blab too much about your board, I would do the same. FWIW, if I was gonna do this board at 1.6 mm thickness I would start from:- 1 Signal 2 Signal 3 Ground 4 Power pours, rarely some slow signals if absolutely needed. ****Thick core, 25 mils or so.**** 5 Power pours, rarely some slow signals if absolutely needed. 6 Ground 7 Signal 8 Signal To be able to route this up, I would use "frickin' laser beam" drilled microvias between layers 1 & 2, and maybe 7 & 8 if I needed it on a congested board. I'd try not to use the I/O balls in the middle of the package, if I could help it. This assumes the BGA is mounted on layer 1. The micro-vias can be 'in pad'. I would use 0.1mm-0.1mm-0.1mm track-gap-track. I use 1oz copper for everything, good for heat transfer. I would think long and hard about the signal assignments on the FPGA to ease the routing. I know Philip uses Altium and he was singing its praises when I last saw him; I was impressed with what it could do wrt pin swapping. I've used this approach on several boards, a few with 1152 BGAs, with small sections of 11G stuff, with multiple different Vccos on the same part, DDR-2 DIMMs and 3G MGT stuff. I can't be arsed to justify this on usenet, so, I'm not proselytising anything to you, because I don't know what your specific requirements are. I offer it as food for thought for you and your PCB vendor. If you are interested, you can google my name and microvias and see what I've posted here in the past. Somewhere you'll find a link to a picture of a board I did long ago that Philip is still hosting I think. Also, here's some reading material about some specific issues with big fast power hungry FPGAs:- http://www.xilinx.com/support/documentation/application_notes/xapp689.pdf I notice the Altera parts have much less I/O pin capacitance, 4pF vs 10pF, so this should help you wrt ground bounce. http://www.xilinx.com/products/virtex4/pdfs/BGA_Crosstalk.pdf Have Altera sorted out their ball positions on Stratix 3? I couldn't find a nice picture. Good luck, Syms. p.s. I see no reason why Jon's suggested stack up wouldn't work either, unless it runs out of routing channels with only four signal layers and through vias.Article: 145605
Pallavi <pallavi_mp@n_o_s_p_a_m.rediffmail.com> wrote: > I'm implementing this project where I've to generate higher output clk > frequencies using DCM module. I have used a counter for delay generator, > for propagation delays(Pls suggest if there is any other method). As a logic designer, one of the things you are responsible for is understanding the timing limitations of the underlying logic. Today, 300MHz is still pretty fast, but some logic families can do that. You do have to keep the logic between registers to a minimum, though, to keep up. It would be much easier, for example, to process four bits at a time at 75MHz than one bit at 300MHz. You may or may not be able to do that in your design, but most of the time you can. -- glenArticle: 145606
Brian Drummond <brian_drummond@btconnect.com> wrote: > On Sun, 14 Feb 2010 20:32:19 -0800 (PST), "chaitanyakurmala@gmail.com" > <chaitanyakurmala@gmail.com> wrote: >>lets say there is a system in which there are N -inputs and 1 - >>output. lets say N-100 or 1000 etc. (snip) > Glenn's answer is good, but I'd add: > - it is best achieved with intimate knowledge of the system under test > (but not necessarily so intimate that the tester shares the designer's > blind spots!) That was the point I was (trying to) make: That the best test method is system specific. > - don't stop at just one test strategy (e.g. testing one bit at a time > with all others '0') See "Hubble Telescope" for a failure to consider > this... That was a specific example for the case of all XOR gates. I believe it is right for that case, but not for a large number of other cases. For an actual example of failure to test appropriately, I once used a system that had some signed comparators. It seesm that no test was done with values of different sign. It gave the right result comparing postiive number to positive numbers, and negative numbers to negative numbers, but not mixed. But that was in the design. I was thinking in this case the problem was to detect fabrication errors. > - Consider and test for pathological cases - e.g. where an internal > counter carries into the next highest bit or rolls over to 0 With the (not necessarily true) assumption that each logic device is independent, you must test for all the combinations for each device. For the 'rolls over to zero' case, there is another one to verify. That is, that the logic gives the right results at the desired clock rate. It might be, for example, that the counter is too slow in the roll over case, but does eventually give the right result. > - test one count either side of such problem areas as well > - as the problem case itself - sometimes a problem has been > - hidden by a quick fix! You do have to know the logic very well, but yes. There are, for example, counters that make the roll over case decision one clock cycle earlier. (That is, pipeline the roll over.) > - make at least one test deliberately fail, to prove that > - a "pass" doesn't mean that reports have been accidentally > - turned off! I was assuming we were talking about test vectors for fabricated chips. That might have been an unwarrented assumption, though. > - "constrained random" testing may find errors you didn't > - consider above. In the days of punched cards, one test for compilers was to feed it cards from the recycle bin. That is, random wrong, but not too wrong, statements. > - some designs CAN be exhaustively tested in a reasonable time. > A 24-bit square root unit can, a 24-bit multiplier (48 inputs) > - cannot (for a suitable definition of reasonable time) And, as Intel knows, floating point dividers also can't be exhaustively checked, even at the design level. -- glenArticle: 145607
Hi, I'm workng with MGT as GT_CUSTOM. I use the MGT for transmiting to pulses of .66ns(1/15Ghg). I check all the delays with FPGA editor and all was ok, but I mesure the pulses at the SATA conector and there are a delay between SATA0 and SATA1 of 500ps. I simplified the program as much as posible and this delay is always present. The mesurment was made with the same cable lenght. Same ideas? Thansk Marcelo --------------------------------------- Posted through http://www.FPGARelated.comArticle: 145608
Hi.I know this thead is older,but i am searching rod carlson,which posted this . if you read it,could contact me? I have send mail this direction,but it seems is out. a lot of thanks >I have done this many times as a contract for other companies that have >lost Verilog, VHDL, or AHDL source code. Its quite common to have a >.sof in control from manufacturing and missing the source code. For >example, if the designer leaves a company and his desktop is lost or >changed by IT or if the designer's hard drive has a sudden death and is >not under control or backed up. The end result of my disassembling / >decompiling the FPGA binary will be much better than a netlist as it >will be readable (.v), (.vhdl) . I usually charge anywhere from $3,000 >to $7,000 US dollars for the time required in reobtaining the source >code depending on the type of FPGA and the amount of LUTS used. I can >usually have the source within a time frame of 2 weeks to a month >depending on my schedule at the time. > >If you would like me to give you a quote on recovering your source code >you can send me an email at: > >rcarlson "|AT|" @ skytekinc. "|DOT| " com <=====My correct email is >without the spaces and "|AT|" and "|DOT|" quotes above. This is to >prevent the spammers from getting my correct email by parsing the >messages on this board. > >Rod Carlson >Senior Hardware Engineer >Sky Tek Inc. > --------------------------------------- Posted through http://www.FPGARelated.comArticle: 145609
On Feb 14, 5:28=A0am, John_H <newsgr...@johnhandwork.com> wrote: > On Feb 14, 12:17=A0am, Patrick Maupin <pmau...@gmail.com> wrote: > > > On Feb 13, 6:21=A0pm, John_H <newsgr...@johnhandwork.com> wrote: > > > > The description comes out a little muddy which is why it took me a fe= w > > > days to buy in to the whole concept. =A0It's sweet! =A0It just takes = some > > > timing diagrams and head scratching. =A0And it's certainly not set up > > > for proper analysis especially in the Xilinx tools where I > > > experimented with the phase domain changes. > > > It's not just FPGA tools. =A0Many of the high-end chip tools don't > > support this very well, and to do it you need a PhD in the tool. > > The sad thing is it *shouldn't* be difficult. =A0For each stage of latch > traversed with an opposite clock edge, one more half cycle is added to > the overall timing spec for the path. =A0By analyzing up to each stage, > a logic delay short enough to change the input of a latch that's still > not transparent starts the timing path fresh from this intermediate > latch. > > It's such a "pretty" cascade of logic delays that I have to research > what you mean by "domino logic" to make sure we're not talking about > the same thing. =A0It truly would be simple to analyze, no PhD required. John_H, Read this paper first, then make your conclusion. "Timing Verification and Optimal Clocking of Synchronous Digital Circuits", published by 3 professors in University of Michigan in 1990, known as SMO algorithm. WengArticle: 145610
Hi, We talked about Intel's super-pipeline logic a few weeks ago, using latch to replace flip-flops. Now I found the paper: patent number: 5796282. http://scholar.google.com/scholar?q=5796282&hl=en&btnG=Search&as_sdt=2001&as_sdtp=on WengArticle: 145611
Hi, Recently I read Intel's a patent "Apparatus and a method for embedding dynamic state machines in a static environment". http://www.google.com/patents?hl=en&lr=&vid=USPAT5712826&id=yqIeAAAAEBAJ&oi=fnd&dq=5712826&printsec=abstract#v=onepage&q=&f=false It direct uses the first level of latches in a normally 2 levels of latches to do a dynamic state machine memory cell: storing information of last half clock and driving through it without output gate to control. Directly driving through the first level of latches without switching between two levels of latches. Really unbelievable ! WengArticle: 145612
In comp.arch.fpga Weng Tianxiang <wtxwtx@gmail.com> wrote: > Recently I read Intel's a patent "Apparatus and a method for embedding > dynamic state machines in a static environment". (snip) Many intel processors historically used dynamic logic, though without much explanation for what they actually did. The 8080 and 8086 have minimum clock rates to satisfy the dynamic logic in use. > Directly driving through the first level of latches without switching > between two levels of latches. Would that also require a minimum clock rate? Or clocking on both edges of a clock signal. The 8086, when clocked at maximum frequency, requires a 33% duty cycle clock. At lower frequencies that requirement isn't there. -- glenArticle: 145613
Hi Has anyone made use of the Differential Signaling Buffer ipcore in EDK??? I have read the pdf accompanying the ipcore and managed to add it properly. But I am confused as how to connect the output of this buffer to a custom fifo i have created. please help!!!! --------------------------------------- Posted through http://www.FPGARelated.comArticle: 145614
On Feb 15, 4:41=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > Many intel processors historically used dynamic logic, though > without much explanation for what they actually did. Someone at AMI published a book on PMOS logic design, which included good material on the principles of four-phase and two-phase dynamic PMOS logic. The same principles were generally applicable to NMOS. > The 8080 and 8086 have minimum clock rates to satisfy the > dynamic logic in use. As did the original 186/188, 286, and 386. In particular the original Intel 386 was dynamic even though it was CMOS; when AMD reverse- engineered it they reimplemented the logic as fully static for their 386. The drawback was that the fully static design required a larger die.Article: 145615
Hi my co-worker has a problem with EDK (used on w7, 32bit) OLD project can be built but any new projexcts created stop during implementation xilinx claims that the following table http://www.xilinx.com/ise/ossupport/index.htm is UPTODATE OS support list for Xilinx tools, in that table win7 is missing so what is wrong? is there something wrong with the installation, but hey why then old projects pass full flow? any ideas? AnttiArticle: 145616
>Hi > > Has anyone made use of the Differential Signaling Buffer ipcore in EDK??? >I have read the pdf accompanying the ipcore and managed to add it properly. >But I am confused as how to connect the output of this buffer to a custom >fifo i have created. > please help!!!! > >--------------------------------------- >Posted through http://www.FPGARelated.com > solved it!! --------------------------------------- Posted through http://www.FPGARelated.comArticle: 145617
Please help me I have really mess in my head with titles above. A have got custom processor that uses RAM which is created from Block RAMs. RAM is generated from CoreGen. I was initilizing BlockRAM's using .coe file. But it takes 'hours' to update code/data in .coe file and reimplement design. I wish to update data in .bit file without re-design. I found that there is a tool data2mem that do that for me. But it takes .bmm files and .mem files and this is problem for me...I don't know how to create files like this... I have seen syntax in .bmm files and I was quite scary for me... I'm FPGA beginner and can anybody tell me what to do in steps to create those .bmm files and .mem files. I was searching it for few hours and I don't catch this... Please help and thank you for any answer... Best Regards, Mac --------------------------------------- Posted through http://www.FPGARelated.comArticle: 145618
http://www.xilinx.com/itp/xilinx92/books/docs/d2m/d2m.pdf Read that. Then come back and ask questions. HTH, Syms.Article: 145619
First you should constrain the used BRAMs to fixed locations, so you don't have to recreate a new bmm file after each P&R run. Most probably, you will have to write the BMM file "by hand" (see the link posted by Symon, tell me if theres an automated way ;) The mem-file syntax is quite simple, but there are tools to create these mem files from binary files like srecord (srecord.sourceforge.net): $ srec_cat bram_content.bin -binary -o ram.mem -vmem 8 hth, HE de4 schrieb: > Please help me I have really mess in my head with titles above. > A have got custom processor that uses RAM which is created from Block > RAMs. > RAM is generated from CoreGen. I was initilizing BlockRAM's using .coe > file. > But it takes 'hours' to update code/data in .coe file and reimplement > design. > I wish to update data in .bit file without re-design. I found that there is > a tool data2mem that do that for me. But it takes .bmm files and .mem files > and this is problem for me...I don't know how to create files like this... > I have seen syntax in .bmm files and I was quite scary for me... > > I'm FPGA beginner and can anybody tell me what to do in steps to create > those .bmm files and .mem files. I was searching it for few hours and I > don't catch this... > > Please help and thank you for any answer... > Best Regards, > Mac > > > --------------------------------------- > Posted through http://www.FPGARelated.comArticle: 145620
On 2/16/2010 12:45 PM, he wrote: > First you should constrain the used BRAMs to fixed locations, so you > don't have to recreate a new bmm file after each P&R run. > Most probably, you will have to write the BMM file "by hand" (see the > link posted by Symon, tell me if theres an automated way ;) I dimly recall analysing the RBT format, and then writing a perl script that searched through the RBT file for a BRAM with contents beginning "DEADBEEF", or whatever I'd tagged the BRAM with, to automatically update the BMM after a PAR. However, as you point out, constraining the placement was much easier. Cheers, Syms.Article: 145621
>http://www.xilinx.com/itp/xilinx92/books/docs/d2m/d2m.pdf > >Read that. Then come back and ask questions. >HTH, Syms. > I read that before but It didn't give me much... I was thinking CoreGen generating RAM so probably map of this RAM can be generated also automatic. I see it can't. .mem file is not a problem I've got my assembler program so I will generate code in mem format but those .bmm are stupidness... Why it cant be generated by software ? I don't know what constarin placement is ? I have got something like that generated from CoreGen : LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off Library XilinxCoreLib; -- synthesis translate_on ENTITY BlockRAM4 IS port ( clka: IN std_logic; wea: IN std_logic_VECTOR(0 downto 0); addra: IN std_logic_VECTOR(10 downto 0); dina: IN std_logic_VECTOR(15 downto 0); douta: OUT std_logic_VECTOR(15 downto 0); clkb: IN std_logic; web: IN std_logic_VECTOR(0 downto 0); addrb: IN std_logic_VECTOR(10 downto 0); dinb: IN std_logic_VECTOR(15 downto 0); doutb: OUT std_logic_VECTOR(15 downto 0)); END BlockRAM4; ARCHITECTURE BlockRAM4_a OF BlockRAM4 IS -- synthesis translate_off component wrapped_BlockRAM4 port ( clka: IN std_logic; wea: IN std_logic_VECTOR(0 downto 0); addra: IN std_logic_VECTOR(10 downto 0); dina: IN std_logic_VECTOR(15 downto 0); douta: OUT std_logic_VECTOR(15 downto 0); clkb: IN std_logic; web: IN std_logic_VECTOR(0 downto 0); addrb: IN std_logic_VECTOR(10 downto 0); dinb: IN std_logic_VECTOR(15 downto 0); doutb: OUT std_logic_VECTOR(15 downto 0)); end component; -- Configuration specification for all : wrapped_BlockRAM4 use entity XilinxCoreLib.blk_mem_gen_v3_2(behavioral) generic map( c_has_regceb => 0, c_has_regcea => 0, c_mem_type => 2, c_rstram_b => 0, c_rstram_a => 0, c_has_injecterr => 0, c_rst_type => "SYNC", c_prim_type => 1, c_read_width_b => 16, c_initb_val => "0", c_family => "spartan3", c_read_width_a => 16, c_disable_warn_bhv_coll => 0, c_write_mode_b => "WRITE_FIRST", c_init_file_name => "no_coe_file_loaded", c_write_mode_a => "WRITE_FIRST", c_mux_pipeline_stages => 0, c_has_mem_output_regs_b => 0, c_has_mem_output_regs_a => 0, c_load_init_file => 0, c_xdevicefamily => "spartan3a", c_write_depth_b => 2048, c_write_depth_a => 2048, c_has_rstb => 0, c_has_rsta => 0, c_has_mux_output_regs_b => 0, c_inita_val => "0", c_has_mux_output_regs_a => 0, c_addra_width => 11, c_addrb_width => 11, c_default_data => "0", c_use_ecc => 0, c_algorithm => 1, c_disable_warn_bhv_range => 0, c_write_width_b => 16, c_write_width_a => 16, c_read_depth_b => 2048, c_read_depth_a => 2048, c_byte_size => 9, c_sim_collision_check => "ALL", c_common_clk => 0, c_wea_width => 1, c_has_enb => 0, c_web_width => 1, c_has_ena => 0, c_use_byte_web => 0, c_use_byte_wea => 0, c_rst_priority_b => "CE", c_rst_priority_a => "CE", c_use_default_data => 0); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_BlockRAM4 port map ( clka => clka, wea => wea, addra => addra, dina => dina, douta => douta, clkb => clkb, web => web, addrb => addrb, dinb => dinb, doutb => doutb); -- synthesis translate_on END BlockRAM4_a; how I can create some .bmm from this ? I know that those things are simple for exprets but I not an expert... Thanks for aswers... --------------------------------------- Posted through http://www.FPGARelated.comArticle: 145622
> I read that before but It didn't give me much... I was thinking CoreGen > generating RAM so probably map of this RAM can be generated also automatic. > I see it can't. .mem file is not a problem I've got my assembler program so > I will generate code in mem format but those .bmm are stupidness... Why it > cant be generated by software ? I don't know what constarin placement is ? Look up the number and names of your BRAMs in your routed design, for example with fpga_editor or Planahead. You can pin these BRAMs to fixed locations with the approprate entries in your ucf file. This is an example ucf entry for 4 BRAMs used in 8 bit mode in parallel: ---8<---- ## BRAM location constraints INST "BRAM/blockram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[3].ram.r/v4_init.ram/SP.SINGLE_PRIM.SP" LOC = "RAMB16_X3Y1"; INST "BRAM/blockram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/v4_init.ram/SP.SINGLE_PRIM.SP" LOC = "RAMB16_X3Y0"; INST "BRAM/blockram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/v4_init.ram/SP.SINGLE_PRIM.SP" LOC = "RAMB16_X4Y1"; INST "BRAM/blockram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v4_init.ram/SP.SINGLE_PRIM.SP" LOC = "RAMB16_X4Y0"; ---8<---- you have to insert the approprate names/paths for your design... > how I can create some .bmm from this ? write it by hand, the commands are described in the data2mem user guide. This is an example for the four BRAMs shown above: ---8<---- ADDRESS_MAP mymap PPC405 0 ADDRESS_SPACE BRAM COMBINED INDEX_ADDRESSING[0x00000000:0x00001FFF] ADDRESS_RANGE RAMB16 BUS_BLOCK wb_arbiter/BRAM/BU2/U0/blk_mem_generator/valid.cstr/ramloop[3].ram.r/v4_init.ram/SP.SINGLE_PRIM.SP [31:24] PLACED=X5Y1; wb_arbiter/BRAM/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/v4_init.ram/SP.SINGLE_PRIM.SP [23:16] PLACED=X5Y0; wb_arbiter/BRAM/BU2/U0/blk_mem_generator/valid.cstr/ramloop[1].ram.r/v4_init.ram/SP.SINGLE_PRIM.SP [15:8] PLACED=X4Y1; wb_arbiter/BRAM/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v4_init.ram/SP.SINGLE_PRIM.SP [7:0] PLACED=X4Y0; END_BUS_BLOCK; END_ADDRESS_RANGE; END_ADDRESS_SPACE; END_ADDRESS_MAP; ---8<---- now you can use data2mem to show or change the BRAM contents via $ data2mem -bm brams.bmm -bt yourbitfile.bit > log.txt $ data2mem -bm brams.bmm -bt yourbitfile.bit -bd ram_content.mem -o -b bitfile_with_new_contents.bit hth HEArticle: 145623
On 2/15/2010 10:08 PM, msegura wrote: > Hi, I'm workng with MGT as GT_CUSTOM. > I use the MGT for transmiting to pulses of .66ns(1/15Ghg). > I check all the delays with FPGA editor and all was ok, but I mesure the > pulses at the SATA conector and there are a delay between SATA0 and SATA1 > of 500ps. What are these two signals? Where do they connect to your FPGA? Syms.Article: 145624
Thank you very much, You helped me really a lot... They should write it in datasheet as you said that. Thanks again and I going now to fight with this Best regards, maciek --------------------------------------- Posted through http://www.FPGARelated.com
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