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Messages from 145700

Article: 145700
Subject: Re: System design in FPGA
From: Magne Munkejord <magnemunk@yahoo.no>
Date: Fri, 19 Feb 2010 13:43:21 +0100
Links: << >>  << T >>  << A >>
RCIngham wrote:
>> Hi all,
>>
>> I am a budding FPGA designer and I am in the process of designing
>> first system. Until now I have partitioned my system into various
>> entities, each entity implementing a small part of the system. It is
>> also easier for implementation. However I have found myself in routing
>> a lot of signals from one entity to another which increases complexity
>> in a way.
>>
>> The other option is implement the system in a single entity and a
>> number of process. This would simplify matters because I would not
>> need to route lots signals between one  entity and another. The
>> disadvantage is a lack of clarity.
>>
>> What is the best way for implementation? Any ideas and suggestions
>> would be welcome.
>>
>> Thanks very much,
>>
>> Regards,
>>
>> Joseph
>>
> 
> Part of the "art" of system design is structuring and organizing the
> hierarchy in a near-optimal way. Don't expect to get it right the first
> time that you do it. Do aspire to get better with subsequent projects.
> 
> HTH!
> 	   
> 					
> ---------------------------------------		
> Posted through http://www.FPGARelated.com
Hi,

the one-entity option seems like a step in the wrong direction. Try to 
have a look at your design again, see if you can identify data paths and 
controls signals. Drawing sketches on a piece of paper usually helps.

Article: 145701
Subject: Re: using an FPGA to emulate a vintage computer
From: jmfbahciv <jmfbahciv@aol>
Date: Fri, 19 Feb 2010 09:10:23 -0500
Links: << >>  << T >>  << A >>
Abby Brown wrote:
> "Eric Chomko" <pne.chomko@comcast.net> wrote in message 
> news:badc12c3-cb2b-4ce9-9543-237d60fc22d5@o8g2000vbm.googlegroups.com...
>> Has anyone created a copy machine of an old system using an 
>> FPGA? I
>> was wondering if it would be possible to take an entire SWTPC 
>> 6800 and
>> compile the schematics and have it run on an FPGA board.? 
>> Wouldn't
>> even have to be the latest Xylinx product, I suspect.
> 
> Absolutely.  There a number of them.  This guy has done a PDP-4 
> and PDP-8,
> 
>     http://homepage.mac.com/dgcx/pdp4x/
> 
>     http://homepage.mac.com/dgcx/pdp4x/
> 
> I am in the process of doing a PDP-1.  My  background is high 
> performance computers so it is a high performance design. 
> Todays FPGAs and CAD allow a much more agressive implementation 
> than the original designers could afford and with far less 
> effort.  The original PDP-1s sold for about $100K in early 
> 1960s' dollars.  Mine will cost only a few hundred dollars to 
> build.
> 
> Those interested in the subject might also be interested in the 
> simh group,
> 
>     http://simh.trailing-edge.com/
> 
> which does simulators for legacy computers.

Re your background is high performance, what do you like best
about the PDP-1?  (Or haven't you got that far?)

/BAH

Article: 145702
Subject: Re: System design in FPGA
From: Curt Johnson <curt.johnson@dicombox.net>
Date: Fri, 19 Feb 2010 07:37:33 -0800
Links: << >>  << T >>  << A >>
jozamm wrote:
> Hi all,
> 
> I am a budding FPGA designer and I am in the process of designing
> first system. Until now I have partitioned my system into various
> entities, each entity implementing a small part of the system. It is
> also easier for implementation. However I have found myself in routing
> a lot of signals from one entity to another which increases complexity
> in a way.
> 
> The other option is implement the system in a single entity and a
> number of process. This would simplify matters because I would not
> need to route lots signals between one  entity and another. The
> disadvantage is a lack of clarity.
> 
> What is the best way for implementation? Any ideas and suggestions
> would be welcome.
> 
> Thanks very much,
> 
> Regards,
> 
> Joseph

Grouping signals into records can reduce the pain of routing signals 
between entities.

Curt

Article: 145703
Subject: Re: rocketio TX delay between sata0 and sata1
From: Marcelo <user@compgroups.net/>
Date: Fri, 19 Feb 2010 13:58:25 -0600
Links: << >>  << T >>  << A >>
Ed, 
So you told me that its no posible to sent two bits using diferent MGT with the same delay?
But how work the comm systems that use several paralle channels?
I'll check the datasheet for my virtex2p.
Marcelo

---
frmsrcurl: http://compgroups.net/comp.arch.fpga/rocketio-TX-delay-between-sata0-and-sata1

Article: 145704
Subject: Re: System design in FPGA
From: Mike Treseler <mtreseler@gmail.com>
Date: Fri, 19 Feb 2010 12:29:48 -0800
Links: << >>  << T >>  << A >>
jozamm wrote:

> I am a budding FPGA designer and I am in the process of designing
> first system. Until now I have partitioned my system into various
> entities, each entity implementing a small part of the system. It is
> also easier for implementation. However I have found myself in routing
> a lot of signals from one entity to another which increases complexity
> in a way.

I like big modules/entities because HDLs give me leverage
inside the box, but little leverage wiring boxes together.

If all else is equal,
Architectures that need the same signal   want to be merged.
Processes     that need the same variable want to be merged.

For me, the modules/entity size is limited by the unit test.

 -- Mike Treseler

Article: 145705
Subject: Re: Unpredictable design
From: "de4" <de4@n_o_s_p_a_m.poczta.onet.pl>
Date: Fri, 19 Feb 2010 15:59:52 -0600
Links: << >>  << T >>  << A >>
>Also
>
>http://www.xilinx.com/support/documentation/white_papers/wp272.pdf
>

I read those documents and I stared to looking at does resets.
I've changed all D flip flops. Now they are reset synch. because asynch.
reset is a bad practice. In document wp272 I read that I don't need global
reset at all. But I notice two things.

1. When I reconfigure FPGA and don't touch anything on a board procesor
executes program wrongly. When executing is finished and I resert procesor
it executes program in good way.

2. When I reconfigure FPGA and I will hold reset button until download
process will be finished and I will realase button it executes good also.

Where can be a problem ? Should I use some GSR net ? I heard it is not good
solution also... If I should what is best practise ? Or maybe some setting
in CoreGen (ram) are bad - I don't use any EN oraz RST pins in my
design...

Thank you for any response.

Regards,
Maciek



	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 145706
Subject: Re: System design in FPGA
From: rickman <gnuarm@gmail.com>
Date: Fri, 19 Feb 2010 14:04:44 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 19, 5:50=A0am, jozamm <joz...@gmail.com> wrote:
> Hi all,
>
> I am a budding FPGA designer and I am in the process of designing
> first system. Until now I have partitioned my system into various
> entities, each entity implementing a small part of the system. It is
> also easier for implementation. However I have found myself in routing
> a lot of signals from one entity to another which increases complexity
> in a way.
>
> The other option is implement the system in a single entity and a
> number of process. This would simplify matters because I would not
> need to route lots signals between one =A0entity and another. The
> disadvantage is a lack of clarity.
>
> What is the best way for implementation? Any ideas and suggestions
> would be welcome.
>
> Thanks very much,
>
> Regards,
>
> Joseph

I see entities as being a unit I will want to test independently.
Many designers don't test each entity, but I find that to be the most
productive use of my time.  I partition my entities to minimize the
number of I/O while preserving a logical grouping of signaling.  At
the lowest level, there are times I will have an entity of only 20
lines or so.  Other times a low level entity will have 400 lines of
code.  I don't like making such large entities, but there are times
when it is just too awkward to partition a portion of a design.  That
may be a sign that I am not be thinking of the problem the right way,
other times it may just be too hard to do better and I need to get on
with it.

The easy way to stitch your modules together is to use your tools
testbench generator to create the boiler place code for you.  You can
then copy and paste much of the code into your higher level entity and
just touch up the formatting.  By testing your entities before
integrating them minimizes the rework in higher level modules of
keeping the stitching updated as the interfaces change.

Rick

Article: 145707
Subject: Re: rocketio TX delay between sata0 and sata1
From: Muzaffer Kal <kal@dspia.com>
Date: Fri, 19 Feb 2010 20:06:28 -0800
Links: << >>  << T >>  << A >>
On Fri, 19 Feb 2010 13:58:25 -0600, Marcelo <user@compgroups.net/>
wrote:

>Ed, 
>So you told me that its no posible to sent two bits using diferent MGT with the same delay?
>But how work the comm systems that use several paralle channels?

Inter-lane skew is handled in the controller during training. Transmit
skew is not the only cause of skew, channel (cable or pcb) and
receivers also contribute to it too. It's much easier to manage it in
digital domain after data recovery than to try to make perfect
channels.
-- 
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

Article: 145708
Subject: Re: System design in FPGA
From: jozamm <jozamm@gmail.com>
Date: Sat, 20 Feb 2010 01:44:23 -0800 (PST)
Links: << >>  << T >>  << A >>
On 19 Feb, 23:04, rickman <gnu...@gmail.com> wrote:
> On Feb 19, 5:50=A0am, jozamm <joz...@gmail.com> wrote:
>
>
>
>
>
> > Hi all,
>
> > I am a budding FPGA designer and I am in the process of designing
> > first system. Until now I have partitioned my system into various
> > entities, each entity implementing a small part of the system. It is
> > also easier for implementation. However I have found myself in routing
> > a lot of signals from one entity to another which increases complexity
> > in a way.
>
> > The other option is implement the system in a single entity and a
> > number of process. This would simplify matters because I would not
> > need to route lots signals between one =A0entity and another. The
> > disadvantage is a lack of clarity.
>
> > What is the best way for implementation? Any ideas and suggestions
> > would be welcome.
>
> > Thanks very much,
>
> > Regards,
>
> > Joseph
>
> I see entities as being a unit I will want to test independently.
> Many designers don't test each entity, but I find that to be the most
> productive use of my time. =A0I partition my entities to minimize the
> number of I/O while preserving a logical grouping of signaling. =A0At
> the lowest level, there are times I will have an entity of only 20
> lines or so. =A0Other times a low level entity will have 400 lines of
> code. =A0I don't like making such large entities, but there are times
> when it is just too awkward to partition a portion of a design. =A0That
> may be a sign that I am not be thinking of the problem the right way,
> other times it may just be too hard to do better and I need to get on
> with it.
>
> The easy way to stitch your modules together is to use your tools
> testbench generator to create the boiler place code for you. =A0You can
> then copy and paste much of the code into your higher level entity and
> just touch up the formatting. =A0By testing your entities before
> integrating them minimizes the rework in higher level modules of
> keeping the stitching updated as the interfaces change.
>
> Rick

Hi all,

Thanks very much for your ideas and suggestions.

Someone pointed out using using records to transfer signals from one
entity to another. While this is a good idea, will synthesis tools
like Xilinx accept a record of STD_LOGIC or STD_LOGIC_VECTOR in the
description of an entity?

Thanks again,

Regards,

Joseph

Article: 145709
Subject: how to read bmp file in vhdl
From: suni <sunitaraul5@gmail.com>
Date: Sat, 20 Feb 2010 06:47:43 -0800 (PST)
Links: << >>  << T >>  << A >>
helo
 i am in B.E.-E&TC,doing project on DIGITAL WATER MARKING TECH.. I
need to convert matlab code in to vhdl for downloading,if not then how
to read bmp file in vhdl?..Can u please help me out..

Article: 145710
Subject: Re: System design in FPGA
From: Petter Gustad <newsmailcomp6@gustad.com>
Date: Sat, 20 Feb 2010 17:24:04 +0100
Links: << >>  << T >>  << A >>
Curt Johnson <curt.johnson@dicombox.net> writes:

> Grouping signals into records can reduce the pain of routing signals
> between entities.

Or interfaces if you're using SystemVerilog. Interfaces can carry
signals which run in both directions. VHDL records can only carry
signals running in a single direction.

Petter
-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 145711
Subject: Re: System design in FPGA
From: Petter Gustad <newsmailcomp6@gustad.com>
Date: Sat, 20 Feb 2010 17:24:52 +0100
Links: << >>  << T >>  << A >>
jozamm <jozamm@gmail.com> writes:

> entity to another. While this is a good idea, will synthesis tools
> like Xilinx accept a record of STD_LOGIC or STD_LOGIC_VECTOR in the

I don't know about xst, but it works in Quartus.

Petter
-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 145712
Subject: Re: BRAM16 error
From: Gabor <gabor@alacron.com>
Date: Sat, 20 Feb 2010 09:06:45 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 19, 5:24=A0am, "bh.ines1...@gmail.com" <bh.ines1...@gmail.com>
wrote:
> On Feb 18, 7:48=A0pm, austin <aus...@xilinx.com> wrote:
>
> > Gabor,
>
> > Using BRAM blocks as 'look up tables' for logic is a way to pack more
> > "stuff" into the design, so, yes, the BRAMs are only "unused" until
> > you then use them for this purpose (the English language is probably
> > one of the worst languages for describing technical stuff, except for
> > all the others).
>
> > That is a fairly arcane use of the BRAM blocks, and it would be
> > interesting to know how often folks do this,
>
> > Austin
>
> Hi,
> Thank you (Austin and Gabor) for the answers.
> But is this error caused by the fact that the application software is
> big enough? I dont' think so cause the soft application is very
> simple, it just light the 8 LEDs.
> Also in the MHS file I put 16k for DLMB and 16k for the ILMB too!
> So I couldn'tt understand where the problem lies: in the design in
> hard or soft implementation!!
> I will be thankfull if you give me some help!!
>
> Best Regards,
> Ines

Block RAMs on Spartan 3 are 18Kb where "b" means bits.  For
16KB, where "B" means bytes, you need 8 BRAMs.  Your memory
for the MicroBlaze would therefore need 16 BRAMs.  Add to that
any additional BRAMs you might use, for example FIFO's and
MIG cores.  So the question is:

How many BRAM devices does your FPGA have?
How many BRAM's are shown in the Map report?
How many BRAM's from the Map report are not accounted for?

Regards,
Gabor

PS to Austin:
  Arcane or not, the tools are supposed to be able to use extra
BRAM's for stuffing extra logic.  I believe it is a bug if the
tools overmap BRAM's when I have no means to tell the tools
how many of the BRAM's it can use for logic.  It doesn't seem
like rocket science for the tools to first allow for any
explicitly required BRAM's in the design before mapping logic
into the remaining "unused" ones.

Article: 145713
Subject: Re: rocketio TX delay between sata0 and sata1
From: Symon <symon_brewer@hotmail.com>
Date: Sat, 20 Feb 2010 17:21:29 +0000
Links: << >>  << T >>  << A >>
On 2/19/2010 7:58 PM, Marcelo wrote:
> Ed,
> So you told me that its no posible to sent two bits using diferent MGT with the same delay?
> But how work the comm systems that use several paralle channels?

http://en.wikipedia.org/wiki/XAUI

Article: 145714
Subject: Re: Unpredictable design
From: Symon <symon_brewer@hotmail.com>
Date: Sat, 20 Feb 2010 17:25:28 +0000
Links: << >>  << T >>  << A >>
On 2/19/2010 9:59 PM, de4 wrote:
>
> 1. When I reconfigure FPGA and don't touch anything on a board procesor
> executes program wrongly. When executing is finished and I resert procesor
> it executes program in good way.
>
> 2. When I reconfigure FPGA and I will hold reset button until download
> process will be finished and I will realase button it executes good also.
>
> Where can be a problem ? Should I use some GSR net ? I heard it is not good
> solution also... If I should what is best practise ? Or maybe some setting
> in CoreGen (ram) are bad - I don't use any EN oraz RST pins in my
> design...
>
Hi Maciek,
It sounds as though some state machine in your design is set to the 
proper initial conditions when the FPGA is loaded. You should be able to 
find this with simulation.
HTH., Syms.

Article: 145715
Subject: Re: Unpredictable design
From: -jg <jim.granville@gmail.com>
Date: Sat, 20 Feb 2010 14:55:54 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 20, 10:59=A0am, "de4" <de4@n_o_s_p_a_m.poczta.onet.pl> wrote:
> 1. When I reconfigure FPGA and don't touch anything on a board procesor
> executes program wrongly. When executing is finished and I resert proceso=
r
> it executes program in good way.
>
> 2. When I reconfigure FPGA and I will hold reset button until download
> process will be finished and I will realase button it executes good also.

 That sounds like your Reset, and the Config-Exit are not quite the
same thing.

 Most uC have a POR exit State-timer, that asserts reset for a few
cycles. (Some may also delay reasonable times to allow Xtal Osc
startup etc )

 So rather than hope config-exit duplicates your reset, why not try
the add of small logic that generates a signal you OR into your reset-
button path ?

Article: 145716
Subject: Legal syntax for VHDL expression
From: rickman <gnuarm@gmail.com>
Date: Sat, 20 Feb 2010 17:53:38 -0800 (PST)
Links: << >>  << T >>  << A >>
I am writing a case statement and it doesn't seem to like an attribute
as a selection expression.  Is an attribute not a legal item in an
expression?

It flags an error at the "of" on the first line saying 'keyword "is"
expected'
and at the beginning of the last line shown here saying 'keyword "end"
expected'

	  case LFSRReg'high of
		when 2 =>
		  Feedback := Feedback xor LFSRReg(2);
		  Feedback := Feedback xor LFSRReg(1);
		when 3 =>

I seem to get rusty on VHDL between projects, but I thought I knew how
to construct a case statement.  Am I just getting old?

Rick

Article: 145717
Subject: Re: System design in FPGA
From: rickman <gnuarm@gmail.com>
Date: Sat, 20 Feb 2010 17:56:26 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 20, 4:44=A0am, jozamm <joz...@gmail.com> wrote:
> On 19 Feb, 23:04, rickman <gnu...@gmail.com> wrote:
>
>
>
> > On Feb 19, 5:50=A0am, jozamm <joz...@gmail.com> wrote:
>
> > > Hi all,
>
> > > I am a budding FPGA designer and I am in the process of designing
> > > first system. Until now I have partitioned my system into various
> > > entities, each entity implementing a small part of the system. It is
> > > also easier for implementation. However I have found myself in routin=
g
> > > a lot of signals from one entity to another which increases complexit=
y
> > > in a way.
>
> > > The other option is implement the system in a single entity and a
> > > number of process. This would simplify matters because I would not
> > > need to route lots signals between one =A0entity and another. The
> > > disadvantage is a lack of clarity.
>
> > > What is the best way for implementation? Any ideas and suggestions
> > > would be welcome.
>
> > > Thanks very much,
>
> > > Regards,
>
> > > Joseph
>
> > I see entities as being a unit I will want to test independently.
> > Many designers don't test each entity, but I find that to be the most
> > productive use of my time. =A0I partition my entities to minimize the
> > number of I/O while preserving a logical grouping of signaling. =A0At
> > the lowest level, there are times I will have an entity of only 20
> > lines or so. =A0Other times a low level entity will have 400 lines of
> > code. =A0I don't like making such large entities, but there are times
> > when it is just too awkward to partition a portion of a design. =A0That
> > may be a sign that I am not be thinking of the problem the right way,
> > other times it may just be too hard to do better and I need to get on
> > with it.
>
> > The easy way to stitch your modules together is to use your tools
> > testbench generator to create the boiler place code for you. =A0You can
> > then copy and paste much of the code into your higher level entity and
> > just touch up the formatting. =A0By testing your entities before
> > integrating them minimizes the rework in higher level modules of
> > keeping the stitching updated as the interfaces change.
>
> > Rick
>
> Hi all,
>
> Thanks very much for your ideas and suggestions.
>
> Someone pointed out using using records to transfer signals from one
> entity to another. While this is a good idea, will synthesis tools
> like Xilinx accept a record of STD_LOGIC or STD_LOGIC_VECTOR in the
> description of an entity?
>
> Thanks again,
>
> Regards,
>
> Joseph

Is a record really a solution?  You then have to declare the record
which is as much work as entering the entity port list and you have to
do a lot of typing to use the record.  Why not try a -small- example
to see if that really suits you.  then you can experiment to verify
that it all works like you want it to.

Rick

Article: 145718
Subject: Re: Legal syntax for VHDL expression
From: Alan Fitch <apf@invalid.invalid>
Date: Sun, 21 Feb 2010 01:57:07 +0000
Links: << >>  << T >>  << A >>
On 21/02/10 01:53, rickman wrote:
> I am writing a case statement and it doesn't seem to like an attribute
> as a selection expression.  Is an attribute not a legal item in an
> expression?
> 
> It flags an error at the "of" on the first line saying 'keyword "is"
> expected'
> and at the beginning of the last line shown here saying 'keyword "end"
> expected'
> 
> 	  case LFSRReg'high of
> 		when 2 =>
> 		  Feedback := Feedback xor LFSRReg(2);
> 		  Feedback := Feedback xor LFSRReg(1);
> 		when 3 =>
> 
> I seem to get rusty on VHDL between projects, but I thought I knew how
> to construct a case statement.  Am I just getting old?
> 
> Rick

The syntax is
  case expression is

so replace "of" by "is",

regards
Alan

-- 
Alan Fitch

Article: 145719
Subject: Re: Unpredictable design
From: rickman <gnuarm@gmail.com>
Date: Sat, 20 Feb 2010 18:03:39 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 19, 4:59=A0pm, "de4" <de4@n_o_s_p_a_m.poczta.onet.pl> wrote:
> >Also
>
> >http://www.xilinx.com/support/documentation/white_papers/wp272.pdf
>
> I read those documents and I stared to looking at does resets.
> I've changed all D flip flops. Now they are reset synch. because asynch.
> reset is a bad practice. In document wp272 I read that I don't need globa=
l
> reset at all. But I notice two things.
>
> 1. When I reconfigure FPGA and don't touch anything on a board procesor
> executes program wrongly. When executing is finished and I resert proceso=
r
> it executes program in good way.
>
> 2. When I reconfigure FPGA and I will hold reset button until download
> process will be finished and I will realase button it executes good also.
>
> Where can be a problem ? Should I use some GSR net ? I heard it is not go=
od
> solution also... If I should what is best practise ? Or maybe some settin=
g
> in CoreGen (ram) are bad - I don't use any EN oraz RST pins in my
> design...

It sounds to me like your reset is not being asserted when you
reconfigure.  I think Symon meant to say your initial conditions are
*not* being set when you configure the device.

Personally, I have no trouble using the async reset.  I just make sure
all of my logic is capable of either starting correctly on an async
reset (like adding a short shift register to qualify the reset) or
verifying that the logic is waiting for some external event to start
or even for it to "recover" if started badly like a state machine.

Rick

Article: 145720
Subject: Re: Legal syntax for VHDL expression
From: rickman <gnuarm@gmail.com>
Date: Sat, 20 Feb 2010 18:07:22 -0800 (PST)
Links: << >>  << T >>  << A >>
On Feb 20, 8:57=A0pm, Alan Fitch <a...@invalid.invalid> wrote:
> On 21/02/10 01:53, rickman wrote:
>
>
>
> > I am writing a case statement and it doesn't seem to like an attribute
> > as a selection expression. =A0Is an attribute not a legal item in an
> > expression?
>
> > It flags an error at the "of" on the first line saying 'keyword "is"
> > expected'
> > and at the beginning of the last line shown here saying 'keyword "end"
> > expected'
>
> > =A0 =A0 =A0case LFSRReg'high of
> > =A0 =A0 =A0 =A0 =A0 =A0when 2 =3D>
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0Feedback :=3D Feedback xor LFSRReg(2);
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0Feedback :=3D Feedback xor LFSRReg(1);
> > =A0 =A0 =A0 =A0 =A0 =A0when 3 =3D>
>
> > I seem to get rusty on VHDL between projects, but I thought I knew how
> > to construct a case statement. =A0Am I just getting old?
>
> > Rick
>
> The syntax is
> =A0 case expression is
>
> so replace "of" by "is",
>
> regards
> Alan
>
> --
> Alan Fitch

Maybe I am working to hard.  I even looked at a reference guide
several times and kept reading "of" instead of "is"...  If I'm not
getting old, I guess I'm at least getting tired!

Thanks a lot for the *really* fast reply!

Rick

Article: 145721
Subject: Question about altera root-port for Stratix4GX Hard IP
From: Test01 <cpandya@yahoo.com>
Date: Sat, 20 Feb 2010 18:51:38 -0800 (PST)
Links: << >>  << T >>  << A >>
I have a question about Altera Stratix4GX PCIe Hard IP root port
question.  As per my understanding, the back end of the root-port
supports Avalon ST Bus thorugh which I can feed TLPs to pass
transactions downstream using the Hard IP root port.  Is it possible
to put it in a mode where all the transactions are passed on
downstream - even the PCI conig cycles?

Article: 145722
Subject: Quartus II IDE freezing on Arch 64
From: bizarrefish <leeguy92@googlemail.com>
Date: Sat, 20 Feb 2010 19:52:10 -0800 (PST)
Links: << >>  << T >>  << A >>
Hello, all.
I just got quartus II linux web edition operational on my Arch64
lappy. This involved installing a bunch of libraries, tweaking my /etc/
issue file to correct something that altera was getting upset about,
and LD_PRELOADing a library or two.
All a lot of messing around, but it ended up actually working. JTAG n
all.

Unfortunately, just several days ago, it started to fail. When viewing
certain files, in the built-in text editor, it would freeze up.
The only way to un-freeze is to attach to quartus with gdb, and return
from the current function with null by providing the command "return
(void*)0".
The function that it's trapped in is LexerModule::find(int),
apparently part of scintilla.
I have only seen one other mention of this specific issue, and that's
here: http://www.mail-archive.com/scintilla-interest@lyra.org/msg02093.html
No help there, i can't modify the function that quartus uses, because
they have it as part of a proprietary shared object.

Is there any kind of workaround for this, or am I at the mercy of
altera to come out with a fix?

Lee.
Any help here would be great.

Article: 145723
Subject: State machines in Quartus
From: Giorgos Tzampanakis <gt67@hw.ac.uk>
Date: Sun, 21 Feb 2010 04:34:00 +0000 (UTC)
Links: << >>  << T >>  << A >>
I'm trying to get Quartus to recognize my state machines. I'm 
using version 9.0. I tried generating a state machine using the 
State Machine Wizard, but after compiling, if I try to look at it 
with the State Machine Viewer I get "This design has no State 
Machine." I tried to copy the Verilog code from the Help file, 
and I still get the same problem.

Is it possible to get Quartus to understand my state machines?

Article: 145724
Subject: Re: System design in FPGA
From: Thomas Stanka <usenet_nospam_valid@stanka-web.de>
Date: Sun, 21 Feb 2010 01:08:40 -0800 (PST)
Links: << >>  << T >>  << A >>
> Someone pointed out using using records to transfer signals from one
> entity to another. While this is a good idea, will synthesis tools
> like Xilinx accept a record of STD_LOGIC or STD_LOGIC_VECTOR in the
> description of an entity?

Each serious synthesis tool accepts records. Unfortunately some of the
common used tools tend to replace a record by a vector after synthesis
which makes debugging in netlist simulation a pain. Better tools
synthesis to names like record.entry1 and record.entry2.

bye Thomas



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