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On Dec 5, 11:11=A0am, emeb <ebromba...@gmail.com> wrote: > I just came across a couple of old Avnet eval boards for the Xilinx > XC3VP7. Part number is ADS-XLX-V2PRO-EVLP7-5 and there's a product > brief here: > > http://www.em.avnet.com/ctf_shared/evk/df2df2usa/Xilinx_Virtex-II_Pro... > > I'd like to find a schematic, or at least an I/O pin mapping for this > board, but Avnet seems to have removed all the design materials from > their site. Can anyone help? > > Thanks > > Eric Nevermind - I found the documentation on the Avnet DRC. Now I just need to think of what to do with all these boards (I got a whole box full of them for $20)Article: 144426
On 5 Dez., 16:08, "ines_fr" <benhlima_i...@yahoo.fr> wrote:
> I am using spartan 3 Starter Board, and I want to know if it supports
> multiprocessor architecture or not?
Sure - if you can find a processor core small enough to fit on the
rather
small Spartan 3 on the Starter Board. A good starting point might be
the ZPU - this is a space-optimized (and, thus, comparatively slow)
stack
machine (32 bit, with gcc toolchain support) we are using to build
experimental manycore systems (up to nearly 100 cores on a Virtex 5
XUP
board...). Some smallers 8-bit cores (like the picoblaze) may also
work for you.
Information on the ZPU can be found at:
http://opencores.org/project,zpu and
http://opensource.zylin.com/zpu.htm
Of course, you'll have to design some communication method, otherwise
the multicore system on your FPGA won't be much fun :-).
Best wishes,
Michael
Article: 144427> I'd strongly suggest reading and following the guidelines I outlined Kevin Jennings, THANK YOU for all your input! I have finally found the error and it was a coding error. It wasn't READY after all, although READY was involved. There are some regs in the FPGA that both master and slave CPUs can access. Master has access when READY='1'. Input to those regs are ADDRESS and DATA so I have this MUXes: REGADDR <= MASTER_ADDR when READY='1' else SLAVE_ADDR; REGDATA <= MASTER_DATA when READY='1' else SLAVE_DATA; Sometimes, there was a write to those regs at the exact point in time when READY changes which resulted in selecting random regs and random data.Article: 144428
I have some code you can use. But you didn't say what you need. Master or Slave? Multiple addresses? What FPGA or development board? VHDL or Verilog?Article: 144429
> Did you use the architecture wizard (or CoreGen) to "create" > your DCM? This method has a habit of adding the input pin > buffer, which you obviously don't want if the input to the > DCM comes from an internal signal. Thank you very much: Yes, I use the wizard and there is a checkbox if the clkin source is internal or external. But after a change of this checkbox it is necessary to make a little change in the source code. A view to the intantiation template is helpful. Mathias.Article: 144430
Anyone have TCP/IP offload (TOE) core in FPGA or design experience? plz mail: arcdoos@yahoo.comArticle: 144431
Hi, Thank you for the reply, I want to start with a small example for Core 2 processors in spartan 3, because I am beginner in this area, and I have a little knowledge on multiprocessor architectures! So if you know where I can find a tutorial that can helps me, please give the link! INES --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144432
kendor wrote: > hello there > > for a measuring utility (running @ 100MHZ) I need a counter of 42-bit width > whose value is used by several sub blocks of my design. As a first, somehow > dirty solution I have implemented this like follows. Since this approach > needs quite a huge amount of FFs and leads to long delaytimes (bit 0 to 42) > I am looking for an alternative. I was thinking about using Block RAM > (Spartan3) to reduce routing effort and delaytimes. (see also > http://courses.ece.illinois.edu/ece412/References/datasheets/xapp463.pdf) > > Has anyone ever done such a thing or do you have any suggestions on solving > my task? > <snip> > > thank you in advance > > kendor > Do you need a binary output? Before carry chains, I used linear feedback shift registers for wide counters and converted to result to binary in software. CurtArticle: 144433
I would use the DSP48 circuit. It easily runs at well over 100 MHz in Spartan6 and much faster in Virtex 5 and 6. No need for pre-scaling or fancy carry tricks. It's all done for you! Look at the short description in the Spartan 6 User Guide Lite: "Each DSP48A1 slice consists of a dedicated 18 - 18 bit two's complement multiplier and a 48-bit accumulator, both capable of operating at 250 MHz. The DSP48A1 slice provides extensive pipelining and extension capabilities that enhance speed and efficiency of many applications, even beyond digital signal processing, such as wide dynamic bus shifters, memory address generators, wide bus multiplexers, and memory-mapped I/O register files. The accumulator can also be used as a synchronous up/down counter. " Peter AlfkeArticle: 144434
I hope your comment on the declaration of WD is not what you really wanted... Also, en='0' disables the cnt increment, but not the prescaler (temp), which will lead to problems if en is disabled at the wrong time or for long enough. Depending on how much latency you can tolerate (other posts regarding register retiming/rebalancing), you may want to register the output of the prescaler comparison, so that it's logic path does not add to the counter path. AndyArticle: 144435
On Nov 30, 8:24=A0am, Antti <antti.luk...@googlemail.com> wrote: > On Nov 30, 5:55=A0pm, ASPENLOGIC <use...@aspenlogic.com> wrote: > > > I've started a new ASIC Prototyping group on LinkedIn. To join, search > > for "ASIC Prototyping" in the groups directory. > > 1 reason todo so is: <insert here why> ? A little snotty Antti. I have joined. You are welcome to ignore.Article: 144436
ni wrote:
> Is there any application note which explains this stuff?
> I am more interested in optimizing bram usage for my architecture.
I use a vhdl or verilog block ram template for the size I want,
run synthesis, and look at the block ram utilization.
-- Mike Treseler
Article: 144437On Dec 7, 12:48=A0pm, Mike Treseler <mtrese...@gmail.com> wrote: > ni wrote: > > Is there any application note which explains this stuff? > > I am more interested in optimizing bram usage for my architecture. > > I use a vhdl or verilog block ram template for the size I want, > run synthesis, and look at the block ram utilization. > > =A0 =A0 =A0 =A0 -- Mike Treseler Running synthesis, translate, map, etc. is how I found out about these quirks of architecture, but if you dig deep into the User Guide (not the datasheet) you'll find this information. Unfortunately the datasheet / user guide approach almost always overloads you with so much information you're bound to miss something that could be a showstopper for a board-level design completed before the guts of the FPGA are designed. In a similar Virtex II design I found out I couldn't use all of my DQ lines for a DDR SDRAM because of clock routing limitations to adjacent IOB's. This was before MIG was around to help you find workable pinouts up front. I had paired some DQ pins with DQS pins and run out of clock routes because of the DDR routing being shared with the adjacent IOB of a pair. So my 64-bit wide SO-DIMM became a 59-bit wide memory. The lesson seems to be that if all possible get a workable design going in the FPGA before board layout. Regards, GaborArticle: 144438
Hi,
I'm trying to implement a 10-bit rotating priority encoder. The two
inputs are a 10-bit valid vector and a 4-bit index indicating which
input has the highest priority. The output is a 10-bit 1-hot vector
where the position of the 1 corresponds to the highest priority input
that is also valid;
For example, for in_valid = 10'b0000111101:
priority = 1 => out_select = 10'b0000000100
priority = 6 => out_select = 10'b0000000001
My implementation consists of two rotate shifters and a simple
priority encoder. The Verilog code is attached at the end of this
message.
My questions are related to the resource utilization of this design.
I'm using ISE 10.1.03 and targeting an XC2VP30-6ff896 device. When
synthesized independently, I got the following LUT counts for the
modules:
10-bit rotate_shift_left: 45 4LUTs
10-bit rotate_shift_right: 43 4LUTs
10-bit 1-in-11 priority encoder: 12 4LUTs
First question: I expect the overall cost of the rotating priority
encoder to be 45 + 43 + 12 = 100 4LUTs because it is a simple cascade
of the three sub-modules. But in reality XST reports 106 4LUTs. I
can't figure out what the 6 extra LUTs are for. This result is
obtained using the default XST settings, where KEEP_HIERARCHY is set
to NO. Forcing KEEP_HIERARCHY to YES results in 99 total 4LUTs, which
is more inline with my original estimate. Am I just missing something
obvious?
The second question is related to the logic cost of the shifters. From
the XST numbers it seems that they are probably not implemented using
10-bit 10-to-1 MUXes (which would use about 50 4LUTs) . How are they
actually implemented and how should I estimate their area cost?
I appreciate any help.
Danyao
------------------------------------------------------------
Verilog code:
module rotate_prio (in_valid, prio, out_sel);
input [ 9: 0] in_valid;
input [ 3: 0] prio;
output [ 9: 0] out_sel;
wire [ 9: 0] w_norm_valid; // "Normalized" valid vector
wire [ 9: 0] w_norm_sel;
// Sub modules are used so that I can independently synthesize
each module and get resource numbers
rotate_shift_right sr (.in(in_valid), .offset(prio), .out
(w_norm_valid));
prio_encoder enc (.in_valid(w_norm_valid), .out_sel(w_norm_sel));
rotate_shift_left sl (.in(w_norm_sel), .offset(prio), .out
(out_sel));
endmodule
module rotate_shift_left (in, offset, out);
input [ 9: 0] in;
input [ 3: 0] offset;
output [ 9: 0] out;
wire [ 9: 0] temp;
assign {out, temp} = {in, in} << offset;
endmodule
module rotate_shift_right (in, offset, out);
input [ 9: 0] in;
input [ 3: 0] offset;
output [ 9: 0] out;
wire [ 9: 0] temp;
assign {temp, out} = {in, in} >> offset;
endmodule
module prio_encoder (in_valid, out_sel);
input [ 9: 0] in_valid;
output reg [ 9: 0] out_sel;
always @(*)
begin
if (in_valid[0]) out_sel = 10'h001;
else if (in_valid[1]) out_sel = 10'h002;
else if (in_valid[2]) out_sel = 10'h004;
else if (in_valid[3]) out_sel = 10'h008;
else if (in_valid[4]) out_sel = 10'h010;
else if (in_valid[5]) out_sel = 10'h020;
else if (in_valid[6]) out_sel = 10'h040;
else if (in_valid[7]) out_sel = 10'h080;
else if (in_valid[8]) out_sel = 10'h100;
else if (in_valid[9]) out_sel = 10'h200;
else out_sel = 10'h000;
end
endmodule
Article: 144439>I have some code you can use. >But you didn't say what you need. >Master or Slave? Multiple addresses? >What FPGA or development board? >VHDL or Verilog? Hi, I want to use the core in Master mode, one slave address (although it's easy to make this programmable). I'm more after the sate machine that would take care of the 'byte level' transfer and make it look more like macro I2C transaction. Verilog ideally, but I can deal with both. It's on an FPGA. Thanks for the help. Diego --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144440
On 7 Dez., 18:43, mike_la_jolla <md...@dinigroup.com> wrote: > On Nov 30, 8:24=A0am, Antti <antti.luk...@googlemail.com> wrote: > > > On Nov 30, 5:55=A0pm, ASPENLOGIC <use...@aspenlogic.com> wrote: > > > > I've started a new ASIC Prototyping group on LinkedIn. To join, searc= h > > > for "ASIC Prototyping" in the groups directory. > > > 1 reason todo so is: <insert here why> ? > > A little snotty Antti. =A0I have joined. =A0You are welcome to ignore. Atti is right, as long as we have these newsgroups there is less reason to divide attention in different places on several forums and social networks instead of focusing on one and spam some advertising in all other places. Especially as usenet has the advantage of beeing complete independend which allows employees of vendors to write here in a much easier way I guess. regards ThomasArticle: 144441
Hello there, I got a project about medical electronics and here's a problem bother me a lot. I need a delay module that can delay the input signal from 10ns to 0.1s. I know i can achieve the ns level delay by using registers and ms level delay by using a counter, but how can i make the transition between them smoothly? Thanks FrankArticle: 144442
hello everybody; Please is there anyone who know how to make 2 cores of processors on the MicroBlaze using the XPS Mutex core?? Please, if anyone have information, give it me because I'm stuck!!!!! INES --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144443
"FarseeR" <ystyle2004@gmail.com> wrote in message news:9f1eed0b-f420-40f3-8572-0daf339eba70@v15g2000prn.googlegroups.com... > Hello there, > > I got a project about medical electronics and here's a problem bother > me a lot. I need a delay module that can delay the input signal from > 10ns to 0.1s. I know i can achieve the ns level delay by using > registers and ms level delay by using a counter, but how can i make > the transition between them smoothly? You need to decide the delay resolution you need. If you need 10ns steps all the way to 0.1s, you need 1E-1/1E-9=1E8 memory cells and you may configure the memory with input and output ring counter with an offset depending on your wanted delay. You also need to investigate what will happen when you change delay factor. Do you accept: -a copy of last delayed when you increase delay? (you will get the pattern you just had over again) -skip some data when reducing the delay? -Maybe you want to delete the content of the stored data when changing the delay?Article: 144444
On Dec 7, 7:19=A0pm, Danyao <danyao.w...@gmail.com> wrote: > Hi, > > I'm trying to implement a 10-bit rotating priority encoder. The two > inputs are a 10-bit valid vector and a 4-bit index indicating which > input has the highest priority. The output is a 10-bit 1-hot vector > where the position of the 1 corresponds to the highest priority input > that is also valid; > > For example, for in_valid =3D 10'b0000111101: > priority =3D 1 =3D> out_select =3D 10'b0000000100 > priority =3D 6 =3D> out_select =3D 10'b0000000001 > > My implementation consists of two rotate shifters and a simple > priority encoder. The Verilog code is attached at the end of this > message. > > My questions are related to the resource utilization of this design. > I'm using ISE 10.1.03 and targeting an XC2VP30-6ff896 device. When > synthesized independently, I got the following LUT counts for the > modules: > > 10-bit rotate_shift_left: 45 4LUTs > 10-bit rotate_shift_right: 43 4LUTs > 10-bit 1-in-11 priority encoder: 12 4LUTs > > First question: I expect the overall cost of the rotating priority > encoder to be 45 + 43 + 12 =3D 100 4LUTs because it is a simple cascade > of the three sub-modules. But in reality XST reports 106 4LUTs. I > can't figure out what the 6 extra LUTs are for. This result is > obtained using the default XST settings, where KEEP_HIERARCHY is set > to NO. Forcing KEEP_HIERARCHY to YES results in 99 total 4LUTs, which > is more inline with my original estimate. Am I just missing something > obvious? > > The second question is related to the logic cost of the shifters. From > the XST numbers it seems that they are probably not implemented using > 10-bit 10-to-1 MUXes (which would use about 50 4LUTs) . How are they > actually implemented and how should I estimate their area cost? > > I appreciate any help. > > Danyao > [snip] I'm not sure why you need to know these details unless you're either doing this as a research project or you need to use a whole pile of these. In any case one of the best ways to answer your questions is to take a look at the "Technology Schematic" after synthesis to see what XST did with your logic. My best guess on question 1 is that when flattening the design, XST tried to merge the shift and encode functions into fewer logic levels and ended up using more LUT's as a result of that. Regards, GaborArticle: 144445
I am having problems reading from the Ethernet PHY chip on both my custom board and on the Xilinx ml403 board, both of which use the same part (Marvell 88E1111) and design. Background: For our custom board, the Ethernet PHY chip incorrectly detects and enables its crossover feature approximately 50% of the time. The solution is to disable this feature, as we have no need for it. However, to do so, I must read and write to the PHY registers. Using EDK 11.3i, I can indeed correctly read and write these registers, and implement a software fix. However, this is an old design, and the project is in the "end game". Therefore, there is much resistance to changing the EDK version at this late stage; everything else works, there are a number of custom IP that would need to be updated, and of course, drivers would need to be updated or re- written. So, I've tried the same approach with our existing 9.1i tools, but reading and writing works sporadically. The easiest example of the problem are the two PHY ID registers (2 and 3), that should always return the values $0141 and $0cc2 respectively, and that for the 9.1i version, they are both read incorrectly the first time, and then correctly the second time! Specifically, I read 0x0000 and 0x0400 the first time (both incorrect), and later, read 0x0141 and 0x0cc2 (both correct). There are other examples, but this is the most obvious. Note that this occurs even when building a design for the ml403, using the Base System Builder. I'm thinking some constraints might be needed on the signals of the V4/ PHY interface, but I don't know how to specify them. Has anyone an example or a reference to guide me? Or am I missing something else? Thanks, -BobArticle: 144446
On Dec 8, 4:58=A0am, "ines_fr" <benhlima_i...@yahoo.fr> wrote: > hello everybody; > Please is there anyone who know how to make 2 cores of processors on the > MicroBlaze using the XPS Mutex core?? > Please, if anyone have information, give it me because I'm stuck!!!!! > > INES =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > This message was sent using the comp.arch.fpga web interface onhttp://www= .FPGARelated.com At first glance, it would appear that you didn't really look all that hard for an answer. Take a look at page 3: <http://www.xilinx.com/support/documentation/ application_notes/xapp996.pdf> ALArticle: 144447
Hi everyone, I updated to ISE 11.3 recently and I noticed that memory consumption for xst.exe during synthesis is really high (more than 2.5 gigs for me). I use vista professional 64-bit. Memory usage is so high that I can't use any other application (I have 3 gigs in all). Plus synthesis seems slower, so is it possible that there is some kind of memory leak? Am I the only one that has this problem? Best regardsArticle: 144448
I have this working in both 8.2 and 10.3. I've never tried 9.1. I suspect however that this is a software porblem. Make sure that PHY is not being reset when you try to read it the first time. If that's not the case perhaps the MDIO interface is not reset properly before the first read... If the behaviour consistent you could just ignore the first read as a simple workaround. /Mikhail "Bob" <rsg.uclinux@gmail.com> wrote in message news:bd19585a-98ee-461f-a18f-8389ba0d3b67@p30g2000vbt.googlegroups.com... >I am having problems reading from the Ethernet PHY chip on both my > custom board and on the Xilinx ml403 board, both of which use the same > part (Marvell 88E1111) and design. > > Background: For our custom board, the Ethernet PHY chip incorrectly > detects and enables its crossover feature approximately 50% of the > time. The solution is to disable this feature, as we have no need for > it. However, to do so, I must read and write to the PHY registers. > > Using EDK 11.3i, I can indeed correctly read and write these > registers, and implement a software fix. However, this is an old > design, and the project is in the "end game". Therefore, there is > much resistance to changing the EDK version at this late stage; > everything else works, there are a number of custom IP that would need > to be updated, and of course, drivers would need to be updated or re- > written. So, I've tried the same approach with our existing 9.1i > tools, but reading and writing works sporadically. > > The easiest example of the problem are the two PHY ID registers (2 and > 3), that should always return the values $0141 and $0cc2 respectively, > and that for the 9.1i version, they are both read incorrectly the > first time, and then correctly the second time! Specifically, I read > 0x0000 and 0x0400 the first time (both incorrect), and later, read > 0x0141 and 0x0cc2 (both correct). There are other examples, but this > is the most obvious. > > Note that this occurs even when building a design for the ml403, using > the Base System Builder. > > I'm thinking some constraints might be needed on the signals of the V4/ > PHY interface, but I don't know how to specify them. Has anyone an > example or a reference to guide me? Or am I missing something else? > > Thanks, > -BobArticle: 144449
I had a webcase on this issue. My design failed in Win32 but synthesized fine in 64-bit Linux. Supposedly the problem was fixed in 11.4, which is now available for download. It is a huge download as usual, so it won't be until tomorrow when I can try if it actually works. /Mikhail "Benjamin Couillard" <benjamin.couillard@gmail.com> wrote in message news:cb32d393-d872-47dd-9a7a-84a086442217@m3g2000yqf.googlegroups.com... > Hi everyone, > > I updated to ISE 11.3 recently and I noticed that memory consumption > for xst.exe during synthesis is really high (more than 2.5 gigs for > me). I use vista professional 64-bit. Memory usage is so high that I > can't use any other application (I have 3 gigs in all). Plus synthesis > seems slower, so is it possible that there is some kind of memory > leak? Am I the only one that has this problem? > > Best regards
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