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On Nov 18, 11:12=A0pm, timinganalyzer <timinganaly...@gmail.com> wrote: > Hi All, > > The latest version of the program is beta version 0.945. =A0Python > scripting, =A0improved GUI zooming, and logic function simulations have > been the focus in the 0.94X series > > An application note on the website shows how to automatically generate > timing diagrams directly from vhdl. Using file I/O from VHDL or any > RTL, =A0you output text files that are python scripts that the > TimingAnalyzer executes to build timing diagrams from simulations. > One use is automatically generating 100s of timing of timing diagrams > from simulations for documentation purposes. > > Also, =A0I hope you know that the program is now freeWare so this is not > a marketing or sales message but just a message to keep others in our > business informed about new features. =A0As always, =A0user feedback is > welcome and your opinions and suggestions are shaping the look and > feel of the program. > > You can see a list of all the changes athttp://www.timing-diagrams.com/do= kuwiki/doku.php?id=3Ddownload > > Thank you, > Dan Fabriziowww.timing-diagrams.com Very cool. Please give another post when the Verilog example is available. Regards, GaborArticle: 144201
On Nov 19, 8:38=A0am, Adam G=F3rski <totutousungors...@malpawp.pl> wrote: > Test01 pisze: > > > > > > > For Altera Straix4 GX FPGA, Is there a bridge module available > > between > > the Avalon-ST to Avalon-MM? =A0Trying to use the PCIE endpoint hard IP > > using Altera Megawizard software. =A0But this interface generates the > > Avalon streaming output. I think for what I am doing I do not need > > very high performance bus and Avalon-MM may work. =A0Avalon MM is much > > simpler bus =A0The thing is that the PCIE endpoint interface needs to > > be > > connected to several modules with other users trying to design. =A0It > > may be much easier in multi-user environment to use the Avalon-MM bus > > then to use the Avalon-ST bus. This is why I was just curious if > > there > > is Avalon-ST to Avalon-MM bus bridge? =A0This way the endpoint can use > > the Avalon-ST bus but then bridge will have Avalon-MM interface which > > will allow numerous devices to be on that bus. > > > I understand that SOPC flow provides this capability but here is what > > I am looking for from the PCIe endpoint Verilog module. > > > - Needs to be verilog module that I can instantiate and synthesize in > > my Top verilog file. =A0It seems to be generating the verilog output > > but > > it also has a lot other things in that file I may not need. =A0The > > verilog output also has some stuff related to simulation. =A0I guess it > > is OK to start removing the stuff form this file if I do not need it. > > For example I may not need the DMA controller module. > > - Only contains PCIe endpoint that has Avelon-MM interface on the the > > backside. It will be good to not have other modules. > > - I use VCS to simulate and Synplify for synthesis. I am not sure how > > well it fits in this flow. =A0I am sure this is documented somewhere > > but > > it is taking some time for me to dig through the information. > > > Any suggestions? > > http://www.altera.com/literature/hb/nios2/qts_qii55013.pdf?GSA_pos=3D2&..= . > > Adam- Hide quoted text - > > - Show quoted text - Thanks for giving the information. It seems that I still need to use the SOPC flow to generate this. Is there Avalon-ST to Avalon-MM bridge Verilog module somewhere that can use?Article: 144202
Hi, Somebody know where can I found a free IP core for Bluetooth or Wifi? I would like to use it. I don't mind use a USB or UART module. Best.Article: 144203
>> It seems to me that a fast float to ASCII conversion function would be a >> common function of many embedded systems. Rather than me reinventing the >> wheel, can anyone point me to a resource (example on the web or a product >> for sale) that I can use to achieve my goal? > Which NIOS version are you using ? > How fast it should be ? > CPU freq ? It's Nios2. We selected the standard core but can pick the fast core if necessary. The core will be clocked at 80 MHz. I need to be able to convert from float to string in about 25% of the time to process a single measurement at 10 KHz. That is, 100 usec times 25% or 25 usec. JJSArticle: 144204
John Speth <johnspeth@yahoo.com> wrote: > It's Nios2. We selected the standard core but can pick the fast core if > necessary. The core will be clocked at 80 MHz. I need to be able to > convert from float to string in about 25% of the time to process a single > measurement at 10 KHz. That is, 100 usec times 25% or 25 usec. Are all allowable floating point values possible in your case, or a reduced set? If the set is reduced, it might be that a simple routine will get out the needed value. -- glenArticle: 144205
sa, http://en.wikipedia.org/wiki/Noisy-channel_coding_theorem Is a good place to start for an overview. It took me roughly 1 year of graduate studies, after my 4 years as an undergraduate, to "master" communications theory. I think that is typical... If you have no background in communications theory, I suggest you start by reading Shannon's two papers: 1. A Mathematical Theory of Communication 2. Communication in the presence of noise Starting there, it should probably take you less than two years to get to the latest codes (Shannon's limits apply to the best possible coding, but there is no known way to derive, or construct a best possible code - other than trial and error), and no more than another year to understand MIMO systems ... and so on. Once you think you know something, design and build communications system, and plot the Eb/No, and see if it matches what you designed. If you get that far, you probably know enough to be very dangerous. http://en.wikipedia.org/wiki/Eb/N0 AustinArticle: 144206
On Nov 17, 8:10=A0pm, d_s_klein <d_s_kl...@yahoo.com> wrote: > On Nov 14, 3:18=A0pm, Michael S <already5cho...@yahoo.com> wrote: > > > > > > > Hi > > We have a problem with Altera Stratix IV GX FPGA Development Kit. > > Specifically, we build a PCI Express design based on Altera's own > > "hard" PCI-E core configured for Gen.1 x4 operation. The design works > > (more or less, but that's behind the scope of this message) when it is > > plugged into x8 mechanical/x4 electrical slot. However when plugged in > > x8 or x16 mechanical slots which are electrically x8 the design not > > only doesn't work but not even recognized by the host as valid PCI-E > > device. Exactly the same happens when we are trying to build x1 > > device. > > We validated (by plugging off-the-shelf x1 and x4 PCI-E cards) that > > it's not a host issue. > > My only PCI-E book (Mindshare "PCI Express System Architecture") tells > > virtually nothing about width negotiation so right now I am totally > > lost. > > > Any ideas to help? I talked to two of our PCIe experts, and they suggested checking three things: The DIP switch that controls how many lanes are supported via the PCIe connector presence detect settings could be set wrong. It is SW5 on the board, see table 2-15 in the board reference manual http://www.altera.com/literature/manual/rm_sivgx_fpga_dev_board.pdf. If it is an Intel motherboard in some cases they send out Vendor Defined messages. The customer=92s application design needs to be designed to ignore these messages (unless the customer is Intel then their application might need to know what these messages are and do the right thing). If the application design doesn=92t accept these messages from the core it will lock things up and cause configuration problems. If you have Engineering Sample (not production) silicon, it could be a case of the Stratix IV GX ES erratum entitled =93Endpoints Using the Hard IP Implementation Incorrectly Handle CfgRd0=94 as described in the IP Release notes: http://www.altera.com/literature/rn/rn_ip.pdf. Workaround for this is to use production devices or use soft IP (v9.0 or later) on ES devices. Hope this helps, Vaughn Betz Altera [v b e t z (at) altera.com]Article: 144207
On Nov 19, 10:25=A0am, Test01 <cpan...@yahoo.com> wrote: > > Thanks for giving the information. =A0It seems that I still need to use > the SOPC flow to generate this. =A0Is there Avalon-ST to Avalon-MM > bridge Verilog module somewhere that can use?- Hide quoted text - > The streaming transfer and memory mapped interfaces are logically almost the same, they name the signals differently though. The places where they are truly different represent things that don't map when trying to convert an ST to an MM protocol. The basic concepts in the protocols are: - In ST is that data transfers of occur between a 'source' and a 'sink'; in MM it is 'master' and 'slave'. - In ST data always goes from a source to a sink; in MM data can go in either direction. A 'write' command moves data from master to source; a 'read' command moves data from source to master. Given that, under certain scenarios, you can view an ST source as being logically the same as an MM slave; an ST sink as being logically the same as an MM master. In those scenarios, the 'ST to MM bridge' would simply consist of the following trivial logic which presumably you could write yourself and add it as a wrapper around the core. MM Signal Equivalent ST signal =3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D read ready waitrequest not(valid) or... waitrequest_n valid readdata data So now the question is what are the scenarios where this works? The key signals that ST has that MM doesn't are 'endofpacket' and 'channel'. If your system will always have either fixed size packets or the slave/source can be queried to determine the packet size then might not have a need for the 'endofpacket' signal to flag the end of a data transfer. If your slave/source has only a point to point connection to a single master/sink then you won't have a need for the 'channel'. There are a whole bunch of other signals that an ST interface could potentially have, per figure 6-1 in the Avlon Interface Specification. Basically any signal that is defined in that table as having a direction of 'source to sink' other than the 'data' and 'valid' signals are problems because there is no MM equivalent to work with. Whether those signals are required depends on your particular application and use of that interface and it may also depend on how the core you'd like to use is designed. The fact that there are these potentially problem signals means that you can't construct a generic ST to MM convertor without customizing the 'data' signal. To do this, one would start by constructing a data record that consists of the various other signals that go from source to sink (i.e. 'channel', 'error', 'startofpacket', 'endofpacket' and 'empty'). The ST to MM convertor would then simply append these signals with the ST data in order to make it be the MM readdata. Now the MM master receives a wider 'readdata' input that includes not only the ST 'data' but all of the other ST status signals. The one clinker in the above is the 'channel' signal. The ST 'channel' signal is the equivalent of an MM 'address' signal. The problem comes in that MM 'address' is generated by an MM master, not a slave. So if you need the capability provided by the channel signal, then your ST source will now need to become an MM master, rather than an MM slave. This isn't necessarily difficult it just means that the mapping of signals is different. Again the logic is rather trivial MM Signal Equivalent ST signal =3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D write valid waitrequest not(ready) writedata data It would also be possible to do the same trick with expanding ST data with the other ST status signals to widen the MM writedata that I described earlier. In fact, because of the lack of a suitable MM slave equivalent to the ST 'channel' signal it would likely be best that the ST to MM convertor be written so that the MM side is a master and not a slave. The last clinker will come in if your other Avalon devices require byte enables and data resizing. That's gets a bit more complex (but not impossible) then I want to go into here...suffice it to say that the resizing of data busses would best be accomplished as a separate module that then could get instantiated within your ST to MM convertor. No matter how you cut it, the logic to implement the ST to MM bridge is not at all difficult to come up with. Now that I've walked you through the basic steps for creating the convertor, the real question is why? ST data transfers are fundamentally nearly the same as MM. In some ways it is easier to grasp, I'm not getting how you think it is harder than MM and how any designer would have trouble with ST but not MM...makes no sense to me. But in any case, you should have enough info now to construct a bridge between the two protocols.. Good luck. Kevin JenningsArticle: 144208
On Oct 28, 5:05=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > On Oct 28, 8:27=A0am, LucienZ <lucien.zh...@gmail.com> wrote: > > > > > > > Dear all, > > > Has anyone ordered and used the ML605 Evaluation Kit?http://www.xilinx.= com/products/devkits/EK-V6-ML605-G.htm > > I noticed some attractive features like DDR3, PCIe Gen 2 and quite > > high FPGA capacity (241,152 logic cells). Before my ordering I would > > like to hear some comments. > > > Another feature of this board is the adoption of the FMC interfaces. > > This is a new face to me, but it looks quite promising. However I have > > a concern about it: if I just want to interface some simple IO devices > > (e.g. a LCD panel and some push buttons), does that mean I still have > > to do the PCB layout for them with a FMC connection (previously it > > could be solved just by some IO pin headers)? > > > I also do not quite understand the pricing, I notice that the > > XC6VLX240T-1FFG1156CES chip itself costs about $2,100, but the fledged > > ML506 Kit only takes $1,995. Is this just a marketing scheme or there > > are some other reasons? > > > Thanks very much for your time! > > Lucien > > Yes, the features do make it a pretty cool board. :-) > > The main board already has push buttons, LEDS and a LCD so you are > covered there. If you do want add on additional peripherals then yes, > you will need to design a board as it isn't practical to attach wires > to the FMC connectors. > > Xilinx will/should be releasing a FMC that is primarily intending for > simple debug and is comprised of a series of 100 mil headers that are > connected to the FMC connector. =A0This board could also be used for > prototyping purposes. > > Ed McGettigan > -- > Xilinx Inc.- Hide quoted text - > > - Show quoted text - This board is now available for sale. http://www.xilinx.com/products/devkits/HW-FMC-DBG-G.htm it should be sold under the HW-FMC-105-DEBUG-G part number, I'm not sure what happened along the way. Ed McGettigan -- Xilinx Inc.Article: 144209
On Nov 20, 6:40=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > On Oct 28, 5:05=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > > > > On Oct 28, 8:27=A0am, LucienZ <lucien.zh...@gmail.com> wrote: > > > > Dear all, > > > > Has anyone ordered and used the ML605 Evaluation Kit?http://www.xilin= x.com/products/devkits/EK-V6-ML605-G.htm > > > I noticed some attractive features like DDR3, PCIe Gen 2 and quite > > > high FPGA capacity (241,152 logic cells). Before my ordering I would > > > like to hear some comments. > > > > Another feature of this board is the adoption of the FMC interfaces. > > > This is a new face to me, but it looks quite promising. However I hav= e > > > a concern about it: if I just want to interface some simple IO device= s > > > (e.g. a LCD panel and some push buttons), does that mean I still have > > > to do the PCB layout for them with a FMC connection (previously it > > > could be solved just by some IO pin headers)? > > > > I also do not quite understand the pricing, I notice that the > > > XC6VLX240T-1FFG1156CES chip itself costs about $2,100, but the fledge= d > > > ML506 Kit only takes $1,995. Is this just a marketing scheme or there > > > are some other reasons? > > > > Thanks very much for your time! > > > Lucien > > > Yes, the features do make it a pretty cool board. :-) > > > The main board already has push buttons, LEDS and a LCD so you are > > covered there. If you do want add on additional peripherals then yes, > > you will need to design a board as it isn't practical to attach wires > > to the FMC connectors. > > > Xilinx will/should be releasing a FMC that is primarily intending for > > simple debug and is comprised of a series of 100 mil headers that are > > connected to the FMC connector. =A0This board could also be used for > > prototyping purposes. > > > Ed McGettigan > > -- > > Xilinx Inc.- Hide quoted text - > > > - Show quoted text - > > This board is now available for sale.http://www.xilinx.com/products/devki= ts/HW-FMC-DBG-G.htmit should be > sold under the HW-FMC-105-DEBUG-G part number, I'm not sure what > happened along the way. > > Ed McGettigan > -- > Xilinx Inc. super! 159$ for simplest connector brreakout board this is more than many lower cost FPGA boards cost. but this is Xilinx marketing. AnttiArticle: 144210
I think I found a chip for the job. It even has jtag drivers available. http://www.ftdichip.com/Products/FT4232H.htmArticle: 144211
On Nov 20, 12:22=A0pm, "Morten Leikvoll" <mleik...@yahoo.nospam> wrote: > I think I found a chip for the job. It even has jtag drivers available.ht= tp://www.ftdichip.com/Products/FT4232H.htm ah :) well you did not say what you needed sure the FT2232H/FT4232H would download at super speed over USB if that is all you need, can just use ftdi jtag dll hm did not read original posting, original usb blaster can not run at very high speeds because of protocol overhead and FS only, ok, the usb blaster could be done using FT2232H too, but the current HDL code for blaster would have to be modified to speed up (most the blaster implementations read out the FTDI fifo tooslowly) AnttiArticle: 144212
John Speth pisze: >>> It seems to me that a fast float to ASCII conversion function would be a >>> common function of many embedded systems. Rather than me reinventing the >>> wheel, can anyone point me to a resource (example on the web or a product >>> for sale) that I can use to achieve my goal? > >> Which NIOS version are you using ? >> How fast it should be ? >> CPU freq ? > > It's Nios2. We selected the standard core but can pick the fast core if > necessary. The core will be clocked at 80 MHz. I need to be able to > convert from float to string in about 25% of the time to process a single > measurement at 10 KHz. That is, 100 usec times 25% or 25 usec. > > JJS > > What kind of output you are using ? What you are using to measure coputation time ? Could you put testing code here ? I can verify your project if you want. AdamArticle: 144213
A new white paper from Xilinx talks about migrating designs to the new Spartan 6 series. http://fpgajournal.net/fpgajournal/ondemand/20091119-01-xilinx/ There are some architecture changes in this family that could affect designs that use extended set/reset functionality of the current Spartan 3 and older generations: Asynchronous set and reset of the same flip-flop Asynchronous set with initialization to 0 Asynchronous reset with initialization to 1 Apparently adding more flip-flops to a slice has reduced the routing resources for set/reset functionality to each flip-flop. Regards, GaborArticle: 144214
On Nov 20, 5:40=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > On Oct 28, 5:05=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > > On Oct 28, 8:27=A0am, LucienZ <lucien.zh...@gmail.com> wrote: > > > > Dear all, > > > > Has anyone ordered and used the ML605 Evaluation Kit?http://www.xilin= x.com/products/devkits/EK-V6-ML605-G.htm > > > I noticed some attractive features like DDR3, PCIe Gen 2 and quite > > > high FPGA capacity (241,152 logic cells). Before my ordering I would > > > like to hear some comments. > > > > Another feature of this board is the adoption of the FMC interfaces. > > > This is a new face to me, but it looks quite promising. However I hav= e > > > a concern about it: if I just want to interface some simple IO device= s > > > (e.g. a LCD panel and some push buttons), does that mean I still have > > > to do the PCB layout for them with a FMC connection (previously it > > > could be solved just by some IO pin headers)? > > > > I also do not quite understand the pricing, I notice that the > > > XC6VLX240T-1FFG1156CES chip itself costs about $2,100, but the fledge= d > > > ML506 Kit only takes $1,995. Is this just a marketing scheme or there > > > are some other reasons? > > > > Thanks very much for your time! > > > Lucien > > > Yes, the features do make it a pretty cool board. :-) > > > The main board already has push buttons, LEDS and a LCD so you are > > covered there. If you do want add on additional peripherals then yes, > > you will need to design a board as it isn't practical to attach wires > > to the FMC connectors. > > > Xilinx will/should be releasing a FMC that is primarily intending for > > simple debug and is comprised of a series of 100 mil headers that are > > connected to the FMC connector. =A0This board could also be used for > > prototyping purposes. > > > Ed McGettigan > > -- > > Xilinx Inc.- Hide quoted text - > > > - Show quoted text - > > This board is now available for sale.http://www.xilinx.com/products/devki= ts/HW-FMC-DBG-G.htmit should be > sold under the HW-FMC-105-DEBUG-G part number, I'm not sure what > happened along the way. > > Ed McGettigan > -- > Xilinx Inc. Nice! Thank you Ed!Article: 144215
On Nov 17, 1:14 pm, Mike Treseler <mtrese...@gmail.com> wrote:
> maxascent wrote:
> > Try looking in the synthesis report to see how that
> > input is being synthesized.
>
> Yes, a coding errorcangive an unexpectedclockinput.
>
> -- Mike Treseler
I ended up updating the peripheral (removing from design, adding it
again), which removed the previous error, but now there is the
following (my custom peripheral is event_counter_0 which has 7
exterior ports on it:
ERROR:Place:864 - Incompatible IOB's are locked to the same bank 9
Conflicting IO Standards are:
IO Standard 1: Name = LVCMOS25, VREF = NR, VCCO = 2.50, TERM = NONE
List of locked IOB's:
event_counter_0_pixels_in_pin<6>
IO Standard 2: Name = LVCMOS33, VREF = NR, VCCO = 3.30, TERM = NONE
List of locked IOB's:
fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0>
fpga_0_SRAM_Mem_A_pin<7>
fpga_0_SRAM_Mem_A_pin<8>
These IO Standards are incompatible due to VCCO mismatch.
So, in an attempt to grasp what was going on here, I commented out the
corresponding port in the .ucf file and now I get:
WARNING:MapLib:701 - Signal event_counter_0_pixels_in_pin<4> connected
to top
level port event_counter_0_pixels_in_pin<4> has been removed.
WARNING:MapLib:701 - Signal event_counter_0_pixels_in_pin<5> connected
to top
level port event_counter_0_pixels_in_pin<5> has been removed.
and the original problem rears its head once more, now with a friend:
ERROR:Place:645 - A clock IOB clock component is not placed at an
optimal clock
IOB site. The clock IOB component
<event_counter_0_pixels_in_pin<0>> is
placed at site <E7>. The clock IO site can use the fast path
between the IO
and the Clock buffer/GCLK if the IOB is placed in the master Clock
IOB Site.
If this sub optimal condition is acceptable for this design, you
may use the
CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this
message to a
WARNING and allow your design to continue. However, the use of this
override
is highly discouraged as it may lead to very poor timing results.
It is
recommended that this error condition be corrected in the design. A
list of
all the COMP.PINs used in this clock placement rule is listed
below. These
examples can be used directly in the .ucf file to override this
clock rule.
< NET "event_counter_0_pixels_in_pin<0>" CLOCK_DEDICATED_ROUTE =
FALSE; >
WARNING:Place:971 - A GCLK / GCLK clock component pair have been found
that are
not placed at an optimal GCLK / GCLK site pair. The GCLK component
<clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/
Using_BUFG_for_CLKF
X.CLKFX_BUFG_INST> is placed at site <BUFGCTRL_X0Y4>. The
corresponding GCLK
component
<Soft_TEMAC/Soft_TEMAC/SOFT_SYS.I_TEMAC/GMII0.I_CLOCK_INST_0/
V6V5V4S6.BUFGMUX
_SPEED_CLK> is placed at site <BUFGCTRL_X0Y22>. The GCLK site can
use the
fast path to the other GCLK if both the GCLK components are placed
in the
same half of the device (TOP or BOTTOM). You may want to analyze
why this
problem exists and correct it. This is not an error so processing
will
continue.
---
My peripheral is simple:
CHECK_PIXELS: process (Bus2IP_Clk)
begin -- process
if pin_in(0) = '1' then
pixel_0 <= pixel_0 + '1';
end if;
if pin_in(1) = '1' then
pixel_1 <= pixel_1 + '1';
end if;
if pin_in(2) = '1' then
pixel_2 <= pixel_2 + '1';
end if;
if pin_in(3) = '1' then
pixel_3 <= pixel_3 + '1';
end if;
if pin_in(4) = '1' then
pixel_4 <= pixel_4 + '1';
end if;
if pin_in(5) = '1' then
pixel_5 <= pixel_5 + '1';
end if;
if pin_in(6) = '1' then
pixel_6 <= pixel_6 + '1';
end if;
slv_reg0 <= pixel_0 & pixel_1;
slv_reg1 <= pixel_2 & pixel_3;
slv_reg2 <= pixel_4 & pixel_5;
slv_reg3(0 to 15) <= pixel_6;
slv_reg3(16 to 31) <= (others => '0');
end process;
I have added it to the template created by the EDK Create or Import
Peripheral wizard (with the corresponding port/signal declarations in
the right spots).
pin_in: std_logic_vector(0 to 6);
signal pixel_0 : std_logic_vector(0 to 15):= (others => '0');
signal pixel_1 : std_logic_vector(0 to 15):= (others => '0');
signal pixel_2 : std_logic_vector(0 to 15):= (others => '0');
signal pixel_3 : std_logic_vector(0 to 15):= (others => '0');
signal pixel_4 : std_logic_vector(0 to 15):= (others => '0');
signal pixel_5 : std_logic_vector(0 to 15):= (others => '0');
signal pixel_6 : std_logic_vector(0 to 15):= (others => '0');
Any thoughts?
Thanks in advance.
Article: 144216On Nov 20, 2:40=A0am, Antti <antti.luk...@googlemail.com> wrote: > On Nov 20, 6:40=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > > On Oct 28, 5:05=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > On Oct 28, 8:27=A0am, LucienZ <lucien.zh...@gmail.com> wrote: > > > > > Dear all, > > > > > Has anyone ordered and used the ML605 Evaluation Kit?http://www.xil= inx.com/products/devkits/EK-V6-ML605-G.htm > > > > I noticed some attractive features like DDR3, PCIe Gen 2 and quite > > > > high FPGA capacity (241,152 logic cells). Before my ordering I woul= d > > > > like to hear some comments. > > > > > Another feature of this board is the adoption of the FMC interfaces= . > > > > This is a new face to me, but it looks quite promising. However I h= ave > > > > a concern about it: if I just want to interface some simple IO devi= ces > > > > (e.g. a LCD panel and some push buttons), does that mean I still ha= ve > > > > to do the PCB layout for them with a FMC connection (previously it > > > > could be solved just by some IO pin headers)? > > > > > I also do not quite understand the pricing, I notice that the > > > > XC6VLX240T-1FFG1156CES chip itself costs about $2,100, but the fled= ged > > > > ML506 Kit only takes $1,995. Is this just a marketing scheme or the= re > > > > are some other reasons? > > > > > Thanks very much for your time! > > > > Lucien > > > > Yes, the features do make it a pretty cool board. :-) > > > > The main board already has push buttons, LEDS and a LCD so you are > > > covered there. If you do want add on additional peripherals then yes, > > > you will need to design a board as it isn't practical to attach wires > > > to the FMC connectors. > > > > Xilinx will/should be releasing a FMC that is primarily intending for > > > simple debug and is comprised of a series of 100 mil headers that are > > > connected to the FMC connector. =A0This board could also be used for > > > prototyping purposes. > > > > Ed McGettigan > > > -- > > > Xilinx Inc.- Hide quoted text - > > > > - Show quoted text - > > > This board is now available for sale.http://www.xilinx.com/products/dev= kits/HW-FMC-DBG-G.htmitshould be > > sold under the HW-FMC-105-DEBUG-G part number, I'm not sure what > > happened along the way. > > > Ed McGettigan > > -- > > Xilinx Inc. > > super! > 159$ for simplest connector brreakout board > > this is more than many lower cost FPGA boards cost. > > but this is Xilinx marketing. > > Antti Have you priced out the connectors?Article: 144217
Griffin wrote:
> I ended up updating the peripheral (removing from design, adding it
> again), which removed the previous error, but now there is the
> following (my custom peripheral is event_counter_0 which has 7
> exterior ports on it:
I've never used EDK, but I know that it locks down
lots of fpga resources and only let's me use a piece
of the fpga if I follow the EDK rules and use their
special interfaces to make my "custom peripheral".
-- Mike Treseler
Article: 144218On Nov 19, 11:40=A0pm, Antti <antti.luk...@googlemail.com> wrote: > On Nov 20, 6:40=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > > > > On Oct 28, 5:05=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > On Oct 28, 8:27=A0am, LucienZ <lucien.zh...@gmail.com> wrote: > > > > > Dear all, > > > > > Has anyone ordered and used the ML605 Evaluation Kit?http://www.xil= inx.com/products/devkits/EK-V6-ML605-G.htm > > > > I noticed some attractive features like DDR3, PCIe Gen 2 and quite > > > > high FPGA capacity (241,152 logic cells). Before my ordering I woul= d > > > > like to hear some comments. > > > > > Another feature of this board is the adoption of the FMC interfaces= . > > > > This is a new face to me, but it looks quite promising. However I h= ave > > > > a concern about it: if I just want to interface some simple IO devi= ces > > > > (e.g. a LCD panel and some push buttons), does that mean I still ha= ve > > > > to do the PCB layout for them with a FMC connection (previously it > > > > could be solved just by some IO pin headers)? > > > > > I also do not quite understand the pricing, I notice that the > > > > XC6VLX240T-1FFG1156CES chip itself costs about $2,100, but the fled= ged > > > > ML506 Kit only takes $1,995. Is this just a marketing scheme or the= re > > > > are some other reasons? > > > > > Thanks very much for your time! > > > > Lucien > > > > Yes, the features do make it a pretty cool board. :-) > > > > The main board already has push buttons, LEDS and a LCD so you are > > > covered there. If you do want add on additional peripherals then yes, > > > you will need to design a board as it isn't practical to attach wires > > > to the FMC connectors. > > > > Xilinx will/should be releasing a FMC that is primarily intending for > > > simple debug and is comprised of a series of 100 mil headers that are > > > connected to the FMC connector. =A0This board could also be used for > > > prototyping purposes. > > > > Ed McGettigan > > > -- > > > Xilinx Inc.- Hide quoted text - > > > > - Show quoted text - > > > This board is now available for sale.http://www.xilinx.com/products/dev= kits/HW-FMC-DBG-G.htmitshould be > > sold under the HW-FMC-105-DEBUG-G part number, I'm not sure what > > happened along the way. > > > Ed McGettigan > > -- > > Xilinx Inc. > > super! > 159$ for simplest connector brreakout board > > this is more than many lower cost FPGA boards cost. > > but this is Xilinx marketing. > > Antti- Hide quoted text - > > - Show quoted text - I'm not quite sure what you mean by "Xilinx marketing". Our cost and the resulting list priced is based on the build volume, component, fab, assembly, test costs, overhead, shipping costs and Xilinx/distributor margin. The expectation is that we will sell a few hundred lifetime for a FMC module vs several thousand a year for a development board so the cost structures are very different and are reflected in the pricing. The FMC-105-DEBUG is a bit more than a simple breakout card. The design and construction enables high speed and quality signaling between the carrier and the debug connectors and includes a high precision Silicon Labs SI570 programmable clock source. Ed McGettigan -- Xilinx Inc.Article: 144219
On Nov 20, 8:44=A0am, Gabor <ga...@alacron.com> wrote: > On Nov 20, 2:40=A0am, Antti <antti.luk...@googlemail.com> wrote: > > > > > > > On Nov 20, 6:40=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > On Oct 28, 5:05=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > > On Oct 28, 8:27=A0am, LucienZ <lucien.zh...@gmail.com> wrote: > > > > > > Dear all, > > > > > > Has anyone ordered and used the ML605 Evaluation Kit?http://www.x= ilinx.com/products/devkits/EK-V6-ML605-G.htm > > > > > I noticed some attractive features like DDR3, PCIe Gen 2 and quit= e > > > > > high FPGA capacity (241,152 logic cells). Before my ordering I wo= uld > > > > > like to hear some comments. > > > > > > Another feature of this board is the adoption of the FMC interfac= es. > > > > > This is a new face to me, but it looks quite promising. However I= have > > > > > a concern about it: if I just want to interface some simple IO de= vices > > > > > (e.g. a LCD panel and some push buttons), does that mean I still = have > > > > > to do the PCB layout for them with a FMC connection (previously i= t > > > > > could be solved just by some IO pin headers)? > > > > > > I also do not quite understand the pricing, I notice that the > > > > > XC6VLX240T-1FFG1156CES chip itself costs about $2,100, but the fl= edged > > > > > ML506 Kit only takes $1,995. Is this just a marketing scheme or t= here > > > > > are some other reasons? > > > > > > Thanks very much for your time! > > > > > Lucien > > > > > Yes, the features do make it a pretty cool board. :-) > > > > > The main board already has push buttons, LEDS and a LCD so you are > > > > covered there. If you do want add on additional peripherals then ye= s, > > > > you will need to design a board as it isn't practical to attach wir= es > > > > to the FMC connectors. > > > > > Xilinx will/should be releasing a FMC that is primarily intending f= or > > > > simple debug and is comprised of a series of 100 mil headers that a= re > > > > connected to the FMC connector. =A0This board could also be used fo= r > > > > prototyping purposes. > > > > > Ed McGettigan > > > > -- > > > > Xilinx Inc.- Hide quoted text - > > > > > - Show quoted text - > > > > This board is now available for sale.http://www.xilinx.com/products/d= evkits/HW-FMC-DBG-G.htmitshouldbe > > > sold under the HW-FMC-105-DEBUG-G part number, I'm not sure what > > > happened along the way. > > > > Ed McGettigan > > > -- > > > Xilinx Inc. > > > super! > > 159$ for simplest connector brreakout board > > > this is more than many lower cost FPGA boards cost. > > > but this is Xilinx marketing. > > > Antti > > Have you priced out the connectors?- Hide quoted text - > > - Show quoted text - Again, with the FUD on the connector cost?? The FMC connector that is used on the board is not a significant factor in the cost of the board. If the component cost was reduced to $0 the end price would not have changed by very much. Ed McGettigan -- Xilinx Inc.Article: 144220
Hello I have to send and receive some data through ethernet, try to make a transceiver. I found the LAN91C111 to save me from writing the part of layer 2 (MAC). Does anyone have any example in VHDL or Verilog how to send and receive data with the integrated layer 2?. I'm new to fpga and do not really know how to start this. thank you very much. greetingsArticle: 144221
On Nov 20, 1:18=A0pm, Mike Treseler <mtrese...@gmail.com> wrote: > Griffin wrote: > > I ended up updating the peripheral (removing from design, adding it > > again), which removed the previous error, but now there is the > > following (my custom peripheral is event_counter_0 which has 7 > > exterior ports on it: > > I've never used EDK, but I know that it locks down > lots of fpga resources and only let's me use a piece > of the fpga if I follow the EDK rules and use their > special interfaces to make my "custom peripheral". > > =A0 =A0 -- Mike Treseler I know that I'm not using pins that EDK has locked off as (at least for the time being), I'm using the GPIO buttons on the FPGA board (the ML402). I'm now at a loss as to why EDK would think that these ports are clocks, all I am doing is mapping their values to some signals.Article: 144222
On Nov 20, 10:08=A0am, Griffin <captain.grif...@gmail.com> wrote: > On Nov 17, 1:14 pm, Mike Treseler <mtrese...@gmail.com> wrote: > > > maxascent wrote: > > > Try looking in the synthesis report to see how that > > > input is being synthesized. > > > =A0Yes, a coding errorcangive an unexpectedclockinput. > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0-- Mike Treseler > > I ended up updating the peripheral (removing from design, adding it > again), which removed the previous error, but now there is the > following (my custom peripheral is event_counter_0 which has 7 > exterior ports on it: > > ERROR:Place:864 - Incompatible IOB's are locked to the same bank 9 > =A0 =A0Conflicting IO Standards are: > =A0 =A0IO Standard 1: Name =3D LVCMOS25, VREF =3D NR, VCCO =3D 2.50, TERM= =3D NONE > =A0 =A0List of locked IOB's: > =A0 =A0 =A0 =A0 event_counter_0_pixels_in_pin<6> > =A0 =A0IO Standard 2: Name =3D LVCMOS33, VREF =3D NR, VCCO =3D 3.30, TERM= =3D NONE > =A0 =A0List of locked IOB's: > =A0 =A0 =A0 =A0 fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0> > =A0 =A0 =A0 =A0 fpga_0_SRAM_Mem_A_pin<7> > =A0 =A0 =A0 =A0 fpga_0_SRAM_Mem_A_pin<8> > =A0 =A0These IO Standards are incompatible due to VCCO mismatch. > > So, in an attempt to grasp what was going on here, I commented out the > corresponding port in the .ucf file and now I get: > > WARNING:MapLib:701 - Signal event_counter_0_pixels_in_pin<4> connected > to top > =A0 =A0level port event_counter_0_pixels_in_pin<4> has been removed. > WARNING:MapLib:701 - Signal event_counter_0_pixels_in_pin<5> connected > to top > =A0 =A0level port event_counter_0_pixels_in_pin<5> has been removed. > > and the original problem rears its head once more, now with a friend: > > ERROR:Place:645 - A clock IOB clock component is not placed at an > optimal clock > =A0 =A0IOB site. The clock IOB component > <event_counter_0_pixels_in_pin<0>> is > =A0 =A0placed at site <E7>. The clock IO site can use the fast path > between the IO > =A0 =A0and the Clock buffer/GCLK if the IOB is placed in the master Clock > IOB Site. > =A0 =A0If this sub optimal condition is acceptable for this design, you > may use the > =A0 =A0CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this > message to a > =A0 =A0WARNING and allow your design to continue. However, the use of thi= s > override > =A0 =A0is highly discouraged as it may lead to very poor timing results. > It is > =A0 =A0recommended that this error condition be corrected in the design. = A > list of > =A0 =A0all the COMP.PINs used in this clock placement rule is listed > below. These > =A0 =A0examples can be used directly in the .ucf file to override this > clock rule. > =A0 =A0< NET "event_counter_0_pixels_in_pin<0>" CLOCK_DEDICATED_ROUTE =3D > FALSE; > > > WARNING:Place:971 - A GCLK / GCLK clock component pair have been found > that are > =A0 =A0not placed at an optimal GCLK / GCLK site pair. The GCLK component > =A0 =A0<clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/ > Using_BUFG_for_CLKF > =A0 =A0X.CLKFX_BUFG_INST> is placed at site <BUFGCTRL_X0Y4>. The > corresponding GCLK > =A0 =A0component > =A0 =A0<Soft_TEMAC/Soft_TEMAC/SOFT_SYS.I_TEMAC/GMII0.I_CLOCK_INST_0/ > V6V5V4S6.BUFGMUX > =A0 =A0_SPEED_CLK> is placed at site <BUFGCTRL_X0Y22>. The GCLK site can > use the > =A0 =A0fast path to the other GCLK if both the GCLK components are placed > in the > =A0 =A0same half of the device (TOP or BOTTOM). You may want to analyze > why this > =A0 =A0problem exists and correct it. This is not an error so processing > will > =A0 =A0continue. > > --- > > My peripheral is simple: > CHECK_PIXELS: process (Bus2IP_Clk) > =A0 begin =A0-- process > =A0 =A0 if pin_in(0) =3D '1' then > =A0 =A0 =A0 pixel_0 <=3D pixel_0 + '1'; > =A0 =A0 end if; > > =A0 =A0 if pin_in(1) =3D '1' then > =A0 =A0 =A0 pixel_1 <=3D pixel_1 + '1'; > =A0 =A0 end if; > > =A0 =A0 if pin_in(2) =3D '1' then > =A0 =A0 =A0 pixel_2 <=3D pixel_2 + '1'; > =A0 =A0 end if; > > =A0 =A0 if pin_in(3) =3D '1' then > =A0 =A0 =A0 pixel_3 <=3D pixel_3 + '1'; > =A0 =A0 end if; > > =A0 =A0 if pin_in(4) =3D '1' then > =A0 =A0 =A0 pixel_4 <=3D pixel_4 + '1'; > =A0 =A0 end if; > > =A0 =A0 if pin_in(5) =3D '1' then > =A0 =A0 =A0 pixel_5 <=3D pixel_5 + '1'; > =A0 =A0 end if; > > =A0 =A0 if pin_in(6) =3D '1' then > =A0 =A0 =A0 pixel_6 <=3D pixel_6 + '1'; > =A0 =A0 end if; > > =A0 =A0 slv_reg0 <=3D pixel_0 & pixel_1; > =A0 =A0 slv_reg1 <=3D pixel_2 & pixel_3; > =A0 =A0 slv_reg2 <=3D pixel_4 & pixel_5; > =A0 =A0 slv_reg3(0 to 15) <=3D pixel_6; > =A0 =A0 slv_reg3(16 to 31) <=3D (others =3D> '0'); > > =A0 end process; > > I have added it to the template created by the EDK Create or Import > Peripheral wizard (with the corresponding port/signal declarations in > the right spots). > > =A0pin_in: std_logic_vector(0 to 6); > > =A0 signal pixel_0 : std_logic_vector(0 to 15):=3D (others =3D> '0'); > =A0 signal pixel_1 : std_logic_vector(0 to 15):=3D (others =3D> '0'); > =A0 signal pixel_2 : std_logic_vector(0 to 15):=3D (others =3D> '0'); > =A0 signal pixel_3 : std_logic_vector(0 to 15):=3D (others =3D> '0'); > =A0 signal pixel_4 : std_logic_vector(0 to 15):=3D (others =3D> '0'); > =A0 signal pixel_5 : std_logic_vector(0 to 15):=3D (others =3D> '0'); > =A0 signal pixel_6 : std_logic_vector(0 to 15):=3D (others =3D> '0'); > > Any thoughts? > > Thanks in advance. I see two problems. First, in your process you left off "if Rising_edge(Bus2IP_Clk)" after the process statement. That is causing XST to think the signals are being used as clocks. The second problem is that the event_counter_0_pixels_in_pin inputs are not using the same voltage as the other pins in that bank. That is a problem in your UCF of either not specifying the IO standard for those inputs, or not putting a LOC constraint and letting the tools pick where to put them. Regards, John McCaskill www.FasterTechnology.comArticle: 144223
ISE/EDK11 has been crashing on me lately relentlessly complaining about the lack of memory and just for no reason. I am considering moving to a 64-bit OS just to eliminate the memory issue although I believe the root of the problem is in the tools. Anyways, I was just wondering if the latest EDK is indeed fully supported under 64-bit Linux as shown here http://www.xilinx.com/ise/ossupport/index.htm? Thanks, /MikhailArticle: 144224
On Nov 19, 10:08=A0pm, KJ <kkjenni...@sbcglobal.net> wrote: > On Nov 19, 10:25=A0am, Test01 <cpan...@yahoo.com> wrote: > > > > > Thanks for giving the information. =A0It seems that I still need to use > > the SOPC flow to generate this. =A0Is there Avalon-ST to Avalon-MM > > bridge Verilog module somewhere that can use?- Hide quoted text - > > The streaming transfer and memory mapped interfaces are logically > almost the same, they name the signals differently though. =A0The places > where they are truly different represent things that don't map when > trying to convert an ST to an MM protocol. > > The basic concepts in the protocols are: > - In ST is that data transfers of occur between a 'source' and a > 'sink'; in MM it is 'master' and 'slave'. > - In ST data always goes from a source to a sink; in MM data can go in > either direction. =A0A 'write' command moves data from master to source; > a 'read' command moves data from source to master. > > Given that, under certain scenarios, you can view an ST source as > being logically the same as an MM slave; an ST sink as being logically > the same as an MM master. =A0In those scenarios, the 'ST to MM bridge' > would simply consist of the following trivial logic which presumably > you could write yourself and add it as a wrapper around the core. > > MM Signal =A0 =A0 Equivalent ST signal > =3D=3D=3D=3D=3D=3D=3D=3D =A0 =A0=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D > read =A0 =A0 =A0 =A0 =A0 =A0 =A0ready > waitrequest =A0 =A0not(valid) or... > waitrequest_n valid > readdata =A0 =A0 =A0 =A0data > > So now the question is what are the scenarios where this works? =A0The > key signals that ST has that MM doesn't are 'endofpacket' and > 'channel'. =A0If your system will always have either fixed size packets > or the slave/source can be queried to determine the packet size then > might not have a need for the 'endofpacket' signal to flag the end of > a data transfer. =A0If your slave/source has only a point to point > connection to a single master/sink then you won't have a need for the > 'channel'. > > There are a whole bunch of other signals that an ST interface could > potentially have, per figure 6-1 in the Avlon Interface > Specification. =A0Basically any signal that is defined in that table as > having a direction of 'source to sink' other than the 'data' and > 'valid' signals are problems because there is no MM equivalent to work > with. =A0Whether those signals are required depends on your particular > application and use of that interface and it may also depend on how > the core you'd like to use is designed. > > The fact that there are these potentially problem signals means that > you can't construct a generic ST to MM convertor without customizing > the 'data' signal. =A0To do this, one would start by constructing a data > record that consists of the various other signals that go from source > to sink (i.e. 'channel', 'error', 'startofpacket', 'endofpacket' and > 'empty'). =A0The ST to MM convertor would then simply append these > signals with the ST data in order to make it be the MM readdata. =A0Now > the MM master receives a wider 'readdata' input that includes not only > the ST 'data' but all of the other ST status signals. > > The one clinker in the above is the 'channel' signal. =A0The ST > 'channel' signal is the equivalent of an MM 'address' signal. =A0The > problem comes in that MM 'address' is generated by an MM master, not a > slave. =A0So if you need the capability provided by the channel signal, > then your ST source will now need to become an MM master, rather than > an MM slave. =A0This isn't necessarily difficult it just means that the > mapping of signals is different. =A0Again the logic is rather trivial > > MM Signal =A0 =A0 Equivalent ST signal > =3D=3D=3D=3D=3D=3D=3D=3D =A0 =A0=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D > write =A0 =A0 =A0 =A0 =A0 =A0 =A0valid > waitrequest =A0 =A0not(ready) > writedata =A0 =A0 =A0 =A0data > > It would also be possible to do the same trick with expanding ST data > with the other ST status signals to widen the MM writedata that I > described earlier. =A0In fact, because of the lack of a suitable MM > slave equivalent to the ST 'channel' signal it would likely be best > that the ST to MM convertor be written so that the MM side is a master > and not a slave. > > The last clinker will come in if your other Avalon devices require > byte enables and data resizing. =A0That's gets a bit more complex (but > not impossible) then I want to go into here...suffice it to say that > the resizing of data busses would best be accomplished as a separate > module that then could get instantiated within your ST to MM > convertor. > > No matter how you cut it, the logic to implement the ST to MM bridge > is not at all difficult to come up with. > > Now that I've walked you through the basic steps for creating the > convertor, the real question is why? =A0ST data transfers are > fundamentally nearly the same as MM. =A0In some ways it is easier to > grasp, I'm not getting how you think it is harder than MM and how any > designer would have trouble with ST but not MM...makes no sense to > me. =A0But in any case, you should have enough info now to construct a > bridge between the two protocols.. =A0Good luck. > > Kevin Jennings Hi Kevin Thanks for providing lots of good information. You mention that Avalon-ST to Avalon-MM interface should be fairly straight forward. The thing that is confusing me is that the ST bus is packet based. For example, ST bus drive complete PCIe TLP packet. These packets contain PCIe protocol specific information. For example if it is a command request then it contains the tag, requester ID. Thus I see the command on ST bus form PCIe hatrdIP, I need to process the response that has some the attributes of the request - response may need to contain the tag used on the corresponding request (as per my understanding). But if we use the Avalon-MM bus then all that is transparent. Is that true? Avalon-MM bus master from HardIP side will issue address/data/command and then the slave device will respond to but the slave does not need to track the response with corresponding tag and other fileds. Is this not done by Avalon-ST to Avalon-MM bridge? I would like to use the Avalon-ST but I am trying to figure out how to interpret the Avalon-ST packets coming out of the PCIe hard IP. The Avalon ST interface that is coming from the Stratix4GX PCIe hard IP. I do not have enough understanding on this so I am not sure whom to ask about this. This is for the Stratix4GX Gen1 x1 PCIe endpoint hard IP simulation and the very first transaction on the Avalon ST bus. I see the following sequence on the waveform viewer. (1)Clock1 - Start of Packet =3D 1 (Pulse) - Rx_St_Data[63:0] =3D 0000_000F_4000_0001, Rx_St_Be0[7:0] =3D F0 Rx_St_Eop0 =3D 0 (2)Clock2 =96 Start of Packet =3D 0 Rx_St_Data[63:0] =3D 0300_0000_0020_0010, Rx_St_Be0[7:0] =3D 0F, St_Eop0 =3D 0 (3)Clock3 =96 Start of Packet =3D 0 Rx_St_Data[63:0] =3D 0000_0003_0000_0003, Rx_St_Be0[7:0] =3D 0F, St_Eop0 =3D 1 If anyone can help me interpet this then that will be great. This how I am interpreting this transaction Header0_Byte0 =3D 40 =96 This means 32 Bit Memory write =96 This is a 3DW memory write (32 bit address and not 64 bit address) Header0_Byte1 =3D 00 Header0_Byte2 =3D 00 Header0_Byte3 =3D 01 =96 1 DW write? Header1_Byte4 =3D 00 Header1_Byte5 =3D 00 Header1_Byte6 =3D 00 - Tag =3D 0? (This does not make sense) Header1_Byte7 =3D 0F =96 First DW is valid. //Following are the address bytes? Header2_Byte8 =3D 00 Header2_Byte9 =3D 20 Header2_Byte10 =3D 00 Header2_Byte11 =3D 10 - Address =3D 0020_0010hex Is that correct? Byte12 to 15 is not valid? This is because Rx_St_Be0[7:0] =3D 0F for the second clock. This is why there is third clock to complete the tranaction? The 3rd clock has DW data =3D 0000_0003h with BE =3D 0Fh. Lower DW of the Rx_St_Data [63:0] has valid data. In summary, it is trying to do 3 DW (32 bit address) memory write at address 0020_0010 with data 0000_0003h. Any suggestions will be great.
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