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On the same note, I would appreciate an advice on what kind of CPU makes the most sense for today's and future Xilinx tools running under 64-bit Linux. Should I get a quad core or dual core? And if someone wants to give me a very specific advice it has to be Dell :) Thanks, /MikhailArticle: 144226
M, I use EDK on a 64b RHEL system...and it doesn't crash (for me). AustinArticle: 144227
I'm trying to implement an SDRAM controller for the Altera EP2C8 on a
TS-7300 board (from http://www.embeddedarm.com), and I found a
document from Altera (http://www.pldworld.net/_altera/html/_excalibur/
nios-sdram-tuning/SDRAM_PLL_Tuning.pdf) which looks helpful in
calculating how the PLL ought to be set up.
The problem I'm facing is that the datasheet (http://www.altera.com/
literature/hb/cyc2/cyc2_cii5v1_01.pdf) for the EP2C8 doesn't seem to
have the information needed by the calculations in the tuning guide.
The tuning guide is referencing a table ("table 4:36. EP1C20 Column
pin global clock external i/o timing parameters) that shows t_su,
s_inh, and t_outco for a Cyclone 1, and the closest table I can find
in the datasheet for the cyclone 2 has t_cin, t_cout, t_pllcin, and
t_pllcout (table 5-23 : EP2C8/A Column pins global clock timing
parameters). These don't appear to be the same thing :)
Can anyone point me in the right direction ? Much appreciated if you
do :)
Cheers,
Simon
Article: 144228MM <mbmsv@yahoo.com> wrote: > ISE/EDK11 has been crashing on me lately relentlessly complaining about the > lack of memory and just for no reason. I am considering moving to a 64-bit > OS just to eliminate the memory issue although I believe the root of the > problem is in the tools. Anyways, I was just wondering if the latest EDK is > indeed fully supported under 64-bit Linux as shown here > http://www.xilinx.com/ise/ossupport/index.htm? I use 11.3 on Fedora 10 64 bit and it's OK for me. Oh, except I can't get the SDK to load, something to do with missing libraries for which I've followed all the advice I can find but can't get to work. Don't use it though, so don't care. NobbyArticle: 144229
On Nov 20, 4:12=A0pm, Test01 <cpan...@yahoo.com> wrote: > On Nov 19, 10:08=A0pm, KJ <kkjenni...@sbcglobal.net> wrote: > > Hi Kevin > > Thanks for providing lots of good information. =A0You mention that > Avalon-ST to Avalon-MM interface should be fairly straight forward. > The thing that is confusing me is that the ST bus is packet based. > For example, ST bus drive complete PCIe TLP packet. =A0These packets > contain PCIe protocol specific information. =A0For example if it is a > command request then it contains the tag, requester ID. =A0Thus I see > the command on ST bus form PCIe hatrdIP, I need to process the > response that has some the attributes of the request - response may > need to contain the tag used on the corresponding request (as per my > understanding). =A0 None of what you described has anything to do with either Avalon streaming transfers or Avalon memory mapped interfaces...those interfaces are simply the protocols for passing data. > But if we use the Avalon-MM bus then all that is > transparent. Is that true? =A0 Transparent to what? If the PCIe core really does need you to "...process the response that has some the attributes of the request - response may need to contain the tag used on the corresponding request (as per my understanding)" then you're completely mistaken if you think that Avalon (or any other bus interface) will take care of any of that for you. > Avalon-MM bus master from HardIP side will > issue address/data/command and then the slave device will respond to > but the slave does not need to track the response with corresponding > tag and other fileds. =A0 OK > Is this not done by Avalon-ST to Avalon-MM > bridge? > No. Bus interfaces don't give a hoot about what data is being transferred. They exist to give a common framework for transferring data. What data gets transferred, what higher level protocols get put on top of that is not relevant. That's like wondering if the specifications for to wire a building will somehow make the Ethernet, TCP, IP protocols transparent...it won't...it's just wire. > I would like to use the Avalon-ST but I am trying to figure out how to > interpret the Avalon-ST packets coming out of the PCIe hard IP. > Now we get to the real problem and it has nothing to do with ST or MM. Since I haven't looked at the PCIe core though I can't help you out in interpreting the data that is coming and going, I was only helping with the handshake protocol of ST and MM. > The Avalon ST interface that is coming from the Stratix4GX PCIe hard > IP. I do not have enough understanding on this so I am not sure whom > to ask about this. The manual for the core is a good start. Kevin JenningsArticle: 144230
Potxoka <potxoka@gmail.com> writes: >Hello >I have to send and receive some data through ethernet, try to make a >transceiver. I found the LAN91C111 to save me from writing the part of >layer 2 (MAC). Does anyone have any example in VHDL or Verilog how to >send and receive data with the integrated layer 2?. I'm new to fpga >and do not really know how to start this. thank you very much. >greetings I'm just starting on a similar project (luckily for my own interest with no schedule or deadline :-)). I'm starting off with a Dragon board: http://www.knjn.com/FPGA-PCI.html which has a PHYless 10 megabit only implementation in VHDL source form as part of the documentation (the connector with magnetics and a crystal was another $9 :-)). Once I've got my feet wet playing with that I have a 10/100 PHY daughter card to add to the board to be able to do 10/100 with a real PHY (the only PHY daughter card I've found at a reasonable price :-)) http://www.enterpoint.co.uk/moelbryn/modules/ethernet_phy.html and intend on using the ethernet open source MACs available from opencores.org. It appears that 10/100/1000 PHYs run around $600 on daughter cards which will make Gig somewhat exciting via DMA. It would probably be worthwhile to have a look at the opencores.org site in the RISC CPU area since I think some of them have interfaces to the 10/100 MAC core which uses the wishbone bus and that may help you alone. The LAN91C111 looks to be a 10/100 integrated PHY/MAC with an ISA bus type (i.e. not PCI) bus interface. Interfacing that to the FPGA shouldn't be all that hard, but then you are going to need an IP stack of some kind to actually get packets to it. If all you need to do is get some (non wire speed) packets on to the wire, you may be better off with one of the MCUs with built in ethernet such as a PIC. They aren't fast enough to do wire speed but they will get packets on the wire relatively easily although you are still going to need an IP stack (as in Internet Protocol rather than Intellectual Property given the group this is in :-)) to generate appropriate packets to give to the ethernet MAC. Peter Van EppArticle: 144231
On Nov 21, 4:32=A0am, van...@sfu.ca (Peter Van Epp) wrote: > Potxoka <potx...@gmail.com> writes: > >Hello > >I have to send and receive some data through ethernet, try to make a > >transceiver. I found the LAN91C111 to save me from writing the part of > >layer 2 (MAC). Does anyone have any example in VHDL or Verilog how to > >send and receive data with the integrated layer 2?. I'm new to fpga > >and do not really know how to start this. thank you very much. > >greetings > > =A0 =A0 =A0 =A0 I'm just starting on a similar project (luckily for my ow= n interest > with no schedule or deadline :-)). I'm starting off with a Dragon board: > > http://www.knjn.com/FPGA-PCI.html > > which has a PHYless 10 megabit only implementation in VHDL source form as > part of the documentation (the connector with magnetics and a crystal was > another $9 :-)). Once I've got my feet wet playing with that I have a 10/= 100 > PHY daughter card to add to the board to be able to do 10/100 with a real > PHY (the only PHY daughter card I've found at a reasonable price :-)) > > http://www.enterpoint.co.uk/moelbryn/modules/ethernet_phy.html > > and intend on using the ethernet open source MACs available from opencore= s.org. > It appears that 10/100/1000 PHYs run around $600 on daughter cards which = will > make Gig somewhat exciting via DMA. It would probably be worthwhile to ha= ve > a look at the opencores.org site in the RISC CPU area since I think some = of > them have interfaces to the 10/100 MAC core which uses the wishbone bus a= nd > that may help you alone. > =A0 =A0 =A0 =A0 The LAN91C111 looks to be a 10/100 integrated PHY/MAC wit= h an ISA bus > type (i.e. not PCI) bus interface. Interfacing that to the FPGA shouldn't= be > all that hard, but then you are going to need an IP stack of some kind to > actually get packets to it. > =A0 =A0 =A0 =A0 If all you need to do is get some (non wire speed) packet= s on to the > wire, you may be better off with one of the MCUs with built in ethernet s= uch > as a PIC. They aren't fast enough to do wire speed but they will get pack= ets > on the wire relatively easily although you are still going to need an IP = stack > (as in Internet Protocol rather than Intellectual Property given the grou= p > this is in :-)) to generate appropriate packets to give to the ethernet M= AC. > > Peter Van Epp hi, I had already looked into OpenCores, the problem is that I=B4m newbie to fpga and more in vhdl / verilog, so as not to implement it properly. why LAN91C111 had thought of that I avoid having to implement the mac. IP stack do not need, since the only need that I have to send and receive packets in a layer 2 (mac), but being a rookie, also going to cost me to use this phy from the fpga ;-). so wondered if anyone had already implemented this. National PHY have sent me some samples and is relatively cheap (5 dollars to 16 dollars of LAN91C111, ufff). My main idea was to have used these for this purpose and implement the mac on the fpga, but I think I would be very difficult. I have also seen some phy (National) with pci connection, but a PCI attack from an FPGA must not be easy (apart from implementing the mac ;-P ), right?. Thanks GreetingsArticle: 144232
On 21 nov, 14:23, Potxoka <potx...@gmail.com> wrote: > On Nov 21, 4:32=A0am, van...@sfu.ca (Peter Van Epp) wrote: > > > > > Potxoka <potx...@gmail.com> writes: > > >Hello > > >I have to send and receive some data through ethernet, try to make a > > >transceiver. I found the LAN91C111 to save me from writing the part of > > >layer 2 (MAC). Does anyone have any example in VHDL or Verilog how to > > >send and receive data with the integrated layer 2?. I'm new to fpga > > >and do not really know how to start this. thank you very much. > > >greetings > > > =A0 =A0 =A0 =A0 I'm just starting on a similar project (luckily for my = own interest > > with no schedule or deadline :-)). I'm starting off with a Dragon board= : > > >http://www.knjn.com/FPGA-PCI.html > > > which has a PHYless 10 megabit only implementation in VHDL source form = as > > part of the documentation (the connector with magnetics and a crystal w= as > > another $9 :-)). Once I've got my feet wet playing with that I have a 1= 0/100 > > PHY daughter card to add to the board to be able to do 10/100 with a re= al > > PHY (the only PHY daughter card I've found at a reasonable price :-)) > > >http://www.enterpoint.co.uk/moelbryn/modules/ethernet_phy.html > > > and intend on using the ethernet open source MACs available from openco= res.org. > > It appears that 10/100/1000 PHYs run around $600 on daughter cards whic= h will > > make Gig somewhat exciting via DMA. It would probably be worthwhile to = have > > a look at the opencores.org site in the RISC CPU area since I think som= e of > > them have interfaces to the 10/100 MAC core which uses the wishbone bus= and > > that may help you alone. > > =A0 =A0 =A0 =A0 The LAN91C111 looks to be a 10/100 integrated PHY/MAC w= ith an ISA bus > > type (i.e. not PCI) bus interface. Interfacing that to the FPGA shouldn= 't be > > all that hard, but then you are going to need an IP stack of some kind = to > > actually get packets to it. > > =A0 =A0 =A0 =A0 If all you need to do is get some (non wire speed) pack= ets on to the > > wire, you may be better off with one of the MCUs with built in ethernet= such > > as a PIC. They aren't fast enough to do wire speed but they will get pa= ckets > > on the wire relatively easily although you are still going to need an I= P stack > > (as in Internet Protocol rather than Intellectual Property given the gr= oup > > this is in :-)) to generate appropriate packets to give to the ethernet= MAC. > > > Peter Van Epp > > hi, > > I had already looked into OpenCores, the problem is that I=B4m newbie to > fpga and more in vhdl / verilog, so as not to implement it properly. > why LAN91C111 had thought of that I avoid having to implement the mac. > IP stack do not need, since the only need that I have to send and > receive packets in a layer 2 (mac), but being a rookie, also going to > cost me to use this phy from the fpga ;-). so wondered if anyone had > already implemented this. > > National PHY have sent me some samples and is relatively cheap (5 > dollars to 16 dollars of LAN91C111, ufff). My main idea was to have > used these for this purpose and implement the mac on the fpga, but I > think I would be very difficult. I have also seen some phy (National) > with pci connection, but a PCI attack from an FPGA must not be easy > (apart from implementing the mac ;-P ), right?. Thanks > > Greetings Sorry, lan91c111 25 dolars.Article: 144233
Potxoka <potxoka@gmail.com> writes: <snip> >hi, >I had already looked into OpenCores, the problem is that I=B4m newbie to >fpga and more in vhdl / verilog, so as not to implement it properly. >why LAN91C111 had thought of that I avoid having to implement the mac. >IP stack do not need, since the only need that I have to send and >receive packets in a layer 2 (mac), but being a rookie, also going to >cost me to use this phy from the fpga ;-). so wondered if anyone had >already implemented this. >National PHY have sent me some samples and is relatively cheap (5 >dollars to 16 dollars of LAN91C111, ufff). My main idea was to have >used these for this purpose and implement the mac on the fpga, but I >think I would be very difficult. I have also seen some phy (National) >with pci connection, but a PCI attack from an FPGA must not be easy >(apart from implementing the mac ;-P ), right?. Thanks >Greetings I think you are going to find you need an IP stack. At the very least you are going to need to implement arp to find the MAC address of whoever you want to communicate with and perhaps DHCP to get an IP address for your device (although you could hardcode both although it won't be too flexable). Then you will need to format UDP packets with appropriate headers, data and crc to send to the MAC address you found via arp. A TCP connection is much more complex. A PHY/MAC combination will only get packets (with appropriate content from somewhere, usually the IP stack :-)), on the wire. You may want to look at something like the PIC18F66J60-I which is around $6 at Digikey. It has a 10 meg phy and Mac on board and I think there is an IP library available from Microchip. Your FPGA would send the data to the PIC which would then run it through the IP stack and send it as appropriate. I expect you are correct that getting one of the opencores MACs to work isn't easy (I haven't gotten that far yet so I can't say for sure :-)). Depending on your time line and budget you may be best to start with the Dragon board I mentioned as it comes with do it your self VHDL to do 10 meg (no PHY) ethernet and a PCI interface (the Dragon is $299 US + as noted $9 for the ether connector and oscillator) that may be your best bet to learn more about ethernet and fpgas. Good luck! Peter Van Epp From usenet+6@ladybug.xs4all.nl Sat Nov 21 12:10:30 2009 Path: unlimited.newshosting.com!s02-b69!npeersf02.iad.highwinds-media.com!npeer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!news3.google.com!feeder3.cambriumusenet.nl!feed.tweaknews.nl!194.109.133.84.MISMATCH!newsfeed.xs4all.nl!newsfeed5.news.xs4all.nl!xs4all!post.news.xs4all.nl!not-for-mail From: Arlet <usenet+6@ladybug.xs4all.nl> Subject: Re: FPGA + Ethernet Date: Sat, 21 Nov 2009 21:10:30 +0100 User-Agent: Pan/0.14.2.91 (As She Crawled Across the Table (Debian GNU/Linux)) Message-Id: <pan.2009.11.21.20.10.30.523371@ladybug.xs4all.nl> Newsgroups: comp.arch.fpga References: <b4768b1e-ac07-4025-a969-7a7879fcb3a3@a21g2000yqc.googlegroups.com> <he7n0c$5ab$1@morgoth.sfu.ca> <107fd14e-9047-4da3-b47a-e6baaef3e359@k4g2000yqb.googlegroups.com> <he9fvh$br9$1@morgoth.sfu.ca> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 24 NNTP-Posting-Host: 83.163.219.105 X-Trace: 1258834231 news.xs4all.nl 22920 [::ffff:83.163.219.105]:48649 X-Complaints-To: abuse@xs4all.nl Xref: unlimited.newshosting.com comp.arch.fpga:95548 X-Received-Date: Sat, 21 Nov 2009 20:10:31 UTC (s02-b69) On Sat, 21 Nov 2009 19:44:49 +0000, Peter Van Epp wrote: > I think you are going to find you need an IP stack. At the very least > you are going to need to implement arp to find the MAC address of whoever > you want to communicate with and perhaps DHCP to get an IP address for your > device (although you could hardcode both although it won't be too flexable). > Then you will need to format UDP packets with appropriate headers, data and > crc to send to the MAC address you found via arp. A TCP connection is much > more complex. A PHY/MAC combination will only get packets (with appropriate > content from somewhere, usually the IP stack :-)), on the wire. Sending raw ethernet packets may be good enough for some applications. If you have a private network, and use some dedicated software on an attached PC, you can define your own protocol using ethernet packets. I've used such a method for a tiny bootloader that could boot over ethernet, using proprietary packet format, and a special boot server program running on a PC. Of course, if the device needs to talk to existing IP-family protocols, some more code is required, although it's possible to cut some corners too. For instance, if the device is passive, you can skip ARP, and just reverse the src/dst MAC address to turn a request into a response.Article: 144234
Hello all, I'm trying to implement a ring oscillator using 1 nand gate connected to a series of not gates. Synthesis produces no relevant warnings, but translation says all the wires are source-less and is removing them, despite settings I have provided through constraints. In the ISE map options, I have checked "Register Duplication" as well as adding a Keep constraint in the verilog source, which is below. Here is an example of some of the messages I'm seeing: The signal "puf1/mux2/N1" is sourceless and has been removed. The signal "puf1/mux2/N2" is sourceless and has been removed. The signal "puf1/mux1/N1" is sourceless and has been removed. The signal "puf1/mux1/N2" is sourceless and has been removed. The signal "puf1/oscillator1/N0" is sourceless and has been removed. The signal "puf1/oscillator1/N1" is sourceless and has been removed. The signal "puf1/oscillator1/inputGate/N1" is sourceless and has been removed. The signal "puf1/oscillator1/inputGate/N2" is sourceless and has been removed. The signal "puf1/oscillator1/GATELOOP[35]..endGate/N1" is sourceless and has been removed. The signal "puf1/oscillator1/GATELOOP[35]..endGate/N2" is sourceless and has been removed. The signal "puf1/oscillator1/GATELOOP[35].gate/N1" is sourceless and has been removed. The signal "puf1/oscillator1/GATELOOP[35].gate/N2" is sourceless and has been removed. The signal "puf1/oscillator1/GATELOOP[34].gate/N1" is sourceless and has been removed. The signal "puf1/oscillator1/GATELOOP[34].gate/N2" is sourceless and has been removed. ... What is also interesting, is my Verilog source does not define an N1 or N2 signal, and I can't figure out what these correspond to. Here is the Verilog code I'm using. module ringoscillator( output wire out ); (* KEEP = "TRUE" *) wire connector; (* KEEP = "TRUE" *) wire [36:0] w; nandgate inputGate(.i1(connector), .i2(1'b1), .out(w[0])); // generate inverters genvar i; generate for(i = 0; i < 36; i = i + 1) begin : GATELOOP invertergate gate(.in(w[i]), .out(w[i+1])); if(i+1 == 36) invertergate endGate(.in(w[i+1]), .out(connector)); end endgenerate assign out = connector; endmodule module nandgate(input wire i1, i2, output wire out); assign out = ~(i1 & i2); endmodule module invertergate(input wire in, output wire out); assign out = ~in; endmodule Are there any flaws in the code or settings I can make to stop ISE from removing my logic? Thanks for any help!Article: 144235
On Nov 21, 11:34=A0pm, Sam Kerr <stk...@purdue.edu> wrote: > Hello all, > > I'm trying to implement a ring oscillator using 1 nand gate connected to = a > series of not gates. Synthesis produces no relevant warnings, but > translation says all the wires are source-less and is removing them, > despite settings I have provided through constraints. > > In the ISE map options, I have checked "Register Duplication" as well as > adding a Keep constraint in the verilog source, which is below. > > Here is an example of some of the messages I'm seeing: > > The signal "puf1/mux2/N1" is sourceless and has been removed. > The signal "puf1/mux2/N2" is sourceless and has been removed. > The signal "puf1/mux1/N1" is sourceless and has been removed. > The signal "puf1/mux1/N2" is sourceless and has been removed. > The signal "puf1/oscillator1/N0" is sourceless and has been removed. > The signal "puf1/oscillator1/N1" is sourceless and has been removed. > The signal "puf1/oscillator1/inputGate/N1" is sourceless and has been rem= oved. > The signal "puf1/oscillator1/inputGate/N2" is sourceless and has been rem= oved. > The signal "puf1/oscillator1/GATELOOP[35]..endGate/N1" is sourceless and = has been removed. > The signal "puf1/oscillator1/GATELOOP[35]..endGate/N2" is sourceless and = has been removed. > The signal "puf1/oscillator1/GATELOOP[35].gate/N1" is sourceless and has = been removed. > The signal "puf1/oscillator1/GATELOOP[35].gate/N2" is sourceless and has = been removed. > The signal "puf1/oscillator1/GATELOOP[34].gate/N1" is sourceless and has = been removed. > The signal "puf1/oscillator1/GATELOOP[34].gate/N2" is sourceless and has = been removed. > ... > > What is also interesting, is my Verilog source does not define an N1 or N= 2 > signal, and I can't figure out what these correspond to. > > Here is the Verilog code I'm using. > > module ringoscillator( > output wire out > ); > > (* KEEP =3D "TRUE" *) wire connector; > (* KEEP =3D "TRUE" *) wire [36:0] w; > > nandgate inputGate(.i1(connector), .i2(1'b1), .out(w[0])); > > // generate inverters > genvar i; > > generate > =A0 =A0for(i =3D 0; i < 36; i =3D i + 1) > =A0 =A0begin : GATELOOP > =A0 =A0 =A0 =A0 invertergate gate(.in(w[i]), .out(w[i+1])); > =A0 =A0 =A0 =A0 if(i+1 =3D=3D 36) > =A0 =A0 =A0 =A0 invertergate endGate(.in(w[i+1]), .out(connector)); > =A0 =A0end > endgenerate > > assign out =3D connector; > > endmodule > > module nandgate(input wire i1, i2, output wire out); > =A0 =A0 =A0 =A0 assign out =3D ~(i1 & i2); > endmodule > > module invertergate(input wire in, output wire out); > =A0 =A0 =A0 =A0 assign out =3D ~in; > endmodule > > Are there any flaws in the code or settings I can make to stop ISE from r= emoving my logic? > > Thanks for any help! WHY SO COMPLICATED?? just take xilinx own ring oscillator code, it works (one place is s3e sk ref designs, freq measurement example) AnttiArticle: 144236
Peter Van Epp wrote: > Depending on your time line and > budget you may be best to start with the Dragon board I mentioned as it comes > with do it your self VHDL to do 10 meg (no PHY) ethernet and a PCI interface > (the Dragon is $299 US + as noted $9 for the ether connector and oscillator) > that may be your best bet to learn more about ethernet and fpgas. Good luck! If money is an issue but not time or bandwidth, I suggest buying a ready-made module based on the ENC28J60. I have found (and bought) several on eBay, they are _cheap_ and _small_ . Mine are marked as coming from http://www.the0.net BTW the interface is synchronous serial (SPI) up to 20MHz (so it's only 10BasetT) but it is easier to start using Ethernet with the HW/MAC/PHT already designed. And later it can be integrated in a product, due to the size and price. just .2$, > Peter Van Epp yg -- http://ygdes.com / http://yasep.orgArticle: 144237
whygee wrote: > If money is an issue but not time or bandwidth, I suggest buying > a ready-made module based on the ENC28J60. I have found (and bought) > several on eBay, they are _cheap_ and _small_ . Mine are marked > as coming from http://www.the0.net I've found the store's address again : http://cgi.ebay.com/ws/eBayISAPI.dll?ViewItem&item=300368473658 the cost is about $17, +$7 for shipping. If someone finds even cheaper, please tell me. At least it's cheaper and smaller than Microchip's own modules. OK, it's not 100BaseT but the serial interface requires much less pins than the original poster's solution. I have also found several step-by-step introductions to this chips on the 'net. Though I have not yet had the time to try the module. yg -- http://ygdes.com / http://yasep.orgArticle: 144238
We are looking at doing some Cameralink support in our products. Given there are options on that interface, or even the number of interfaces, we might support I am looking for feedback on what you would all like to have available. We are also looking at a number of implementation options e.g. direct driving by FPGAs V using buffers so it's your chance to comment and guide us in what we product for the market. John Adair EnterpointArticle: 144239
On Nov 10, 3:48=A0am, Dave <doomedd...@yahoo.co.uk> wrote: > Hi Group, > > In the past when I have wanted to use a script with ISE I have always > simply run the flow using the gui first and then created a batch file > using the command lines printed in the individual reports from xst, > ngdbuild, etc. =A0Seemed to work quite well especially when using the > errorlevel returns (in Windows) to catch errors. > > I am aware of the xflow system and that something can also no doubt be > done using tcl and I am wondering what the "best" method is. > > What do you use and why? > > One key feature I want to include in the design I'm starting now is > automatic build number increments by way of automatically increasing > an integer generic supplied to XST. =A0This will be used to set the > reset value of a register in the VHDL. =A0I am guessing a tcl script > would be best for this but can this also be done using xflow? > > Many thanks for your time. I would recommend Makefile for command line flow. Not only does it check the return code, but also it checks dependencies. You can find a Makefile example here: http://groups.google.com/group/my-design-space/web/m= y-tools-page Cheers, Jim http://myfpgablog.blogspot.com/Article: 144240
This message is in MIME format. The first part should be readable text, while the remaining parts are likely unreadable without MIME-aware tools. --70899012-26691-1258909663=:5028 Content-Type: TEXT/PLAIN; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: QUOTED-PRINTABLE On Sat, 21 Nov 2009, Antti wrote: > On Nov 21, 11:34=A0pm, Sam Kerr <stk...@purdue.edu> wrote: > > Hello all, > > > > I'm trying to implement a ring oscillator using 1 nand gate connected t= o a > > series of not gates. Synthesis produces no relevant warnings, but > > translation says all the wires are source-less and is removing them, > > despite settings I have provided through constraints. > > > > In the ISE map options, I have checked "Register Duplication" as well a= s > > adding a Keep constraint in the verilog source, which is below. > > > > Here is an example of some of the messages I'm seeing: > > > > The signal "puf1/mux2/N1" is sourceless and has been removed. > > The signal "puf1/mux2/N2" is sourceless and has been removed. > > The signal "puf1/mux1/N1" is sourceless and has been removed. > > The signal "puf1/mux1/N2" is sourceless and has been removed. > > The signal "puf1/oscillator1/N0" is sourceless and has been removed. > > The signal "puf1/oscillator1/N1" is sourceless and has been removed. > > The signal "puf1/oscillator1/inputGate/N1" is sourceless and has been r= emoved. > > The signal "puf1/oscillator1/inputGate/N2" is sourceless and has been r= emoved. > > The signal "puf1/oscillator1/GATELOOP[35]..endGate/N1" is sourceless an= d has been removed. > > The signal "puf1/oscillator1/GATELOOP[35]..endGate/N2" is sourceless an= d has been removed. > > The signal "puf1/oscillator1/GATELOOP[35].gate/N1" is sourceless and ha= s been removed. > > The signal "puf1/oscillator1/GATELOOP[35].gate/N2" is sourceless and ha= s been removed. > > The signal "puf1/oscillator1/GATELOOP[34].gate/N1" is sourceless and ha= s been removed. > > The signal "puf1/oscillator1/GATELOOP[34].gate/N2" is sourceless and ha= s been removed. > > ... > > > > What is also interesting, is my Verilog source does not define an N1 or= N2 > > signal, and I can't figure out what these correspond to. > > > > Here is the Verilog code I'm using. > > > > module ringoscillator( > > output wire out > > ); > > > > (* KEEP =3D "TRUE" *) wire connector; > > (* KEEP =3D "TRUE" *) wire [36:0] w; > > > > nandgate inputGate(.i1(connector), .i2(1'b1), .out(w[0])); > > > > // generate inverters > > genvar i; > > > > generate > > =A0 =A0for(i =3D 0; i < 36; i =3D i + 1) > > =A0 =A0begin : GATELOOP > > =A0 =A0 =A0 =A0 invertergate gate(.in(w[i]), .out(w[i+1])); > > =A0 =A0 =A0 =A0 if(i+1 =3D=3D 36) > > =A0 =A0 =A0 =A0 invertergate endGate(.in(w[i+1]), .out(connector)); > > =A0 =A0end > > endgenerate > > > > assign out =3D connector; > > > > endmodule > > > > module nandgate(input wire i1, i2, output wire out); > > =A0 =A0 =A0 =A0 assign out =3D ~(i1 & i2); > > endmodule > > > > module invertergate(input wire in, output wire out); > > =A0 =A0 =A0 =A0 assign out =3D ~in; > > endmodule > > > > Are there any flaws in the code or settings I can make to stop ISE from= removing my logic? > > > > Thanks for any help! >=20 > WHY SO COMPLICATED?? >=20 > just take xilinx own ring oscillator code, it works > (one place is s3e sk ref designs, freq measurement example) >=20 > Antti > Thanks for this advice, where can I find these designs? --70899012-26691-1258909663=:5028--Article: 144241
On Nov 20, 1:31=A0pm, Simon <goo...@gornall.net> wrote:
> I'm trying to implement an SDRAM controller for the Altera EP2C8 on a
> TS-7300 board (fromhttp://www.embeddedarm.com), and I found a
> document from Altera (http://www.pldworld.net/_altera/html/_excalibur/
> nios-sdram-tuning/SDRAM_PLL_Tuning.pdf) which looks helpful in
> calculating how the PLL ought to be set up.
>
> The problem I'm facing is that the datasheet (http://www.altera.com/
> literature/hb/cyc2/cyc2_cii5v1_01.pdf) for the EP2C8 doesn't seem to
> have the information needed by the calculations in the tuning guide.
> The tuning guide is referencing a table ("table 4:36. EP1C20 Column
> pin global clock external i/o timing parameters) that shows t_su,
> s_inh, and t_outco for a Cyclone 1, and the closest table I can find
> in the datasheet for the cyclone 2 has t_cin, t_cout, t_pllcin, and
> t_pllcout (table 5-23 : =A0EP2C8/A Column pins global clock timing
> parameters). These don't appear to be the same thing :)
>
> Can anyone point me in the right direction ? Much appreciated if you
> do :)
>
> Cheers,
> =A0 =A0Simon
No-one got any hints ?
Cheers,
Simon.
Article: 144242On Nov 22, 7:07=A0pm, Sam Kerr <stk...@purdue.edu> wrote: > On Sat, 21 Nov 2009, Antti wrote: > > On Nov 21, 11:34=A0pm, Sam Kerr <stk...@purdue.edu> wrote: > > > Hello all, > > > > I'm trying to implement a ring oscillator using 1 nand gate connected= to a > > > series of not gates. Synthesis produces no relevant warnings, but > > > translation says all the wires are source-less and is removing them, > > > despite settings I have provided through constraints. > > > > In the ISE map options, I have checked "Register Duplication" as well= as > > > adding a Keep constraint in the verilog source, which is below. > > > > Here is an example of some of the messages I'm seeing: > > > > The signal "puf1/mux2/N1" is sourceless and has been removed. > > > The signal "puf1/mux2/N2" is sourceless and has been removed. > > > The signal "puf1/mux1/N1" is sourceless and has been removed. > > > The signal "puf1/mux1/N2" is sourceless and has been removed. > > > The signal "puf1/oscillator1/N0" is sourceless and has been removed. > > > The signal "puf1/oscillator1/N1" is sourceless and has been removed. > > > The signal "puf1/oscillator1/inputGate/N1" is sourceless and has been= removed. > > > The signal "puf1/oscillator1/inputGate/N2" is sourceless and has been= removed. > > > The signal "puf1/oscillator1/GATELOOP[35]..endGate/N1" is sourceless = and has been removed. > > > The signal "puf1/oscillator1/GATELOOP[35]..endGate/N2" is sourceless = and has been removed. > > > The signal "puf1/oscillator1/GATELOOP[35].gate/N1" is sourceless and = has been removed. > > > The signal "puf1/oscillator1/GATELOOP[35].gate/N2" is sourceless and = has been removed. > > > The signal "puf1/oscillator1/GATELOOP[34].gate/N1" is sourceless and = has been removed. > > > The signal "puf1/oscillator1/GATELOOP[34].gate/N2" is sourceless and = has been removed. > > > ... > > > > What is also interesting, is my Verilog source does not define an N1 = or N2 > > > signal, and I can't figure out what these correspond to. > > > > Here is the Verilog code I'm using. > > > > module ringoscillator( > > > output wire out > > > ); > > > > (* KEEP =3D "TRUE" *) wire connector; > > > (* KEEP =3D "TRUE" *) wire [36:0] w; > > > > nandgate inputGate(.i1(connector), .i2(1'b1), .out(w[0])); > > > > // generate inverters > > > genvar i; > > > > generate > > > =A0 =A0for(i =3D 0; i < 36; i =3D i + 1) > > > =A0 =A0begin : GATELOOP > > > =A0 =A0 =A0 =A0 invertergate gate(.in(w[i]), .out(w[i+1])); > > > =A0 =A0 =A0 =A0 if(i+1 =3D=3D 36) > > > =A0 =A0 =A0 =A0 invertergate endGate(.in(w[i+1]), .out(connector)); > > > =A0 =A0end > > > endgenerate > > > > assign out =3D connector; > > > > endmodule > > > > module nandgate(input wire i1, i2, output wire out); > > > =A0 =A0 =A0 =A0 assign out =3D ~(i1 & i2); > > > endmodule > > > > module invertergate(input wire in, output wire out); > > > =A0 =A0 =A0 =A0 assign out =3D ~in; > > > endmodule > > > > Are there any flaws in the code or settings I can make to stop ISE fr= om removing my logic? > > > > Thanks for any help! > > > WHY SO COMPLICATED?? > > > just take xilinx own ring oscillator code, it works > > (one place is s3e sk ref designs, freq measurement example) > > > Antti > > Thanks for this advice, where can I find these designs? read what i said :) www.xilinx.com look for S3E starter kit reference designs picoblaze frequency meter AnttiArticle: 144243
John Speth wrote: > Altera has a nice tool called C to HDL compiler which I'm > looking at now. Have you considered the custom instruction feature of the NIOS? Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266 From prenom.nom@gmail.com Mon Nov 23 01:13:28 2009 Path: unlimited.newshosting.com!s02-b82!npeersf02.iad.highwinds-media.com!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!news.glorb.com!news2.glorb.com!feeder.erje.net!proxad.net!feeder1-2.proxad.net!cleanfeed1-a.proxad.net!nnrp10-1.free.fr!not-for-mail Date: Mon, 23 Nov 2009 10:13:28 +0100 From: Matthieu Michon <prenom.nom@gmail.com> Newsgroups: comp.arch.fpga Subject: Re: EDK11 under 64-bit OS Message-Id: <20091123101328.9dae9375.prenom.nom@gmail.com> References: <7mofa0F3h6og8U1@mid.individual.net> <7mog23F3gomnqU1@mid.individual.net> X-Newsreader: Sylpheed 2.7.1 (GTK+ 2.10.14; i686-pc-mingw32) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Lines: 22 Organization: Guest of ProXad - France NNTP-Posting-Date: 23 Nov 2009 10:13:28 MET NNTP-Posting-Host: 213.215.9.6 X-Trace: 1258967608 news-2.free.fr 21971 213.215.9.6:53321 X-Complaints-To: abuse@proxad.net Xref: unlimited.newshosting.com comp.arch.fpga:95580 X-Received-Date: Mon, 23 Nov 2009 09:13:28 UTC (s02-b82) On Fri, 20 Nov 2009 16:21:53 -0500 "MM" <mbmsv@yahoo.com> wrote: > On the same note, I would appreciate an advice on what kind of CPU makes the > most sense for today's and future Xilinx tools running under 64-bit Linux. > Should I get a quad core or dual core? And if someone wants to give me a > very specific advice it has to be Dell :) > Hi My company replaced my previous workstation last month with a Dell Precision T1500 (P55/Core-i7 architecture). Works great and the price difference with the T3500 series (X58/Xeon-35XX) allowed my to order a secondary display. One of my co-workers noticed a two-fold decrease in compiling time --on a large V5 SX50T design-- with a Precision T3500 (Xeon W3520 @2.66 GHz) over a Precision T3400 (Core-2 Duo E6300 @1.86 Ghz). With a dual-core Xeon 3500 series you will lose 4 MB of L3 cache memory, therefore I would suggest you to go with a quad-core Xeon 3520 series (Precision T3500) or with a Core-i7 (Precision T1500). Hope this helps. -- Matthieu Michon <prenom.nom@gmail.com>Article: 144244
Griffin <captain.griffin@gmail.com> writes: > ERROR:Place:864 - Incompatible IOB's are locked to the same bank 9 > Conflicting IO Standards are: > IO Standard 1: Name = LVCMOS25, VREF = NR, VCCO = 2.50, TERM = NONE > List of locked IOB's: > event_counter_0_pixels_in_pin<6> > IO Standard 2: Name = LVCMOS33, VREF = NR, VCCO = 3.30, TERM = NONE > List of locked IOB's: > fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0> > fpga_0_SRAM_Mem_A_pin<7> > fpga_0_SRAM_Mem_A_pin<8> > These IO Standards are incompatible due to VCCO mismatch. Have you stated IO standards for all your IOs? They will default to LVCMOS25 if not, which can leave you with a rogue LVCMOS25 IO in amongst a bunch of LVCMOS33s, which gives errors like you have above. <snip> > --- > > My peripheral is simple: > CHECK_PIXELS: process (Bus2IP_Clk) > begin -- process A couple of lines too simple, maybe :) You have no "if rising_edge (bus2ip_clk) then" here. At written, this process will run on both edges of the clock. What the synthesizer will do with it is unlikely to be helpful IME... I'm surprised it got as far as placement! <snip> Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 144245
Hi! I am designing a system that needs PCIe and multiboot operation. I would like to be able to reprogram the application FPGA at any moment. The safest option would be using a GN4124 and any FPGA. That would be clean and simple. But if you think of PCIe and multiboot then using a single Spartan6 comes out as the cheap and flexible option. I still have some doubts... What is the behaviour of the Spartan6 PCIe endpoint during a multiboot? Is it possible to use partial reconfiguration in such a way that the PCIe bus does not notice that the FPGA has been reprogrammed? Ok, let us assume that the PCIe end point is reset after an FPGA reconfiguration. Will the PCIe bus manager be able to handle it? Best Regards PabloArticle: 144246
I am looking at using the ISERDES block in a V5 design for a DDR2 controller. I want to input the DQ into an IODELAY block and then into the ISERDES. Problem is I am not sure that you can do this anymore. I have seen some old app notes with this configuration and a DDLY input on the ISERDES. But the new user guides dont have this input and they call the ISERDES a NODELAY block. Does anyone know anymore info regarding this? Jon --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144247
It looks like you can use the ISERDES with an IODELAY but you have to instantiate a Virtex 4 ISERDES not the Virtex 5 ISEDES_NODELAY. Just tried it with ISE and it mapped and p&r ok. Jon --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144248
Hi Matthieu, Which OS are you running? Can you see the usage for all of the 4 cores when you run MAP and/or PAR? Thanks, /Mikhail "Matthieu Michon" <prenom.nom@gmail.com> wrote in message news:20091123101328.9dae9375.prenom.nom@gmail.com... > On Fri, 20 Nov 2009 16:21:53 -0500 > "MM" <mbmsv@yahoo.com> wrote: > >> On the same note, I would appreciate an advice on what kind of CPU makes >> the >> most sense for today's and future Xilinx tools running under 64-bit >> Linux. >> Should I get a quad core or dual core? And if someone wants to give me a >> very specific advice it has to be Dell :) >> > > Hi > > > My company replaced my previous workstation last month with a Dell > Precision T1500 (P55/Core-i7 architecture). Works great and the price > difference with the T3500 series (X58/Xeon-35XX) allowed my to order a > secondary display. > > One of my co-workers noticed a two-fold decrease in compiling time --on a > large V5 SX50T design-- with a Precision T3500 (Xeon W3520 @2.66 GHz) over > a Precision T3400 (Core-2 Duo E6300 @1.86 Ghz). > > With a dual-core Xeon 3500 series you will lose 4 MB of L3 cache memory, > therefore I would suggest you to go with a quad-core Xeon 3520 series > (Precision T3500) or with a Core-i7 (Precision T1500). > > > Hope this helps. > -- > Matthieu Michon <prenom.nom@gmail.com>Article: 144249
I suggest that you post your question to rec.crafts.metalworking. "shereen.ahmed" <shereen.ahmed@gmail.com> wrote in message news:29e72e10-baa8-44e4-9477-8417941f219a@v30g2000yqm.googlegroups.com... >I simulate LDPC code over AWGN channel > I need to simulate over fading channel > How implement fading channel in matlab ? ad what is the modification > require in my code ?
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