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Hi, For sensitive analog application with FPGA you can use switch power supply as soon as you have a very good filtering strategy (ferrite + capa) In my FPGA past experience, i used a Switch supply as Main power supply (U > 12V => U = 5V) and then Linear regulator (3.3 / 2.5 / 1.2) I used this configuration for very precise clock (10-12 / sec) dedicated to military device and telecom syncrhonisation and also in railway application. If you used application schematic, and power supply recommend by Altera, Xilinx, Actel .... it will work fine !!! Alex On 10 nov, 12:09, Nick <es1...@gmail.com> wrote: > What are peoples' experiences of power supplies to sensitive analog > rails in FPGAs? > > For example, the guideline for both Xilinx and Altera all recommend > the use of linear regulators to supply such things as high speed > transceivers and PLLs. > > But does this really help? Is a linear reg really any better than > using switchers and good local filtering? Does the linear reg actually > filter out any noise itself, or is it only as good as its input (which > is quite probably another switcher!)? > > Thanks, > > NickArticle: 144076
Hello: Today I am announcing a series of blog posts about my views on HDL Design, hosted on the Sigasi website. If you are interested, here is the page: http://www.sigasi.com/JanHDL and the RSS feed: http://www.sigasi.com/taxonomy/term/52/0/feed Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.comArticle: 144077
Linear regulators are good as low frequency noise filters, but not the noise that is generated by switchers. The opamps in the analog signal path are not fast enough for the linear regulators to actively respond to noise much above 100 kHz. By 1 MHz they are pretty much useless. Did you make any measurements to verify that you had less noise on your FPGA rails? There is a great deal of "info" in the vendor's app notes that is overkill. Good design procedures are much better than blindly following app notes at a high level. Do the data sheets and app notes give you info on how much supply noise is tolerable so you can properly design your power supplies to specifications? Rick On Nov 10, 7:47=A0am, Alexandre <alexandre.lazar...@gmail.com> wrote: > Hi, > > For sensitive analog application with FPGA you can use switch power > supply as soon as you have a very good filtering strategy (ferrite + > capa) > In my FPGA past experience, i used a Switch supply as Main power > supply (U > 12V =3D> U =3D 5V) and then Linear regulator (3.3 / 2.5 / 1.2= ) > > I used this configuration for very precise clock (10-12 / sec) > dedicated to military device and telecom syncrhonisation and also in > railway application. > > If you used application schematic, and power supply recommend by > Altera, Xilinx, Actel .... it will work fine !!! > > Alex > > On 10 nov, 12:09, Nick <es1...@gmail.com> wrote: > > > What are peoples' experiences of power supplies to sensitive analog > > rails in FPGAs? > > > For example, the guideline for both Xilinx and Altera all recommend > > the use of linear regulators to supply such things as high speed > > transceivers and PLLs. > > > But does this really help? Is a linear reg really any better than > > using switchers and good local filtering? Does the linear reg actually > > filter out any noise itself, or is it only as good as its input (which > > is quite probably another switcher!)? > > > Thanks, > > > NickArticle: 144078
"akohan" <amit.kohan@gmail.com> wrote in message news:41604e94-0e1a-4965-a8e6-5019b35126bd@g22g2000prf.googlegroups.com... > > hi group, > > In following page, in what order should I start to learn about Virtex > 4 ? > > > http://www.xilinx.com/support/documentation/virtex-4_user_guides.htm > Start with the Virtex-4 FPGA User Guide, the third from the top. /MikhailArticle: 144079
I use xflow, it has a couple small advantages over batch/shell script. One is that you don't have to do any exit code checking, xflow will automatically stop if one of the backend tools fails. Another is that the format of the file lends itself to commenting the various tool options a little cleaner that a batch/script would. I haven't done this, but I believe that xflow can rerun only a portion of the flow, for example static timing or bitgen, depending on the command line arguments. What it can't do (I don't think) is run a point tool more than once. I usually run static timing twice, once for an error report and once for an unconstrained path report. I can't get xflow to run both of these reports in a single invocation. I haven't used XST so I can't comment on that part. --steve "Dave" <doomeddave@yahoo.co.uk> wrote in message news:53b2d3d7-69e3-4454-b5f4-b1c13ad5d469@v25g2000yqk.googlegroups.com... : Hi Group, : : In the past when I have wanted to use a script with ISE I have always : simply run the flow using the gui first and then created a batch file : using the command lines printed in the individual reports from xst, : ngdbuild, etc. Seemed to work quite well especially when using the : errorlevel returns (in Windows) to catch errors. : : I am aware of the xflow system and that something can also no doubt be : done using tcl and I am wondering what the "best" method is. : : What do you use and why? : : One key feature I want to include in the design I'm starting now is : automatic build number increments by way of automatically increasing : an integer generic supplied to XST. This will be used to set the : reset value of a register in the VHDL. I am guessing a tcl script : would be best for this but can this also be done using xflow? : : Many thanks for your time.Article: 144080
I tried creating a new account, but it tells me "The CAPTCHA field is required." and no captcha field is visible. Did someone forget something on this page? Rick On Nov 10, 10:18=A0am, Jan Decaluwe <j...@jandecaluwe.com> wrote: > Hello: > > Today I am announcing a series of blog posts about my > views on HDL Design, hosted on the Sigasi website. > > If you are interested, here is the page: > =A0 =A0http://www.sigasi.com/JanHDL > and the RSS feed: > =A0 =A0http://www.sigasi.com/taxonomy/term/52/0/feed > > Jan > > -- > Jan Decaluwe - Resources bvba -http://www.jandecaluwe.com > =A0 =A0Python as a HDL:http://www.myhdl.org > =A0 =A0VHDL development, the modern way:http://www.sigasi.com > =A0 =A0Analog design automation:http://www.mephisto-da.com > =A0 =A0World-class digital design:http://www.easics.comArticle: 144081
The captcha iss clearly visible in my browser. I'm using firefox 3.5.5 with adblock plus enabled. It's immediately below the phrase "Word verification". ~Zheng On Tue, 10 Nov 2009 08:42:11 -0800 (PST) rickman <gnuarm@gmail.com> wrote: > I tried creating a new account, but it tells me "The CAPTCHA field is > required." and no captcha field is visible. Did someone forget > something on this page? >=20 > Rick >=20 >=20 >=20 > On Nov 10, 10:18=A0am, Jan Decaluwe <j...@jandecaluwe.com> wrote: > > Hello: > > > > Today I am announcing a series of blog posts about my > > views on HDL Design, hosted on the Sigasi website. > > > > If you are interested, here is the page: > > =A0 =A0http://www.sigasi.com/JanHDL > > and the RSS feed: > > =A0 =A0http://www.sigasi.com/taxonomy/term/52/0/feed > > > > Jan > > > > -- > > Jan Decaluwe - Resources bvba -http://www.jandecaluwe.com > > =A0 =A0Python as a HDL:http://www.myhdl.org > > =A0 =A0VHDL development, the modern way:http://www.sigasi.com > > =A0 =A0Analog design automation:http://www.mephisto-da.com > > =A0 =A0World-class digital design:http://www.easics.com >=20Article: 144082
On 10 Nov., 12:09, Nick <es1...@gmail.com> wrote: > What are peoples' experiences of power supplies to sensitive analog > rails in FPGAs? _How_ sensitive is always the question. And at which frequency. And if it is correlated to some working/sampling/processing frequency or not. > For example, the guideline for both Xilinx and Altera all recommend > the use of linear regulators to supply such things as high speed > transceivers and PLLs. As long as you're using non-ldo's with good PSRR and good pre- filtering you are quite safe. LDO's may have a ugly PSRR depending on dropout. Pre-filtering for the worsening PSRR at high frequencies of analog regulators may also become big at the current you want. > But does this really help? Is a linear reg really any better than > using switchers and good local filtering? Does the linear reg actually > filter out any noise itself, or is it only as good as its input (which > is quite probably another switcher!)? PSRR is freqency dependent. Look at the DS. And be careful with switchers, as they may switch between two operating modes for better low load efficency creating ugly noise which would demand a huge post filter. But using a good switcher which doesnt have similar problems LC post filtering for the analog part may work good.Article: 144083
Dave <doomeddave@yahoo.co.uk> writes: > What do you use and why? Well, I've mostly used a "straight up" script file to just run the commands, which is fine but not very flexible. But it doesn't eat much in the way of developement time either. At a customer site once they had a perl script to run the flow which was pretty handy. It read tool options and file names from a config file, so tweaking settings was easy. There was also the option to start the flow from a certain point. On the other hand the script was typical perl spaghetti code, so I didn't want to touch it and it only went as far as bitgen. We needed to insert software and produce both an MCS and a special byte swapped raw binary. We also had slightly complicated synthesis which we basically did by hand, in a few steps. Also we used Chipscope and again we had to do the insertion part by hand every time, but after that the script was again useful since we could start it from the right phase after Chipscope insertion. Based on this, flexibility and maintainability is useful especially in a large project and if you want to use your script in different projects. But then, that goes for any software...Article: 144084
Hi, I'm working on an Xilinx Spartan FPGA design which will consists of the following main blocks, with corresponding clock domain and frequency: SPI_slave (sclk - 30MHz) Main_logic (mclk - needs a minimum of 24MHz) Coming from an ASIC background, I would do this with two separate clock domains, with the appropriate 'resync' logic between them. As far as I know, I can do this on the FPGA as well. However, the 'sclk' would need to come in from a 'dedicated' clock pin. This imposes additionnal constraint on the board layout and design, and complicates changing FPGA later on. The other option is to 'resync' everything to mclk. Although this seems 'cleaner', it imposes a constraint on the minimum 'mclk' required. I would need to run the whole thing at >100Mhz to be able to resync the 30MHz 'sclk' with no worries. I don't care about power, but I already see my simple design now requiring the use of multi-cycle paths etc...I'd like to avoid this! So here it is: -could the SPI_slave module run using 'sclk' directly, without using a dedicated clock pin? -is this a good idea? -what do FPGA people do when they have to deal with 6-10 clock domains? Thank you very much, DiegoArticle: 144085
On Nov 10, 10:33=A0am, "dlopez" <d...@designgame.ca> wrote: > > So here it is: > -could the SPI_slave module run using 'sclk' directly, without using a > dedicated clock pin? Yes. 30MHz is no big deal (anymore). > -is this a good idea? Why not? Run the serial part at 'sclk', the parallel part at 'mclk'. > -what do FPGA people do when they have to deal with 6-10 clock domains? Watch their hair fall out and wish they had an ASIC. Or redesign so that the bulk of it runs on just one clock. > > Thank you very much, > > DiegoArticle: 144086
dlopez wrote:
> Coming from an ASIC background, I would do this with two separate clock
> domains, with the appropriate 'resync' logic between them.
>
> As far as I know, I can do this on the FPGA as well.
Yes.
> However, the 'sclk'
> would need to come in from a 'dedicated' clock pin. This imposes
> additional constraint on the board layout and design, and complicates
> changing FPGA later on.
If I'm spinning the board anyway, what's the complication?
> The other option is to 'resync' everything to mclk.
I would run everything on 30 MHz.
> So here it is:
> -could the SPI_slave module run using 'sclk' directly, without using a
> dedicated clock pin?
Run static timing and find out.
> -is this a good idea?
> -what do FPGA people do when they have to deal with 6-10 clock domains?
I would try to put everything on the fastest clock.
Clock enables are free on FPGAs
-- Mike Treseler
Article: 144087On Nov 10, 1:33=A0pm, "dlopez" <d...@designgame.ca> wrote: > Hi, > I'm working on an Xilinx Spartan FPGA design which will consists of the > following main blocks, with corresponding clock domain and frequency: > > SPI_slave (sclk - 30MHz) > Main_logic (mclk - needs a minimum of 24MHz) > > Coming from an ASIC background, I would do this with two separate clock > domains, with the appropriate 'resync' logic between them. > > As far as I know, I can do this on the FPGA as well. However, the 'sclk' > would need to come in from a 'dedicated' clock pin. This imposes > additionnal constraint on the board layout and design, and complicates > changing FPGA later on. > > The other option is to 'resync' everything to mclk. Although this seems > 'cleaner', it imposes a constraint on the minimum 'mclk' required. I woul= d > need to run the whole thing at >100Mhz to be able to resync the 30MHz > 'sclk' with no worries. I don't care about power, but I already see my > simple design now requiring the use of multi-cycle paths etc...I'd like t= o > avoid this! > > So here it is: > -could the SPI_slave module run using 'sclk' directly, without using a > dedicated clock pin? > -is this a good idea? > -what do FPGA people do when they have to deal with 6-10 clock domains? > > Thank you very much, > > Diego As others have noted, at 30 MHz you don't need to use a global clock pin, although the tools will bark at you for running on a non-global pin. Non-global pins incur a significant additional delay, so you need to be sure your inputs meet the hold time requirements. I've done several FPGA designs that needed more clock domains than there were global clock nets (in Spartan 2, with only 4 global clocks this happens easily). I built my own little clock-crossing circuit using local routing for the input clock and using both edges of the clock to avoid internal hold-time issues. Normally modern FPGA's can handle more clock domains with regional clock routing that doesn't need to go to this extent. FIFO's are relatively easy to add to the design using distributed memory for short FIFO's where you don't need to deal with build-up of bursty input data. My clock-crossing circuit was basically a 16-deep FIFO that required the output clock to run faster than the input and uses only one bit of depth, so the output always gets 8 clocks worth of data in a row. Since the process is continuous there is no need to empty the "FIFO". HTH, GaborArticle: 144088
On Nov 10, 10:18=A0am, Jan Decaluwe <j...@jandecaluwe.com> wrote: > Hello: > > Today I am announcing a series of blog posts about my > views on HDL Design, hosted on the Sigasi website. > > If you are interested, here is the page: > =A0 =A0http://www.sigasi.com/JanHDL > and the RSS feed: > =A0 =A0http://www.sigasi.com/taxonomy/term/52/0/feed > > Jan > > -- > Jan Decaluwe - Resources bvba -http://www.jandecaluwe.com > =A0 =A0Python as a HDL:http://www.myhdl.org > =A0 =A0VHDL development, the modern way:http://www.sigasi.com > =A0 =A0Analog design automation:http://www.mephisto-da.com > =A0 =A0World-class digital design:http://www.easics.com O.K., since you posted this to comp.lang.verilog I have to ask if Sigasi HDT will be supporting Verilog? Regards, GaborArticle: 144089
On Nov 10, 8:59=A0am, -jg <jim.granvi...@gmail.com> wrote: Hi Jim, thanks for trying to help. > ... > Xilinx used to include some .abl source examples - if you search for > .abl, what do you find ? Nothing. This in what I downloaded from xilinx' site a month (or was it a few months) ago. It installed 4-5 separate things, all useless so far. Impact 11, ISE 11, Plan ahead 11, system generator 11, some accelDSP 11 thing. No .abl files to be seen. After a few hours of toying with the schematics tool I could not make it assign pins - just put a 74161 and wanted it to compile, no - it wants me to edit the vhdl file to finish, just does not work. Then I tried to start that "plan ahead" thing - just as useless, it offers me only FPGA choices. The rest of the applications appear to be stuff I won't ever need. I located a CD here I with their webpack 3.2 - it has survived somehow. It does get installed and there are 4 .abl files on it - the syntax looks sane enough. But (on the menus) I can see no way to make it generate a jedec file, this is probably done by the programmer part (the second icon it installed) which just does not work, pollutes the whole screen with "OK" windows in a loop (probably because it does not find its programmer). So I seem to be stuck - no Xilinx tool I have managed to locate so far will do Abel -> jedec. Paying them up to let me do that is not an option I would even consider. Can you please suggest something you have used and know it will work? Thanks, Dimiter ------------------------------------------------------ Dimiter Popoff Transgalactic Instruments http://www.tgi-sci.com ------------------------------------------------------ http://www.flickr.com/photos/didi_tgi/sets/72157600228621276/Article: 144090
On Nov 11, 3:17=A0am, Didi <d...@tgi-sci.com> wrote: > .... > So I seem to be stuck - no Xilinx tool I have managed to locate > so far will do Abel -> jedec. > .... No longer that. I located on my disk something I had downloaded some months back while planning this effort - webpack 6.3i., on someones advice IIRC. It does seem to compile ABEL files, gets stuck at the end (with my source only) so far but this is after it generates the jedec file which is what I am after. Cannot see what it thinks it has done in the html report (it just does not work, "child process failed"), but well, this is a step in the right direction. But I am sure I will have to invest a few weeks into integrating the xpla3 into my logic compiler, these xilinx tools just are not usable. Here is a simple source for a 64 cell coolrunner from the Philips times: http://tgi-sci.com/misc/mb2ata.txt , I am used to be able to generate that within < a day... I will of course still welcome all help, I am still far from done with this. Dimiter ------------------------------------------------------ Dimiter Popoff =A0 =A0 =A0 =A0 =A0 =A0 =A0 Transgalactic Instruments http://www.tgi-sci.com ------------------------------------------------------ http://www.flickr.com/photos/didi_tgi/sets/72157600228621276/Article: 144091
On Nov 11, 5:43=A0pm, Didi <d...@tgi-sci.com> wrote: > > I will of course still welcome all help, I am still far from > done with this. > > Dimiter > I have a handful of ABL files on a Xilinx stub here, I can compile those and zip the results if you give an email ? -jgArticle: 144092
gabor wrote:
> On Nov 10, 10:18 am, Jan Decaluwe <j...@jandecaluwe.com> wrote:
>> Hello:
>>
>> Today I am announcing a series of blog posts about my
>> views on HDL Design, hosted on the Sigasi website.
> O.K., since you posted this to comp.lang.verilog I have to
> ask if Sigasi HDT will be supporting Verilog?
There are plans (of course), but not yet a schedule.
Hopefully, this blog will make the site more useful for
everyone interested in the concepts behind HDL design.
For the most part, these are language neutral. For Sigasi,
this is the public they like to interact with to steer
future developments.
Regards,
Jan
--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Python as a HDL: http://www.myhdl.org
VHDL development, the modern way: http://www.sigasi.com
Analog design automation: http://www.mephisto-da.com
World-class digital design: http://www.easics.com
Article: 144093On Nov 11, 8:24=A0am, -jg <jim.granvi...@gmail.com> wrote: > On Nov 11, 5:43=A0pm, Didi <d...@tgi-sci.com> wrote: > > > I will of course still welcome all help, I am still far from > > done with this. > > > Dimiter > > I have a handful of ABL files on a Xilinx stub here, I can compile > those and zip the results if you give an email ? > > -jg Thanks Jim, I'll ask for that if I get stuck again. But for now I seem to be through, I managed to do some simplest code (1 toggling bit shifted through 5 others, just what I typed in without thinking) and lo and behold, this not only made it through the xilinx tool but got programmed into the part by my jedec->isp translator and my jtag thing... To my amazement the correct pins are toggling :-). Dimiter P.S. BTW, my email address here ( dp@tgi-sci.com ) is valid, in case you need it.Article: 144094
On Nov 11, 7:24=A0pm, -jg <jim.granvi...@gmail.com> wrote: > On Nov 11, 5:43=A0pm, Didi <d...@tgi-sci.com> wrote: > > > I will of course still welcome all help, I am still far from > > done with this. > > > Dimiter > > I have a handful of ABL files on a Xilinx stub here, I can compile > those and zip the results if you give an email ? > > -jg I've blown the dust off the directory(s), and it barfed on converting the old projects - but it happily made new ones. * new Project (name becomes subdir) * right click add source [select .ABL file] * double click on device, select XCR3128XL * click on source * Double click on Fitter report in process list * Double click on generate Jtag file in process list and voila, truckloads of files, but the ones that matter are .rpt, and .jed If I right-click on [fit].properties, I can select HDL equation style, where you can choose Source/ABEL/Verilog/VHDL, and that's what it uses in the fitter report files. - select the most readable This is a legacy tool chain, but Xilinx can't have broken any of this, on newer versions can they ?! ;) -jgArticle: 144095
On Nov 11, 9:46=A0am, -jg <jim.granvi...@gmail.com> wrote: > On Nov 11, 7:24=A0pm, -jg <jim.granvi...@gmail.com> wrote: > > > On Nov 11, 5:43=A0pm, Didi <d...@tgi-sci.com> wrote: > > > > I will of course still welcome all help, I am still far from > > > done with this. > > > > Dimiter > > > I have a handful of ABL files on a Xilinx stub here, I can compile > > those and zip the results if you give an email ? > > > -jg > > I've blown the dust off the directory(s), and it barfed on converting > the old projects - but it happily made new ones. > * new Project =A0(name becomes subdir) > * right click add source [select .ABL file] > * double click on device, select XCR3128XL > * click on source > =A0 * Double click on Fitter report in process list > =A0 * Double click on =A0generate Jtag file in process list > > and voila, truckloads of files, but the ones that matter are .rpt, > and > .jed > > If I right-click on [fit].properties, I can select HDL equation style, > where you can choose Source/ABEL/Verilog/VHDL, and that's what it uses > in the fitter report files. - select the most readable > > This is a legacy tool chain, but Xilinx can't have broken any of this, > on newer versions can they ?! ;) > > -jg sure they can break any legacy with any minor update of the tools they can AnttiArticle: 144096
On Nov 11, 9:09=A0pm, Antti <antti.luk...@googlemail.com> wrote: > > This is a legacy tool chain, but Xilinx can't have broken any of this, > > on newer versions can they ?! ;) > > > -jg > > sure they can > break any legacy with any minor update of the tools > they can Antti - Did you miss the winky ?? ;) I've sent Dimiter a disk image of an .ABL project compiled into a XCR3128, so he can check what has changed.... Who knows, the gods might even smile, and given him the same answer...?! -jgArticle: 144097
On Nov 11, 11:13=A0am, -jg <jim.granvi...@gmail.com> wrote: > On Nov 11, 9:09=A0pm, Antti <antti.luk...@googlemail.com> wrote: > > > > This is a legacy tool chain, but Xilinx can't have broken any of this= , > > > on newer versions can they ?! ;) > > > > -jg > > > sure they can > > break any legacy with any minor update of the tools > > they can > > Antti - Did you miss the winky =A0?? =A0;) > > I've sent Dimiter a disk image of an .ABL project compiled into a > XCR3128, so he can check what has changed.... > > Who knows, the gods might even smile, and given him the same > answer...?! > > -jg Thanks Jim, I'll hopefully know more after some sleep (dead tired now). Why am I getting to sleep at 12 AM is another story, I get out of sync sometimes and the I get back an hour per day (yesterday it was 10 AM but today I pushed it some more). DimiterArticle: 144098
hi... i m using edk 10.1 version.i m new to edk.now i m able to create simple pheripheral(it is not having any submodules and user libaries). actualy my code having many submodules and user libraries.please can any one tell how to add other suhmodules and user libraries with custom pherpheral using create or import pheripheral wizard.or how compile my libaries and submodules in the custom pheripheral directory.if any tells it will be more usefull for me. thanku....Article: 144099
On Mon, 9 Nov 2009 13:28:12 -0600 "Steve Ravet" <steve.ravet@arm.com> wrote: > If you're using makefiles, you might want to investigate xflow, which > is the xilinx flow manager. It takes a text file which has all the > options for all the backend tools, runs the tools in order, checking > the status of the previous step before running the next step. It's > similar to a makefile flow but more flexible I'd say. >=20 > Outside of some vendor training classes I've never actually run the > ISE gui. >=20 =46rom your description, the other thread on here, and a quick read on Xilinx's site, it seems like it's a bit of a domain-specific reimplementation of make with particular quirks. I suppose the upside is that it's supported under windows as well, where you don't usually get make without a bit of effort.=20 I am somewhat surprised about the assertion that it's more flexible than make, as the entire point of make is to be as generic and flexible as possible.=20 Thanks for pointing it out, as I was previously unaware of it, and it might come in handy one day.=20 //Oscar
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