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W A:
84094: 05/05/12: How to turn off auto bufg insertion in ISE 7.1 ???
84195: 05/05/13: Re: How to turn off auto bufg insertion in ISE 7.1 ???
84402: 05/05/18: Re: Detaching the schematic viewer under ISE Webpack
W. C. Wilson:
1487: 95/06/28: Backannotation to Leapfrog
W. Oswald:
198: 94/09/19: Re: Partly reconfigurable FPGAs
W. S. Zuk:
2395: 95/11/28: Re: NeoCAD and AT&T vs. Xilinx
7687: 97/10/02: Re: High Speed FPGAs
W. Scott Cranston:
2449: 95/12/06: Re: Altera Verilog Problems
W.Turk:
29389: 01/02/18: what
29493: 01/02/23: how do i?
30394: 01/04/05: Modlesim5.5
wa11:
70676: 04/06/23: Virtex II slave selectMap config mode
90791: 05/10/21: netgen port renaming
Waage:
89822: 05/09/27: Sythesis software for Virtex-4
89827: 05/09/27: I am planning to purchase a Virtex-4 Eval board.
89857: 05/09/28: Re: Sythesis software for Virtex-4
89868: 05/09/28: Using 3rd Party FPGA flows and Xilinx
89980: 05/09/30: Synthesis with Icarus Verilog
90291: 05/10/08: 3rd party JTAG cables/controllers for Virtex-4
90324: 05/10/10: Re: 3rd party JTAG cables/controllers for Virtex-4
90471: 05/10/13: Linux and Platform USB Cable
90586: 05/10/17: Re: Linux and Platform USB Cable
90765: 05/10/20: Avnet Technical Support Terrible!!!
90768: 05/10/20: Re: Avnet Technical Support Terrible!!!
90788: 05/10/20: Re: Avnet Technical Support Terrible!!!
90826: 05/10/21: Re: Avnet Technical Support Terrible!!!
91087: 05/10/28: Re: Avnet Technical Support Terrible!!!
<wabac0@gmail.com>:
156938: 14/07/31: Professional VHDL Examples?
<wachob~c@lazerlink.com>:
10157: 98/04/30: Schematic entry -> JEDEC fpr CPLD??
Wade:
58599: 03/07/28: Re: asynchronous FIFO
Wade D. Peterson:
6948: 97/07/14: Best FPGA language for portability
7082: 97/07/30: Re: Design Protection in FPGAs
7091: 97/07/30: Re: Design Protection in FPGAs
7138: 97/08/05: Re: Are 2 PCs better than One?
7169: 97/08/09: Re: Price of Serial EEPROM is Outrageous
7187: 97/08/12: Re: Price of Serial EEPROM is Outrageous
7209: 97/08/14: Re: Price of Serial EEPROM is Outrageous
7212: 97/08/15: Re: Price of Serial EEPROM is Outrageous
7890: 97/10/27: XILINX pin compatible replacements
8305: 97/12/07: Re: A suggestion for Xilinx
9534: 98/03/21: Re: question fpga?
11188: 98/07/24: Silicore VHDL 8-bit RISC uC core for FPGA
11203: 98/07/24: Re: Silicore VHDL 8-bit RISC uC core for FPGA
11213: 98/07/26: Re: Delay Element for async design.
11284: 98/08/02: Re: how much ? prices of Xilinx chips
11335: 98/08/05: Re: Silicore VHDL 8-bit RISC uC core for FPGA
11345: 98/08/05: Re: Silicore VHDL 8-bit RISC uC core for FPGA
11369: 98/08/07: Re: Silicore VHDL 8-bit RISC uC core for FPGA
11391: 98/08/09: Re: Radiation and Relaibility
11285: 98/08/02: Re: Examples of report on FPGA
11326: 98/08/05: Re: VHDL std_logic_vector to integer
11521: 98/08/20: Silicore announces 8-Bit RISC uP / VHDL IP Core for FPGA
11572: 98/08/25: Re: PROM alternative
11716: 98/09/03: Re: Curious problem...FPGA/CPLD Architecture and Logic Implementations
11717: 98/09/03: Re: Design Re-use, IP cores, Megafunctions, etc...
11751: 98/09/07: Re: 22V10 programming
11842: 98/09/13: Re: ASIC -> FPGA async issues
12442: 98/10/12: Re: Processor Cores
12478: 98/10/13: Re: FOCUS FOCUS FOCUS
12745: 98/10/27: Re: FPGA Decouple Capacitor values
12927: 98/11/05: Re: A suggestion for Xilinx
12928: 98/11/05: Re: Parallel port interface
13166: 98/11/18: Re: CPUs: Big Endianness vs Small Endianness
13377: 98/11/30: Re: Will XILINX survive?
13382: 98/11/30: Re: Will XILINX survive?
13408: 98/12/01: Re: Will XILINX survive?
13410: 98/12/01: Re: Will XILINX survive?
13525: 98/12/08: Re: Will XILINX survive?
14173: 99/01/17: Re: 300 MHz core with 50 MHz bus
14430: 99/01/29: Re: Hazard
14939: 99/02/25: Re: Your view on this article?
16937: 99/06/17: WISHBONE Interconnection Standard for IP Core Reuse
16949: 99/06/18: Re: Read/Writes to memories/register files for PIC core
16951: 99/06/18: Re: Read/Writes to memories/register files for PIC core
17144: 99/07/02: Re: neuron logic
17206: 99/07/08: Re: Benchmark circuits - in VHDL for FPGA
17303: 99/07/19: Re: License sharing for synopsys/cadence/modeltech
17379: 99/07/23: System-on-Chip and its effect on VMEbus / uC Bus Products
17405: 99/07/24: Microcomputer buses for use inside FPGA/ASIC devices?
17409: 99/07/25: Re: Microcomputer buses for use inside FPGA/ASIC devices?
17418: 99/07/26: Re: Microcomputer buses for use inside FPGA/ASIC devices?
17429: 99/07/27: Re: Microcomputer buses for use inside FPGA/ASIC devices?
17435: 99/07/27: Re: Microcomputer buses for use inside FPGA/ASIC devices?
17440: 99/07/28: Re: Microcomputer buses for use inside FPGA/ASIC devices?
17459: 99/07/29: Re: Microcomputer buses for use inside FPGA/ASIC devices?
17474: 99/07/30: Re: Microcomputer buses for use inside FPGA/ASIC devices?
17482: 99/07/30: Re: Microcomputer buses for use inside FPGA/ASIC devices?
17557: 99/08/10: Re: Emulating a transputer on FPGA
17627: 99/08/16: Re: VHDL/Verilog? - Can of Worms
17906: 99/09/16: Re: PCI core for Orca 3T
18085: 99/09/28: Lucent FPGA with PCI hard core
18090: 99/09/29: =?iso-8859-1?Q?Re:_Performance_of_reprogrammable_FPGA=B4s=3F?=
18130: 99/10/02: Re: Producing 60/40 clock in vhdl
18131: 99/10/02: Re: Lucent FPGA with PCI hard core
28408: 01/01/11: Latest on: WISHBONE System-on-chip (SoC) Interconnection Architecture for Portable IP Cores
30167: 01/03/26: Alternatives for Xilinx Spartan-II configuration PROM
31621: 01/05/31: Second source for Altera EPC1 or EPC2 configuration devices
35905: 01/10/23: WISHBONE / SoC Interconnect / IP Core
37089: 01/11/29: Re: Spartan2 problems with 5V periphery
60323: 03/09/10: Silicore adopts open source business model for semiconductor IP; releases SLC1657 uP core under LGPL license
Wade Hassler:
140315: 09/05/08: Re: Quartus II negative bus dimensions in Schematic file
Wade Nelson:
7856: 97/10/23: FPGA Synthesis Tools - Synplicity, Exemplar, Synopsis
<wade_h@saber.net>:
81056: 05/03/16: Re: Altera free web FPGA software license question
Wagner:
11146: 98/07/21: Re: EEPROM <> XC1700 ?
waing gyi:
131261: 08/04/17: Re: Xilinx and Modelsim?
<waishanl@gmail.com>:
109522: 06/09/27: ddr2 sodimm controller
109560: 06/09/28: Re: ddr2 sodimm controller
walala:
50097: 02/12/02: anybody used synopsys pathmill give me a hand please
59344: 03/08/15: where can I find DWT source code(verilog or vhdl)?
59864: 03/08/30: how to design this datapath unit for DSP using VHDL/Verilog?
59881: 03/08/30: Re: how to design this datapath unit for DSP using VHDL/Verilog?
60060: 03/09/04: How to contact the writer of Xilinx FPGA application notes?
63403: 03/11/20: graphic card accelarator vs. FPGA: which is better for the following task?
63574: 03/11/25: Re: graphic card accelarator vs. FPGA: which is better for the following task?
63576: 03/11/25: what is the fastest speed that FPGA deals with CPU?
63624: 03/11/26: Re: what is the fastest speed that FPGA deals with CPU?
63668: 03/11/27: Re: what is the fastest speed that FPGA deals with CPU?
63669: 03/11/27: Re: what is the fastest speed that FPGA deals with CPU?
63670: 03/11/27: Re: graphic card accelarator vs. FPGA: which is better for the following task?
Waldek Hebisch:
158797: 16/04/09: Re: FPGA Internal or external USB PHY/SIE ??
walke:
94002: 06/01/04: Re: Serious Typo in the Xilinx Floating-Point Core Manual?
Wallace V Rose:
12388: 98/10/10: Re: test
12389: 98/10/10: Re: test
12390: 98/10/10: Re: FIR Filter Design
12470: 98/10/12: Re: FIR Filter Design
<wallace_exemplar@my-dejanews.com>:
12708: 98/10/24: Re: Need VHDL tools for Win NT/ Win 95
wallge:
110299: 06/10/13: multithreaded Synthesis and Place and route... Finally!
112709: 06/11/27: problems with verilog SDRAM models
112880: 06/11/30: Re: Thesis
112881: 06/11/30: Re: wanted: FPGA programmer
112884: 06/11/30: Re: Can I see the detail timing parameter by Quartus II tools?
112894: 06/11/30: Re: Can I see the detail timing parameter by Quartus II tools?
113174: 06/12/07: Re: FPGA to Camera (Channel) link
113243: 06/12/08: computer vision projects for open cores
113342: 06/12/11: Re: approximation of an exponential ramp?
113388: 06/12/12: Re: Camera Link to XUP V2Pro Board
114102: 07/01/04: iterative algorithms + tightly coupled CPU with cloud of logic in FPGA
114282: 07/01/10: inserting text into a video stream (from a pre-existing video source)
114329: 07/01/11: Re: inserting text into a video stream (from a pre-existing video source)
114359: 07/01/12: Re: inserting text into a video stream (from a pre-existing video source)
114731: 07/01/23: Good hardware design code re-use strategies, reference book
114820: 07/01/24: video buffering scheme, nonsequential access (no spatial locality)
114872: 07/01/25: Re: video buffering scheme, nonsequential access (no spatial locality)
114881: 07/01/25: Re: video buffering scheme, nonsequential access (no spatial locality)
114892: 07/01/25: Re: video buffering scheme, nonsequential access (no spatial locality)
114933: 07/01/26: Re: video buffering scheme, nonsequential access (no spatial locality)
115009: 07/01/29: Re: video buffering scheme, nonsequential access (no spatial locality)
115070: 07/01/30: Re: video buffering scheme, nonsequential access (no spatial locality)
116102: 07/03/01: suggestions for good MPEG encoder dev kit, embedded hard disk dev kit
116107: 07/03/01: Re: suggestions for good MPEG encoder dev kit, embedded hard disk dev kit
116113: 07/03/01: Re: suggestions for good MPEG encoder dev kit, embedded hard disk dev kit
116233: 07/03/05: Re: Ideas for Masters Project.
117580: 07/04/04: TFP410 acceptable video input timings (trying to run 1280x1024 at 60Hz with clock slower than 108 MHz)
117682: 07/04/06: Re: TFP410 acceptable video input timings (trying to run 1280x1024 at 60Hz with clock slower than 108 MHz)
117845: 07/04/11: has anyone used mathstar field programmable object arrays?
117890: 07/04/12: Re: has anyone used mathstar field programmable object arrays?
118300: 07/04/23: Re: VHDL editing with UltraEdit
121325: 07/07/02: Re: How to choose FPGA for a huge computation?
129141: 08/02/15: PC configuration for fastest compiles (synthesis, place and route,
134659: 08/08/25: Analog Imager interface to FPGA
134662: 08/08/25: Re: Analog Imager interface to FPGA
134670: 08/08/25: Re: Analog Imager interface to FPGA
134712: 08/08/27: Re: Analog Imager interface to FPGA
135038: 08/09/11: Quartus II compile speedup with New Quad Core Intel machine (compared
135057: 08/09/12: Re: Quartus II compile speedup with New Quad Core Intel machine
141104: 09/06/05: digital RGB Video to Analog VGA triple DAC question
141112: 09/06/06: Re: digital RGB Video to Analog VGA triple DAC question
141161: 09/06/09: Re: dsp with fpgas by Uwe Meyer-Baese
141248: 09/06/12: NTSC/PAL Encoder using FPGA and DAC
141305: 09/06/16: 5.0V and 3.3V PCI interfacing with Altera Cyclone III
141320: 09/06/17: Re: 5.0V and 3.3V PCI interfacing with Altera Cyclone III
147587: 10/05/05: sopc builder custom component and passing parameters to VHDL package
<wallge@gmail.com>:
96511: 06/02/05: Re: advanced vhdl lerning
wallra:
135532: 08/10/06: learning videos for xilinx edk tools
136297: 08/11/10: hi all
136315: 08/11/10: Re: hi all
136582: 08/11/23: hi need help in VHDL code For Input sequence Design
136811: 08/12/06: Re: hi all
Wally:
32997: 01/07/14: Re: WTB:50 Mhz 24 CHANNEL LOGIC ANALYZER only $199
Wally Daniels:
54843: 03/04/20: Moving from PAL's to Altera ATF750 Series
54854: 03/04/20: Re: Moving from PAL's to Altera ATF750 Series
wallytempe:
49896: 02/11/24: Re: Why do post-synthesis simulation result fall into unknow output state 'X' or "XX..."?
Walt:
25686: 00/09/17: Freelance Designer Needed: Protel & FPGA
34156: 01/08/15: Re: Development Boards for FPGA based Application
45674: 02/07/31: Re: VirtexE : OrCAD capture part symbol
Walt Bax:
14695: 99/02/12: reconfiguring Logiblox ROM's
Walt Manaker:
1607: 95/07/26: Re: "Circuit Loops" in NeoCad??
Walter:
101631: 06/05/03: Re: Interfacing Spartan 3 board to PC parallel port??
128913: 08/02/09: Re: Prom alternatives for xilinx
141623: 09/07/01: Re: pinout
142481: 09/08/12: Re: System gates: Altera <-> Actel
144323: 09/11/26: Re: webpack crashed how do I get these things back?
145178: 10/01/30: Re: In system memory editor of Altera for Xilinx
145185: 10/01/31: Re: In system memory editor of Altera for Xilinx
149472: 10/10/27: Re: using FPGA editor to add a new output pin
151643: 11/04/29: Re: same RTL on two same boards giving different behaviour
walter:
17749: 99/08/30: Re: looking for image processing hardware
Walter Banks:
76851: 04/12/14: Re: Introducing MANIK - a 32 bit Soft-Core RISC Processor
106974: 06/08/23: Re: CPU design
107506: 06/08/29: Re: CPU design
107622: 06/08/30: Re: CPU design
130298: 08/03/19: Re: A Challenge for serialized processor design and implementation
130320: 08/03/20: Re: A Challenge for serialized processor design and implementation
130322: 08/03/20: Re: A Challenge for serialized processor design and implementation
130331: 08/03/20: Re: A Challenge for serialized processor design and implementation
130567: 08/03/27: Re: A Challenge for serialized processor design and implementation
130575: 08/03/27: Re: A Challenge for serialized processor design and implementation
130578: 08/03/27: Re: A Challenge for serialized processor design and implementation
130594: 08/03/27: Re: A Challenge for serialized processor design and implementation
130595: 08/03/27: Re: A Challenge for serialized processor design and implementation
138856: 09/03/12: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138869: 09/03/12: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138885: 09/03/13: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138893: 09/03/13: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
138924: 09/03/14: Re: Nibz processor @ <570 MAXII LEs (16 bit generic specified), 20MHz
142585: 09/08/18: Re: Soft Processor IP core report
155827: 13/09/26: Re: Legal Issues Reproducing Old CPU
156178: 14/01/09: Re: addsubs on FPGA
156633: 14/05/16: Re: need coding
158108: 15/08/10: Re: Finally! A Completely Open Complete FPGA Toolchain
158114: 15/08/11: Re: Finally! A Completely Open Complete FPGA Toolchain
158610: 16/01/25: Re: Fully preposterous gate arranger
159277: 16/09/20: Re: Minimal-operation shift-and-add (or subtract)
Walter Bushell:
145445: 10/02/09: Re: using an FPGA to emulate a vintage computer
146136: 10/03/06: Re: using an FPGA to emulate a vintage computer
Walter C. Washington:
8800: 98/01/27: fw
8802: 98/01/27: Divide by N counter with Altera:7064/7096
Walter Daniel Gallegos:
9216: 98/03/03: Re: Free FPGA tools???
9378: 98/03/08: Re: The case for free operating systems and EDA
10762: 98/06/17: Re: Xilinx Foundation
Walter Dvorak:
45373: 02/07/20: Re: Spartan II JTAG connection with other devices
45461: 02/07/24: Re: Editing constraints in WebPack
52428: 03/02/09: Re: JTAG Download Problems iMPACT and Insight parallel cable
54804: 03/04/18: Re: LFSR MAXIMUM LENGTH
57393: 03/06/29: Re: STARTUP_WAIT
58844: 03/08/02: Re: Ground planes on 4-layer PCB
69307: 04/05/05: Re: frequency multiplication
75325: 04/11/02: Re: Clock Extraction from Bi-Phase Data
76493: 04/12/04: Re: Stupid tools question...
78713: 05/02/06: Re: How to fix this synthese warnings?
85105: 05/06/04: Re: How to get *.mcs file containing both *.bit and *.elf file, to port linux on my memec virtex-ii board.
117929: 07/04/13: Re: Which are the best books about CORDIC algorithms and applications
120168: 07/06/02: Re: Seeing DCM LOCKED getting asserted in simulation at the same time CLKDV and CLKFX/CLKFX180 begin toggling
122939: 07/08/11: Re: spartan3 picoblaze how to make .bmm file work
125630: 07/10/30: Re: X3100A design with Synplify 8.8 and foundation 1.5 possible?
127982: 08/01/11: Re: Real examples of metastability causing bugs
130125: 08/03/15: Re: BRAM synthesis question
Walter Gallegos:
74679: 04/10/16: Re: How many Altera LE's to Xilinx Slices????
74695: 04/10/16: Re: How many Altera LE's to Xilinx Slices????
74789: 04/10/19: Re: How many Altera LE's to Xilinx Slices????
75643: 04/11/11: Re: C Compiler for Picoblaze !!!!!
75926: 04/11/19: Re: microblaze: execute program from external memory
76492: 04/12/04: Re: Cylone Problem with Large Shift Register
76527: 04/12/05: Re: Stupid tools question...
139847: 09/04/16: Re: Xilinx ISE bug, or?
walter haas:
27447: 00/11/22: Clock Skew : Does Xilinx know what they're doing?
27481: 00/11/23: Re: Clock Skew : Does Xilinx know what they're doing?
Walter Haas:
26345: 00/10/12: Re: Category : Subject:Floorplanning
26539: 00/10/19: PCI Core : Clock Problem
26642: 00/10/23: Re: PCI Core : Clock Problem
27073: 00/11/09: Re: Non routable design
27450: 00/11/22: Re: Clock Skew : Does Xilinx know what they're doing?
27458: 00/11/22: Re: Clock Skew : Does Xilinx know what they're doing?
27521: 00/11/27: Re: Clock Skew : Does Xilinx know what they're doing?
27545: 00/11/28: Re: Clock Skew : Does Xilinx know what they're doing?
27546: 00/11/28: Newsgroup : Accessing through Netscape Navigator
27548: 00/11/28: Re: Newsgroup : Accessing through Netscape Navigator
27759: 00/12/06: Re: fpga: 32 bit parity generation in 4 ns for virtexE
Walter Harley:
53612: 03/03/17: Re: more footprints...
Walter Lang (Operator):
3755: 96/07/25: ATT serial EEPROMs
3838: 96/08/08: WindowsNT and XACT
3921: 96/08/20: Windows NT and XACT
Walter Roberson:
120535: 07/06/08: Re: Arbiter
Walter Schweigart:
10943: 98/07/06: How to download bitstream on a SUN ...
Walter Soto Encinas Jr:
19317: 99/12/13: Velab and VSS simulation
19453: 99/12/22: EDIF and VITAL
19527: 99/12/29: VITAL timing parameter
Walter Soto Encinas Junior:
19272: 99/12/09: Synopsys backannotation
19276: 99/12/09: Re: Synopsys backannotation
Walter Welwarsky:
27154: 00/11/13: Re: Xilinx configuration: JTAG and SPROM
walter zabel:
89303: 05/09/12: xilinx ise / update schematics
<walter@chasque.apc.org>:
14990: 99/03/02: Re: PC for CAD
walterb:
12089: 98/09/28: Re: FIR Filter Design
12146: 98/10/01: Re: FIR Filter Design
<WalterChristler@rufgfofsj.org>:
19667: 00/01/07: .,.IF AOL WAS A CAR..,,
Walters:
124685: 07/09/30: Walking 1's
124835: 07/10/05: FiberChannel SOF
125522: 07/10/27: Bitfile checking
<walterwang@gmail.com>:
83586: 05/05/03: VHDL help with adding modules
walterwwongjr@gmail.com:
103107: 06/05/25: Startup in Dynamic Reconfigurable Computing needs a FPGA Designer
waltherz:
128590: 08/01/31: iru1209 regulator
128622: 08/01/31: Re: Design security for pre-Virtex2 parts ?
128623: 08/01/31: Re: iru1209 regulator
129621: 08/02/29: Re: Is there any way to disable JTAG for Sptantan3AN
Wamsi Mohan:
32791: 01/07/09: Virtexe Config problem
<wamsi@my-deja.com>:
20955: 00/02/29: Xilinx Tools Vs Altera tools
20963: 00/03/01: Re: Xilinx Tools Vs Altera tools
wanch:
89903: 05/09/29: High Speed Newbie: Xilinx Spartan3 DCM CLK2X is not locked if CLKIN > 140MHz
89995: 05/10/01: Re: High Speed Newbie: Xilinx Spartan3 DCM CLK2X is not locked if CLKIN > 140MHz
89996: 05/10/01: Re: High Speed Newbie: Xilinx Spartan3 DCM CLK2X is not locked if CLKIN > 140MHz
Wang Feng:
63473: 03/11/22: any FPGA design for video frame memory control?
68403: 04/04/03: SAA7111 YUV
Wang Jinfeng:
109004: 06/09/20: Re: S3 - alive and doing very well, thank you
Wang Xiao-yun:
43908: 02/06/05: Bad Behavior of JTAG Download on Altera CPLD with Other Devices
48700: 02/10/22: Re: Decoupling BF957 Virtex II package
53902: 03/03/27: Differential LVPECL Inteface of Spartan IIE
53912: 03/03/27: Re: Differential LVPECL Inteface of Spartan IIE
53944: 03/03/28: Re: Differential LVPECL Inteface of Spartan IIE
WangoTango:
157070: 14/09/22: Re: opencores.org
WangQiang:
99034: 06/03/19: Have you ever considered of mousing ambidextrously?
<wangtiffany313@gmail.com>:
121105: 07/06/25: How to deal with RAM issue when generating blif
wangw8021:
112992: 06/12/04: how can I use DCM in paritial reconfiguration design?
wannarat:
16016: 99/04/28: Need HELP!!! Hurry
16226: 99/05/11: USB core design
16334: 99/05/17: Glue logic
16888: 99/06/16: aobut analog
16890: 99/06/16: Re: FPGA board for ISA bus wanted
17810: 99/09/07: xilinx software
19543: 99/12/30: FG and H function in Xilinx FPGA
20814: 00/02/23: Noise to RAM
21104: 00/03/07: Xilinx software
want.a.friendlier.world@gmail.com:
128820: 08/02/07: Re: beleive
128821: 08/02/07: Re: Single Top FPGA Tips
<want.a.friendlier.world@gmail.com>:
128817: 08/02/07: Re: beleive
wanwan:
113072: 06/12/05: Altera starter kits
113086: 06/12/06: Re: Altera starter kits
War pawn:
56429: 03/06/05: Re: Is it possible to simulate Nios designs with Quartus?
<warchol@cloud.enet.dec.com>:
1717: 95/08/18: Re: Simulation not matching lab results
<wardrg@my-deja.com>:
17605: 99/08/13: FIREFLY Embeddable MicroController Cores
Warine:
64213: 03/12/20: How to use differential clock pin of SpartanIIE?
Warland, Tim [CRK:E930:EXCH]:
18600: 99/11/02: WEB reconfigurable FPGA, How?
warren:
67295: 04/03/09: xilinx configuration problem
67303: 04/03/09: xilinx configuration problem
67348: 04/03/10: xilinx jtag problems
67349: 04/03/10: Re: xilinx configuration problem
67371: 04/03/10: Re: xilinx configuration problem
Warren Postma:
48031: 02/10/09: Intel ARM 'XScale' cores as IP blocks that can be synthesized into an FPGA/ASIC?
Warren Wisnewski:
37363: 01/12/08: aldec
40111: 02/02/27: quicklogic parts request
Was:
52706: 03/02/19: Messaging Unit + Dorbells etc ..
Wasif Shams:
133872: 08/07/17: Need help regarding xupv2p board....
wasifgreen:
136779: 08/12/04: Problems using minimal CPU design by Tim Boescke
wasp:
64725: 04/01/12: Xilinx JBit v1.x
64795: 04/01/14: Simulation model of SRAM
Wastrel:
147276: 10/04/21: Quartus II under Windows7?
147348: 10/04/23: Re: Quartus II under Windows7?
147349: 10/04/23: Re: Quartus II under Windows7?
147361: 10/04/23: Re: Quartus II under Windows7?
147415: 10/04/26: Re: Quartus II under Windows7?
147448: 10/04/27: Re: Quartus II under Windows7?
147516: 10/04/29: Re: Quartus II under Windows7?
147536: 10/04/30: Re: Quartus II under Windows7?
water:
140264: 09/05/06: raid controller
142719: 09/08/28: usb3.0 PHY wrapper for Xilinx V5/V6 device
143305: 09/09/30: V6-based SATA 6.0G Host controller
143529: 09/10/14: Gen3 SATA 6.0Gbps HDD simulation model
144164: 09/11/16: who have a usb3.0 pipe3 wrapper for xilinx V5/V6 FPGA?
144170: 09/11/16: Re: who have a usb3.0 pipe3 wrapper for xilinx V5/V6 FPGA?
144172: 09/11/16: Re: who have a usb3.0 pipe3 wrapper for xilinx V5/V6 FPGA?
144430: 09/12/07: TCP/IP offload in hardware
water7:
101861: 06/05/07: PCI Core compatibility
101868: 06/05/08: Re: PCI Core compatibility
101869: 06/05/08: Re: PCI Core compatibility
103215: 06/05/29: Re: PCI related documents
103308: 06/05/30: PCI Design
103486: 06/06/04: Re: PCI Design
water9580@yahoo.com:
121462: 07/07/04: Xilinx V4/V5 FPGA SATA GTP
121512: 07/07/06: Re: Xilinx V4/V5 FPGA SATA GTP
121524: 07/07/06: ML555 SATA GTP dosen't work
121555: 07/07/07: ML555 SFP module
121556: 07/07/07: Re: ML555 SFP module
121652: 07/07/10: Re: ML555 SFP module
122161: 07/07/21: how do Xilinx PCSPMA IP core detect presence of optical input?
125770: 07/11/04: Xilinx PCI-Express Endpoint Block IP
125771: 07/11/04: Xilinx PCI-express coregen
125780: 07/11/04: Re: Xilinx PCI-Express Endpoint Block IP
130023: 08/03/13: MAXDELAY="1.0"
130252: 08/03/18: serval PCIE issue
130332: 08/03/20: PCI Express Configuration Testing
130453: 08/03/24: Re: PCI Express Configuration Testing
130506: 08/03/25: Re: PCI Express Configuration Testing
130548: 08/03/26: Re: PCI Express Configuration Testing
130755: 08/03/31: Re: PCI Express Configuration Testing
131104: 08/04/10: why to trigger a NMI error after just receiving 35 pakcets?
131719: 08/04/29: I use a ftp tool test my V5-based PCIE ethernet NIC controller.
131723: 08/04/29: how to optimize this comparator for better synthesis result?
131749: 08/04/30: Re: how to optimize this comparator for better synthesis result?
132366: 08/05/23: it doesn't work if increase a little traffic for DMA read.
132376: 08/05/23: Re: it doesn't work if increase a little traffic for DMA read.
133056: 08/06/16: TXCOMSTART/TXCMOTYPE of V5 SATA GTP with ISE10.1.1
135998: 08/10/26: pci-express sata host controller and Giga ethernet controller for V5
136015: 08/10/27: pci-express sata controller,bridge,ethernet controller
136789: 08/12/05: is it a bug?(Xilinx Xapp859 reference design: DDR2 SDRAM controller)
136804: 08/12/05: Re: is it a bug?(Xilinx Xapp859 reference design: DDR2 SDRAM
138253: 09/02/10: SATA GTP aligning commas to the LSB RXDATA byte
<waters@npss.enet.dec.com>:
4464: 96/11/01: Re: What is the fastest fpga for ...
<waterwork1@aol.com>:
11281: 98/08/02: Pool cleaning Aquabot
wathelet:
15726: 99/04/10: simulator
watm:
11474: 98/08/18: Help on Xilinx !
11497: 98/08/19: Re: Help on Xilinx !
11509: 98/08/20: 4PPM Algoritm
11530: 98/08/21: Re: 4PPM Algoritm
<WATomb@gmail.com>:
116306: 07/03/06: Re: Routing problem of DCM
116308: 07/03/06: Re: Ideas for Masters Project.
116371: 07/03/07: Re: Routing problem of DCM
Watson A.Name - Watt Sun, Dark Remover:
63651: 03/11/27: Re: Slightly unmatched UART frequencies
Watts:
18222: 99/10/08: Re: RAM in xilinx FPGAs.
<wavemediagram@gmail.com>:
159386: 16/10/21: Re: Free timing diagram drawing software
wayne:
29483: 01/02/22: programmable coefficient fir filter?
29502: 01/02/23: Re: programmable coefficient fir filter?
Wayne:
24287: 00/08/02: Re: QuickLogic PCI/FPGA chip (QL5064)...experiences?
34066: 01/08/13: Re: this code doesn't work properly
42223: 02/04/18: Re: how comes the clk suddenly pause?
42387: 02/04/22: use coregen rlocs or not ?
42676: 02/04/30: Xilinx fpgas for sale
44967: 02/07/08: Re: amplify and xilinx : map error 679
51897: 03/01/24: Altera Cyclone EP1C12 pins changed in Quartus 2.2 from 2.1
52038: 03/01/29: Re: GNU C for custom processor
52039: 03/01/29: Re: JTAG
101901: 06/05/08: Re: FPGA-based hardware accelerator for PC
Wayne Addy:
2212: 95/11/02: altera problems
Wayne Fisher:
50593: 02/12/13: Re: FPGA/PCI on low budget
Wayne Hammerschlag:
2365: 95/11/24: Re: PC VHDL synth for FPGA?
Wayne Long:
17904: 99/09/16: Question for Circuit Designers of Large High-Speed Boards: Best Means to
17903: 99/09/16: Question for Circuit Designers of Large High-Speed Boards: Best Means to
Wayne Miller:
17772: 99/09/01: QuickLogic FPGAs
17873: 99/09/14: Re: simple VHDL?
Wayne Thomas:
859: 95/03/15: Re: FPGA multi-chip modules ?
Wayne Turner:
3958: 96/08/24: Re: BIG FPGA
3988: 96/08/29: Re: USB Host Core for FPGA/Gate Array
4037: 96/09/05: Re: What is the REAL address of XOILINX and ALTERA?
4047: 96/09/05: Re: speed up Xilinx P & R
4311: 96/10/13: Re: Info/opinions wanted for PCI interface in an FPGA
4408: 96/10/24: Re: VHDL for Xilinx designs?
4414: 96/10/25: Re: Altera FPGA's
4415: 96/10/25: Re: Synplicity vs. FPGA Express
4446: 96/10/30: Re: Multipliers on Xilinx FPGAs
4447: 96/10/30: Re: Synplicity vs. FPGA Express
4782: 96/12/14: Re: Anyone tried a FFT in a FPGA?
4791: 96/12/16: Re: Fpga, Epld, cpld....
4790: 96/12/16: Re: ASICs Vs. FPGA in Safety Critical Apps.
4813: 96/12/17: Re: Fpga, Epld, cpld....
4844: 96/12/19: Re: ASICs Vs. FPGA in Safety Critical Apps.
4843: 96/12/19: Re: Anyone tried a FFT in a FPGA?
4858: 96/12/20: Re: ASICs Vs. FPGA in Safety Critical Apps.
4860: 96/12/20: Re: ASICs Vs. FPGA in Safety Critical Apps.
4873: 96/12/23: Re: ASICs Vs. FPGA in Safety Critical Apps.
4894: 96/12/26: Re: ASICs Vs. FPGA in Safety Critical Apps.
4901: 96/12/27: Re: ASICs Vs. FPGA in Safety Critical Apps.
4902: 96/12/27: Re: ASICs Vs. FPGA in Safety Critical Apps.
4909: 96/12/29: Re: ASICs Vs. FPGA in Safety Critical Apps.
4910: 96/12/29: Re: ASICs Vs. FPGA in Safety Critical Apps.
4921: 96/12/30: Re: ASICs Vs. FPGA in Safety Critical Apps.
4922: 96/12/30: Re: ASICs Vs. FPGA in Safety Critical Apps.
4923: 96/12/30: Re: ASICs Vs. FPGA in Safety Critical Apps.
4928: 96/12/31: Re: ASICs Vs. FPGA in Safety Critical Apps.
4999: 97/01/10: Re: Altera clique
5092: 97/01/22: Re: GATEFIELD from Zycad
5165: 97/01/28: Re: Altera support better than Xilinx
5166: 97/01/28: Re: FPGAs with internal Tri-state busses ?
5173: 97/01/29: Re: FPGA power dissipation
5187: 97/01/29: Re: Altera support better than Xilinx
5188: 97/01/29: Re: Altera support better than Xilinx
5219: 97/01/31: Re: Altera support better than Xilinx
5218: 97/01/31: Re: Altera BitBlaster
5220: 97/01/31: Re: Altera support better than Xilinx
5417: 97/02/14: Re: Altera support better than Xilinx
5531: 97/02/22: Re: Xilinx or Altera?
5577: 97/02/25: Re: Xilinx or Altera?
5667: 97/03/05: Re: Altera support better than Xilinx
5706: 97/03/09: Re: Altera support better than Xilinx
6106: 97/04/12: Re: prep benchmarks for FPGAs
6119: 97/04/13: TMS380SRA in an FPGA?
6118: 97/04/13: Re: XILINX FOUNDATION STUFF!!
6193: 97/04/24: Re: prep benchmarks for FPGAs
7215: 97/08/15: Re: 10K100 socket?
7869: 97/10/25: Re: Anyone know of an I2C Controller design for an FPGA?
8468: 97/12/18: Re: bus design in Altera 10K, how to increase speed
<waynet@pop.phnx.uswest.net>:
9088: 98/02/18: Re: Why altera CPLDS are slow to power-up?
<wbenrath@mail.ru>:
98077: 06/03/03: Re: arctangent again
<wdblyth@my-deja.com>:
17636: 99/08/17: Re: Virtx' Configuration with the Xchecker cable
<wdc.crest2@gmail.com>:
133389: 08/06/26: Re: Xilinx SecureIP simulation and third-party simulators?
<wddwkq@GetResponse.com>:
15594: 99/04/02: Spam Free ? 3815
wdeninger:
142907: 09/09/07: Spartan 3 loading from MCU slave serial problems
wdmun:
13344: 98/11/27: Bus Conflict
Web Admin:
1743: 95/08/22: CADmazing Web Page Update
Web Master:
1483: 95/06/28: Announcement : CADmazing Web Site Update
webber:
23786: 00/07/09: Where can I get Altera MAX+Plus2 9.x software?
Webmaster:
14966: 99/02/28: Over 1400 semiconductor links!
16702: 99/06/03: Over 1450 Semiconductor Links!
webmaster:
5903: 97/03/24: *** SUMMIT Microelectronics - new semiconductor manufacturer website ***
5915: 97/03/25: Re: *** SUMMIT Microelectronics - new semiconductor manufacturer website ***
5914: 97/03/25: Re: *** SUMMIT Microelectronics - new semiconductor manufacturer website ***
weddick:
77390: 05/01/05: Counter
Weddick:
69384: 04/05/10: Serial Data Capture
69424: 04/05/11: Re: Serial Data Capture
77355: 05/01/04: Re: Latches
78348: 05/01/30: Re: Trouble with Post-Place Simulation
78427: 05/01/31: Re: Trouble with Post-Place Simulation
78428: 05/01/31: Re: Trouble with Post-Place Simulation
78540: 05/02/02: Re: Model Sim: Color Printing
79757: 05/02/23: Memory Controller Operation
81747: 05/03/30: Re: Bi-directional Pin Use
84066: 05/05/11: Counting Clocks
84505: 05/05/19: Re: Serial Input Review and Questions
86276: 05/06/23: Re: Serial I/O - Delay Output
89431: 05/09/14: Re: VHDL: Address Decoder
89432: 05/09/14: Re: Address Decoder
92211: 05/11/23: Unconnected Ports
101826: 06/05/07: Re: flashing a led
103200: 06/05/28: COREGEN: DCM
<weese.stanford@gmail.com>:
99182: 06/03/21: Re: Ace file for design with dual ppc405
99184: 06/03/21: Re: EDK : PPC405 Interrupt question
<weg22@drexel.edu>:
121780: 07/07/12: Help with Libero IDE and Verilog...
134952: 08/09/08: IEEE 1394 interface for FPGA??
Wei Chen:
121959: 07/07/16: 1ms delay in V5 FPGA
wei ming:
69918: 04/05/24: I have problem with readback for virtex2
69962: 04/05/25: Readback on Vritex2, help me.
70567: 04/06/21: readback on Virtex2 , anybody help me!
Wei Wang:
118178: 07/04/19: Ask: why xilinx FPGA pin assignment couldn't pass p&r?
120578: 07/06/11: synthesis - design compiler or synplify pro?
120593: 07/06/11: Re: synthesis - design compiler or synplify pro?
120687: 07/06/13: Re: synthesis - design compiler or synplify pro?
121038: 07/06/23: Re: Modelsim simulation Q
122670: 07/08/02: Re: Best CPU platform(s) for FPGA synthesis
122671: 07/08/02: Re: Best CPU platform(s) for FPGA synthesis
122672: 07/08/02: Re: Best CPU platform(s) for FPGA synthesis
122673: 07/08/02: Re: Altera or Xilinx
122690: 07/08/03: Re: Best CPU platform(s) for FPGA synthesis
123627: 07/08/31: Is it possible to make bit files generated by Xilinx ISE readable?
124388: 07/09/20: Is it possible for two wires to share the same FPGA pin?
124512: 07/09/25: How can I find out the input/output interface of SDR SDRAM Kingston KVR100X64C2/128?
124526: 07/09/25: Re: How can I find out the input/output interface of SDR SDRAM Kingston KVR100X64C2/128?
124550: 07/09/26: Re: How can I find out the input/output interface of SDR SDRAM Kingston KVR100X64C2/128?
124559: 07/09/26: Re: How can I find out the input/output interface of SDR SDRAM Kingston KVR100X64C2/128?
124615: 07/09/28: Re: How can I find out the input/output interface of SDR SDRAM Kingston KVR100X64C2/128?
124734: 07/10/02: Any better ways for interfacing fpga with dynamic memory?
125324: 07/10/21: microprocessor on fpga problems
125362: 07/10/23: Re: microprocessor on fpga problems
125567: 07/10/29: How to make sure processor memories have been correctly mapped onto block ram on fpga?
125575: 07/10/29: Is it possible to check how cache memories are mapped to FPGA block rams?
125611: 07/10/30: Re: Is it possible to check how cache memories are mapped to FPGA block rams?
128209: 08/01/18: How is FIFO implemented in FPGA and ASIC?
132857: 08/06/09: readmem[b|h]
wei yao:
31559: 01/05/30: Re: Peripheral for Microcontroller
Wei-sheng Chong:
74111: 04/10/04: meaning of "field-programmable" in FPGA
<wei.wang.cantab@googlemail.com>:
126932: 07/12/06: Synplify .sdc file
127006: 07/12/08: What to look for when synthesising verilog code originally written
Weifeng Xu:
44833: 02/07/02: Bitstream Verification (JBITS)
44871: 02/07/03: Re: Bitstream Verification (JBITS)
44878: 02/07/03: Re: Bitstream Verification (JBITS)
46160: 02/08/20: And detailed documentation about XDL format?
48985: 02/10/28: From NCD to Bitstream (Xilinx FPGA)
50841: 02/12/20: How to handle Fautly Interconnection in Virtex ?
54879: 03/04/21: Re: Xilinx Virtex switchbox details...
54882: 03/04/21: Re: configuration file
54885: 03/04/21: Re: Question about Xilinx Classes
54887: 03/04/21: Re: JBits & Tristate
54889: 03/04/21: Re: FPGA BitStream
55417: 03/05/07: Re: How failures happen, and how they don't
55426: 03/05/07: Re: How failures happen, and how they don't
<weinhard@ipd.info.uni-karlsruhe.de>:
256: 94/10/04: VCC's EVC1 experiences
Weiss:
156679: 14/06/03: ECG signals Compression/Decompression
156697: 14/06/05: Re: ECG signals Compression/Decompression
156703: 14/06/05: Re: ECG signals Compression/Decompression
Weizbox:
73662: 04/09/27: Simple Counter in Verilog
73664: 04/09/27: Re: Simple Counter in Verilog
73590: 04/09/24: Re: Getting info from a digital line
73595: 04/09/24: Re: Getting info from a digital line
73598: 04/09/24: Re: Getting info from a digital line
weizbox:
73583: 04/09/24: Getting info from a digital line
74182: 04/10/05: 8-bit word to 4-digit, 7-segment display
75556: 04/11/09: Where to find very basic FPGAs
75582: 04/11/10: Re: Where to find very basic FPGAs
75639: 04/11/11: Re: Where to find very basic FPGAs
<weknews@my-deja.com>:
24666: 00/08/16: Re: Non-disclosures in job interviews
24667: 00/08/16: Re: Non-disclosures in job interviews
weldat:
146330: 10/03/12: how can i add memory
146371: 10/03/15: Re: ERROR: overlaps section...
146373: 10/03/15: Re: how can i add memory
146694: 10/03/26: result on hyperterminal is not displayed
146884: 10/03/30: Re: result on hyperterminal is not displayed
146968: 10/04/05: Re: result on hyperterminal is not displayed
Weltraumbaer:
105985: 06/08/04: Xilinx PCI Core burst problem
106216: 06/08/09: Xilinx PCI Core & CardBus
106218: 06/08/09: Re: Xilinx PCI Core burst problem
106219: 06/08/09: Re: Xilinx PCI Core & CardBus
106249: 06/08/09: Re: Xilinx PCI Core & CardBus
129999: 08/03/12: Temporarely no answer on MEM32 Read request
weMPEC:
29554: 01/02/26: VHDL:case
Wen-King Su:
2142: 95/10/19: Where to find more info on PCI
2733: 96/01/31: Re: GAL programming for hobby use...Is there no hope?
3268: 96/05/07: Re: so little posts about PCI :(
3625: 96/07/04: Re: Problems with ORCA c40 FPGAs
4106: 96/09/10: Re: FPGA design project
5418: 97/02/14: Re: Lucent Orcas ...
5453: 97/02/17: Re: Lucent Orcas ...
5739: 97/03/11: Re: Reverse Engineering FPGAs
6025: 97/04/06: Re: PCI Bus Problems
6121: 97/04/13: Re: PCI Bus Problems
6132: 97/04/14: Re: PCI Bus Problems
6152: 97/04/18: Re: PCI Reset Spec...
6161: 97/04/19: Re: PCI Reset Spec...
6459: 97/05/25: Re: Fine Pitch PQFP : anyone any hassles?
6468: 97/05/26: Re: Fine Pitch PQFP : anyone any hassles?
6614: 97/06/05: Re: VHDL PCI FPGA Implementation
6722: 97/06/19: Re: 100MHz SDRAMs with Xilinx?
7000: 97/07/21: Re: PCI burst transfers
7004: 97/07/22: Re: PCI burst transfers
7011: 97/07/22: Re: PCI burst transfers
7046: 97/07/26: Re: PCI burst transfers
7127: 97/08/03: Re: Are 2 PCs better than One?
7135: 97/08/04: Re: Are 2 PCs better than One?
7355: 97/08/29: Re: fpga configuration over PCI
7591: 97/09/24: Re: Can 3.3v Xilinx drive CMOS?
9297: 98/03/05: Re: The case for free operating systems and EDA
9320: 98/03/06: Re: The case for free operating systems and EDA
9386: 98/03/08: Re: The case for free operating systems and EDA
9397: 98/03/09: Re: The case for free operating systems and EDA
9367: 98/03/07: Re: The case for free operating systems and EDA
10227: 98/05/05: Re: Xilinx Foundation and Linux
10291: 98/05/09: Re: Xilinx Foundation and Linux
12268: 98/10/07: Re: A Johnson counter
13899: 98/12/31: Re: Can a cross coupled latch "oscillate"? was Re: ..........
13903: 99/01/01: Re: Can a cross coupled latch "oscillate"? was Re: ..........
13909: 99/01/01: Re: Can a cross coupled latch "oscillate"? was Re: ..........
13912: 99/01/01: Re: Can a cross coupled latch "oscillate"? was Re: ..........
13928: 99/01/02: Re: Can a cross coupled latch "oscillate"? was Re: ..........
13932: 99/01/02: Re: Can a cross coupled latch "oscillate"? was Re: ..........
13936: 99/01/03: Re: Can a cross coupled latch "oscillate"? was Re: ..........
13942: 99/01/04: Re: IS: y2k-1 problem: when is this year gonna end???????? (WAS: Re: Can a cross coupled latch "oscillate"? was Re: .........._
14052: 99/01/09: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
14057: 99/01/10: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
17331: 99/07/21: Re: Solaris vs. NT
17352: 99/07/22: Re: Solaris vs. NT
17773: 99/09/01: Re: QuickLogic FPGAs
Wenchang:
84813: 05/05/28: Synplify 8.1 vs. Quartus II 5.0 QoR
Wendell:
159460: 16/11/19: Re: Tools on Linux
Wendy Lockhart:
14644: 99/02/08: career
18496: 99/10/27: Re: Estimating Gates in FPGA
18497: 99/10/27: Re: Wanted: HOTWORKS board
18498: 99/10/27: Re: PREP benchmarks
Weng Tianxiang:
82966: 05/04/20: Re: Bug in DDR template in Lattice FPGAs ?
85167: 05/06/06: Re: 32/16 divider, ASIC(Designware) Vs Xilinx FPGA(Coregen)
85566: 05/06/10: Re: Fast/low area Sorting hardware.
85571: 05/06/10: Re: Fast/low area Sorting hardware.
91116: 05/10/29: Why are there two patents with same title
91118: 05/10/29: Re: Why are there two patents with same title
91414: 05/11/05: Font requirements for patent applications
91467: 05/11/07: Re: Font requirements for patent applications
92632: 05/12/02: Is it legal to write an logical equation for a FPGA LUT in claims of a patent?
92640: 05/12/02: Re: Is it legal to write an logical equation for a FPGA LUT in claims of a patent?
92710: 05/12/05: Re: Is it legal to write an logical equation for a FPGA LUT in claims of a patent?
92731: 05/12/05: Re: Is it legal to write an logical equation for a FPGA LUT in claims of a patent?
92757: 05/12/06: Re: Is it legal to write an logical equation for a FPGA LUT in claims of a patent?
93402: 05/12/21: Re: Data Decoding at 10 Gbit/s
98188: 06/03/06: Re: Asynchronous FIFO design question
98229: 06/03/07: Re: processor bus tristate at two places
98262: 06/03/07: Re: Asynchronous FIFO design question
98557: 06/03/12: How to specify a package in Xilinx 8.1i
98562: 06/03/12: Re: How to specify a package in Xilinx 8.1i
98866: 06/03/17: Re: Instantiating addsub, comparators in Xilinx
99245: 06/03/21: Re: Xilinx Square Root Unit
99279: 06/03/22: Re: Xilinx Square Root Unit
99317: 06/03/22: Re: Xilinx Square Root Unit
99324: 06/03/22: Re: OpenSPARC released
99379: 06/03/23: Re: OpenSPARC released
99475: 06/03/24: Re: Xilinx Square Root Unit
100550: 06/04/11: Re: PCI speed.
100896: 06/04/20: An experience with Xilinx 8.1.02i
100905: 06/04/20: Re: Multiple Independent Circuits on a Single FPGA
101330: 06/04/28: How to see *.vcd file outported from ChipScope from different computer
101353: 06/04/29: Re: How to see *.vcd file outported from ChipScope from different computer
101533: 06/05/02: Improvement suggestions for Xilinx ChipScope
101697: 06/05/04: RFID chip has battary in it or not
101702: 06/05/04: Re: RFID chip has battary in it or not
101821: 06/05/07: The differences between behaviors of 'std_logic_vector' and 'unsigned'
101825: 06/05/07: Re: The differences between behaviors of 'std_logic_vector' and 'unsigned'
102267: 06/05/12: Re: reverse engineering ?
102274: 06/05/13: Re: reverse engineering ?
103706: 06/06/08: Good free or paid merge software that edits two similar files?
103708: 06/06/08: Re: Good free or paid merge software that edits two similar files?
103725: 06/06/09: Re: Good free or paid merge software that edits two similar files?
103755: 06/06/10: Re: Good free or paid merge software that edits two similar files?
103818: 06/06/12: How to get lowest price for a ModelSim license?
103873: 06/06/13: Re: How to get lowest price for a ModelSim license?
104461: 06/06/27: Preserve patent materials through a notary
104478: 06/06/28: Re: Preserve patent materials through a notary
104482: 06/06/28: Reverse engineering has the protection of law in the U.S.
104499: 06/06/28: Re: Preserve patent materials through a notary
104534: 06/06/29: Re: Preserve patent materials through a notary
104776: 06/07/05: How much time does it need to sort 1 million random 64-bit/32-bit integers?
104793: 06/07/06: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
104819: 06/07/06: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
104825: 06/07/06: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
104848: 06/07/07: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
104882: 06/07/07: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
104987: 06/07/11: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
105051: 06/07/12: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
105056: 06/07/12: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
105068: 06/07/12: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
105129: 06/07/14: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
105157: 06/07/14: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
105159: 06/07/14: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
105282: 06/07/19: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
105340: 06/07/20: Re: Sorting algorithm for FPGA availlable?
105364: 06/07/20: Re: Sorting algorithm for FPGA availlable?
105365: 06/07/20: Re: Hardware book like "Code Complete"?
105423: 06/07/22: How to print a state flow graph for a state machine using Xilinx ISE or ModelSim
105527: 06/07/25: Re: How to print a state flow graph for a state machine using Xilinx ISE or ModelSim
105591: 06/07/26: Re: An idea for a product (FPGA/ASIC based)
105636: 06/07/27: Re: An idea for a product (FPGA/ASIC based)
105652: 06/07/27: Re: Hardware book like "Code Complete"?
105666: 06/07/28: Re: Hardware book like "Code Complete"?
105688: 06/07/28: Re: Hardware book like "Code Complete"?
105703: 06/07/28: Re: Hardware book like "Code Complete"?
105810: 06/08/01: Where are Huffman encoding applications?
105843: 06/08/01: Re: Where are Huffman encoding applications?
105855: 06/08/01: Re: Sorting algorithm for FPGA availlable?
105915: 06/08/02: Re: Sorting algorithm for FPGA availlable?
105916: 06/08/02: Re: Where are Huffman encoding applications?
105920: 06/08/02: Re: Where are Huffman encoding applications?
105923: 06/08/02: Re: Where are Huffman encoding applications?
105925: 06/08/02: Re: Where are Huffman encoding applications?
105938: 06/08/03: Re: Sorting algorithm for FPGA availlable?
105951: 06/08/03: Re: Where are Huffman encoding applications?
106016: 06/08/05: Re: Where are Huffman encoding applications?
107993: 06/09/03: How to resolve a Xilinx 8.1 BlockRAM problem
107999: 06/09/03: Re: How to resolve a Xilinx 8.1 BlockRAM problem
108027: 06/09/04: Re: How to resolve a Xilinx 8.1 BlockRAM problem
108029: 06/09/04: Re: What is the best testbook on algorithms in graph
108166: 06/09/06: Global constants definition problem
108174: 06/09/06: Re: Global constants definition problem
108203: 06/09/06: Re: Global constants definition problem
108204: 06/09/06: Re: Global constants definition problem
108265: 06/09/07: Re: Global constants definition problem
108272: 06/09/07: Re: Global constants definition problem
108317: 06/09/07: Re: Why No Process Shrink On Prior FPGA Devices ?
108390: 06/09/10: Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
108391: 06/09/10: Re: HOLD violations in Xilinx fpga
108403: 06/09/10: Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
108405: 06/09/10: Re: HOLD violations in Xilinx fpga
108406: 06/09/10: Re: ddr with multiple users
108434: 06/09/11: Re: ddr with multiple users
108435: 06/09/11: Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
108444: 06/09/11: Re: ddr with multiple users
108445: 06/09/11: Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
108446: 06/09/11: Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
108447: 06/09/11: Re: ddr with multiple users
108508: 06/09/12: Re: ddr with multiple users
108539: 06/09/12: Re: ddr with multiple users
108579: 06/09/13: Re: ddr with multiple users
108651: 06/09/14: Re: csptool : Chipscope Pro perl script to group buses automatically
108653: 06/09/14: Re: ddr with multiple users
108832: 06/09/17: Re: A strange problem of Chipscope
108990: 06/09/19: Re: A strange problem of Chipscope
109383: 06/09/25: Re: An algorithm with Minimum vertex cover without considering its performance
109399: 06/09/26: Re: An algorithm with Minimum vertex cover without considering its performance
109403: 06/09/26: Re: An algorithm with Minimum vertex cover without considering its performance
109405: 06/09/26: Re: An algorithm with Minimum vertex cover without considering its performance
109419: 06/09/26: Re: An algorithm with Minimum vertex cover without considering its performance
109514: 06/09/27: Re: An algorithm with Minimum vertex cover without considering its performance
109628: 06/10/01: Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!
109694: 06/10/03: How to create a library for a Xilinx project
109704: 06/10/03: Re: How to create a library for a Xilinx project
109705: 06/10/03: Re: How to create a library for a Xilinx project
109727: 06/10/04: Re: How to create a library for a Xilinx project
110743: 06/10/20: How many clocks are needed for a fastest ADD instruction of latest Intel CPU
110761: 06/10/21: Re: How many clocks are needed for a fastest ADD instruction of latest Intel CPU
110767: 06/10/21: Re: How many clocks are needed for a fastest ADD instruction of latest Intel CPU
110872: 06/10/24: What should I do with std.textio.all of ModelSim
110889: 06/10/25: Re: What should I do with std.textio.all of ModelSim
110890: 06/10/25: Re: What should I do with std.textio.all of ModelSim
110893: 06/10/25: Re: What should I do with std.textio.all of ModelSim
110952: 06/10/25: Re: What should I do with std.textio.all of ModelSim
110994: 06/10/26: Re: What should I do with std.textio.all of ModelSim
111010: 06/10/26: Re: What should I do with std.textio.all of ModelSim
111011: 06/10/26: Re: What should I do with std.textio.all of ModelSim
112912: 06/11/30: How to save a changed *.wlf file with ModelSim
112934: 06/12/01: Re: How to save a changed *.wlf file with ModelSim
114369: 07/01/12: How to get correct initial values from Xilinx Vertex II single port distributed ram with ModelSim
114384: 07/01/13: Re: How to get correct initial values from Xilinx Vertex II single port distributed ram with ModelSim
114430: 07/01/15: Re: How to get correct initial values from Xilinx Vertex II single port distributed ram with ModelSim
114638: 07/01/21: How to exclude timing violations in Xilinx *.ucf file
114974: 07/01/28: How to make an internal signal embedded deep in hierarchy to a gloal output signal
114978: 07/01/28: Re: How to make an internal signal embedded deep in hierarchy to a gloal output signal
114985: 07/01/28: Re: How to make an internal signal embedded deep in hierarchy to a gloal output signal
115034: 07/01/29: Re: How to make an internal signal embedded deep in hierarchy to a gloal output signal
116040: 07/02/28: Re: Modelsim (errno = ENOSPC) error
116115: 07/03/01: What is the running frequency for a typical FPGA application using Virtex 5
116262: 07/03/05: VHDL and Latch
116263: 07/03/05: Re: What is the running frequency for a typical FPGA application using Virtex 5
116291: 07/03/06: Re: VHDL and Latch
116294: 07/03/06: Re: VHDL and Latch
116307: 07/03/06: Re: VHDL and Latch
116309: 07/03/06: Re: Block RAM in VirtexE FPGA - 'Read-after-Write' and 'No-Read-on-Write' modes
116332: 07/03/07: Re: VHDL and Latch
116344: 07/03/07: Re: Block RAM in VirtexE FPGA - 'Read-after-Write' and 'No-Read-on-Write' modes
116347: 07/03/07: Re: VHDL and Latch
116370: 07/03/07: Re: VHDL and Latch
116406: 07/03/08: Re: VHDL and Latch
116409: 07/03/08: Re: Multiple devices within one ISE project
116436: 07/03/08: Re: VHDL and Latch
116468: 07/03/09: Re: VHDL and Latch
116763: 07/03/16: What official function should I call to genertate a sum of products in VHDL
116771: 07/03/17: Use of both positive reference and negative reference of the same signal for Xilinx chips would cause additional LUT delay?
116779: 07/03/17: Re: Use of both positive reference and negative reference of the same signal for Xilinx chips would cause additional LUT delay?
116795: 07/03/18: Re: Use of both positive reference and negative reference of the same signal for Xilinx chips would cause additional LUT delay?
117213: 07/03/26: A suggestion for a new input interface for functions in VHDL: XOR(a0, a1, ...)
117275: 07/03/27: Re: A suggestion for a new input interface for functions in VHDL: XOR(a0, a1, ...)
117287: 07/03/27: What is the best application notes or patents filed by Xilinx to disclose Vertex-5 Slice L
117291: 07/03/27: Re: What is the best application notes or patents filed by Xilinx to disclose Vertex-5 Slice L
117297: 07/03/27: Re: What is the best application notes or patents filed by Xilinx to disclose Vertex-5 Slice L
117320: 07/03/28: Re: A suggestion for a new input interface for functions in VHDL: XOR(a0, a1, ...)
117415: 07/03/30: Re: A suggestion for a new input interface for functions in VHDL: XOR(a0, a1, ...)
117442: 07/03/30: Re: A suggestion for a new input interface for functions in VHDL: XOR(a0, a1, ...)
117443: 07/03/30: Re: What is the best application notes or patents filed by Xilinx to disclose Vertex-5 Slice L
117463: 07/03/31: Re: What is the best application notes or patents filed by Xilinx to disclose Vertex-5 Slice L
117865: 07/04/11: Which are the best books about CORDIC algorithms and applications
117878: 07/04/12: Re: Which are the best books about CORDIC algorithms and applications
117894: 07/04/12: Re: Which are the best books about CORDIC algorithms and applications
117938: 07/04/13: Re: Which are the best books about CORDIC algorithms and applications
117939: 07/04/13: Re: Which are the best books about CORDIC algorithms and applications
118635: 07/05/01: Where can I find the pass transistor's working curve under 1.2V?
118653: 07/05/01: Re: Where can I find the pass transistor's working curve under 1.2V?
118662: 07/05/01: Re: Where can I find the pass transistor's working curve under 1.2V?
118698: 07/05/02: Re: Where can I find the pass transistor's working curve under 1.2V?
119023: 07/05/09: Re: Where can I find the pass transistor's working curve under 1.2V?
119436: 07/05/18: How to insert tab in Write() function in VHDL
119454: 07/05/19: Re: How to insert tab in Write() function in VHDL
119510: 07/05/21: ModelSim version upgrade problem from 6.1c to 6.2c
121933: 07/07/15: Re: Chipscope 9.1: Any easy way to rename and regroup signals?
122576: 07/07/31: Re: ASIC Digital Design Blog
122577: 07/07/31: Re: DDR Simulation Model
123282: 07/08/22: Re: Old issues of XCell magazine
123395: 07/08/27: Null statement in VHDL
123399: 07/08/27: Re: Null statement in VHDL
123406: 07/08/27: Re: Null statement in VHDL
123419: 07/08/28: New keyword 'orif' and its implications
123461: 07/08/28: Re: New keyword 'orif' and its implications
123468: 07/08/28: Re: New keyword 'orif' and its implications
123472: 07/08/28: Re: New keyword 'orif' and its implications
123477: 07/08/28: Re: New keyword 'orif' and its implications
123479: 07/08/28: Re: New keyword 'orif' and its implications
123523: 07/08/29: Re: New keyword 'orif' and its implications
123547: 07/08/29: Re: New keyword 'orif' and its implications
123590: 07/08/30: Re: New keyword 'orif' and its implications
123593: 07/08/30: Re: New keyword 'orif' and its implications
123609: 07/08/30: Re: New keyword 'orif' and its implications
123612: 07/08/30: Re: New keyword 'orif' and its implications
123641: 07/08/31: Re: New keyword 'orif' and its implications
123664: 07/08/31: Re: New keyword 'orif' and its implications
123666: 07/08/31: Re: New keyword 'orif' and its implications
123674: 07/08/31: Re: New keyword 'orif' and its implications
123689: 07/09/01: Re: New keyword 'orif' and its implications
123695: 07/09/02: Re: New keyword 'orif' and its implications
123721: 07/09/02: Re: New keyword 'orif' and its implications
123723: 07/09/02: Re: New keyword 'orif' and its implications
123738: 07/09/03: Re: New keyword 'orif' and its implications
123739: 07/09/03: Re: New keyword 'orif' and its implications
123748: 07/09/03: Re: New keyword 'orif' and its implications
123764: 07/09/04: Re: New keyword 'orif' and its implications
123827: 07/09/05: Re: New keyword 'orif' and its implications
123828: 07/09/05: Re: New keyword 'orif' and its implications
123846: 07/09/05: Re: New keyword 'orif' and its implications
123880: 07/09/06: Re: New keyword 'orif' and its implications
123884: 07/09/06: Re: New keyword 'orif' and its implications
123886: 07/09/06: Re: New keyword 'orif' and its implications
123954: 07/09/07: New keyword 'OIF' and its implications
123996: 07/09/10: What is the name of Altera latest and most advanced chip serial that is competable in technology with Vertex V in terms of system strucute(LUT6...)
123997: 07/09/10: What is called carry chain structure in FPGA is called in IC?
124012: 07/09/10: Re: What is the name of Altera latest and most advanced chip serial that is compatible in technology with Virtex-5 in terms of system strucute(LUT6...)
124013: 07/09/10: Re: What is called carry chain structure in FPGA is called in IC?
124132: 07/09/12: Re: Good VHDL reference?
124253: 07/09/16: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
124255: 07/09/16: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
124267: 07/09/17: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
124273: 07/09/17: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
124275: 07/09/17: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
124279: 07/09/17: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
124319: 07/09/18: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
124341: 07/09/18: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
124358: 07/09/19: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
124368: 07/09/19: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
124371: 07/09/19: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
124372: 07/09/20: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
124406: 07/09/20: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
124408: 07/09/20: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
124441: 07/09/21: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
124447: 07/09/21: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
124450: 07/09/21: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
124455: 07/09/22: Answer: maximum number of state machines in a current chip: > 500k
124470: 07/09/23: Re: Gated Clock Problems
124518: 07/09/25: Re: How can I find out the input/output interface of SDR SDRAM Kingston KVR100X64C2/128?
124530: 07/09/26: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
124551: 07/09/26: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
124822: 07/10/05: Re: JPEG-LS hardware implementation
124842: 07/10/07: Re: JPEG-LS hardware implementation
135206: 08/09/19: Re: Peter says Good Bye
135483: 08/10/04: Do two clock system blocks with one clock running half of other's
135501: 08/10/05: Re: Do two clock system blocks with one clock running half of other's
135552: 08/10/07: Re: Do two clock system blocks with one clock running half of other's
135553: 08/10/07: Re: Do two clock system blocks with one clock running half of other's
135581: 08/10/08: Re: Do two clock system blocks with one clock running half of other's
138450: 09/02/23: Where can a cheap programmer for Xilinx Virtex II XC2V1500 be found?
138457: 09/02/23: Re: Where can a cheap programmer for Xilinx Virtex II XC2V1500 be
138477: 09/02/24: Re: Where can a cheap programmer for Xilinx Virtex II XC2V1500 be
138505: 09/02/25: Can Xilinx IST automatically detect non-compatible library?
138508: 09/02/25: Re: Where can a cheap programmer for Xilinx Virtex II XC2V1500 be
138509: 09/02/25: Re: Can Xilinx IST automatically detect non-compatible library?
138551: 09/02/26: Re: Where can a cheap programmer for Xilinx Virtex II XC2V1500 be
138571: 09/02/27: Re: Where can a cheap programmer for Xilinx Virtex II XC2V1500 be
138579: 09/02/28: Re: Where can a cheap programmer for Xilinx Virtex II XC2V1500 be
139018: 09/03/18: Xilinx XAPP052 LFSR and its understanding
139039: 09/03/18: Re: Xilinx XAPP052 LFSR and its understanding
139068: 09/03/19: Re: Xilinx XAPP052 LFSR and its understanding
139069: 09/03/19: Re: Xilinx XAPP052 LFSR and its understanding
139073: 09/03/19: Re: Xilinx XAPP052 LFSR and its understanding
139081: 09/03/19: Re: Xilinx XAPP052 LFSR and its understanding
139160: 09/03/22: Re: Xilinx XAPP052 LFSR and its understanding
139164: 09/03/22: Re: Xilinx XAPP052 LFSR and its understanding
139169: 09/03/22: Re: Xilinx XAPP052 LFSR and its understanding
139191: 09/03/22: Re: Xilinx XAPP052 LFSR and its understanding
139238: 09/03/23: Re: Xilinx XAPP052 LFSR and its understanding
139267: 09/03/24: Re: Xilinx XAPP052 LFSR and its understanding
139268: 09/03/24: Xilinx ISE 10.1 Error reporting
139564: 09/04/03: Re: 8b10b encoding + line encoding
140636: 09/05/20: Are all these claims in VHDL correct?
140675: 09/05/21: Re: Are all these claims in VHDL correct?
140703: 09/05/22: Re: Are all these claims in VHDL correct?
140740: 09/05/23: Re: Are all these claims in VHDL correct?
140764: 09/05/25: Re: Adders with multiple inputs?
140766: 09/05/25: When is it to generate transparent latch or usual combinational
140777: 09/05/25: Re: When is it to generate transparent latch or usual combinational
140800: 09/05/26: Re: Adders with multiple inputs?
140803: 09/05/26: Re: When is it to generate transparent latch or usual combinational
140805: 09/05/26: Re: Architecture of FPGA
140821: 09/05/26: Re: When is it to generate transparent latch or usual combinational
140882: 09/05/28: Are Virtex-5 FPGA Handbook or Altera latest Handbooks available to
140927: 09/05/29: Re: Are Virtex-5 FPGA Handbook or Altera latest Handbooks available
140928: 09/05/29: Re: Are Virtex-5 FPGA Handbook or Altera latest Handbooks available
140974: 09/06/01: Re: Peter Alfke's 6 EASY
140977: 09/06/01: Re: Are Virtex-5 FPGA Handbook or Altera latest Handbooks available
141189: 09/06/10: Re: What the switch of FFT implementation in FPGA for
141268: 09/06/14: About Altera patent application "Logic Cell Supporting Addition of
141274: 09/06/15: Re: About Altera patent application "Logic Cell Supporting Addition
141280: 09/06/15: Re: About Altera patent application "Logic Cell Supporting Addition
141283: 09/06/15: Re: About Altera patent application "Logic Cell Supporting Addition
141285: 09/06/15: Re: About Altera patent application "Logic Cell Supporting Addition
141286: 09/06/15: Re: About Altera patent application "Logic Cell Supporting Addition
141289: 09/06/15: Re: About Altera patent application "Logic Cell Supporting Addition
141298: 09/06/16: Re: About Altera patent application "Logic Cell Supporting Addition
141299: 09/06/16: Re: About Altera patent application "Logic Cell Supporting Addition
141301: 09/06/16: Do you know how aggressive the patent fighting between Xilinx and
141306: 09/06/16: Re: About Altera patent application "Logic Cell Supporting Addition
141311: 09/06/16: Re: About Altera patent application "Logic Cell Supporting Addition
141314: 09/06/17: Re: Do you know how aggressive the patent fighting between Xilinx and
141317: 09/06/17: Re: Do you know how aggressive the patent fighting between Xilinx and
141323: 09/06/17: Re: Do you know how aggressive the patent fighting between Xilinx and
141373: 09/06/21: Re: Subtleties of Booth's Algorithm Implementation
141379: 09/06/22: Re: Subtleties of Booth's Algorithm Implementation
141388: 09/06/22: Re: Subtleties of Booth's Algorithm Implementation
141416: 09/06/23: Re: Subtleties of Booth's Algorithm Implementation
141448: 09/06/24: Re: Subtleties of Booth's Algorithm Implementation
141562: 09/06/27: Expand unsigned 4*4 module to signed 16*16 module
141565: 09/06/27: Re: Expand unsigned 4*4 module to signed 16*16 module
141834: 09/07/11: Why do both Xilinx and Altera DPS use 18*18?
141838: 09/07/11: Re: Why do both Xilinx and Altera DPS use 18*18?
141840: 09/07/12: Re: Why do both Xilinx and Altera DPS use 18*18?
142255: 09/07/30: Re: Using OPEN in port map
142710: 09/08/27: Where is Altera On-Demand Webinars show on radar signal processing?
142737: 09/08/29: Does ModelSim or any simulator software have a function similar to
142741: 09/08/29: Re: Does ModelSim or any simulator software have a function similar
142752: 09/08/30: Re: Does ModelSim or any simulator software have a function similar
142774: 09/08/31: Re: Where is Altera On-Demand Webinars show on radar signal
142813: 09/09/02: GF(233) example
142825: 09/09/02: Re: GF(233) example
142843: 09/09/03: Re: GF(233) example
142846: 09/09/03: Re: GF(233) example
142871: 09/09/04: Re: Spartan-6 boards now REALLY in online shops
142983: 09/09/12: Re: Does ModelSim or any simulator software have a function similar
143437: 09/10/11: How to enter lower boundary character pair within Microsoft Office
143474: 09/10/12: Re: How to enter lower boundary character pair within Microsoft
143475: 09/10/12: Re: How to enter lower boundary character pair within Microsoft
143482: 09/10/12: Re: How to enter lower boundary character pair within Microsoft
143521: 09/10/14: What is the basis on flip-flop replaced by a latch
143525: 09/10/14: Re: What is the basis on flip-flop replaced by a latch
143531: 09/10/14: Re: What is the basis on flip-flop replaced by a latch
143547: 09/10/15: Re: What is the basis on flip-flop replaced by a latch
143549: 09/10/15: Re: What is the basis on flip-flop replaced by a latch
143570: 09/10/16: Re: What is the basis on flip-flop replaced by a latch
143577: 09/10/16: Re: What is the basis on flip-flop replaced by a latch
143584: 09/10/16: Re: What is the basis on flip-flop replaced by a latch
143642: 09/10/19: Re: What is the basis on flip-flop replaced by a latch
144064: 09/11/09: Re: Xcell Journal Issue 69: FPGAs in the Networked Battlefield
144138: 09/11/12: Re: Xcell Journal Issue 69: FPGAs in the Networked Battlefield
144786: 10/01/02: ASM hardware language definition file for Altera/Xilinx
144812: 10/01/06: Re: ASM hardware language definition file for Altera/Xilinx
144813: 10/01/06: A VHDL compiler error report in Xilinx ISE 10.1 and service pack 3
144839: 10/01/07: Re: ASM hardware language definition file for Altera/Xilinx
144854: 10/01/07: Re: ASM hardware language definition file for Altera/Xilinx
145118: 10/01/28: Thank you, SunMicrosystem
145121: 10/01/28: Re: Thank you, SunMicrosystem
145122: 10/01/28: Re: Thank you, SunMicrosystem
145485: 10/02/11: What is the basis on flip-flops replaced by a latch
145520: 10/02/12: Re: What is the basis on flip-flops replaced by a latch
145609: 10/02/15: Re: What is the basis on flip-flops replaced by a latch
145610: 10/02/15: Intel's super-pipeline logic circuit paper is found
145611: 10/02/15: The more you read, the more you are confused: about Intel's a patent
145631: 10/02/16: Re: What is the basis on flip-flops replaced by a latch
145645: 10/02/17: How a state machine is constructed using latches?
145648: 10/02/17: Re: How a state machine is constructed using latches?
145651: 10/02/17: Re: How a state machine is constructed using latches?
145652: 10/02/17: Re: How a state machine is constructed using latches?
145655: 10/02/17: Re: How a state machine is constructed using latches?
145663: 10/02/17: Re: How a state machine is constructed using latches?
145664: 10/02/17: Re: What is the basis on flip-flops replaced by a latch
145679: 10/02/18: Re: How a state machine is constructed using latches?
145693: 10/02/18: Re: What is the basis on flip-flops replaced by a latch
145769: 10/02/22: Re: How a state machine is constructed using latches?
145802: 10/02/24: Re: using an FPGA to emulate a vintage computer
145813: 10/02/24: Re: How a state machine is constructed using latches?
145850: 10/02/25: Re: How a state machine is constructed using latches?
146216: 10/03/08: Why doesn't this situation generate a latch?
146224: 10/03/09: Re: Why doesn't this situation generate a latch?
146229: 10/03/09: Re: Why doesn't this situation generate a latch?
146295: 10/03/10: Re: Why doesn't this situation generate a latch?
146314: 10/03/11: Re: Why doesn't this situation generate a latch?
146326: 10/03/11: Re: Why doesn't this situation generate a latch?
146407: 10/03/16: Any advice on which is the best book on CMOS digital circuit design?
146411: 10/03/16: Re: Why doesn't this situation generate a latch?
146427: 10/03/17: Re: Any advice on which is the best book on CMOS digital circuit
146450: 10/03/18: Re: Why doesn't this situation generate a latch?
146487: 10/03/19: Re: Why doesn't this situation generate a latch?
146679: 10/03/25: Re: Any advice on which is the best book on CMOS digital circuit
146762: 10/03/27: Re: Any advice on which is the best book on CMOS digital circuit
146786: 10/03/28: Which is the most beautiful and memorable hardware structure in a
146867: 10/03/30: Re: Which is the most beautiful and memorable hardware structure in a
146898: 10/03/31: Re: Any advice on which is the best book on CMOS digital circuit
146929: 10/04/02: Re: Which is the most beautiful and memorable hardware structure in a
147368: 10/04/23: Re: Efficient Multi-Ported Memories for FPGAs
147380: 10/04/24: Re: Efficient Multi-Ported Memories for FPGAs
147391: 10/04/25: Re: Efficient Multi-Ported Memories for FPGAs
148325: 10/07/07: How to declare a port with a new type
148965: 10/09/15: Re: Question about OC PCI Cores
148968: 10/09/16: Re: Question about OC PCI Cores
148981: 10/09/17: Re: Question about OC PCI Cores
152344: 11/08/10: Re: Synthesizable heap-sorter for FPGA - BSD licensed sources
153901: 12/06/28: The definition of comnatorial prcess?
153902: 12/06/28: The definition of combinatorial process?
153915: 12/06/29: Re: The definition of comnatorial prcess?
153921: 12/06/29: Re: The definition of comnatorial prcess?
153923: 12/06/29: Re: The definition of comnatorial prcess?
153927: 12/06/29: Re: The definition of comnatorial prcess?
153929: 12/06/30: Re: The definition of comnatorial prcess?
153935: 12/07/01: Re: The definition of comnatorial prcess?
153954: 12/07/02: Re: The definition of comnatorial prcess?
157732: 15/02/24: New invention: Systematic method of coding wave pipelined circuits in HDL
157777: 15/03/13: Re: New invention: Systematic method of coding wave pipelined
157828: 15/04/05: Does each core of 8-core Intel processor has an independent floating
158635: 16/02/21: Where is a code example on how to use a floating multiplier on FPGA
158637: 16/02/21: Re: Where is a code example on how to use a floating multiplier on
158660: 16/03/04: Re: Where is a code example on how to use a floating multiplier on
158661: 16/03/04: How to define a counter whose width is big enough to hold integer 27?
158663: 16/03/04: Re: Where is a code example on how to use a floating multiplier on
158664: 16/03/04: Re: How to define a counter whose width is big enough to hold integer 27?
158670: 16/03/04: Re: How to define a counter whose width is big enough to hold integer 27?
158682: 16/03/07: Re: How to define a counter whose width is big enough to hold integer 27?
158683: 16/03/07: Re: How to define a counter whose width is big enough to hold integer 27?
158693: 16/03/09: Re: How to define a counter whose width is big enough to hold integer 27?
158694: 16/03/09: Re: How to define a counter whose width is big enough to hold integer 27?
160390: 18/01/10: Re: HDL simple survey - what do you actually use
160392: 18/01/10: My invention: Coding wave-pipelined circuits with buffering function
160400: 18/01/12: Re: My invention: Coding wave-pipelined circuits with buffering
160408: 18/01/13: Re: My invention: Coding wave-pipelined circuits with buffering
160412: 18/01/16: Re: My invention: Coding wave-pipelined circuits with buffering
160417: 18/01/17: Re: My invention: Coding wave-pipelined circuits with buffering
160423: 18/01/19: Re: My invention: Coding wave-pipelined circuits with buffering
160427: 18/01/21: Re: My invention: Coding wave-pipelined circuits with buffering
160431: 18/01/21: Re: My invention: Coding wave-pipelined circuits with buffering
160436: 18/01/22: Re: My invention: Coding wave-pipelined circuits with buffering
160438: 18/01/22: Re: My invention: Coding wave-pipelined circuits with buffering
160439: 18/01/22: Re: My invention: Coding wave-pipelined circuits with buffering
160441: 18/01/22: Re: My invention: Coding wave-pipelined circuits with buffering
160443: 18/01/22: Re: My invention: Coding wave-pipelined circuits with buffering
160448: 18/01/23: Re: My invention: Coding wave-pipelined circuits with buffering
160451: 18/01/23: Re: My invention: Coding wave-pipelined circuits with buffering
160453: 18/01/24: Re: My invention: Coding wave-pipelined circuits with buffering
160460: 18/01/24: Re: My invention: Coding wave-pipelined circuits with buffering
160468: 18/01/26: Re: My invention: Coding wave-pipelined circuits with buffering
160831: 18/12/04: How to write an "alias" statement
160832: 18/12/04: Re: How to write an "alias" statement
160833: 18/12/04: How to make Altera-Modelsim free download version to work?
160837: 18/12/05: Re: How to write an "alias" statement
160838: 18/12/05: Re: How to make Altera-Modelsim free download version to work?
160839: 18/12/05: Re: How to make Altera-Modelsim free download version to work?
160843: 18/12/05: Re: How to make Altera-Modelsim free download version to work?
160854: 18/12/06: Re: How to make Altera-Modelsim free download version to work?
160859: 18/12/07: Re: How to make Altera-Modelsim free download version to work?
160863: 18/12/08: Re: How to make Altera-Modelsim free download version to work?
160868: 18/12/11: Re: How to make Altera-Modelsim free download version to work?
160871: 18/12/13: What is the name of the circuit structure that generates a state
160875: 18/12/13: Re: What is the name of the circuit structure that generates a state
160877: 18/12/13: Re: What is the name of the circuit structure that generates a state
160879: 18/12/13: Re: What is the name of the circuit structure that generates a state
160880: 18/12/13: Re: How to make Altera-Modelsim free download version to work?
160887: 18/12/13: Re: What is the name of the circuit structure that generates a state
160888: 18/12/13: Re: How to make Altera-Modelsim free download version to work?
160891: 18/12/14: Re: What is the name of the circuit structure that generates a state
160892: 18/12/14: Re: How to make Altera-Modelsim free download version to work?
160894: 18/12/14: Re: How to make Altera-Modelsim free download version to work?
160896: 18/12/14: Re: What is the name of the circuit structure that generates a state
160900: 18/12/15: Re: What is the name of the circuit structure that generates a state
160901: 18/12/15: Re: How to make Altera-Modelsim free download version to work?
160902: 18/12/15: Re: How to make Altera-Modelsim free download version to work?
160905: 18/12/15: Re: What is the name of the circuit structure that generates a state
160906: 18/12/15: Re: What is the name of the circuit structure that generates a state
160911: 18/12/16: Re: What is the name of the circuit structure that generates a state
160930: 18/12/22: Re: What is the name of the circuit structure that generates a state
160932: 18/12/22: Re: What is the name of the circuit structure that generates a state
160935: 18/12/23: Re: How to make Altera-Modelsim free download version to work?
160936: 18/12/23: Re: What is the name of the circuit structure that generates a state
160953: 19/01/04: Can I use Verilog or SystemVerilog to write a state machine with
160955: 19/01/05: Re: Can I use Verilog or SystemVerilog to write a state machine with
160960: 19/01/05: Re: Can I use Verilog or SystemVerilog to write a state machine with
160962: 19/01/06: Re: Can I use Verilog or SystemVerilog to write a state machine with
160965: 19/01/06: Re: Can I use Verilog or SystemVerilog to write a state machine with
160967: 19/01/06: Re: Can I use Verilog or SystemVerilog to write a state machine with
160971: 19/01/07: Re: Can I use Verilog or SystemVerilog to write a state machine with
160973: 19/01/08: Re: Can I use Verilog or SystemVerilog to write a state machine with
160976: 19/01/08: Re: Can I use Verilog or SystemVerilog to write a state machine with
160979: 19/01/08: Re: Can I use Verilog or SystemVerilog to write a state machine with
160981: 19/01/08: Re: Can I use Verilog or SystemVerilog to write a state machine with
160984: 19/01/08: Re: Can I use Verilog or SystemVerilog to write a state machine with
160987: 19/01/08: Re: Can I use Verilog or SystemVerilog to write a state machine with
160988: 19/01/08: Re: Can I use Verilog or SystemVerilog to write a state machine with
160989: 19/01/08: Re: Can I use Verilog or SystemVerilog to write a state machine with
160994: 19/01/09: Re: Can I use Verilog or SystemVerilog to write a state machine with
160996: 19/01/09: Re: Can I use Verilog or SystemVerilog to write a state machine with
160999: 19/01/09: Re: Can I use Verilog or SystemVerilog to write a state machine with
161001: 19/01/09: Re: Can I use Verilog or SystemVerilog to write a state machine with
161003: 19/01/09: Re: Can I use Verilog or SystemVerilog to write a state machine with
161006: 19/01/09: Re: Can I use Verilog or SystemVerilog to write a state machine with
161013: 19/01/10: Re: Can I use Verilog or SystemVerilog to write a state machine with
161021: 19/01/11: Re: Can I use Verilog or SystemVerilog to write a state machine with
161025: 19/01/14: Need help to understand: Efficient Multi-Ported Memories for FPGAs
161027: 19/01/14: Re: Need help to understand: Efficient Multi-Ported Memories for FPGAs
161035: 19/01/15: Re: Need help to understand: Efficient Multi-Ported Memories for FPGAs
161036: 19/01/15: Re: Need help to understand: Efficient Multi-Ported Memories for FPGAs
161044: 19/01/15: Re: Need help to understand: Efficient Multi-Ported Memories for FPGAs
161046: 19/01/15: Re: Need help to understand: Efficient Multi-Ported Memories for FPGAs
161421: 19/08/09: Why differences between Merly-type and Moore-type clock-gated state
161423: 19/08/09: Re: Why differences between Merly-type and Moore-type clock-gated
161443: 19/09/25: Re: How to write a correct code to do 2 writes to an array on same cycle?
161445: 19/09/25: Re: How to write a correct code to do 2 writes to an array on same cycle?
161447: 19/09/25: Re: How to write a correct code to do 2 writes to an array on same cycle?
161448: 19/09/25: New keyword "if_2" for HDL is suggested for dealing with 2-write port memory
161450: 19/09/25: Re: New keyword "if_2" for HDL is suggested for dealing with 2-write
161452: 19/09/25: Re: New keyword "if_2" for HDL is suggested for dealing with 2-write
161456: 19/09/26: Re: How to write a correct code to do 2 writes to an array on same cycle?
161460: 19/09/26: Here is new definition for keyword "if_2", version 2.
161462: 19/09/27: Re: Here is new definition for keyword "if_2", version 2.
161464: 19/09/27: Re: Here is new definition for keyword "if_2", version 2.
161467: 19/09/28: Re: Here is new definition for keyword "if_2", version 2.
161470: 19/09/28: Re: Here is new definition for keyword "if_2", version 2.
161472: 19/09/29: Re: Here is new definition for keyword "if_2", version 2.
161524: 19/11/25: New coding method for a state machine in groups in HDL
161528: 19/11/26: Re: New coding method for a state machine in groups in HDL
161530: 19/11/26: Re: New coding method for a state machine in groups in HDL
161535: 19/11/27: Re: New coding method for a state machine in groups in HDL
161537: 19/11/27: Re: New coding method for a state machine in groups in HDL
161540: 19/11/27: Re: New coding method for a state machine in groups in HDL
161541: 19/11/27: Re: New coding method for a state machine in groups in HDL
161542: 19/11/27: Re: New coding method for a state machine in groups in HDL
161544: 19/11/28: Re: New coding method for a state machine in groups in HDL
161561: 19/11/29: Re: New coding method for a state machine in groups in HDL
161565: 19/11/30: Re: New coding method for a state machine in groups in HDL
161576: 19/12/02: Re: New coding method for a state machine in groups in HDL
161647: 20/02/13: How to generate bits info for a record structure?
161649: 20/02/13: Re: How to generate bits info for a record structure?
161657: 20/02/14: Re: How to generate bits info for a record structure?
161660: 20/02/14: Re: How to generate bits info for a record structure?
wenger:
23722: 00/07/06: Before and after configuration, are the undefined I/O ports input or output?
wenghong:
67731: 04/03/17: logic Core: getting started(newbie)
Wenhui Pan:
73092: 04/09/14: Can ACEX work well in high EMI environment?
73096: 04/09/14: is there a way to convert ALTERA MAXPLUS GDF file to LATTICE file?
weniyaa:
45225: 02/07/16: Active HDL 4.2SE library update
Wenju Fu:
83623: 05/05/04: Gated clock problem
Wenjun Fu:
83402: 05/04/28: Gated Clock Timing
83679: 05/05/05: Re: Gated clock problem
83680: 05/05/05: Re: Gated clock problem
83681: 05/05/05: Re: Gated clock problem
83683: 05/05/05: Re: Gated clock problem
Wenrui Gong:
81595: 05/03/28: Re: C++ code to FPGA
Wenwei Qiao:
14816: 99/02/18: Re: Orcad Express Plus vs Foundation Express
16729: 99/06/04: Re: XILINX/ALTERA compatibility
<wenweizha@gmail.com>:
140554: 09/05/16: Bug in Xilinx's hwicap_v1_01_a/src/xhwicap_srp.c
Wenyi - Feng:
6890: 97/07/06: test
Wenyi Feng:
18594: 99/11/02: Re: Optimizing Logic Cells
Wenyi_Feng:
36159: 01/10/31: Re: Can anyone guide me in selecting an FPGA?
Weri Kuolstad:
15755: 99/04/12: Re: FPGA vs CPLD? Any Experts out there?
15784: 99/04/14: Re: FPGA vs CPLD? Any Experts out there?
15991: 99/04/26: Re: Free Xilinx CPLD design software on the web
Werner:
152479: 11/08/29: Re: cheating Arria FPGA i/o count
Werner Dreher:
5813: 97/03/17: Re: PEEL16V8 with PALASM
6662: 97/06/10: Re: ATMEL 17Cxxx ISP function
19019: 99/11/24: Re: Trouble with ATMEL's AT40K20
20145: 00/01/28: Re: Atmel config PROMs
30186: 01/03/27: Re: Xilinx FPGA Config file sizes.
30188: 01/03/27: Re: Alternatives for Xilinx Spartan-II configuration PROM
31813: 01/06/06: Xilinx SpartanII Configuration
31926: 01/06/08: Re: Xilinx SpartanII Configuration
32735: 01/07/06: Re: Downloading file to Xilinx (Vertex_E) FPGA.
33042: 01/07/16: Re: Downloading file to Xilinx (Vertex_E) FPGA.
33447: 01/07/26: Re: XC4010 ! help please
42762: 02/05/02: Re: JTAG programmer (ick!)
42768: 02/05/02: Re: Xilinx Download Cable III
44138: 02/06/12: Re: programming xc3030 using atmel's ATDH2225 programmer cable
Werner Kittinger:
31659: 01/06/01: bitstream compression in Xilinx
wert:
147211: 10/04/19: Strange problem about Virtex-5 during working
werty:
108115: 06/09/05: Re: Forth-CPU design
108410: 06/09/10: Re: Forth-CPU design
115520: 07/02/12: Re: Building Coaxial transmission line on PCB?
115651: 07/02/15: Re: Building Coaxial transmission line on PCB?
115652: 07/02/15: Re: Building Coaxial transmission line on PCB?
129134: 08/02/15: Re: microblaze firmware + UART handshaking blues
Wes.:
56588: 03/06/10: Recovering Data from MACH210 PLDs with Securty Fuse blown
56790: 03/06/16: Re: Recovering Data from MACH210 PLDs with Securty Fuse blown
Wesley J. Landaker:
41438: 02/03/29: Re: cyphers
45913: 02/08/10: Re: EDIF and JHDL information
Wesley Webb:
6897: 97/07/07: VHDL to EDIF translater
<westspeed@gmail.com>:
127265: 07/12/16: [help]SAS with FPGAs
127900: 08/01/10: Can you help me about SAS IP core implementing
<wetstein@my-deja.com>:
25039: 00/08/24: Re: Instantiation of Virtex-E Block SelectRAMs
wflee:
105738: 06/07/30: Re: EDK + Assembly Output Files + External Memory Usage
<wfwyqm@yahoo.com>:
<wgilles@my-dejanews.com>:
15220: 99/03/15: Possible problem with die shrink of xc4010
What Order:
34244: 01/08/17: Re: Internal clock skew when using DLL
whatisasics:
73992: 04/10/02: Re: Open-Source MicroBlaze IP-Core working in FPGA :)
whatisofdm:
87995: 05/08/05: Good intro books on OFDM?
whazzup:
39328: 02/02/06: Re: FPGA vs GAL : Lattice
39378: 02/02/07: Re: FPGA vs GAL : Lattice
whit3rd:
121776: 07/07/12: Re: highly-parallel highspeed connection between two FPGA boards
whitehat09:
150513: 11/01/25: newbie looking for Xilinx help
<whitmoreg@my-deja.com>:
20335: 00/02/06: Alternate to Altera Flex family
whizkid:
75203: 04/10/28: dw_prefer_mc_inside command in DC
75269: 04/10/31: max frequency with TSMC .18u std cell library
75308: 04/11/01: TIME borrowing in synthesis
75314: 04/11/02: How to preserve net names in DC while synthesis
74749: 04/10/18: Constrained Random Value in verilog
74830: 04/10/20: Re: Constrained Random Value in verilog
75361: 04/11/03: Physical Compiler Vs Design Complier
75419: 04/11/05: how to get SDF file from netlist
75463: 04/11/06: how to force DC to use a specific cell ?
75472: 04/11/06: Re: how to force DC to use a specific cell ?
<whizkid777@gmail.com>:
79166: 05/02/15: wireload model./custom wl creation
<who@is.this.com>:
5952: 97/03/29: Re: viewoffice <--> viewoffice compatibility
whoami:
46009: 02/08/14: Re: Synthesis Verilog to ASIC
74697: 04/10/16: Does Xilinx XST plan on supporting `define macro( X ) ?
why_don't_you_listen?:
96793: 06/02/10: Re: why does speed grade effect VHDL program??
Whygee:
19783: 00/01/12: Re: BGA sockets and Virtex
19784: 00/01/12: Re: BGA sockets and Virtex
whygee:
131765: 08/05/01: Old FPGA question
131772: 08/05/01: FLASH vs SRAM (was Re: Old FPGA question)
131773: 08/05/01: Re: Old FPGA question
131778: 08/05/02: Re: FLASH vs SRAM (was Re: Old FPGA question)
131848: 08/05/03: Re: Old FPGA question
131856: 08/05/05: Re: Old FPGA question
131948: 08/05/08: Re: ps2 mouse protocol
132626: 08/06/04: puzzling [and deceiving ?] Actel kit
132693: 08/06/05: Re: Xilinx vs Altera
132741: 08/06/06: Re: puzzling [and deceiving ?] Actel kit
135065: 08/09/12: Seeking several async. SRAMs at 8ns ( IS61LV51216-8T or GS74116TP-8
135067: 08/09/13: Re: Seeking several async. SRAMs at 8ns ( IS61LV51216-8T or GS74116TP-8)
137192: 09/01/01: Re: FPGA > ASIC
137325: 09/01/08: How to contact SiliconBlue ?
137335: 09/01/09: Re: How to contact SiliconBlue ?
137455: 09/01/18: Re: Actel IGLOO FPGA has lower power consumption then Xilinx Coolrunner-II
137488: 09/01/20: FPGA granularity (was Re: Actel IGLOO FPGA)
137490: 09/01/20: Re: FPGA granularity (was Re: Actel IGLOO FPGA)
137520: 09/01/21: Re: FPGA granularity (was Re: Actel IGLOO FPGA)
137522: 09/01/21: Re: FPGA granularity
137525: 09/01/21: Re: FPGA granularity (was Re: Actel IGLOO FPGA)
137527: 09/01/21: Re: FPGA granularity
137535: 09/01/22: Re: FPGA granularity
137536: 09/01/22: Re: FPGA granularity
137537: 09/01/22: Re: FPGA granularity (was Re: Actel IGLOO FPGA)
137544: 09/01/22: Re: How to add some SDRAM to a FPGA board ?
137547: 09/01/22: Re: FPGA granularity
137548: 09/01/22: Re: FPGA granularity
137584: 09/01/22: Re: FPGA granularity
137585: 09/01/23: Re: How to add some SDRAM to a FPGA board ?
137586: 09/01/23: Re: FPGA granularity
137589: 09/01/23: Re: FPGA granularity
137590: 09/01/23: Re: How to add some SDRAM to a FPGA board ?
137591: 09/01/23: Re: How to add some SDRAM to a FPGA board ?
137612: 09/01/23: Re: Spartan chip expulses an extrange substance
139319: 09/03/26: Re: FPGAs in automotive apps
139425: 09/03/29: Re: What does Xilinx mean by "Real 6-input look-up (LUT) technology"?
139876: 09/04/18: Dual-frequency quartz oscillator with a FPGA ?
139882: 09/04/18: Re: Dual-frequency quartz oscillator with a FPGA ?
139885: 09/04/18: Re: Dual-frequency quartz oscillator with a FPGA ?
139889: 09/04/18: Re: Dual-frequency quartz oscillator with a FPGA ?
139892: 09/04/18: Re: Dual-frequency quartz oscillator with a FPGA ?
139907: 09/04/19: Re: Dual-frequency quartz oscillator with a FPGA ?
139908: 09/04/19: Re: Dual-frequency quartz oscillator with a FPGA ?
139918: 09/04/19: Re: Dual-frequency quartz oscillator with a FPGA ?
139919: 09/04/19: Re: Atari VCS 2600 FPGA Cartridge
139920: 09/04/19: PLL ratios (was Re: Dual-frequency quartz oscillator with a FPGA
139922: 09/04/19: Re: Atari VCS 2600 FPGA Cartridge
139924: 09/04/19: Re: Atari VCS 2600 FPGA Cartridge
139931: 09/04/20: Re: PLL ratios (was Re: Dual-frequency quartz oscillator with a FPGA
139932: 09/04/20: Re: PLL ratios (was Re: Dual-frequency quartz oscillator with a FPGA
139953: 09/04/20: Re: FPGA Internal reset
139960: 09/04/21: Re: Dual-frequency quartz oscillator with a FPGA ?
139966: 09/04/21: Re: new FPGA vendor
140022: 09/04/24: Re: some soft-processors
140040: 09/04/25: Re: actel libero
140043: 09/04/25: Re: actel libero
140060: 09/04/27: Re: way to go Altera!
140061: 09/04/27: Re: Modelsim Actel Edition and Soft FIFO Controller
140066: 09/04/27: Re: Modelsim Actel Edition and Soft FIFO Controller
140349: 09/05/10: Re: implementing arbitrary combinational functions using block rams
140504: 09/05/15: Re: actel block RAM initial value
141051: 09/06/04: Re: the reach of VHDL
141081: 09/06/04: Re: the reach of VHDL
141102: 09/06/05: Re: Actel Fusion AFS600 FPGA Flash Memory Bug
141171: 09/06/10: async. SRAM control signal generation
141177: 09/06/10: Re: async. SRAM control signal generation
141180: 09/06/10: Re: async. SRAM control signal generation
141183: 09/06/10: Re: async. SRAM control signal generation
141227: 09/06/11: Re: Safe margin in FPGA static timing analysis
141255: 09/06/12: Re: NTSC/PAL Encoder using FPGA and DAC
141262: 09/06/13: Re: async. SRAM control signal generation
141625: 09/07/01: Re: How to keep documentation of control and status registers and
141631: 09/07/01: Re: FPGA as FM RADIO transmitter
141716: 09/07/04: Re: 50 000 registered users at OpenCores.org
141771: 09/07/08: Re: webserver
142072: 09/07/23: Re: Laser marking / custom graphics on blank FPGA?
142082: 09/07/24: Re: Almost everything about Virtex-6 in one location
142258: 09/07/31: Re: Xilinx Xcell Journal 68
144177: 09/11/17: Re: Too Easy: Actel FPGA's! :)
144179: 09/11/17: Re: Too Easy: Actel FPGA's! :)
144182: 09/11/18: Re: Too Easy: Actel FPGA's! :)
144187: 09/11/18: Re: ML 403 hardware implementation
144236: 09/11/22: Re: FPGA + Ethernet
144237: 09/11/22: Re: FPGA + Ethernet
144296: 09/11/25: 32KHz RTC for FPGA
144302: 09/11/25: Re: 32KHz RTC for FPGA
144305: 09/11/26: Re: 32KHz RTC for FPGA
144307: 09/11/26: Re: 32KHz RTC for FPGA
144310: 09/11/26: Re: 32KHz RTC for FPGA
144314: 09/11/26: Re: 32KHz RTC for FPGA
144315: 09/11/26: Re: 32KHz RTC for FPGA
144316: 09/11/26: Re: 32KHz RTC for FPGA
144324: 09/11/26: Re: 32KHz RTC for FPGA
144325: 09/11/26: some issues with canned oscillators (was Re: 32KHz RTC for FPGA)
144327: 09/11/26: Re: some issues with canned oscillators (was Re: 32KHz RTC for FPGA)
144329: 09/11/26: Re: some issues with canned oscillators (was Re: 32KHz RTC for FPGA)
144374: 09/12/02: domain crossing and clock synchronisation for a high frequency timer
144378: 09/12/02: Re: domain crossing and clock synchronisation for a high frequency
144380: 09/12/02: Re: domain crossing and clock synchronisation for a high frequency
144382: 09/12/02: Re: domain crossing and clock synchronisation for a high frequency
144385: 09/12/03: Re: domain crossing and clock synchronisation for a high frequency
144604: 09/12/20: Re: Memory Latency
144609: 09/12/20: Re: Memory Latency
144628: 09/12/21: Re: Memory Latency
144629: 09/12/21: Re: Memory Latency
144631: 09/12/21: Re: Memory Latency
144633: 09/12/21: Re: Memory Latency
144705: 09/12/26: Re: Xilinx and Multi-port memories
144717: 09/12/28: Re: Xilinx and Multi-port memories
144778: 10/01/02: Re: Xilinx and Multi-port memories
144842: 10/01/07: Re: new PC specs for Xilinx tools
144861: 10/01/08: Re: new PC specs for Xilinx tools
144866: 10/01/08: Re: new PC specs for Xilinx tools
144935: 10/01/16: Re: Altera Quartus II on Debian GNU/Linux
144951: 10/01/17: Re: Altera Quartus II on Debian GNU/Linux
144953: 10/01/17: Re: Altera Quartus II on Debian GNU/Linux
144979: 10/01/18: Re: Altera Quartus II on Debian GNU/Linux
144980: 10/01/18: bit vs std_logic (was Re: Simulation of VHDL code for a vending machine)
144983: 10/01/18: Re: bit vs std_logic (was Re: Simulation of VHDL code for a vending
144984: 10/01/18: Re: bit vs std_logic (was Re: Simulation of VHDL code for a vending
144985: 10/01/18: Re: bit vs std_logic (was Re: Simulation of VHDL code for a vending
145005: 10/01/19: Re: bit vs std_logic (was Re: Simulation of VHDL code for a vending
145011: 10/01/19: Re: bit vs std_logic (was Re: Simulation of VHDL code for a vending
145014: 10/01/19: Re: compiler output to fpga.
145080: 10/01/25: Re: Achronix FPGA
145083: 10/01/26: Re: Achronix FPGA
145090: 10/01/26: Re: Achronix FPGA
145101: 10/01/27: Re: Please help, Xilinx FIFO problem!
145102: 10/01/27: Re: Achronix FPGA
145104: 10/01/27: Re: Please help, Xilinx FIFO problem!
145195: 10/02/01: Re: Constraining minimum hold times (Xilinx)
145271: 10/02/04: Re: How good are Actel tools
145274: 10/02/04: Re: Matching hadware and software CRC
145349: 10/02/06: Re: Board layout for FPGA
145518: 10/02/13: Re: VHDL vs Verilog
145519: 10/02/13: Re: VHDL vs Verilog
145527: 10/02/13: Re: VHDL vs Verilog
145528: 10/02/13: Re: VHDL vs Verilog
145529: 10/02/13: Re: VHDL vs Verilog
145530: 10/02/13: Re: VHDL vs Verilog
145531: 10/02/13: Re: VHDL vs Verilog (quote found)
145540: 10/02/13: Re: 28nm FPGAs are coming...
145564: 10/02/14: Re: 28nm FPGAs are coming...
145653: 10/02/17: Re: How a state machine is constructed using latches?
145757: 10/02/22: Re: Reading UDP with FPGA
145770: 10/02/23: Re: Reading UDP with FPGA
146076: 10/03/05: Re: Announce: 1 Pin Interface - FPGA and HW debug tool
146123: 10/03/06: Re: FSM in BlockRAM
146317: 10/03/11: Re: Tier Logic introduces the world's first 3D FPGA
146322: 10/03/11: Re: Tier Logic introduces the world's first 3D FPGA
146349: 10/03/13: Re: Tier Logic introduces the world's first 3D FPGA
146350: 10/03/13: Re: Tier Logic introduces the world's first 3D FPGA
146359: 10/03/14: Re: Tier Logic introduces the world's first 3D FPGA
146365: 10/03/14: Re: Tier Logic introduces the world's first 3D FPGA
146372: 10/03/15: Re: Tier Logic introduces the world's first 3D FPGA
146523: 10/03/22: Re: Digilent Nexys2 board
146610: 10/03/23: Re: Why hardware designers should stick to command line tools
146611: 10/03/23: Re: Why hardware designers should switch to Eclipse
146637: 10/03/25: Re: Why hardware designers should switch to Eclipse
146640: 10/03/25: Re: Ring Oscillator -> counter differences
146683: 10/03/26: where is VHDL-POSIX ?
146687: 10/03/26: Re: where is VHDL-POSIX ?
146764: 10/03/28: Re: where is VHDL-POSIX ?
146775: 10/03/28: Re: XST optimization
146776: 10/03/28: Re: XST optimization
146798: 10/03/29: Re: Which is the most beautiful and memorable hardware structure
146833: 10/03/30: Re: Which is the most beautiful and memorable hardware structure
146886: 10/03/31: Re: Spartan 6 PLL - Why such a strict input jitter requirement?
146943: 10/04/03: Re: Free VHDL or Verilog Simulator
146988: 10/04/08: Re: Summing with carry problems ...
147074: 10/04/13: Re: How to find latches in Xilinx ISE 10.1
147082: 10/04/13: Re: How to find latches in Xilinx ISE 10.1
147123: 10/04/14: Re: Read from the compact flash
147171: 10/04/16: Re: I'd rather switch than fight!
147194: 10/04/17: Re: Which 32 bit cores support full Linux?
147201: 10/04/18: Re: Which 32 bit cores support full Linux?
147236: 10/04/20: Re: Developin tool for Xilinx XC2018
147386: 10/04/25: Re: Craignell2-48 - 48 Pin FPGA DIL Module
147435: 10/04/27: Re: Craignell2-48 - 48 Pin FPGA DIL Module
147497: 10/04/29: Re: xilinx arm finally announced
147612: 10/05/07: Re: FPGA Compilation Time Windows vs Linux
147615: 10/05/07: Re: FPGA Compilation Time Windows vs Linux
147682: 10/05/14: Re: New 'standard' compact programming header needed!
147700: 10/05/18: Re: New 'standard' compact programming header needed!
147717: 10/05/19: Re: Xilinx Synthesis Tool generates clock signals from combinatorial
148449: 10/07/24: Is Tier Logic doomed ? :-/
150918: 11/02/22: Actel PA3 hard FIFO: anything i have not understood ?
150920: 11/02/22: Re: Actel PA3 hard FIFO: anything i have not understood ?
151157: 11/03/12: Re: pcb&bitstream
151158: 11/03/12: Re: pcb&bitstream
151170: 11/03/13: Re: pcb&bitstream
151187: 11/03/14: Re: pcb&bitstream
151199: 11/03/15: Re: pcb&bitstream
151200: 11/03/15: Re: pcb&bitstream
151205: 11/03/15: Re: pcb&bitstream
151240: 11/03/17: Re: pcb&bitstream
151731: 11/05/12: Re: Soft Processors and Licensing
Wichai Tang:
133: 94/08/26: I wnat to contact Harris
138: 94/08/29: About harris
838: 95/03/10: How to partitions the design by ppr ?
1025: 95/04/18: Re: I-Cube - contact information ?
1080: 95/04/25: Need help about conference chip
1155: 95/05/07: Re: Need help about conference chip
1156: 95/05/07: Re: Need help about conference chip
<wickedchicken@trioptimum.com>:
54771: 03/04/17: Re: Hardware acceleration for raytracing purposes
wicky:
96827: 06/02/10: Re: FPGA-Programmable power supply
96833: 06/02/11: using FPGA in control field
96839: 06/02/11: Re: using FPGA in control field
96858: 06/02/11: Re: using FPGA in control field
96884: 06/02/12: Re: using FPGA in control field
98080: 06/03/04: can I port ppclinux to virtex4-fx?
98091: 06/03/04: Re: can I port ppclinux to virtex4-fx?
98123: 06/03/05: Re: can I port ppclinux to virtex4-fx?
117695: 07/04/07: can anyone give me a reference price of the following Xilinx boards?
117724: 07/04/08: Re: can anyone give me a reference price of the following Xilinx boards?
117725: 07/04/08: Re: can anyone give me a reference price of the following Xilinx boards?
129947: 08/03/11: Could I develop a new gui using java based on the script language of
129950: 08/03/11: Re: Could I develop a new gui using java based on the script language
129971: 08/03/11: Re: Could I develop a new gui using java based on the script language
130012: 08/03/12: Re: Could I develop a new gui using java based on the script language
132143: 08/05/15: PCI to SATA of industrial class ( -40 - 85 )
132144: 08/05/15: Re: Camera link interface
132197: 08/05/16: Re: PCI to SATA of industrial class ( -40 - 85 )
132198: 08/05/16: Re: difference between 8.2i and 9.2i with respect to Microblaze Core
wicore:
148795: 10/08/25: Re: Mismatch between Xilinx FIR interpolation filter
<widding@birger.com>:
26982: 00/11/06: Synario License
78838: 05/02/08: Re: V4LX25-ES and systemACE
<widding@my-deja.com>:
28905: 01/01/29: Re: Encryption is supported in new Virtex II but.....
wieler:
405: 94/11/08: Using Xilinx Wide edge Decoders
481: 94/11/30: Re: ASIC emulation (Quickturn, etc.)
618: 95/01/19: Re: Partitioning and synthesis
884: 95/03/20: Re: Boundary Scan in a Xilinx 4010
wiezbox:
72980: 04/09/09: new to fpga
Wiggo Olufsen:
14725: 99/02/13: Re: Problems with Xilinx F1.5 & latchs
14800: 99/02/17: Re: Digital PLL
14949: 99/02/26: Re: wanted: info about Fast Ethernet cores
14993: 99/03/02: Re: LCD driver
15103: 99/03/06: Re: Current State of FPGA-based PCI Interfaces?
15405: 99/03/23: Re: From VHDL to FPGA?
20344: 00/02/07: Re: Looking for a small, fast CPU core for FPGA
20929: 00/02/29: Re: atmel fpga starter kit
wiggs:
90344: 05/10/10: Re: Virtex-4 FX20 PPC405 Startup Issue
90349: 05/10/10: Re: Virtex-4 FX20 PPC405 Startup Issue
Wil Limbacher:
55522: 03/05/11: Re: PacMan game in FPGA
55556: 03/05/12: Re: PacMan game in FPGA
Wil Taphoorn:
4888: 96/12/25: Re: I2C Bus Interface in FPGAs
Wilbur Harvey:
64135: 03/12/18: Re: Xilinx 6.1i Tools and Newer Redhat Linux OSes
64179: 03/12/19: Re: Xilinx 6.1i Tools and Newer Redhat Linux OSes
72752: 04/08/31: Re: Impact vs. Linux RedHat Linux
Wilco Vahrmeijer:
37640: 01/12/18: FGPA express bidir pins Xilinx, FPGA-pmap-18
WildBeach:
15562: 99/03/30: Re: PAMette for Rapid Prototyping
17112: 99/07/01: Re: FW: Xilinx Acquisition of CoolRunners
Wilfred Gomes:
513: 94/12/16: Re: Any benchmark for FCMs?.
WIlfredo Falcón:
62224: 03/10/22: Timing analysis
Wilfredo Torres:
6402: 97/05/21: No message
Wilfried Eisele:
5899: 97/03/24: Re: Problem loading XC4010E with XCHECKER!
Wilfried Philippi:
33441: 01/07/26: PCI-Interface
Wilhelm Heupke:
30707: 01/04/25: Re: Failed to configure Spartan2
Wilhelm Klink:
53795: 03/03/23: quartus II error/warning: cannot generate netlist output file -- unsupported port type (std_logic_2d)
58950: 03/08/04: Multiple device configuration using local update over ethernet
58996: 03/08/05: Re: Multiple device configuration using local update over ethernet
71197: 04/07/11: FIR filter running out of FPGA memory in stratix ep1s60
71307: 04/07/14: Re: FIR filter running out of FPGA memory in stratix ep1s60
71340: 04/07/15: Re: FIR filter running out of FPGA memory in stratix ep1s60
72314: 04/08/14: clock enable multicycle doesn't work with altera altshift_taps megafunction
72770: 04/08/31: Sentinel dongle no longer detected by Quartus
72795: 04/09/01: Re: Sentinel dongle no longer detected by Quartus
<Wilhelm.Klink@gmail.com>:
114249: 07/01/08: Quartus II 6.1 Remove Duplicate Logic option removed
118950: 07/05/07: Altera FIR Compiler with clock enable
119336: 07/05/16: Re: Altera FIR Compiler with clock enable
wiliki:
795: 95/03/03: Re: IST Drying Up In North America
Wiljan:
102287: 06/05/14: Picture frame
137864: 09/02/01: Rotate video
Will:
29511: 01/02/24: cpul vs vhdl
29516: 01/02/24: Re: cpul vs vhdl
41635: 02/04/03: Free6502 ops
47848: 02/10/05: Re: TCP/IP in FPGA
47855: 02/10/05: Re: TCP/IP in FPGA
48181: 02/10/12: Re: Verilog vs VHDL discussion on comp.arch.verilog group
48698: 02/10/22: Re: FPGA XC4005E
51591: 03/01/16: Re: Student development board
51600: 03/01/16: Re: Student development board
51660: 03/01/17: Re: Student development board
58936: 03/08/04: Re: Tiny TCP/IP stack and tiny MAC controller on FPGA for direct download to S(D)RAM memory
61088: 03/09/27: Re: FPGA implementation of a lexer and parser - feasible?
61792: 03/10/10: Re: Xilinx XC2S50: Unable to configure through slave serial mode
62571: 03/11/01: Re: WinCE driver for Wildcard from Annapolis Micro System?
63859: 03/12/05: Re: Dual-port and single-port BlockRAM instantiation
64097: 03/12/16: Re: PIN naming confusion xilinx spartan 2E XC2S200E
67429: 04/03/11: Re: Answering Machine RAM
67806: 04/03/19: Re: Why It Is not Recommended to Infer latches in VLSI Design...
69670: 04/05/17: Re: Low cost FPGA dev board with high speed i/f?
82412: 05/04/12: Re: problem in driving I2C bus through memory-mapped register
115567: 07/02/13: Need FPGA recommendation
118148: 07/04/18: IOB and DIFFM/DIFFS
Will Dean:
111087: 06/10/28: Re: Xilinx Virtex4 Outputs for Camera Link
111178: 06/10/30: Re: A pre-emptive strike against blaming the chip
111179: 06/10/30: Re: Xilinx Virtex4 Outputs for Camera Link
111180: 06/10/30: Re: Xilinx Virtex4 Outputs for Camera Link
111412: 06/11/02: Re: Spectre of Metastability Update
111580: 06/11/06: Re: Cypress 68013 - Xilinx FPGA
111700: 06/11/08: Re: Non deterministic behaviour in quartus II ?
111737: 06/11/09: Re: Non deterministic behaviour in quartus II ?
111911: 06/11/13: Re: Stratix-III announced
111936: 06/11/13: Re: FPGA Debug Tool
111949: 06/11/13: Re: FPGA Debug Tool
112502: 06/11/23: Re: Cypress 68013 - Xilinx FPGA
112503: 06/11/23: Re: Altera configuration with microcontroller
112671: 06/11/27: Re: Altera's USB blaster
113379: 06/12/12: Re: linking two fpga boards
113680: 06/12/19: Re: Frequency divider ?
114583: 07/01/19: Re: Considerations for FPGA Based Acceleration in Bio medical simulations/computational biology
115057: 07/01/30: Re: USB 2.0 Streaming using FPGAs
115075: 07/01/30: Re: USB 2.0 Streaming using FPGAs
116428: 07/03/08: Re: Driving PLL from general I/O in Altera Cyclone
116454: 07/03/09: Re: Driving PLL from general I/O in Altera Cyclone
116465: 07/03/09: Re: Driving PLL from general I/O in Altera Cyclone
126290: 07/11/19: Re: Low cost FPGA w/serdes
Will Dwinnell:
50687: 02/12/17: Re: neural networks
Will Hua Zheng:
84967: 05/06/01: Re: how to use GCC compiler
84995: 05/06/02: Re: Basics FPGA
85003: 05/06/02: Re: Basics FPGA
85004: 05/06/02: Re: Basics FPGA
85222: 05/06/06: Re: Basics FPGA
Will Rose:
5302: 97/02/05: Duplicate PLD?
Will Ware:
1437: 95/06/22: Re: Low cost ISA board
1450: 95/06/23: Re: Low cost ISA board
1469: 95/06/27: Re: Place-n-Route service
<will.parks@gmail.com>:
111237: 06/10/31: filter design for low-pass
111262: 06/10/31: Re: filter design for low-pass
111280: 06/10/31: Re: filter design for low-pass
111307: 06/11/01: Re: filter design for low-pass
Willem Oosthuizen:
55475: 03/05/09: Re: Encrypted bitstream - battery lifetime problem
57186: 03/06/25: Re: Interfacing IDE
57246: 03/06/26: Re: Low-power FPGA
58230: 03/07/17: Re: PCI - disabling
58258: 03/07/18: Level translators on PCI
william:
149569: 10/11/05: ucf impact to synplify pro
William:
2112: 95/10/17: Re: Bet you can't do these....
12598: 98/10/19: Re: More: What's wrong at this Address decoder?
15850: 99/04/16: Re: std_logic_arith
26747: 00/10/27: 890622@itri.org.tw
69234: 04/05/01: Nexar for FPGA Design?
74962: 04/10/22: Re: Virtex-4: DSP48 Fmax missing?
74732: 04/10/17: Virtex-4: DSP48 Fmax missing?
William A. Gordon:
2888: 96/02/24: Xilinx 7336 EPLD
William Andrew Publishing:
28477: 01/01/14: Great New Electronics Book
William Banzhof:
27332: 00/11/18: Re: Altera MAX+PlusII v.s. Xilinx Foundation
William Billowitch:
3145: 96/04/12: Re: VHDL conversion function from int to time ...?
3243: 96/05/02: ANNOUNCE: New Products and Prices
3250: 96/05/03: ANNOUNCE: New Products and Prices
William Chow:
24901: 00/08/21: xdl documentation
25219: 00/08/31: directives such as _SUPERBEL, _PINMAP
William D. Billowitch:
9334: 98/03/06: Re: The case for Linux and EDA (Take Discussion Offline !)
William E. Lenihan III:
6357: 97/05/17: Re: xilinx xblox with capture ver 7.00
6449: 97/05/25: Re: Glitches in timing simulation of Xilinx FPGAs with Synopsys
6447: 97/05/25: Re: Best way to learn VHDL?
6450: 97/05/25: Re: What is M1?
6641: 97/06/08: Re: Don't Design With Altera Parts... Altera Obsolete Parts
William F. Gilreath:
31002: 01/05/09: Looking for information on Move-based architectures
William H. Maddox III:
69592: 04/05/14: Clueless newbie question -- what has changed to make moisture such
William Hall:
46069: 02/08/16: Xilinx suppliers in UK
46079: 02/08/16: Re: Xilinx iMPACT/Parallel Port programming in Win XP soloution?
46088: 02/08/17: V2PRO PowerPC floating point
William J. Wolf:
272: 94/10/10: Re: List of FPGA based Computing Systems
314: 94/10/18: Re: FPGA RISC Processor
326: 94/10/20: Re: Analog FPGAs
578: 95/01/09: Re: Motorola FPGA
610: 95/01/18: Partitioning and synthesis
616: 95/01/19: NeoCAD Experience
650: 95/01/27: Re: NeoCAD Experience
742: 95/02/21: Cadence FPGA Designer
735: 95/02/20: Programmable Logic Names & Primers
736: 95/02/20: Newbie Info
967: 95/04/05: Vendor Info
998: 95/04/11: Re: Neocad merges with Xilinx
1003: 95/04/12: Re: AT&T Statement ref Neocad
1030: 95/04/18: Re: Free Hardware
1051: 95/04/21: Re: Neocad merges with Xilinx
1082: 95/04/25: Re: Sunrise ???
1085: 95/04/26: Re: How much performance is enough?
1120: 95/05/02: Re: ASIC group ?
1227: 95/05/18: Re: 1000 pin fpga's ?
1283: 95/05/26: Re: Altera Contacts ...
1387: 95/06/12: Re: Pricing Info anyone?
1438: 95/06/22: Re: usable gates quotes from Altera
1454: 95/06/24: Re: Low cost ISA board
1455: 95/06/24: Re: Low cost ISA board
1771: 95/08/29: Re: Any FPGA FAQ?
2174: 95/10/26: Re: PLD in small package ?? anyone
2181: 95/10/27: Re: Xilinx Configuration Memory Hacking
2194: 95/10/30: Re: Xilinx Configuration Memory Hacking
2255: 95/11/10: Re: Xilinx Configuration Memory Hacking
3267: 96/05/07: Re: Simple Xilinx board
3286: 96/05/09: Re: On FPGAs as PC coprocessors [rererepost]
3681: 96/07/12: Xilinx reconfigurable logic strategy
3836: 96/08/08: Re: "Xilinx nixes its antifuse arrays"
3933: 96/08/22: Re: XC6200 FPGAs
4289: 96/10/10: FPGA Web Links
William Jones:
10001: 98/04/21: C++, C, Java to hardware compiler
William K. McFadden:
916: 95/03/29: Re: Excuse me while I vent about Data I/O & Abel...
William Killian:
24677: 00/08/16: Re: Non-disclosures in job interviews
William L Hunter Jr:
3291: 96/05/09: Re: Simple Xilinx board
36022: 01/10/26: ILA CHIPSCOPE
36847: 01/11/22: Re: Decoupling capacitors on Virtex II
41462: 02/03/29: Re: HELP me, about chipscope analyzer
42156: 02/04/17: GND Outputs being optimized out using FPGA Express 3.6.1 in ISE4.2.01
42180: 02/04/18: Re: GND Outputs being optimized out using FPGA Express 3.6.1 in ISE4.2.01
43151: 02/05/14: Heat Sink/Fan for XC2V3000-4BF957
46935: 02/09/12: XILINX FPGA output not right
William L. Bahn:
10290: 98/05/09: Xilinx Configuration Problem
10313: 98/05/11: Re: Xilinx Configuration Problem
10314: 98/05/11: Re: Xilinx Configuration Problem
10315: 98/05/11: Re: Xilinx Configuration Problem
10366: 98/05/14: Xilinx Configuration Problem - Solved
William Lenihan:
30454: 01/04/09: small, fast, w/ PECL?
30635: 01/04/20: Re: small, fast, w/ PECL?
30720: 01/04/26: Virtex power supplies.
36105: 01/10/30: Guided Design, Xilinx Virtex-E
36319: 01/11/06: Re: Guided Design, Xilinx Virtex-E
40961: 02/03/19: Xilinx JTAG Cables
43909: 02/06/06: xc3042
45600: 02/07/29: timing got worse?
45662: 02/07/31: Re: ntelist problem
William LenihanIii:
21048: 00/03/04: Re: Testbenches
22428: 00/05/09: pipeline shiftreg in virtex
22531: 00/05/11: Re: pipeline shiftreg in virtex
22694: 00/05/18: PCI & Virtex
23013: 00/06/09: Synopsys FPGA Compiler
46285: 02/08/24: upgrade S/W -> timing worse
57397: 03/06/29: SPARTAN-3 vs. VIRTEX-II
57528: 03/07/02: Re: SPARTAN-3 vs. VIRTEX-II
58856: 03/08/03: Unused Pins on big Virtex-II
William M. Wiese Jr.:
9036: 98/02/16: Re: x86 soft cores?
William Marble:
10426: 98/05/18: Re: ++ TMS320C6x DSP info website ++
William Meyer:
33296: 01/07/22: Re: Maxplus II download sites
40859: 02/03/17: Re: just bought...
40890: 02/03/17: Re: just bought...
40892: 02/03/17: Re: just bought...
40931: 02/03/18: Re: just bought...
42179: 02/04/18: Re: just bought Cohen's book...Real Chip Design and Verification using Verilog and VHDL
51045: 02/12/28: Re: BP programmer questions, prices, alternatives
William N. Eatherton:
2055: 95/10/07: Needed: PCI prototyping board, for use testing with FPGA interface
william pawlowski:
15731: 99/04/11: fpga express stripping out Viewlogic busses
William Sealey Gosset:
88234: 05/08/12: Atmel AT40k/94k Configuration Format Documentation
william semonis:
7729: 97/10/08: IT'S YOUR HEALTH
William Stallings:
3595: 96/07/02: Re: REQ:Old Picture of Bus
William Tanksley Google:
50414: 02/12/10: Re: Tiny Forth Processors
50482: 02/12/11: Re: Tiny Forth Processors
50484: 02/12/11: Re: Tiny Forth Processors
50488: 02/12/11: Re: Tiny Forth Processors
50497: 02/12/11: Re: Tiny Forth Processors
William Vollrath:
4451: 96/10/30: Altera & Verilog
4900: 96/12/26: Re: FPGA market overview
4903: 96/12/26: Re: PCI Bus Based designs using FPGA's
5105: 97/01/23: Re: Altera PCI experience anyone?
38599: 02/01/18: Re: Virtex-2 maximum clock speed
William Wallace:
43717: 02/05/30: Re: Engineering Samples for free?
43718: 02/05/30: Re: place and route simulation time
65767: 04/02/05: Re: Is it possible that a Virtex II device performs below its spec?
65768: 04/02/05: Re: Modelsim Error Code 211
65769: 04/02/05: Re: Altera Nios UART communication
65770: 04/02/05: Re: Power extimation?
65820: 04/02/06: Re: Is it possible that a Virtex II device performs below its spec?
65868: 04/02/09: Re: Pricing, 101
65871: 04/02/09: Re: A small clock synchronization challenge with Virtex E
65913: 04/02/09: Re: Artificial Intelligence/FPGA
65984: 04/02/10: Re: Pricing, 101
65985: 04/02/10: Re: Pricing, 101
65986: 04/02/10: Re: Pricing, 101
66183: 04/02/13: Re: How many PCB layers ?
66223: 04/02/14: Re: How many PCB layers ?
66870: 04/02/28: Re: DLL block
66871: 04/02/28: Re: FSM in fpga's
66872: 04/02/28: Re: using fpga for sampling audio
66873: 04/02/28: Re: Using 3.3V compliant FPGA for 5V PCI
66874: 04/02/28: Re: Polyphase filter
66897: 04/02/28: Re: Polyphase filter
67030: 04/03/03: Re: Dongle compatibility
67031: 04/03/03: Re: TRST Pin in Altera FPGAs
67130: 04/03/05: Re: Dongle compatibility
67131: 04/03/05: Re: TRST Pin in Altera FPGAs
67132: 04/03/05: Re: Polyphase filter
67133: 04/03/05: Release asynchrounous resets synchronously
67134: 04/03/05: Re: fatal error : help required
67232: 04/03/08: Re: Release asynchrounous resets synchronously
67233: 04/03/08: Re: Release asynchrounous resets synchronously
67622: 04/03/15: Re: Release asynchrounous resets synchronously
67624: 04/03/15: Re: Release asynchrounous resets synchronously
William Wallis:
32302: 01/06/22: ALTERA CHIPS - ANYBODY WANT TO BUY A "FEW" ONLY?
William White:
1053: 95/04/21: Re: VHDL -> Xilinx synthesis
6731: 97/06/20: Re: Viewlogic- PUSH VHDL
7965: 97/11/04: Re: viewlogic question
9132: 98/02/23: Re: Mach211 fpga programming
9044: 98/02/17: Re: Viewlogic/Speedwave
10571: 98/06/01: Re: SpeedWave Problem
10710: 98/06/11: Re: TESTBENCH
16355: 99/05/18: Re: Post route simulation: EDIF or VHDL?
WilliamGibb@gmail.com:
138274: 09/02/11: Re: Read a PS2 Keyboard input
145107: 10/01/27: Re: Achronix FPGA
williams:
79933: 05/02/26: Interfacing virtex 2 pro to flash memory
80552: 05/03/08: Guideline for PCB routing for PCI signal
80961: 05/03/15: Calling netlist module in a design
81898: 05/04/04: IBUFG and BUFG +xilinx
82478: 05/04/13: Timing and synthesis problem+xilinx
82793: 05/04/18: combining two EDF netlist in ISE
82876: 05/04/19: Strange FPGA problem
willie CHEN:
79763: 05/02/24: How to synthesize the xilinx ip core?
79847: 05/02/25: Re: How to synthesize the xilinx ip core?
<willwestward@gmail.com>:
120484: 07/06/08: Re: Arbiter
120534: 07/06/08: Re: Arbiter
120556: 07/06/09: Re: Arbiter
Willy:
5664: 97/03/05: Re: Antifuse Comparisons?
5665: 97/03/05: XILINX LIBRARY FOR VIEWLOGIC
8208: 97/11/28: Re: Xilinx tech support
9984: 98/04/21: XNF to EDIF utility
11624: 98/08/27: Re: Example Code
11625: 98/08/27: Re: FFT-Speed
Willy_Tsai:
16012: 99/04/28: z80 core
16050: 99/04/30: P I/O core
16223: 99/05/11: We need engineer
22937: 00/06/05: Altera and Atmel FPGA/CPLD in-system-programmer from SmartChip
Wilson Lee:
9866: 98/04/09: Re: Investigate anyone right from your browser!
9974: 98/04/18: FPGA programming info
10182: 98/05/01: Re: Xilinx Foundation and Linux
10340: 98/05/13: Re: Chicken & egg problem in PCI/CardBus designs using FPGA
Wilson TAN:
21151: 00/03/09: Re: help me!...please...
Wilton de Castro Padrao:
15099: 99/03/06: newbie question about PALASM 1.5
Wilwert Marc:
3731: 96/07/22: Daisychain or SPROM?
3739: 96/07/23: Mentor->XC3064
Wim Lewis:
128451: 08/01/27: Re: effect of xray on fpga electronic circuits
Wim Peeters:
43204: 02/05/16: extend jtag downloadcable
43628: 02/05/28: Re: extend jtag downloadcable
Wim Rijkers:
1094: 95/04/27: Re: SIS (where do I find it)
Wim Ton:
71604: 04/07/24: Re: Cheap FPGA's
111251: 06/10/31: Re: Stream cipher
Wim Vanderstraeten:
5966: 97/03/31: XC2018
WiMos:
119080: 07/05/11: Re: Xilinx software quality - how low can it go ?!
Win Hill:
31499: 01/05/28: Re: Want to buy: Old copy of ABEL, Synario or ViewPLD
=?windows-1252?Q?=5BLinuxF8=2D64=5DGaLaKtIkUs=99?=:
141819: 09/07/10: Re: Xilinx Spartan 3 DCM no output!
=?windows-1252?Q?Adam_G=F3rski?=:
156937: 14/07/30: Re: Primitive debuggable UART interface to a Nios within a multi-Nios
157651: 15/01/20: Re: Altera Cyclone II
=?windows-1252?Q?Ale=9A_Svetek?=:
151065: 11/03/03: Re: Problems with Xilinx SDK and LwIP
151136: 11/03/10: Re: Problems with Xilinx SDK and LwIP
=?windows-1252?Q?G=F6ran_Bilski?=:
79774: 05/02/24: Re: FSL : only reads 16 times
=?windows-1252?Q?GaLaKtIkUs=99?=:
136985: 08/12/17: LEON3 processor
140586: 09/05/19: JAM scripts and Altera's USB-Blaster cable
141649: 09/07/02: USB Book
141741: 09/07/06: USB protocol analyzer
146355: 10/03/13: Looking for a G.723.1 codec IP core for Xilinx FPGA
146398: 10/03/15: Re: Looking for a G.723.1 codec IP core for Xilinx FPGA
148803: 10/08/26: Spartan-6 - What is the IODRP2_MCB??
WindowsGeek:
149688: 10/11/17: Signal is connected to multiple drivers
Winefred Washington:
17234: 99/07/13: Re: Why can't output flops be pulled into the IOB's when a module is floorplanned?
Winfield Hill:
88809: 05/08/29: Re: CPLD Jitter
120944: 07/06/20: Re: Can anyone identify the manufacturer of this Chip ?
159855: 17/04/11: fan speed controller
159884: 17/04/14: Re: fan speed controller
Winfried Salomon:
81078: 05/03/17: Xilinx System Generator, Gateways not implemented
81144: 05/03/18: Re: Xilinx System Generator, Gateways not implemented
<Winfried.Gehrke@freenet.de>:
133425: 08/06/28: Re: Error while doing 'Generate Netlist' in xilinx 9.2i
Wing Fong Wong:
63365: 03/11/20: Altera Max 7000 cpld's
63408: 03/11/21: Re: Altera Max 7000 cpld's
64457: 04/01/05: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
65612: 04/02/03: Re: 4 bit divisor with flip-flop ?
67727: 04/03/18: Re: newbie question about fpga internals
72172: 04/08/10: Re: let me have logic design for traffic light
74562: 04/10/14: Re: Where to buy cheap MAXII CPLD?
78911: 05/02/10: Re: Plea for help with MAX7000S
79853: 05/02/25: Re: Ml310(xc2vp30) with ppc 405,multi processor share memory?
80132: 05/03/02: RocketIO minimum bitrate and other questions
80255: 05/03/03: Xilinx ML310 board's IO
80341: 05/03/04: Re: Xilinx ML310 board's IO
81138: 05/03/18: Re: About the usb access in board ML310!
81199: 05/03/19: Re: rocketio
81332: 05/03/22: Re: rocketio
85238: 05/06/07: Re: Sch & Layout Free Program
109450: 06/09/26: Re: LCD(STN) controller
Wing Wong:
81891: 05/04/04: ML310 z-dok connectors
winmaster Winmaster:
30501: 01/04/11: ABEL, syntax for High impedance output
30510: 01/04/11: Re: Re: ABEL, syntax for High impedance output
Winnie Hsu:
44244: 02/06/14: Re: Can someone who is not a student use Xilinx Foundation 2.1i Student
45032: 02/07/10: Re: [FUD msg] Virtex-II PRO Channel alignment not working?
45500: 02/07/24: Re: Wind River Diab Xilinx Edition
<winscatt@googlemail.com>:
128204: 08/01/17: SRL16x2 in Virtex5
128260: 08/01/19: Re: SRL16x2 in Virtex5
winston:
69549: 04/05/13: Updating a XILINX Project
Winston:
69548: 04/05/13: Re: EPCS4 Configuration+firmware, Quartus problem
Winston Smith:
78598: 05/02/04: Re: Exportability of EDA industry from North America?
Winzker:
17724: 99/08/27: Re: Virtex BRAM Initialization
20253: 00/02/02: Re: Virtex DLL inoperability
21371: 00/03/20: Re: Virtex DLL inoperability
21644: 00/03/27: Re: Virtex DLL inoperability
24065: 00/07/25: Re: Xilinx "MUX_OP not inferred" error.
Wipster:
147315: 10/04/22: Problem with data2mem
147354: 10/04/23: Re: Problem with data2mem
Wircom:
14260: 99/01/22: decoder Viterbi
Wireless ATM:
11496: 98/08/19: 4PPM in ABEL
11802: 98/09/10: 16 bit CRC
11837: 98/09/12: Re: 16 bit CRC
Wisut Hantanong:
27145: 00/11/13: Please guide newbies to real PLD ?
31710: 01/06/03: Looking for free (try) xc4000e software ?
<wittenjon@googlemail.com>:
123268: 07/08/22: Need to force all signals in a design to a known value at start of simulation
wixization:
143758: 09/10/23: Picoblaze assembler not running Help!!!
wiy:
40625: 02/03/11: a guide to digital design and synthesis
WJ van der Westhuizen:
6008: 97/04/04: PCI Bus Problems
<wjbonline@126.com>:
71667: 04/07/27: How to set Microblaze frequence?
wjc:
150750: 11/02/08: Re: Looking for off-the-shelf 3.3 <--> 5v level shifter
150753: 11/02/08: Re: Looking for off-the-shelf 3.3 <--> 5v level shifter
<wjk1@my-dejanews.com>:
16019: 99/04/28: Re: Any good book suggestions
<wjmoore2167@my-dejanews.com>:
14350: 99/01/27: Re: FPGA architecture
<wkwplj@my.com>:
wlenihan:
6347: 97/05/16: Re: X-BLOX
6509: 97/05/29: Re: What is M1?
<wlpstxzhd@gmail.com>:
130473: 08/03/25: Chipscope analyzer GUI problem in Linux
<wluka@hotmail.com>:
11712: 98/09/02: Design Re-use, IP cores, Megafunctions, etc...
12956: 98/11/07: Re: FPGA on ASIC (Was: Re: New free FPGA CPU)
12984: 98/11/09: Re: FPGA on ASIC (Was: Re: New free FPGA CPU)
<wmwmurray@gmail.com>:
129667: 08/03/02: FPGA/CPLD group on LinkedIn
129670: 08/03/02: Re: FPGA/CPLD group on LinkedIn
129763: 08/03/04: Re: FPGA/CPLD group on LinkedIn
woellik helmut:
16968: 99/06/21: XILINX PROG-PIN unconnected?
Wojciech M. =?UTF-8?Q?Zabo=C5=82otny?=:
157956: 15/05/30: Re: ESP8266 based Xilinx Virtual Cable server?
160485: 18/02/11: Scripts to maintain list of addresses in VHDL core communicating
Wojciech M. Zabolotny:
151900: 11/06/02: Connecting of IP core simulated in GHDL to pseudoterminal via
153504: 12/03/19: Record type <-> std_logic_vector conversion - Python script
153505: 12/03/19: Re: Record type <-> std_logic_vector conversion - Python script
153740: 12/05/03: L3 protocol for transmission from small FPGA to embedded Linux system
156121: 13/11/30: Use of hardware adders with long words to perform multiple
156142: 13/12/09: How to feed the simulated VHDL implemented synthesizer with MIDI
157951: 15/05/20: ESP8266 based Xilinx Virtual Cable server?
Wojciech Madejski:
27039: 00/11/08: WebPack problem
Wojciech Piechowski:
46964: 02/09/13: exploiting metastability
47047: 02/09/16: Re: exploiting metastability
47048: 02/09/16: Re: exploiting metastability
Wojciech Zabolotny:
32661: 01/07/04: How to read(verify) configuration from SRAM configured (ACEX) Altera
52276: 03/02/05: Java NullPointerException in Xilinx System Generator 2.2
52278: 03/02/05: Re: Java NullPointerException in Xilinx System Generator 2.2 & 2.3
52293: 03/02/06: Re: SOLVED! - Bug in Xilinx SysGen (Was: Java NullPointerException
67794: 04/03/19: Strange FPGA design - part working with divided clock frequency - time constraints problem
68162: 04/03/28: Actel tools (Designer and others) - command line driven compilation?
68186: 04/03/29: Actel tools (Designer and others) - command line driven compilation?
77258: 05/01/02: Re: Free IP-Core for FPGA Config from MMC-Cards
77260: 05/01/02: Adding SD support - more info
78356: 05/01/31: Actel A54SX72A - FF with clear and preset? Necessary for triple
78379: 05/01/31: Re: Actel A54SX72A - FF with clear and preset? Necessary for triple
78421: 05/01/31: Temat:Re: Actel A54SX72A - FF with clear and preset? Necessary for triple redundant register
78444: 05/02/01: Re: Temat:Re: Actel A54SX72A - FF with clear and preset? Necessary
78445: 05/02/01: Re: Actel A54SX72A - FF with clear and preset? Necessary for triple
104102: 06/06/19: Correction: Utility to generate pin assignments (UCF, QSF) from the
104263: 06/06/22: Remote access to Altera FPGA via jtagd in Linux
104266: 06/06/22: One significant correction: Remote access to Altera FPGA via jtagd
104325: 06/06/23: Xilinx cable drivers for Linux 2.6.16?
104328: 06/06/23: Solved: Xilinx cable drivers for Linux 2.6.16?
105411: 06/07/21: fpgadbg - a free & open source tool for FPGA debugging
105682: 06/07/28: New version of fpgadbg available - with serial port support
112970: 06/12/03: Buggy behaviour in Modelsim, when reading from pipe?
112978: 06/12/04: Re: Buggy behaviour in Modelsim, when reading from pipe?
116808: 07/03/19: Jam STAPL Player extensions
116940: 07/03/21: How to make use of two processors with Xilinx ISE (on Linux)
116956: 07/03/21: How to generate STAPL with "pulse PROG" in Impact?
116969: 07/03/21: SOLVED: How to generate STAPL with "pulse PROG" in Impact?
117167: 07/03/25: Tool to convert ISE project into makefile? (for Linux)
120468: 07/06/07: Symbolic names for pll derived clocks in SDC file? (quartus)
125593: 07/10/29: Free & open source USB STAPL Player
125802: 07/11/05: Linux capable free/GPL SOFT CPU for XC3S500E?
125817: 07/11/06: Re: Linux capable free/GPL SOFT CPU for XC3S500E?
125820: 07/11/06: Re: Linux capable free/GPL SOFT CPU for XC3S500E?
125870: 07/11/07: Re: Linux capable free/GPL SOFT CPU for XC3S500E?
127513: 07/12/31: State machine with stack to implement "subroutines"
127729: 08/01/06: Compilation of Plasma SW under Linux
131077: 08/04/09: Specifying strict setup constraint in ISE
132303: 08/05/21: timing constraint is impossible to meet
132347: 08/05/22: Extended burst with ADNP with CY7C1386C/CY7C1387C
133540: 08/07/03: Spartan3: INIT_B doesn't go LOW after PROG_B goes LOW in 2% of cases
<wojjed@gmail.com>:
126457: 07/11/23: xilinx spartan 3 + 16 adc
126461: 07/11/23: Re: xilinx spartan 3 + 16 adc
126877: 07/12/05: "simultaneously switching output"
133989: 08/07/21: audio serial port i2s
133993: 08/07/21: Re: audio serial port i2s
133997: 08/07/21: Re: audio serial port i2s
134000: 08/07/21: Re: audio serial port i2s
134028: 08/07/22: powering fpga with lm317
134073: 08/07/24: using j-link jtag from iar systems to program spratan 3 with
wojt:
115406: 07/02/09: Setting VHDL standard in Xilinx ISE
116273: 07/03/06: Block RAM in VirtexE FPGA - 'Read-after-Write' and 'No-Read-on-Write' modes
Wojtek:
80456: 05/03/06: DCT in FPGA
80496: 05/03/07: Re: DCT in FPGA
82191: 05/04/08: DCT
wojtek:
36277: 01/11/05: Re: Aldec question
134021: 08/07/22: Re: Help to SImulate Uart TX
134022: 08/07/22: Re: Help to SImulate Uart TX
134026: 08/07/22: Re: Help to SImulate Uart TX
134046: 08/07/22: Re: Help to SImulate Uart TX
134613: 08/08/21: Re: Image input
146690: 10/03/26: Re: USB 3.0 implementation on FPGA
146703: 10/03/26: Re: USB 3.0 implementation on FPGA
146708: 10/03/26: Re: USB 3.0 implementation on FPGA
147835: 10/05/26: Re: crc16 with 16 bit inputs
Wojtek =?UTF-8?Q?Zabo=C5=82otny?=:
152734: 11/10/14: Re: Synthesizable heap-sorter for FPGA - BSD licensed sources
Wojtek Zabolotny:
104101: 06/06/19: Utility to generate pin assignments (UCF, QSF) from the Protel netlist
Wojtek2U:
88639: 05/08/24: Does LOCKED signal of Spartan3 DCM require clock to be de-asserted?
98678: 06/03/14: Why Xilinx does not specify clock to output MINIMUM time???
wojtek2U:
98723: 06/03/15: Re: Why Xilinx does not specify clock to output MINIMUM time???
<wojtek2u@wp.pl>:
137155: 08/12/29: Is Implementation in ISE10.1.03 really better than in ISE9.2.03 ???
wojtek_himself:
112820: 06/11/29: modular design / PlanAhead
113160: 06/12/07: PlanAhead : problems
woko:
76112: 04/11/25: Programming flash connected to CPLD via JTAG
76151: 04/11/26: Re: Programming flash connected to CPLD via JTAG
134922: 08/09/07: LVDS Receiver in FPGA
135025: 08/09/11: Re: LVDS Receiver in FPGA
wolahr:
138726: 09/03/06: Re: Want to buy: FPGA T-Shirt $$
138992: 09/03/18: Re: uB and external CPU communications
Wolf:
96149: 06/01/30: power up reset question
<wolf359mmcb@gmail.com>:
88541: 05/08/22: chipscope pro 6.3i clocking issue
<wolfco2006@yahoo.com>:
110191: 06/10/12: Re: ISE 8.2 and partitions from command line
Wolfgang:
67861: 04/03/21: 64bit cpu on Xilinx
wolfgang:
62661: 03/11/04: DCM recover after interruption of input clock
68561: 04/04/08: Fatal error mappin 2v1000 in ISE 6.2
70901: 04/07/01: DCM ISE6.2.3 sim problem
Wolfgang Brandt:
50178: 02/12/04: Modelsim
Wolfgang Denk:
57102: 03/06/23: Re: Q: regarding I2C protocols
71772: 04/07/29: Re: RISCWatch w/ Linux running on ppc405D: Virtual/Physical mem issues
Wolfgang Ecker:
3154: 96/04/15: Re: VHDL conversion function from int to time ...?
11692: 98/09/01: Re: Wait statements and while loops
Wolfgang Freiberger:
19613: 00/01/04: Re: Schematics for ISP
19612: 00/01/04: Re: Schematics for ISP
Wolfgang Friedrich:
28396: 01/01/11: Re: grey code counters
Wolfgang Grafen:
126450: 07/11/22: Re: VHDL language is out of date! Why? I will explain.
126510: 07/11/26: Re: VHDL language is out of date! Why? I will explain.
126605: 07/11/28: Re: VHDL language is out of date! Why? I will explain.
126607: 07/11/28: Re: VHDL language is out of date! Why? I will explain.
Wolfgang Kufer:
27296: 00/11/17: Using FPGA as PCI target
Wolfgang Loewer:
25985: 00/09/29: Re: FPGA development on the cheap?
27541: 00/11/28: Re: hard or soft core for FPGA?
27628: 00/11/30: Re: hard or soft core for FPGA?
27770: 00/12/07: Re: FPGA starter kit
27935: 00/12/15: Re: Multicycle timing requirements in Altera Quartus
28256: 01/01/04: Re: FPGA starter kit recommendations
28257: 01/01/04: Re: NIOS Processor soft core
28995: 01/02/01: Re: 64-bit counter @ 200 MHz on FPGA?
29457: 01/02/22: Re: clock divider by 1.5
29494: 01/02/23: Re: programmable coefficient fir filter?
29881: 01/03/15: Re: NIOS 16-Bit
30521: 01/04/12: Re: Problems Software Build ALTERA Quartus II
30522: 01/04/12: Re: free software
31085: 01/05/11: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
31912: 01/06/08: Re: FPGA / starterkit / VHDL
32218: 01/06/20: Re: Altera EPC16 Question
33135: 01/07/18: Re: How do i see buried nodes in maxplus2?
33147: 01/07/18: Re: Spartan2XC2S30 vs ACEXEP1K30
33199: 01/07/19: Re: possibly stupid lpm_fifo question...
33201: 01/07/19: Re: Altera's MAX devices configuration
33221: 01/07/19: Re: How to see ram contents in maxplus2 simulation?
34330: 01/08/21: Re: FPGA MP3 decoder
34758: 01/09/06: Re: strange behaviour of LPM_FIFO_DC in altera 10k130e
34772: 01/09/07: Re: Selection of a suitable FPGA board
35307: 01/09/28: Re: Programming flash connected to CPLD via JTAG
35718: 01/10/15: Re: Problem about Leonardo Spectrum with Altera MaxPlus II
36606: 01/11/13: Re: Jpeg 2000
36795: 01/11/20: Re: how to imply CAM in APEX20K
36893: 01/11/23: Re: Altera Quartus fork bus on block diagram
36922: 01/11/26: Re: ALTERA's Mercury CDR
37256: 01/12/05: Re: altera max++ baseline and jedec file
37612: 01/12/17: Re: division 64
37637: 01/12/18: Re: SPI interface in VHDL
38513: 02/01/16: Re: info about NIOS softcore processor
39942: 02/02/22: Re: Altera library problems.
40573: 02/03/11: Re: Audio project with an FPGA?
40785: 02/03/15: Re: Proto boards for labs
41292: 02/03/25: Re: synplify, quartus II 2.0
42071: 02/04/15: Re: FPGA eval/dev boards with *serial* interface?
44491: 02/06/21: Re: Multiple Nios CPU's on Altera PLD?
44697: 02/06/27: Re: clock skew in quartus, not in maxplus
45193: 02/07/15: Re: SOPC builder
45300: 02/07/18: Re: NIOS programming related to ISR
45385: 02/07/22: Re: Making my own software
45688: 02/08/01: Re: Pipelined Multiplier Implemented in Slices in Virtex II
48411: 02/10/17: Re: AHDL Command Reference?
48637: 02/10/22: Re: mif /hex files for lpm models
49214: 02/11/05: Re: read and write same address of the ESB memory in the same cycle
49558: 02/11/15: Re: configuration with Altera EPC16?
63894: 03/12/08: Re: How to assign inferred logic to resource in Quartus
79708: 05/02/23: Re: SD Card and FPGA
Wolfgang Pieper:
41120: 02/03/21: RAM initialization
44286: 02/06/16: core generator / where is it?
44350: 02/06/18: ram initialization
Wolfgang Schmiesing:
55476: 03/05/09: help on FPGA-programming tutorial for students
56338: 03/06/03: size of SRAM, antifuses and EPROM elements
wolflame:
110404: 06/10/15: how to change cclk frequency ?
Wolfram Seibold:
5844: 97/03/20: PCI & Altera
Wolfram Sieber:
37066: 01/11/29: Spartan2 problems with 5V periphery
37107: 01/11/30: Re: Spartan2 problems with 5V periphery
Wolfram Stumpf:
59470: 03/08/19: IO tco timing differs between Altera Quartus II versions
<wondering.gnome@gmail.com>:
139486: 09/03/31: Digital design references for timing, etc.
139500: 09/04/01: Re: Digital design references for timing, etc.
Wong:
55569: 03/05/12: VitalGlitch
55608: 03/05/13: Re: VitalGlitch
55652: 03/05/14: Re: VitalGlitch
55654: 03/05/14: Re: VitalGlitch
55698: 03/05/15: Re: VitalGlitch
55907: 03/05/23: FPGA interfacing problems
56135: 03/05/29: Antifuse and SRAM FPGA
56180: 03/05/29: Re: Antifuse and SRAM FPGA
59459: 03/08/19: Synchronous FSM
67495: 04/03/12: FPGA for MPEG2
71636: 04/07/26: Re: Modelsim: No default binding for component
75078: 04/10/25: Best Place and Route
74414: 04/10/11: Actel Fusefile Reverse Engineering
74469: 04/10/12: Re: Actel Fusefile Reverse Engineering
Wong Man Kit:
4357: 96/10/19: Anyone use Lattice's CPLD
4618: 96/11/21: Re: Lattice ISP Question
4835: 96/12/19: Re: PLD
6729: 97/06/20: Re: HELP: FOR 6000 SERIES
wong ying:
14863: 99/02/21: Free Tool For FPGA ??
<wonhwa0815@gmail.com>:
155896: 13/10/13: Re: Xilinx tools for XC3020???
wonttellyahere:
82418: 05/04/12: Re: Ethnet samples using EDK??
Woody Johnson:
5275: 97/02/03: Re: Altera BitBlaster
5549: 97/02/24: Re: replicating structure in MaxPlus
5682: 97/03/06: Re: Altera LPM_MUX Function
6072: 97/04/09: Re: About the usage of maxplus2
<woodyj@pptvision.com>:
16360: 99/05/18: Re: Fancy Dram problem
<wooster.berty@gmail.com>:
139837: 09/04/15: Re: Xilinx ISE bug, or?
Workshop - Gabe Robins:
4176: 96/09/21: ISPD-97 Call for Papers
wosiqiu:
50577: 02/12/12: Can I use bus keeper like this?
50578: 02/12/12: Can I use bus keeper like this?
50614: 02/12/13: Re: Can I use bus keeper like this?
53904: 03/03/26: help! How can I make the messages posted in this group be sent to my E-mail box.
60589: 03/09/16: How to use systemc together with VHDL or Verilog?
62377: 03/10/28: How can I lock design with ISE 5.2?
WOSTER145:
27139: 00/11/12: HOW TO TURN $6 INTO $6,000!!!!!!
Wout Klaren:
1541: 95/07/11: EP330 driver for APLUS
Wouter Coene:
97402: 06/02/22: Re: Xilinx ISE 6.3 confusion with CPLD logic results
Wouter Suverkropp:
4196: 96/09/25: Xilinx X-blox Bidir_IO padnames?
Wouter van Ooijen www.voti.nl:
64390: 04/01/01: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
64393: 04/01/01: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
64408: 04/01/02: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
Wouters Etienne:
1166: 95/05/10: Re: Compression algo's for FPGA's
Woutervh:
115061: 07/01/30: XUP Virtex-II Pro
woutervh:
117671: 07/04/06: XUP virtex-II pro
117830: 07/04/11: Wanted: XUP Virtex II Pro DDR-controller
WowGao Inc:
wpauwels:
12977: 98/11/09: design multipier?
13630: 98/12/15: Neural nets
wpiman@aol.com:
77915: 05/01/20: Xilinx constraint question- DC input
78108: 05/01/24: Re: Xilinx Tshirts in football package.....
81602: 05/03/28: Xilinx- Extract a pin layout
81650: 05/03/29: Re: Xilinx- Extract a pin layout
101904: 06/05/08: Programming the JTAG flash in circuit
<wpiman@aol.com>:
77478: 05/01/07: ise mapping options limited
<wq998@my-deja.com>:
18733: 99/11/10: Re: orcad synthesis for simplepld
24380: 00/08/06: Re: Help! Troubles using async FIFO cores in Virtex
24543: 00/08/12: Re: state encoding in Synplify!!!
25664: 00/09/16: Re: FPGA Express Strikes Again!
<wq998@yahoo.com>:
18198: 99/10/07: Virtex and PCI 5V?
25647: 00/09/16: Re: FPGA Express Strikes Again!
wqg:
17504: 99/08/03: help about PCI bridge
<wqjchn@sdjxtrwhsh.gov>:
23793: 00/07/09: Nuke the Competition!
wreg:
40962: 02/03/19: constrain
40963: 02/03/19: state machine coding style
Wren:
124078: 07/09/12: ML410 Board & 1GB DDR2 DIMM Problem
124085: 07/09/11: Re: ML410 Board & 1GB DDR2 DIMM Problem
wrightjt:
46278: 02/08/23: Re: cdma code acquisition problem
46280: 02/08/23: Re: cdma code acquisition problem
wrth:
36395: 01/11/08: about ise4.1 solaris install
wsacul@gmail.com:
118029: 07/04/16: Re: Writing to BRAM using OPB
WTec:
91521: 05/11/08: 8x8-bit multiply
<wteturttyjr@kjptppwthy.com>:
6886: 97/07/06: Your ONENUMBER for everything!!!
WTorger:
9024: 98/02/14: Re: Devices and Prices
9741: 98/04/02: Re: Lowest POWER FPGAs???
9737: 98/04/02: Re: One time programmables
12528: 98/10/15: Re: 100 MHz FPGA
<wtxwtx@gmail.com>:
92829: 05/12/07: Mean value filter
93094: 05/12/13: Re: Mean value filter
93143: 05/12/14: Re: Mean value filter
93192: 05/12/15: Re: Mean value filter
93271: 05/12/17: Re: Mean value filter
93302: 05/12/19: Re: Mean value filter
93303: 05/12/19: Re: Mean value filter
93355: 05/12/20: Re: Mean value filter
93387: 05/12/21: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
93388: 05/12/21: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
93389: 05/12/21: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
93452: 05/12/22: Re: Mean value filter
93518: 05/12/23: Re: FPGA DDR controller - CKE signal... do I need a pull down?
93519: 05/12/23: Re: Interfacing externally clocked data to an FPGA (Spartan 3)
93599: 05/12/26: Re: XILINX I2C controller core in FPGA and multisource problem.
93602: 05/12/26: Re: XILINX I2C controller core in FPGA and multisource problem.
93609: 05/12/26: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
93616: 05/12/26: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
93618: 05/12/26: Re: XILINX I2C controller core in FPGA and multisource problem.
93620: 05/12/26: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
93622: 05/12/26: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
93634: 05/12/27: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
93679: 05/12/28: Re: DDR2 support for EDK
93681: 05/12/28: What is the difference betwee 'Method' and 'Apparatus' in a patent claim area
93735: 05/12/29: Re: What is the difference betwee 'Method' and 'Apparatus' in a patent claim area
93771: 05/12/30: Re: What is the difference betwee 'Method' and 'Apparatus' in a patent claim area
93772: 05/12/30: Re: XILINX I2C controller core in FPGA and multisource problem.
93775: 05/12/30: Re: XILINX I2C controller core in FPGA and multisource problem.
93797: 05/12/30: Re: What is the difference betwee 'Method' and 'Apparatus' in a patent claim area
93818: 05/12/31: Why 'a plurality of N' must be used for 'N' in patent claims
93837: 06/01/01: Re: What is the difference betwee 'Method' and 'Apparatus' in a patent claim area
93870: 06/01/02: Re: CPU86 (Intel 8086) VHDL now available (thanks to HT-LAB !)
93898: 06/01/03: Re: CPU86 (Intel 8086) VHDL now available (thanks to HT-LAB !)
93891: 06/01/03: Re: Why 'a plurality of N' must be used for 'N' in patent claims
94690: 06/01/16: How to drive 4 output ports with one combinational signal
94696: 06/01/16: Re: How to drive 4 output ports with one combinational signal
94698: 06/01/16: Re: How to drive 4 output ports with one combinational signal
94714: 06/01/16: Re: How to drive 4 output ports with one combinational signal
94756: 06/01/17: How to set Xilinx compiling parameters to get PCI setup time right
94772: 06/01/17: Re: How to set Xilinx compiling parameters to get PCI setup time right
96070: 06/01/29: Re: tristate to logic conversion
96099: 06/01/30: Re: tristate to logic conversion
96101: 06/01/30: Re: tristate to logic conversion
96685: 06/02/08: Re: Async Processors
WU Chi Hang FOX:
23384: 00/06/23: Xilinx xc4000
23403: 00/06/24: Re: Xilinx xc4000
23404: 00/06/24: Different ?
23416: 00/06/24: Re: Different ?
23426: 00/06/24: Re: Different ?
Wu Peng:
141335: 09/06/19: Re: Open source processors
<wudong99_1998@my-deja.com>:
17758: 99/09/01: What's meaning of "Partial Evaluation"
wuqiang:
43697: 02/05/29: about Configure FLEX10K10 with 89c51
43729: 02/05/31: Re: about Configure FLEX10K10 with 89c51
43730: 02/05/31: Re: about Configure FLEX10K10 with 89c51
wuyi316904@gmail.com:
94467: 06/01/12: Conflicts between ISE4.2 and win2000 SP4
94516: 06/01/12: Re: Conflicts between ISE4.2 and win2000 SP4
94552: 06/01/13: Re: Conflicts between ISE4.2 and win2000 SP4
94468: 06/01/12: How to create a delay BUF?
94515: 06/01/12: Re: How to create a delay BUF?
94549: 06/01/13: Re: How to create a delay BUF?
104630: 06/07/03: how to use the xilinx 18v04 config fpga?
104643: 06/07/03: design in vsprom
105336: 06/07/20: system design
<wv9557@yahoo.com>:
86397: 05/06/27: Re: Chess & FPGAs
88616: 05/08/23: Re: Stdin / stdout through RS232
92975: 05/12/10: Re: FPGA : MAP slice logic into BLOCK RAM
96518: 06/02/05: Re: VGA and framebuffer interface (Waste of BlockRAM)
103241: 06/05/29: Re: ISE sends sensitive information to Xilinx site!
wwas:
7134: 97/08/04: Re: VHDL Training at Qualis - posting every week?
<wwkouisi@entireweb.com>:
wwqiao:
74328: 04/10/08: Re: Interfacing an 1GS ADC
83201: 05/04/25: questions on Xilinx Virtex-4 to DDR SDRAM module
www.amontec.com:
70656: 04/06/23: ANN: Low cost & high speed JTAG interface
70873: 04/06/30: Re: a question in the pci interface design
70897: 04/07/01: Re: Compact FPGA Board?
71851: 04/08/02: Re: SPARTANII pinout table mysteries ???
71867: 04/08/03: Re: SPARTANII pinout table mysteries ???
72719: 04/08/30: Re: PCI-Core
72782: 04/09/01: Re: virtex II on pci bus devboard
www.cheapforwholesale.com:
133799: 08/07/15: discount, coach juicy miumiu jimmy choo chloe prada chanel lv
www.cvpages.com:
www.fpga4fun.com:
78105: 05/01/25: Re: epcs prices
<www@synernet.com>:
1159: 95/05/08: CA-BC-Vancouver ***Engineering Jobs Posted***
<wxy0624@gmail.com>:
126429: 07/11/22: DCM with instable clock
126474: 07/11/23: Re: DCM with instable clock
126476: 07/11/23: Re: DCM with instable clock
126480: 07/11/24: Re: DCM with instable clock
126588: 07/11/28: Re: DCM with instable clock
126590: 07/11/28: SLICEL : 92%,SLICEM 2%
127278: 07/12/16: sampling error between 2 clocks
127310: 07/12/17: Re: sampling error between 2 clocks
127344: 07/12/18: Re: sampling error between 2 clocks
127410: 07/12/21: Re: sampling error between 2 clocks
WyndyPickle:
133038: 08/06/14: FPGA IO Pin Unwanted Coupling
WZab:
140598: 09/05/19: BSCAN_SPARTAN3 proper use with CAPTURE and UPDATE
wzab:
116613: 07/03/13: qemu+ghdl or uml+ghdl hardware-software cosimulation?
116816: 07/03/19: Re: Jam STAPL Player extensions
116826: 07/03/19: Re: Jam STAPL Player extensions
120509: 07/06/08: SOLVED!!! Symbolic names for pll derived clocks in SDC file? (quartus)
120511: 07/06/08: TimeQuest - clocks related by default?
127567: 08/01/02: OpenCores tracker and forum doesn't work?
132306: 08/05/21: Re: timing constraint is impossible to meet
133575: 08/07/04: Re: Spartan3: INIT_B doesn't go LOW after PROG_B goes LOW in 2% of
136951: 08/12/15: Synthesizable & open 4DDR Infiniband core
136966: 08/12/16: Re: Synthesizable & open 4DDR Infiniband core
140539: 09/05/16: Access to BSCAN_SPARTANx or BSCAN_VIRTEXx from Python without
140541: 09/05/16: Re: Access to BSCAN_SPARTANx or BSCAN_VIRTEXx from Python without
140559: 09/05/17: Re: Access to BSCAN_SPARTANx or BSCAN_VIRTEXx from Python without
140560: 09/05/17: Re: Access to BSCAN_SPARTANx or BSCAN_VIRTEXx from Python without
140739: 09/05/23: Re: BSCAN_SPARTAN3 proper use with CAPTURE and UPDATE
143573: 09/10/16: Controller to access internal FPGA registers from JTAG
143691: 09/10/21: Xilinx USB programmer - problems with Debian/Linux - Solved
144702: 09/12/25: VHDL: assignment to two different fields of the record in two
144703: 09/12/25: More details: VHDL: assignment to two different fields of the
149253: 10/10/12: Selective blocking of "-iobuf" directive in ISE
149328: 10/10/17: Project including MIG core problems with Chipscope
149335: 10/10/17: Re: Project including MIG core problems with Chipscope
151733: 11/05/13: J1 forth processor in FPGA - possibility of interactive work?
151746: 11/05/14: Re: J1 forth processor in FPGA - possibility of interactive work?
151781: 11/05/18: Re: J1 forth processor in FPGA - possibility of interactive work?
151824: 11/05/21: Re: J1 forth processor in FPGA - possibility of interactive work?
151901: 11/06/02: Re: J1 forth processor in FPGA - possibility of interactive work?
151902: 11/06/02: Re: Connecting of IP core simulated in GHDL to pseudoterminal via
152125: 11/07/11: Synthesizable heap-sorter for FPGA - BSD licensed sources
152126: 11/07/11: Synthesizable heap-sorter for FPGA - BSD licensed sources
152127: 11/07/11: Re: Synthesizable heap-sorter for FPGA - BSD licensed sources
152182: 11/07/15: Re: Any free timing diagram tools?
152188: 11/07/17: Re: Synthesizable heap-sorter for FPGA - BSD licensed sources
152408: 11/08/19: Re: Synthesizable heap-sorter for FPGA - BSD licensed sources
152453: 11/08/24: Running Chipscope >=12.x on Linux.
152795: 11/10/23: Re: wireless module for DSP stratix III
153220: 12/01/11: opendous-jtag support for independent USB drivers for JTAG/Impact/Chipscope?
153281: 12/01/25: Open source cable server for Xilinx - for remote running of tools
153283: 12/01/26: Re: Open source cable server for Xilinx - for remote running of tools
153285: 12/01/26: Re: FPGA not working after programming from EEPROM
153304: 12/01/29: Re: Open source cable server for Xilinx - for remote running of tools
153389: 12/02/15: JAM Stapl player on 64 bit platform?
153390: 12/02/15: Re: JAM Stapl player on 64 bit platform?
153491: 12/03/11: Re: JAM Stapl player on 64 bit platform?
153501: 12/03/16: Re: Free GUI top level integration tool for Verilog and VHDL
153508: 12/03/20: Re: Record type <-> std_logic_vector conversion - Python script
153510: 12/03/20: Re: Record type <-> std_logic_vector conversion - Python script
153514: 12/03/20: Re: Record type <-> std_logic_vector conversion - Python script
155103: 13/04/16: FPGA board with 4 channel 500Msps ADC?
<wzab01@gmail.com>:
154004: 12/07/10: Possibility to use MGTREFCLK1P/MGTREFCLK1N as clock for user logic in
154799: 13/01/11: Quartus 12.1 Web Edition in 64-bit Linux - in System Sources and
154802: 13/01/13: Re: Quartus 12.1 Web Edition in 64-bit Linux - in System Sources and
156124: 13/12/01: Re: Use of hardware adders with long words to perform multiple
156286: 14/02/05: Parametrized, synthesizable FFT engine
156404: 14/03/29: Sending and receiving of 10GBASE-R Ethernet frames via GTX
156421: 14/04/03: Re: Sending and receiving of 10GBASE-R Ethernet frames via GTX
156676: 14/06/02: Linux driver for Xilinx axi_10g_ethernet_0_ten_gig_eth_mac core?
156683: 14/06/03: Re: Linux driver for Xilinx axi_10g_ethernet_0_ten_gig_eth_mac core?
157586: 14/12/22: How to automatically allocate multiple bit fields into constant
157590: 14/12/22: Re: How to automatically allocate multiple bit fields into constant
157591: 14/12/22: Re: How to automatically allocate multiple bit fields into constant
157596: 14/12/22: Re: How to automatically allocate multiple bit fields into constant
157783: 15/03/24: Re: Parametrized, synthesizable FFT engine
158007: 15/06/25: Speed of GTX transceivers in Kintex 7 in FBG package?
158013: 15/07/03: Installation of Vivado on Debian Linux on x86_64 machine
158246: 15/09/28: Automatic latency balancing in VHDL-implemented complex pipelined systems
158248: 15/09/29: Re: Automatic latency balancing in VHDL-implemented complex pipelined systems
158250: 15/09/29: Re: Automatic latency balancing in VHDL-implemented complex pipelined systems
158255: 15/09/29: Re: Automatic latency balancing in VHDL-implemented complex pipelined systems
158264: 15/09/30: Re: Automatic latency balancing in VHDL-implemented complex pipelined systems
158272: 15/10/01: Re: DDR* SDRAM modules for simulation
158646: 16/02/25: Sending multiple MSI interrupts via Xilinx "AXI Memory Mapped to
158647: 16/02/25: Re: Source control and ip cores
158648: 16/02/25: Re: Source control and ip cores
158649: 16/02/25: Re: Source control and ip cores
158653: 16/02/26: Re: Sending multiple MSI interrupts via Xilinx "AXI Memory Mapped to
158655: 16/02/28: Re: Sending multiple MSI interrupts via Xilinx "AXI Memory Mapped to
158696: 16/03/20: Re: Source control and ip cores
158829: 16/04/24: Simplistic AXI4-Lite to IPbus bridge
158845: 16/05/04: Re: Source control and ip cores
158846: 16/05/04: Re: Source control and ip cores
158848: 16/05/07: Re: Matlab-to-Gates for Xilinx
158853: 16/05/11: Re: Matlab-to-Gates for Xilinx
158856: 16/05/11: Problem with AXI4 Lite in Cyclone V
158870: 16/05/13: Re: Problem with AXI4 Lite in Cyclone V
158871: 16/05/13: Problem if compilation order in OOC compilations in Xilinx Vivado
158875: 16/05/13: Re: Problem if compilation order in OOC compilations in Xilinx Vivado
158878: 16/05/13: Re: Problem with AXI4 Lite in Cyclone V
158879: 16/05/13: Re: Problem with AXI4 Lite in Cyclone V
158907: 16/05/16: Re: Problem if compilation order in OOC compilations in Xilinx Vivado
160486: 18/02/11: Re: Scripts to maintain list of addresses in VHDL core communicating
160487: 18/02/12: Re: HDL simple survey - what do you actually use
160614: 18/05/27: Communication between HDL simulation and user software via ZMQ
160763: 18/11/20: Simple system to manage register access in hierarchical
161375: 19/06/13: Microchip UNI/O controller core for FPGA
<wzab@ise.pw.edu.pl>:
140858: 09/05/27: Python code accessing the Altera Virtual JTAG instances (via urJTAG)
<wzjohn@my-deja.com>:
25452: 00/09/12: computing difference between Gray values?
W{ljas Pekka Ilmari:
1683: 95/08/15: ZIF sockets for ORCA 429 PGA ?
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