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I need a tool. I hope that can transfer Altera(ahdl) to Vhdl or verilog.Article: 11751
Raymond Chiu <chiu@gate.net> wrote: >The group assessment is correct: I am interested in having a PLD burned, which >means I need to make a decision a burner. I am having difficulty finding a >burner within my budget ($2000 is a little too rich). >Any suggestions are welcome and appreciated. >Thank you, >Raymond I've got several programmers, but the one I always seem to grab is the Needhams Electronics EMP-20. I think it's about $450 US. Their web page is at <www.needhams.com>. Works over a PC parallel port, supports almost every DIP device you can think of, and free programming algorithms over the net. Wade Peterson Silicore Corporation www.silicore.netArticle: 11752
b_rich2@my-dejanews.com writes:
> I actually looked at the LPM_RAM_DQ but I need 2 read data ports and the
> LPM_RAM only provided one. Also it's a bugger that it doesn't address the
> read and write ports seperately. You can't read a seperate port at the same
> time you are writing data. It would be perfect if it had 1 16 bit data input
> bus, 4 bit write address bus, 2 X 16 bit data read busses. That's what my
> design has at the moment but I would like a way that doesn't use as much real
> estate on the chip. My design is 5 stage pipelined, so I really need single
> clock cycle register file too. Still thinking of alternatives. Thanks for
> any help and also for the replies I've received so far, very much
> appreciated.
Is there a requirement that the pipeline clock and the register file
clock be the same? I'd think that the RAM in the 10K is at about
200MHz (maybe a bit slower, I don't have the data sheet handy) which
your processor is probably not going to make even with 5 pipeline
stages. So having a 4:1 sub-clock on the register file gives you four
ports (perhaps only three because of write turnaround), while your
processor can still go at 50MHz, which isn't too bad. Another idea to
skim off clock cycles is to replicate the register file and write to
all the EAB in parallel (single write port only) and then the next
clock you have as many independent read ports as you can spare EAB for
(two in your case, which sounds like it should be possible).
Achim Gratz.
--+<[ It's the small pleasures that make life so miserable. ]>+--
WWW: http://www.inf.tu-dresden.de/~ag7/{english/}
E-Mail: gratz@ite.inf.tu-dresden.de
Phone: +49 351 463 - 8325
Article: 11753b_rich2@my-dejanews.com wrote: > I actually looked at the LPM_RAM_DQ but I need 2 read data ports and the > LPM_RAM only provided one. Also it's a bugger that it doesn't address the > read and write ports seperately. You can't read a seperate port at the same > time you are writing data. It would be perfect if it had 1 16 bit data input > bus, 4 bit write address bus, 2 X 16 bit data read busses. That's what my > design has at the moment but I would like a way that doesn't use as much real > estate on the chip. My design is 5 stage pipelined, so I really need single > clock cycle register file too. Still thinking of alternatives. Thanks for > any help and also for the replies I've received so far, very much > appreciated. Cheers, Bruce You might want to consider using a Xilinx part. All of the XC4000 devices have dual port memory with two addresses, one write data bus and two read data busses. I think this is exactly what you are asking for. Your 16 bit wide reg file would be 8 CLBs. One address is used for simultaneous Read and Write and the other register is used for a simultaneous and separate Read. Of course this would require that you learn a whole new development system and a new architecture. But life is full of challenges, right? -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 11754
JDR Micro Devices - has a few burners. Reasonable prices good service. Simon ============================================ Raymond Chiu <chiu@gate.net> wrote: >The group assessment is correct: I am interested in having a PLD burned, which >means I need to make a decision a burner. I am having difficulty finding a >burner within my budget ($2000 is a little too rich). > >Any suggestions are welcome and appreciated. > >Thank you, >Raymond > >Peter wrote: > >> >It also seems that Raymond may be interested in actually getting his PLDs >> >physically programmed. I don't have a specific suggestion there, although I >> >have seen plenty of used legacy "universal programmers" for well under $100. >> >While no longer "universal," anything less than 10 years old will probably >> >have no problem programming a 22V10. >> >> Need to be careful here, since almost every vendor's 22V10 has a >> different programming algorithm. >> >> You need to make sure the programmer supports the *specific* >> vendor/device you want to use. And get it in writing, in case the >> algorithm is duff. >> >> -- >> Peter. >> >> Return address is invalid to help stop junk mail. >> E-mail replies to zX80@digiYserve.com but >> remove the X and the Y. > > > Opinions expressed herein are solely my own and may or may not reflect my opinion at this particular time or any other.Article: 11755
Raymond Chiu <chiu@gate.net> wrote: > The group assessment is correct: I am interested in having a PLD > burned, which means I need to make a decision a burner. I am > having difficulty finding a burner within my budget ($2000 is a > little too rich). I would like to suggest some of the in-circuit programable PLD's. While these would be somewhat more costly per part, and would be both a different pinout and (probably) surface mount. If you are designing a new board these issues would probably not be a problem, however if you are modifying an existing design you need the same pinout and package. If you are interesting, here are a few web pages: http://vantis.com http://altera.com http://xilinx.com -- Phil Hays "Irritatingly, science claims to set limits on what we can do, even in principle." Carl SaganArticle: 11756
One idea might be to use two copies of RAM for two ports and when you write, write the same data to both locations. I think this should be doable if you use the sync version of the embedded ram. Do a memory generate on sync input, async output. Then you can read one port on one address and write to both ports on a different address. b_rich2@my-dejanews.com wrote: >In article <35f3780f.0@news3.uswest.net>, > <Ernest Chiu> wrote: >> the 10K family has embedded memory use LPM_RAM > >I actually looked at the LPM_RAM_DQ but I need 2 read data ports and the >LPM_RAM only provided one. Also it's a bugger that it doesn't address the >read and write ports seperately. You can't read a seperate port at the same >time you are writing data. It would be perfect if it had 1 16 bit data input >bus, 4 bit write address bus, 2 X 16 bit data read busses. That's what my >design has at the moment but I would like a way that doesn't use as much real >estate on the chip. My design is 5 stage pipelined, so I really need single >clock cycle register file too. Still thinking of alternatives. Thanks for >any help and also for the replies I've received so far, very much >appreciated. Cheers, Bruce > >> >> b_rich2@my-dejanews.com wrote in message >> <6svbud$7cf$1@nnrp1.dejanews.com>... >> >Hi, I am a student and am currently designing a register file in Altera >> 7.21 >> >to be used in a project I am undertaking (non-commercial). I have a >> question >> >about whether there is a better way of implementing than what I am >> currently >> >doing. I have 16 X 16bit registers which I have constructed out of 16 X >> >LPM_FF (D type, 16 bits wide). So this takes up 256 LC's which is okay. But >> >here's the problem. I need 2 Output data buses from the register file. I am >> >currently using 2 X LPM_MUX (16 lines X 16 bit) to select which registers >> to >> >put on the bus. I have tested and simulated this design and it works okay. >> >The problem is that the 2 MUX's take up 416 LC's!! My whole register file >> >takes up 688 LC's, which is 59% of the space on my device!! This doesn't >> >leave me with much room for the rest of my project. I haven't completed my >> >project yet, but it appears I will be really struggling for space, and I am >> >required to use the 10K20. Surely there would have to be a better way of >> >designing a register file than what I have done, but I just can't seem to >> >think of a better way. I've been working on this problem now for several >> >weeks and am not making any progress. If there is anyone out there who >> would >> >be able to give me some advice I would be eternally grateful. Thanks in >> >advance. Bruce. >> > >> >-----== Posted via Deja News, The Leader in Internet Discussion ==----- >> >http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member Forum >> >> > >-----== Posted via Deja News, The Leader in Internet Discussion ==----- >http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member Forum muzo WDM & NT Kernel Driver Development Consulting <muzok@pacbell.net>Article: 11757
I've used the Cypress PALCE22V10 devices with the Cypress Warp2 software and a Dataman48 programmer and had some quite good results. The simulator with Warp2 is a little basic but it works well enough for small designs. Chris -- Chris Eilbeck mailto:chris@yordas.demon.co.ukArticle: 11758
I'm looking for a basic VHDL PCI core. One can web surf for days on end and never get enough info. Who has the most reasonable prices for a PCI core? I would like to avoid calling every vendor to get prices, etc. I would really appreciate suggestions. TIA EricArticle: 11759
Hello The problem has already been mentionned 1 or 2 months ago. I can't manage to program an Altera PROM EPC1 with the DataIO ChipWriter Someone at DAtaIO told me this problem appeared with designs compiled with Max+ v8.2 and that I should use an *older* version (I'm a bit puzzled here. I hope he meant newer) However, I use Max+ v8.3 Any idea? Nicolas MATRINGE DotCom SA Conception électronique 16 rue du Moulin des Bruyères Tel: 00 33 1 46 67 51 00 92400 COURBEVOIE Fax: 00 33 1 46 67 51 01 Mail reply : remove one dot from the address (guess which :-)Article: 11760
Hi, I am new to real FPGA world. I am looking a cheap FPGA kits that enable me to program my own chip. I understand that each FPGA/CPLD is not that expensive. However, I have no idea about the programmer (burner ?) pricing. Could someone please give me an idea on how much a FPGA Programmer cost. Thank you. -- Yung-Chiang YANGArticle: 11761
Hi, Lattice do some ISP 22V10 parts in PLCC which use the 4 normally unused pins one in the center of each edge. This coupled with a 28 pin PLCC clip on connecter used for debugging should allow an ISP system with standard PLCC parts and no PCB changes just my 2 pence worth. Andy All opinion are my own ....Article: 11762
Hi, We're considering purchasing a code coverage tool. Does anybody have any experiences in this field? Any particular tool you would recommend? We're mainly interested in tools for VHDL. Thanks, Hans-Erik Floryd -- Hans-Erik Floryd Telephone: +46 31 747 00 00 Ericsson Microwave Systems AB Direct: +46 31 747 65 86 Airborne Radar Division Telefax: +46 31 27 10 19 Hans-Erik.Floryd@emw.ericsson.seArticle: 11763
Phil mentioned >If you are interesting, here are a few web pages: > >http://vantis.com > >http://altera.com > >http://xilinx.com > >- I would also recommend Lattice at www.latticesemi.com - ISPGAL22V10 or 1k, 21k, 3k CPLD families In addition to being the inventor of ISP PLDS, they have free s/w on the web which supports GALs and CPLDs, - all you would need for programming is a download cable, from a local Lattice distributor - or build your own, schematic is in the data book. Mike Thomas LSC FAE - NYArticle: 11764
ems@nospam.riverside-machines.com wrote: (in reply to my post about DPLLs for recovering data clocks from synchronous serial data streams) > The point of a PLL is that it should be able to lock over a frequency > range - it shouldn't matter if the transmit clock is at a different > frequency, as long as it's within the lock range of the downstream > station. Are you saying that, in a chain of three SCCs, the third one > couldn't retrieve a data stream generated by the first one (which > would of course make the SCC useless?) No (although of course if there is degradation at each step, there must be some limit to the number of steps before the signal is irrecoverable - to allow an indefinite chain, you have to do something to IMPROVE the signal from time to time). Sorry, my point was slightly different: the particular protocol I was using, SDLC Loop mode, requires *exact* one-to-one matching of transmitted to received bits at each node, over arbitrarily long time periods. So there must be no long-term frequency difference between the two clocks. Short-term you can soak up with suitable FIFOs of course. BTW, I note that the latest version of Zilog's databook on the SCC (Z85230 ESCC) explicitly acknowledges this problem and indicates how to solve it - tho' I haven't yet checked whether their solution is correct, and I couldn't tie it up with the other parts of the databook! > You used fibre optic at *One Megabit* and got distortion of *500 ns* > ??? There seems to be some confusion here - can you tell us (a) which > HP device and connector, (b) what cable, (c) what cable length? OK, so you discovered that I'm a cheapskate. Actually I was using HP's so-called SERCOS-compliant devices (HFBR1604 etc, IIRC) which are supposed to be OK for 2MBd. With a few metres of polymer fibre and SMA connectors - once again, SERCOS-like. After this experience I now know that HP's HEADLINE specs tell you how many transitions per second you can shove down the link - not how precisely their timing is preserved - this latter info is a bit more deeply buried in the detailed data. I got vastly better results (both in terms of dynamic range and pulse distortion) with home-grown AC-coupled receiver circuitry but the HP devices are neat, cheap and compact, and for some applications (not mine as it happens) the DC coupling of the receiver is useful. And of course I could have used faster parts and solved the problem that way. But it remains an interesting problem which, in the end, turned out to be tractable. You don't always have to push the technology envelope to stumble into a puzzle that's worth solving. -- Jonathan Bromley ----------------------------------------------------------------- Electronics is fun. If you want me to take it seriously, call and we'll talk consultancy rates. -----------------------------------------------------------------Article: 11765
Your choice of FPGA/CPLD will determine what you need for programming support. SRAM based FPGA's require an on-board memory, typically an EPROM, or can be programmed via a microcontroller or CPU. Many CPLD's now support in-system-programming (ISP), which may require a hardware adapter that you prurchase from the CPLD vendor and attach to a parallel port on a PC. Your best bet is to find an FPGA/CPLD that will work in your application, then consult the vendor's local reps. for programming information. -RF Yang Yungchiang wrote in message <35F4E421.CAEF3B45@email.sps.mot.com>... >Hi, > >I am new to real FPGA world. I am looking a cheap FPGA kits that enable >me to program my own chip. I understand that each FPGA/CPLD is not that >expensive. However, I have no idea about the programmer (burner ?) >pricing. Could someone please give me an idea on how much a FPGA >Programmer cost. > >Thank you. > >-- >Yung-Chiang YANG > > > >Article: 11766
If you are using MAXPLUS2 you probably need to use a generate statement.
That was the case when I used MAXPLUS2 a year ago.
library ieee;
use ieee.std_logic_1164.all;
library altera;
use altera.maxplus2.all;
entity tri_state_bd is
port
(
input: in std_logic_vector(21 downto 0);
enable: in std_logic_vector(21 downto 0);
output: out std_logic_vector(21 downto 0)
);
end tri_state_bd;
architecture arch_tri_state of tri_state_bd is
begin
#ifdef MAXPLUS2
gen_tri:
for i in input'range generate
tri_buf: tri port map(input(i), enable(i), output(i));
end generate gen_tri;
#endif
#ifdef SYNPLIFY
process(input,enable)
begin
for i in input'range loop
if (enable(i) = '1') then
output(i) <= input(i);
else
output(i) <= 'Z';
end if;
end loop;
end process;
#endif
end arch_tri_state;
--------
Article: 11767wluka@hotmail.com wrote: > > As FPGAs grow, the need to re-use designs and source designs from third > parties is going to become more and more important..... I've been asked on occasion if it would be possible to take pieces of different people's designs and include them in a new design. Their biggest concern was having to regression-test each piece for timing. Because of the limitations of our tools, my answer has always been to start over at the VHDL level and instantiate each piece in the code, and then derive a whole new set of timing constraints for the new design. To me this seems like a waste of good place and route effort! There's no reason why we shouldn't be able to surgically remove entire pieces of netlist (LCA), keeping the timing requirements intact, drop them into a new design, AND give the placer the latitude to place the piece where it sees fit. Having one file such as an .xnf for both netlist (partitioning) and timing would greatly simplify integration. The tool must also enable us to save and maintain the new netlist cores and readily retrieve them into VHDL or schematic. Dear Santa,.... - CraigArticle: 11768
This is one of the bigger problems with using Altera for signal processing applications where delay queues and register files are often needed. The problem is twofold. First, other than the limited EAB resource, you don't really have any way to store bits other than in the LE registers. The EAB resources are quite limited, so implementing various delay queues in the design is difficult. Second, there are no tristates on the LE's so you are forced to use a mux so select between registers. Altera does allow the register to be used separately from the combinatorial part of the LE, so you may be able to put the MUX in the same LE's as the registers if you control the clock. Use the cascade chain to build your mux and save some registers (at the expense of speed). The other big issue I have with Altera for DSP apps is that by using the carry chain, you reduce the LE to a pair of 3 LUTs (one for carry function, one for 'sum' function) and one of those inputs for each is used for the carry input. That means any arithmetic function is limited to 2 inputs (ie plain vanilla adder w/o clear, enable, bypass, or add/subtract controls) unless you go to two levels of logic. That said, the global routing on Altera makes in far less sensitive to placement than many other FPGAs (like Xilinx), which makes it more synthesis friendly. This too is a double edged blade, as it also means the performance for an optimized design is not what it could be if the routing were more local. b_rich2@my-dejanews.com wrote: > Hi, I am a student and am currently designing a register file in Altera 7.21 > to be used in a project I am undertaking (non-commercial). I have a question > about whether there is a better way of implementing than what I am currently > doing. I have 16 X 16bit registers which I have constructed out of 16 X > LPM_FF (D type, 16 bits wide). So this takes up 256 LC's which is okay. But > here's the problem. I need 2 Output data buses from the register file. I am > currently using 2 X LPM_MUX (16 lines X 16 bit) to select which registers to > put on the bus. I have tested and simulated this design and it works okay. > The problem is that the 2 MUX's take up 416 LC's!! My whole register file > takes up 688 LC's, which is 59% of the space on my device!! This doesn't > leave me with much room for the rest of my project. I haven't completed my > project yet, but it appears I will be really struggling for space, and I am > required to use the 10K20. Surely there would have to be a better way of > designing a register file than what I have done, but I just can't seem to > think of a better way. I've been working on this problem now for several > weeks and am not making any progress. If there is anyone out there who would > be able to give me some advice I would be eternally grateful. Thanks in > advance. Bruce. > > -----== Posted via Deja News, The Leader in Internet Discussion ==----- > http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member Forum -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 11769
remy@provide.net wrote: > > I am new to the programmable logic game and have recently purchased > the $95 Xilinx software. I am using one of the 9500 series CLPD's with > schematic entry. All I need for eternal peace is a 4-digit divide by N > counter to be programmed with 4 BCD thumbwheel switches to divide from > 1 to 9,999. I would be GREATLY grateful for any help! Thank you very > Much.... > > Jim Remy > > remy@provide.net Jim, From my experience, you're best off going with a 14-bit down counter with a terminal count that synchronously resets the counter and enables the master clock to clock whatever it is that you're driving. You will first need a BCD-to-binary converter. The binary number will be 14 bits wide (ceiling[log base 2 of 10,000]=14). Next, you will need a 14-bit down counter that runs off of the master clock. The counter's terminal count (TC) will be active when the counter reaches all 0's. Connect TC to the synchronous load pin of the 14-bit counter and attach the 14-bit binary number to the counter's synchronous input. Now you can use the counter's TC to enable the master clock. Say you want to run a D-flop at a rate divided down from the master clock. Attach the TC of the counter to the enable pin of the D-flop. Attach the master clock to the clock pin of the D-flop. Now you're all set! A couple of final notes: 1. A value of '0' for the synchronous input to the counter will cause the counter to divide by one. A value of '1' will cause it to divide by two, etc. So, you will need to subtract by one either before or after the BCD-to-binary conversion (I suggest after). 2. Ensure that the master clock is on a low-skew net (i.e. global buffer or longline). If the amount of skew is greater than the setup time for the flops in the counter, you will have problems. - CraigArticle: 11770
Hans-Erik Floryd wrote: > > Hi, > > We're considering purchasing a code coverage tool. Does anybody have any > experiences in this field? Any particular tool you would recommend? > We're mainly interested in tools for VHDL. Hans, What do you mean by a "code coverage" tool? Synthesis? - CraigArticle: 11771
There are also openings for January 1999. See the web page for more
details.
Stephen Scott
--
Dept. of Computer Science & Engr. Asst. Prof. Stephen D. Scott
University of Nebraska Ferguson 305
Lincoln, NE 68588-0115 sscott@cse.unl.edu
(402) 472-6994 http://www.cse.unl.edu/~sscott/
=====================================================================
University of Nebraska -- Lincoln
Computer Science Engineering Department
The UNL CSE Department invites applications for several tenure-track
faculty appointments at assistant, associate, or full professor rank
to begin August 1999. Applicants should have promise for innovative
research and teaching in:
VLSI design or design automation,
Software engineering,
Enterprise systems including electronic commerce,
Distributed object technologies and middleware,
Human-computer interaction,
Database and information systems,
Computer and communications security, and/or
Theory and algorithms
and hold or be completing a PhD in computer science, computer
engineering, or related field. Exceptional candidates in other areas
will be considered.
The CSE Department offers both computer science and computer
engineering programs leading to BS, MS, and PhD degrees and has 20
tenure faculty lines, over 500 undergraduates and 100 graduate
students. UNL is Nebraska's comprehensive research university with
Carnegie I standing and membership in the American Association of
Universities. In 1998, UNL received the largest gift in its history
to establish the JD Edwards Honors Program in Computer Science and
Management.
Review of applications begins January 18, 1999, and will continue until
all positions are filled. A resume, statement of research and teaching
interests, and three references letters should be sent to:
Al Surkan, CSE Search Committee Chair Computer Science and
Engineering Department University of Nebraska -- Lincoln Lincoln,
Nebraska 68588-0115
See www.cse.unl.edu; email search@cse.unl.edu; phone 402.472.2401; fax
402.472.7767. UNL is committed to a pluralistic campus community
through AA/EO, is responsive to dual career couples, and makes
reasonable ADA accommodations.
--
Dept. of Computer Science & Engr. Asst. Prof. Stephen D. Scott
University of Nebraska Ferguson 305
Lincoln, NE 68588-0115 sscott@cse.unl.edu
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Article: 11772In article <6svbud$7cf$1@nnrp1.dejanews.com>, b_rich2@my-dejanews.com wrote: > Hi, I am a student and am currently designing a register file in Altera 7.21 > to be used in a project I am undertaking (non-commercial). I have a question > about whether there is a better way of implementing than what I am currently > doing. I have 16 X 16bit registers which I have constructed out of 16 X > LPM_FF (D type, 16 bits wide). So this takes up 256 LC's which is okay. But > here's the problem. I need 2 Output data buses from the register file. I am > currently using 2 X LPM_MUX (16 lines X 16 bit) to select which registers to > put on the bus. I have tested and simulated this design and it works okay. > The problem is that the 2 MUX's take up 416 LC's!! My whole register file > takes up 688 LC's, which is 59% of the space on my device!! This doesn't > leave me with much room for the rest of my project. I haven't completed my > project yet, but it appears I will be really struggling for space, and I am > required to use the 10K20. Surely there would have to be a better way of > designing a register file than what I have done, but I just can't seem to > think of a better way. I've been working on this problem now for several > weeks and am not making any progress. If there is anyone out there who would > be able to give me some advice I would be eternally grateful. Thanks in > advance. Bruce. > > -----== Posted via Deja News, The Leader in Internet Discussion ==----- > http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member Forum > You may have a look at the new Vantis VF1 family. The devices have memory blocks that are 32x4 and are dual port. There are four members of the family ranging from 12K upto 36K. Dual port memory simplifies matters! -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member ForumArticle: 11773
Hi Bruce. Your need for a register file is a common one, and as you have found out, it can take a lot of resources. While you offer eternal gratitude for anyone who offers advice, I suspect that your constraints of not being able to change the device type will preclude me from this treasure. It is also a shame that you have spent several weeks on this. The underlying primitives that an FPGA offers you can constrain your design. In your case, the need for two read ports restricts you to a flipflop as your primitive, bacause the FPGA you are using does not offer anything any bigger that is dual ported. The dual ported nature of a flipflop is that you can write to it any time you want (with a clock), and you can read it any time you want ( with muxes, for arrays). The EABs are not dual ported, so they dont help much, unless you can clock them at twice your cycle rate. If you want to write to the register file as well, then even faster clocking will be needed. If a memory supports at least two ports, one read and one write, then register files of 1xW, NxR are possible by writing to all memories at the same time and to the same address, but reading from independent addresses. The EABs can't do this in a single cycle in the devices you are using. Given my Xilinx centric view of the world, let me show you what I believe is the right tool for the job: The XC4000E, or EX, or XL. These devices have a dual ported primitive that supports 1 port that can read or write in one cycle, and one port that is read only. The primitive is a memory of 16 bits, so the mux you need for read (and the decode logic need for write) are part of the primitive. Size wise, it is as big as one of your LC's. (in Xilinx terminology, half a CLB) To build a register file with 16 words by 16 bits, takes 16 of these, 16 LC's, and the reads and writes can occur independently, and without contention, at full clock speed. This is done by using the R/W port in a write-only mode. If your cycle time is long enough, you can put a mux in the address path of the write only side, and mux in a read address to make dual use of this port. Use the rising edge of the clock to write, use clock high to select the read addres, clock low for write address, and falling edge of clock to take a snapshot of the read data into some flipflops, while the address is the write address. 16 LC's for the memory, 4 LC's for the address mux, 16 FF's (4 can share the address mux LC's, 12 need an LC of their own). A cleaner and faster solution is to just duplicate the memory. Two blocks of 16 LC's. On the write side, write to the same address in both blocks. On the read side, each block can have an independent address. This actually implements a 1xW, 2xR register file. Again, if you can afford the cycle time to play around with the write address mux, and dual use the port, the same basic structure gives you 1xW, 4xR. All these solutions are also going to be much faster than an array of flipflops and output select muxes. As I said above, right tool for the job. Sorry, Philip. In article <6svbud$7cf$1@nnrp1.dejanews.com> b_rich2@my-dejanews.com writes: >Hi, I am a student and am currently designing a register file in Altera 7.21 >to be used in a project I am undertaking (non-commercial). I have a question >about whether there is a better way of implementing than what I am currently >doing. I have 16 X 16bit registers which I have constructed out of 16 X >LPM_FF (D type, 16 bits wide). So this takes up 256 LC's which is okay. But >here's the problem. I need 2 Output data buses from the register file. I am >currently using 2 X LPM_MUX (16 lines X 16 bit) to select which registers to >put on the bus. I have tested and simulated this design and it works okay. >The problem is that the 2 MUX's take up 416 LC's!! My whole register file >takes up 688 LC's, which is 59% of the space on my device!! This doesn't >leave me with much room for the rest of my project. I haven't completed my >project yet, but it appears I will be really struggling for space, and I am >required to use the 10K20. Surely there would have to be a better way of >designing a register file than what I have done, but I just can't seem to >think of a better way. I've been working on this problem now for several >weeks and am not making any progress. If there is anyone out there who would >be able to give me some advice I would be eternally grateful. Thanks in >advance. Bruce. > >-----== Posted via Deja News, The Leader in Internet Discussion ==----- >http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member ForumArticle: 11774
On Tue, 08 Sep 1998 10:17:50 -0400, Craig Yarbrough <hyarbr01@harris.com> wrote: >What do you mean by a "code coverage" tool? Synthesis? Nope. A product that can tell you exactly how much of your code has been exercised or "covered" by your testbench. Checking every branch, if-then, case etc. and providing a count of every time the line is executed during your simulation run. Very useful in complex designs or in high reliability, military and medical applications. Also applicable to high quality consultants where a measure of "quality testing" becomes easier to provide to the end customer. Also stops you "testing what is already tested". For VHDL, might I suggest VHDLCover from TransEDA? www.transeda.com for Scandinavia, the local representative is Hardi Electronics Stuart Who works for a distributor of TransEDA product :-) For Email remove "NOSPAM" from the address
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