Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Subject: SHORT ON CASH?? ... TRY THIS!! From: Bob Levine <a711@earthlink.net> Date: Mon, Jul 27, 1998 01:54 EDT Message-id: <35BC1622.6C5C9D71@earthlink.net> THIS REALLY CAN MAKE YOU EASY MONEY, But follow the rules please. A little while back, I was browsing these newsgroups, just like you are now, and came across an article similar to this that said you could make thousands of dollars within weeks with only an initial investment of $6.00! So I thought," Yeah, right, this must be a scam", but like most of us, I was curious, so I kept reading. Anyway, it said that you send $1.00 to each of the 6 names and address stated in the article. You then place your own name and address in the bottom of the list at #6, and post the article in at least 200 newsgroups. (There are thousands) No catch, that was it. The main difference between this system and others is that you have a mailing list of 6 instead of 5... This means that your average gain will be app. 15 times higher!!! So after thinking it over, and talking to a few people first, I thought about trying it. I figured what have I got to lose except 6 stamps and $6.00, right? Like most of us I was a little skeptical and a little worried about the legal aspects of it all. So I checked it out with the U.S. Post Office (1-800-725-2161) and they confirmed that it is indeed legal! Then I invested the measly $6.00.............plus postage Well GUESS WHAT!!... within 7 days, I started getting money in the mail! I was shocked! I still figured it would end soon, and didn't give it another thought. But the money just kept coming in. In my first week, I made about $20.00 to $30.00 dollars. By the end of the second week I had made a total of over $1,000.00!!!!!! In the third week I had over $10,000.00 and it's still growing. This is now my fourth week and I have made a total of just over $42,000.00 and it's still coming in rapidly....... It's certainly worth $6.00, and 6 stamps, I spent more than that on the lottery!! Let me tell you how this works and most importantly, why it works....also, make sure you print a copy of this article NOW, so you can get the information off of it as you need it. The process is very simple and consists of 3 easy steps: STEP 1: Get 6 separate pieces of paper and write the following on each piece of paper "PLEASE PUT ME ON YOUR MAILING LIST." Now get 6 US$1.00 bills (or equivalent in your local currency) and place ONE inside EACH of the 6 pieces of paper so the bill will not be seen through the envelope to prevent thievery. Next, place one paper in each of the 6 envelopes and seal them. You should now have 6 sealed envelopes, each with a piece of paper stating the above phrase, your name and address, and a $1.00 bill. What you are doing is creating a service by this. THIS IS ABSOLUTELY LEGAL! Mail the 6 envelopes to the following addresses: #1 C.Meaux 3150 Soft Breezes Dr. #2029 Las Vegas, NV 89128 USA #2 J.L.B. 1533 NW 91ST Ave #7-24 Coral Springs, FL 33071 #3 M.J.F. 450 13th Ave. S. Wisconsin Rapids, WI 54495 #4 L.McDonald Fritz-Remy-Str.13 63071 Offenbach GERMANY #5 Levine- APT 224 525 N. Sycamore Ave LA-CA 90036 #6 Currie 3114 rocky Crest Katy, TX 77449 STEP 2: Now take the #1 name off the list that you see above, move the other names up (6 becomes 5, 5 becomes 4, etc...) and add YOUR Name as number 6 on the list. STEP 3: Change anything you need to, but try to keep this article as close to original as possible. Now, post your amended article to at least 200 newsgroups. (I think there is close to 24,000 groups) All you need is 200, but remember, the more you post, the more money you make! Don't know HOW to post in the newsgroups? Well do exactly the following: ----------------------------------------------------------- DIRECTIONS - HOW TO POST TO NEWSGROUPS ----------------------------------------------------------- Step 1. You do not need to re-type this entire letter to do your own posting. Simply put your cursor at the beginning of this letter and click and hold down your mouse button. While continuing to hold down the mouse button, drag your cursor to the bottom of this document and over to just after the last character, and release the mouse button. At this point the entire letter should be highlighted. Then, from the 'edit' pull down menu at the top of your screen select 'copy'. This will copy the entire letter into the computers memory. Step 2. Open a blank 'notepad' file and place your cursor at the top of the blank page. From the 'edit' pull down menu select 'paste'. This will paste a copy of the letter into notepad so that you can add your name to the list. Remember to eliminate the #1 position, move everyone up a spot (re-number everyone elses positions), and add yourself in as #6. Step 3. Save your new notepad file as a .txt file. If you want to do your postings in different sittings, you'll always have this file to go back to. ---------------------------------------- FOR NETSCAPE USERS: ---------------------------------------- Step 4. Within the Netscape program, go to the pull-down window entitled 'Window' select 'NetscapeNews'. Then from the pull down menu 'Options', select 'Show all Newsgroups'. After a few moments a list of all the newsgroups on your server will show up. Click on any newsgroup you desire. From within this newsgroup, click on the 'TO NEWS' button, which should be in the top left corner of the newsgroups page. This will bring up a message box. Step 5. Fill in the Subject. This will be the header that everyone sees as they scroll through the list of postings in a particular group. Step 6. Highlight the entire contents of your .txt file and copy them using the same technique as before. Go back to the newsgroup 'TO NEWS' posting you are creating and paste the letter into the body of your posting. Step 7. Hit the 'Send' Button in the upper left corner. You're done with your first one! Congratulations... -------------------------------------------------- INTERNET EXPLORER USERS: -------------------------------------------------- Step 4. Go to newsgroups and select 'Compose Message'. Step 5. Fill in the subject. Step 6. Same as #6 above Step 7. Hit the 'Post' button. ------------------------------------------- THAT'S IT! All you have to do is jump to different newsgroupes and post away, after you get the hang of it, it will take about 30 seconds for each newsgroup! **REMEMBER, THE MORE NEWSGROUPS YOU POST IN, THE MORE MONEY YOU WILL MAKE!! BUT YOU HAVE TO POST A MINIMUM OF 200** That's it! You will begin receiving money from around the world within day's! You may eventually want to rent a P.O.Box due to the large amount of mail you receive. If you wish to stay anonymous, you can invent a name to use, as long as the postman will deliver it. **JUST MAKE SURE ALL THE ADDRESSES ARE CORRECT.** Now the WHY part: Out of 200 postings, say I receive only 5 replies (a very low example). So then I made $5.00 with my name at #6 on the letter. Now, each of the 5 persons who just sent me $1.00 make the MINIMUM 200 postings, each with my name at #5 and only 5 persons respond to each of the original 5, that is another $25.00 for me, now those 25 each make 200 MINIMUM posts with my name at #4 and only 5 replies each, I will bring in an additional $125.00! Now, those 125 persons turn around and post the MINIMUM 200 with my name at #3 and only receive 5 replies each, I will make an additional $626.00! OK, now here is the fun part, each of those 625 persons post a MINIMUM 200 letters with my name at #2 and they each only receive 5 replies, that just made me $3,125.00!!! Those 3,125 persons will all deliver this message to 200 newsgroups with my name at #1 and if still 5 persons per 200 newsgroups react I will receive $15,625,00! With a original investment of only $6.00! AMAZING! And as I said 5 responses is actually VERY LOW! Average is probably 20 to 30! So let's put those figures at just 15 responses per person. Here is what you will make: at #6 $15.00 at #5 $225.00 at #4 $3,375.00 at #3 $50,625.00 at #2 $759,375.00 at #1 $11,390,625.00 When your name is no longer on the list, you just take the latest posting in the newsgroups, and send out another $6.00 to names on the list, putting your name at number 6 again. And start posting again. The thing to remember is, do you realize that thousands of people all over the world are joining the internet and reading these articles everyday, JUST LIKE YOU are now!! So can you afford $6.00 and see if it really works?? I think so... People have said, "what if the plan is played out and no one sends you the money? So what! What are the chances of that happening when there are tons of new honest users and new honest people who are joining the internet and newsgroups everday and are willing to give it a try? Estimates are at 20,000 to 50,000 new users, every day, with thousands of those joining the actual internet. Remember, play FAIRLY and HONESTLY and this will work. You just have to be honest. Make sure you print this article out RIGHT NOW, also. Try to keep a list of everyone that sends you money and always keep an eye on the newsgroups to make sure everyone is playing fairly. Remember, HONESTY IS THE BEST POLICY. You don't need to cheat the basic idea to make the money!! GOOD LUCK to all and please play fairly and reap the huge rewards from this, which is tons of extra CASH.Article: 11226
HI, EVERYONE... I AM USING THE ALTERA TOOL(MAXPLUSII-7.21 STUDENT EDITION). I HAVE ONLY EPF10K10LC84-4 DEVICE...BUT, THIS VERSION NOT SUPPORT IT. Timing-driven compilation is available only for the EPF10K20RC240-4 device. I WHIS TO KNOW HOW TO ADD THE OTHER DEVICE....... ANYONE HELP ME.....PLESASE...Article: 11227
<previous thread snipped> Has anyone managed to do any successful complex asynchronous design in an FPGA? Presumably the various async processor research projects are prototyping on FPGAs. Or, alternatively, does anyone know of an FPGA which guarantees minimum propagation delays? EvanArticle: 11228
URGENT Graduate required as Sales Engineer. Britcomp Sales LTD - Further details please see web site www.britcomp.com Application/Sales Engineer SALARY: £17,000 fully expensed company car (+ expense account, Laptop, fully expensed mobile phone) Technical qualifications required: VHDL (synthesis & simulation), FPGA knowledge, some ASIC, EDA tools (for FPGA or ASIC design), schematic capture. Job Description: Working with existing Blue Chip electronic companies. Candidate will be trained commercially & technically (both in products & new design methodologies, technologies). Candidate will sell and "design-in" high-level EDA tools (VHDL) & ASIC designs. Personal qualifications: Friendly, confident person. Out-going & easy to get along with. A hard worker. Location: Between Birmingham & Oxford area. Availability immediately. note: candidate salary will rise to £25,000 per year within 12-18 months. To apply fax C.V to 01372 362333 or email sales@britcomp.com Contact Louis Tsu or Alasdair Denton-Miller on 01372 362111 Britcomp Sales LTD Leatherhead Surrey Tel +44 (0) 1372 362111 Fax +44 (0) 1372 326333 web http://www.britcomp.comArticle: 11229
You may be interested in Self-Timed FPGA Systems page at the University of Edinburgh. See http://www.dcs.ed.ac.uk/home/rep/selfTimedFPGA/selfTimedFPGA.html. This, and other similar links, are available online in the FPGA Research section of The Programmable Logic Jump Station. Please see http://www.optimagic.com/research.html. ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- ems wrote in message <35bd9e48.6963996@news.dial.pipex.com>... ><previous thread snipped> > >Has anyone managed to do any successful complex asynchronous design in >an FPGA? Presumably the various async processor research projects are >prototyping on FPGAs. > >Or, alternatively, does anyone know of an FPGA which guarantees >minimum propagation delays? > >Evan >Article: 11230
Hello ,I am having a problem with the display of the simulation results using the Leapfrog simulator (version 2.3) Is there any setting option I have missed ? Thank you very much in advanced Benjamin -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member ForumArticle: 11231
Paul Oh <paul@moray.cs.columbia.edu> wrote in article <Pine.GSO.3.96.980727124610.6724A-100000@moray.cs.columbia.edu>... > I am newbie to FPGA. I am looking into programming my own silicon. Can > any one give pointers (books, websites) into developing motion control > IC's? > > Specifially: PID (proportional-integral-derivative) control > Trapezoidal motion profiles IMHO: If you're serious about PID loops, etc, forget the FPGA and use a microcontroller or one of the new fast cheap DSPs. You'll be glad you did. If you're serious about motion control, forget rolling your own and buy an off-the-shelf solution, like CompuMotor or something like that. You'll be glad you did. > PS: I have *never* programmed FPGA's before (I am a mechie). I have a > high-level understanding of the design process: Essentially you burn an > FPGA just like an EPROM right using schematic CAD or C-like programming > languages right? I intend to use Xilinx's development > board/tools. I do have a good grasp on logic, digital design, control > systems, programming and embedded micros though. As for designing FPGAs, check out the web sites of Xilinx or Altera or Actel or any of the other FPGA vendors. And be prepared to climb a somewhat steep learning curve. -andy -- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatories apeters@noao.edu.NOSPAMArticle: 11232
On 20 Jul 1998, Reetinder P. S. Sidhu wrote:
> Is there _any_ way at all of doing behavioral synthesis for the Xilinx
> 6200 FPGA?
> Any help will be greatly appreciated.
>
> Reetinder Sidhu
> Dept. of EE
> University of Southern
> California
>
Hi,
Even I am trying for a solution for behavioral synthesis. maybe the VIRTEX
series from Xilinx will give a better solution.
I am trying one method now but its tedious at the end. I wrote a behavioral
model in VHDL and synthesised it using the autologic II of Mentor. Then I back
annotated it to VHDL. Till here it was easy. Now the back annotated VHDL code
is to be rewritten in structural VHDL and XC6200 FPGA in mind.
Any other solution is welcome!
Thanks
sudheesh
>
>
>
*****************************************************************************
SUDHEESH MADHAVAN * 6001, S Power Rd
sudheesh@asu.edu * #9001
Phone no:602-988-2117 * Mesa
http://www.public.asu.edu/~sudiasu * AZ 85206
******************************************************************************
Quote: End of Education is Character
******************************************************************************
Article: 11233Hi all, Currently I am using ASIC library to synthesis my design (vhdl). I have succeed until gate-level with timing simulation (synopsys synthesizer + leapfrog simulator). Now the problem is : - I need to download my design into XC4025 FPGA in order to simulate it in the real world before we send it to fab. - In some part of my design, i am using tri-state buffers to read/write data onto data bus. If the target library is ASICs then NO Problems. Anyhow if I synthesize using FPGA library then my tristates become unsynthesizable since XC4025 *only* has tristates in its IOBs. Moreover since IOBs are located on periphery then the interconnection may become not realistic anymore (longer than needed) I am trying to replace tristate with mux2-1 style such that : if enable = 1 then dataout <= datain, else dataout <= (others => X). All signals is std_logic type. X is strong unknown (from std_logic table). As you might guess, it CAN NOT work, even just simulate its functionality. Hope anybody could help me how to replace this tristate. TIA -iman -- -iman ================================================== = Watch or be a part in Indonesia transformation = ==================================================Article: 11234
Imanuddin Amril Account wrote: > - I need to download my design into XC4025 FPGA in order to simulate it > in the real world before we send it to fab. > - In some part of my design, i am using tri-state buffers to read/write > data onto data bus. If the target > library is ASICs then NO Problems. Anyhow if I synthesize using FPGA > library then my tristates become unsynthesizable since XC4025 *only* has > tristates in its IOBs. Moreover since IOBs are located on periphery then > the interconnection may become not realistic anymore (longer than needed) I believe ALL Xilinx FPGA's support internal 3 state busses. From the Xilinx Data book: "A pair of 3-state buffers is associated with each CLB in the array. (SeeFigure28 on page 4-31.) These 3-state buffers can be used to drive signals onto the nearest horizontal longlines above and below the CLB. They can therefore be used to implement multiplexed or bidirectional buses on the horizontal longlines, saving logic resources. Programmable pull-up resistors attached to these longlines help to implement a wide wired-AND function." And since the 4025 has 32x32 CLB matrix it should have a total of 64 horizontal long lines that can be used for tri-state busses. -- Regards Glenn Eng glenn.eng@nortel.com (remove "NOSPAM." in header to reply")Article: 11235
Does anybody know of a particular type of FPGA that comes close in power consumption to Philips CoolRunner CPLDs?? thanks, Andrew Nelson andrew.nelson@cdott.comArticle: 11236
Imanuddin Amril Account wrote:
>
> Hi all,
>
> Currently I am using ASIC library to synthesis my design (vhdl). I have
> succeed until gate-level with timing simulation (synopsys synthesizer +
> leapfrog simulator).
>
> Now the problem is :
> - I need to download my design into XC4025 FPGA in order to simulate it
> in the real world before we send it to fab.
> - In some part of my design, i am using tri-state buffers to read/write
> data onto data bus. If the target
> library is ASICs then NO Problems. Anyhow if I synthesize using FPGA
> library then my tristates become unsynthesizable since XC4025 *only* has
> tristates in its IOBs. Moreover since IOBs are located on periphery then
> the interconnection may become not realistic anymore (longer than needed)
>
> I am trying to replace tristate with mux2-1 style such that : if enable = 1
> then dataout <= datain, else dataout <= (others => X). All signals is
> std_logic type. X is strong unknown (from std_logic table).
>
Use 'Z', not 'X'.
This example works:
-------------------------------------------------------------------
vhdl_bidi : PROCESS (data_in_out, data_in, enable)
-------------------------------------------------------------------
BEGIN
IF ( enable = '0' ) THEN
data_in_out <= data_in;
ELSE
data_in_out <= 'Z';
END IF;
END PROCESS vhdl_bidi ;
-- outputs :
--
data_out <= data_in_out AND enable;
-------------------------------------------------------------------
good luck!
Anton
--
__________________________________________________________________
Anton Scherer
MICROSWISS-Center Aargau
Steinackerstrasse 5
CH-5210 Windisch
Switzerland
phone : ++41-56-462-46-11
fax : ++41-56-462-46-15
email : mailto://a.scherer@fh-aargau.ch
www : http://www.microswissag.ch
___________________________________________________________________
Article: 11237> Imanuddin Amril Account wrote: > > > - I need to download my design into XC4025 FPGA in order to simulate it > > in the real world before we send it to fab. > > - In some part of my design, i am using tri-state buffers to read/write > > data onto data bus. If the target > > library is ASICs then NO Problems. Anyhow if I synthesize using FPGA > > library then my tristates become unsynthesizable since XC4025 *only* has > > tristates in its IOBs. Moreover since IOBs are located on periphery then > > the interconnection may become not realistic anymore (longer than needed) Actually, 128 3-State long lines are available in the XC4025E and XC4028EX or XL (recommended for new designs). Each 3-State long line has a splitter in the middle thus effectively doubling their number (each half can have up to 16 drivers): 32(rows) x 2(above and below) x 2(left and right) = 128 3-State long line segments in the 4025 and 4028. Let the bussing begin! -- Ed McCauley Bottom Line Technologies Inc. Specializing Exclusively in Xilinx Design, Development and Training Voice: (500) 447-FPGA, (908) 996-0817 FAX: (908) 996-0817Article: 11238
Glenn Eng wrote: > > Imanuddin Amril Account wrote: > > > - I need to download my design into XC4025 FPGA in order to simulate it > > in the real world before we send it to fab. > > - In some part of my design, i am using tri-state buffers to read/write > > data onto data bus. If the target > > library is ASICs then NO Problems. Anyhow if I synthesize using FPGA > > library then my tristates become unsynthesizable since XC4025 *only* has > > tristates in its IOBs. Moreover since IOBs are located on periphery then > > the interconnection may become not realistic anymore (longer than needed) > > I believe ALL Xilinx FPGA's support internal 3 state busses. From the > Xilinx > Data book: > > "A pair of 3-state buffers is associated with each CLB in the array. > (SeeFigure28 on page 4-31.) These 3-state buffers can be used to drive > signals onto the nearest horizontal longlines above and below the CLB. > They can therefore be used to implement multiplexed or bidirectional > buses on the horizontal longlines, saving logic resources. Programmable > pull-up resistors attached to these longlines help to implement a wide > wired-AND function." > > And since the 4025 has 32x32 CLB matrix it should have a total of 64 > horizontal long lines that can be used for tri-state busses. > > -- > Regards > > Glenn Eng > > glenn.eng@nortel.com > (remove "NOSPAM." in header to reply") And each tristate bus has 34 drivers in a 4025. They can be split into at least two segments for a total of 128 busses with 17 drivers each. They may be splittable into four segments, I can't remember if that is a slightly different family (like the 5200) or it is the larger devices in the 4000 family (or maybe the ORCA devices from Lucent). -- Rick Collins rickman@XYwriteme.com remove the XY to email me.Article: 11239
Ed McCauley wrote: > > > Imanuddin Amril Account wrote: > > > > > - I need to download my design into XC4025 FPGA in order to simulate it > > > in the real world before we send it to fab. > > > - In some part of my design, i am using tri-state buffers to read/write > > > data onto data bus. If the target > > > library is ASICs then NO Problems. Anyhow if I synthesize using FPGA > > > library then my tristates become unsynthesizable since XC4025 *only* has > > > tristates in its IOBs. Moreover since IOBs are located on periphery then > > > the interconnection may become not realistic anymore (longer than needed) > > Actually, 128 3-State long lines are available in the XC4025E and > XC4028EX or XL (recommended for new designs). Each 3-State long line > has a splitter in the middle thus effectively doubling their number > (each half can have up to 16 drivers): 32(rows) x 2(above and below) x > 2(left and right) = 128 3-State long line segments in the 4025 and 4028. > > Let the bussing begin! > > -- > Ed McCauley > Bottom Line Technologies Inc. > Specializing Exclusively in Xilinx Design, Development and Training > Voice: (500) 447-FPGA, (908) 996-0817 > FAX: (908) 996-0817 Ed, Great minds think alike! I didn't get your post until after I made mine. A little redundancy never hurt anybody... -- Rick Collins rickman@XYwriteme.com remove the XY to email me.Article: 11240
A reasonable estimate for a full adder is 10 equivalent 2-input-nand-gates
per bit. This is regardless of implementation technology. Gates are
universal, only the marketting numbers change. So your adder is about 80
gates.
From an implementation point of view, a better metric (at least for
Xilinx chips) is how many CLBs are used. If you are using the carry logic
facilityin the XC4000 style parts, it will take 5 CLBs, 1 to start the
carry chain, and one for each pair of bits to be added (1 + 4).
Here's a good example why just gate counting can lead you astray: Lets say
you want to add an 8 bit register after your adder. Flipflops (with CE
and an async clear) are about an 8 gate equivalent 80 + 64 = 144 gates.
But in CLB's the answer is still 5.
Philip Freidin
In article <6pbs9s$q4j$1@nnrp1.dejanews.com> satish@my-dejanews.com writes:
>Hello Sir
> I am having a simple C code
> # include <stdio.h>
> main()
> {
> unsigned char a=9,b=23,c;
>
> c= a+b; } The same can be converted into VHDL by declaring the bit vector
>of size 8 bits to each variable. Now my problem is how to caluclate the
>number of gates it is going to take for execution in Xlinx XC4004EX series.
>Even let it be at any series, I want to have the number of gates required to
>execute the above simple program Let any body help me Thanks in advance
>Please reply to my email address:satish_me@hotmail.com
>
>-----== Posted via Deja News, The Leader in Internet Discussion ==-----
>http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member Forum
Article: 11241Welcome to the real world!! If you want to know, you've got to ask..... Hamish Moffatt wrote in message <6pf30b$5ce$1@emu.cs.rmit.edu.au>... >Austin Franklin <darkroo5m@ix.netcom.com> wrote: >> Along with being sort-of-SPAM, isn't it funny how so many EDA companies >> fail to post pricing...either in posts or even on their web sites. I >> really don't want to talk to some sales person (who usually just wants to >> get all my particulars and add me to some SPAM data base so they can call, >> mail or e-mail me) before they will give me any pricing information. All I >> just want to know if the product is economically feasable. It really >> amazes me. > >Excellent point. As a student, I want to know whether a product is >shall we say "enterprise-priced" or whether it is in the reach of >students. I recently went through the whole email + phone call from sales >rep etc just to get a quote on an X Windows server, only to find out >that it was over $1000 (still a good product, mind you). > >Hamish >-- >Hamish Moffatt, StudIEAust hamish@debian.org, hamish@moffatt.nu >Student, computer science & computer systems engineering. 4th year, RMIT. >http://hamish.home.ml.org/ (PGP key here) CPOM: [******* ] 70% >Matter cannot be created or destroyed, nor returned without a receipt.Article: 11242
Does somebody know the prices (not exact) of xilinx FPGA and CPLD. (small qantities (10..20))Article: 11243
Thomas Reinemann <thomas.reinemann@mb.uni-magdeburg.de> wrote in
article <35BD8727.65B40E8@mb.uni-magdeburg.de>...
> I am uisng Xilinx-FPGAs (with M1) with ViewLogic's WorkView Office
(WVO)
> design entry is VHDL.
>
> Now I looked at the schematics automatically generated by WVO and I
> discovered that my reset is not connected to CLR of the FF.
>
> Is there a possibility to connect my reset with GSR and when yes,
how
> can I do this?
As Rick points out, see Xilinx tech note:
http://www.xilinx.com/techdocs/1376.htm . Essentially, you'll have
to instantiate a STARTUP component in your top-level VHDL source
file. And while they say that STARTUP is not simulatable, that's not
true - Xilinx has recently released VHDL (and Verilog) simulation
libraries for such components.
Now, as I read through the tech notes, I started to become suspicious
about all of this, and I kept thinking that I was doing something
wrong. Specifically, this tech note mentions:
"It is not necessary to include your set/reset signal in the
behavioral descriptions of the flip-flops in the design. Any signal
that is used to behaviorally set/reset a flip-flop will not use the
dedicated Global Reset network, and that set/reset signal will be
OR'ed with the Global Reset signal to asynchronously set/reset that
flip-flop."
If I read this correctly, this means that:
1) When writing code, for example, for a flip-flop, you *don't* have
to include a reset. This is because the chip automagically resets
all flipflops after configuration. Which means that one can
eliminate the reset term in the usual:
flipflop: process (clock, reset) is
begin
if (reset = '1') then
q <= '0';
elsif (rising_edge(clock)) then
q <= d;
end if;
end process flipflop;
Which of course means, then, that the functional simulation won't
match the chip!
2) "any signal that is used to behaviorally set/reset a ff will NOT
..." means that if you *do* write a behavioral description like
process:flipflop above, then you have the problem where you get TWO
reset nets, one of which is routed through and uses up regular
resources. Apparently! Unless you read further down into the tech
note's examples, where you come across:
--*****************************************************
--Example of using XILINX_GSR attribute to remove RESET
--signal from netlist. Use this for 3K designs, or for
--4K or 5K designs where the STARTUP symbol is on a
--top-level schematic.
library IEEE;
use IEEE.std_logic_1164.all;
entity USE_GSR is
port (RESET, IN1, CLK: in std_logic;
OUT1: out std_logic);
--Declare the Xilinx_GSR attribute and use it to remove the
--RESET signal from the synthesized Xilinx netlist
attribute Xilinx_GSR: boolean;
attribute Xilinx_GSR of RESET: signal is true;
end USE_GSR;
Now, when I read this, I sent an e-note to Xilinx Tech Support that
asked the following question:
"Given the example of USE_GSR above, does this mean that I have to
declare the attribute Xilinx_GSR in EVERY module that's not the top
level?"
The answer that came back was:
"Xilinx Answer 1376 refers to the GSR (or power up reset) i.e. if the
GSR is triggered every thing is reset not just the Flip Flop.
In this case it depends if you want to be able to control when the
flip flop is reset or only have it reset at power up. If you only
want the ff to be reset at power up, then yes remove the reset
signal. If you want to be able to control when the ff is reset (i.e.
reset just that flip flop) then you need to keep the reset signal in
your code.
In response to your second question no you do not need to declare the
Xilinx_GSR attribute in every lower level module. Having it declared
once at the top level is enough."
Note the last sentence: "Having it declared once at the top level is
enough." This, of course, contradicts the tech note. Or maybe it
doesn't. Perhaps what the tech note should have said was that the
attribute needs to be placed in the top-level entity.
Regarding simulation, I was referred to the Synopsys Design Guide.
Now, I'm not sure how relevant that guide is if I'm using the Metamor
synthesizer.
> Furthermore, I have got a warning during DRC:
>
> WARNING:basnu - The input pad net "CLK" is driving one or more
clock
> loads,
> but is not using a dedicated clock buffer (e.g., BUFG, BUFGP,
> BUFGS). This
> could result in large clock skews on this net.
>
> How can I insert the buffer?
> I already tried to use library metamor shipped with M1, but I was't
able
> to use it.
Make sure you synthesize your top-level module as "Chip" and not
"Macro." Your project file list (in the Project Manager) should only
have ONE VHDL file included. When that file is open in the HDL
editor, choose "Synthesis -> Options" and make sure that "Chip" is
selected under compile. This will automagically insert the clock
buffers when you choose "Synthesis -> Synthesize."
Also note that you shouldn't use "Synthesis -> Synthesize" for your
lower-level modules. For that, choose "Project -> Create Macro."
--
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatories
apeters@noao.edu.NOSPAM
Article: 11244Glenn Eng wrote: > > Imanuddin Amril Account wrote: > >> - I need to download my design into XC4025 FPGA in order to >> simulate it in the real world before we send it to fab. > > - In some part of my design, i am using tri-state buffers to You can get data sheets online at: http://www.xilinx.com > I believe ALL Xilinx FPGA's support internal 3 state busses. > And since the 4025 has 32x32 CLB matrix it should have a total of 64 > horizontal long lines that can be used for tri-state busses. Long lines can be split in the middle to make two three-state buses per long line for 128 total. Oh, and up to 32 more using the edge decoder logic, but these are wire-and buses. -- Phil Hays "Irritatingly, science claims to set limits on what we can do, even in principal." Carl SaganArticle: 11245
satish@my-dejanews.com wrote:
>
> Hello Sir
> I am having a simple C code
> # include <stdio.h>
> main()
> {
> unsigned char a=9,b=23,c;
>
> c= a+b; } The same can be converted into VHDL by declaring the bit vector
> of size 8 bits to each variable. Now my problem is how to caluclate the
> number of gates it is going to take for execution in Xlinx XC4004EX series.
> Even let it be at any series, I want to have the number of gates required to
> execute the above simple program Let any body help me Thanks in advance
> Please reply to my email address:satish_me@hotmail.com
>
> -----== Posted via Deja News, The Leader in Internet Discussion ==-----
> http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member Forum
My suggestion is to forget counting gates. What you want is to determine
what size chip a given design will fit. In a Xilinx 4000 series part you
would do much better to estimate how many CLBs it will take. If you are
implementing 2 input multiplexers, you are using only six - two input
gates per CLB. If you are implementing a more complex function you could
be using many more gates per CLB. But in each case you will be using the
full logic within the CLB (give or take the H block).
So gate count is not a useful measure of how a design will fit an FPGA.
Your 8 bit adder will take 4 CLBs. That is a well defined, known
quantity. The number of gates used can be argued depending on how you
wish to represent the logic of the adder and the (invisible) carry
chain.
--
Rick Collins
rickman@XYwriteme.com
remove the XY to email me.
Article: 11246Andy Peters wrote: > As Rick points out, see Xilinx tech note: > http://www.xilinx.com/techdocs/1376.htm . Essentially, you'll have > to instantiate a STARTUP component in your top-level VHDL source > file. And while they say that STARTUP is not simulatable, that's not > true - Xilinx has recently released VHDL (and Verilog) simulation > libraries for such components. > > Now, as I read through the tech notes, I started to become suspicious > about all of this, and I kept thinking that I was doing something > wrong. Specifically, this tech note mentions: > > "It is not necessary to include your set/reset signal in the > behavioral descriptions of the flip-flops in the design. Any signal > that is used to behaviorally set/reset a flip-flop will not use the > dedicated Global Reset network, and that set/reset signal will be > OR'ed with the Global Reset signal to asynchronously set/reset that > flip-flop." > > If I read this correctly, this means that: > > 1) When writing code, for example, for a flip-flop, you *don't* have > to include a reset. This is because the chip automagically resets > all flipflops after configuration. Which means that one can > eliminate the reset term in the usual: > > flipflop: process (clock, reset) is > begin > if (reset = '1') then > q <= '0'; > elsif (rising_edge(clock)) then > q <= d; > end if; > end process flipflop; > > Which of course means, then, that the functional simulation won't > match the chip! I don't remember reading this, and this is not what I do. I make sure that I DO include an asynchronous reset in my code for all FFs so that I can control the Reset state as either a 1 or a 0. If you want all of your FFs to go to '0' on Reset, you don't need to do anything other than add the Startup component and wire a pin to it. The GSR path is ALWAYS present and by default Resets all FFs to '0'. > 2) "any signal that is used to behaviorally set/reset a ff will NOT > ..." means that if you *do* write a behavioral description like > process:flipflop above, then you have the problem where you get TWO > reset nets, one of which is routed through and uses up regular > resources. Apparently! Unless you read further down into the tech > note's examples, where you come across: > > --***************************************************** > --Example of using XILINX_GSR attribute to remove RESET > --signal from netlist. Use this for 3K designs, or for > --4K or 5K designs where the STARTUP symbol is on a > --top-level schematic. > > library IEEE; > use IEEE.std_logic_1164.all; > > entity USE_GSR is > port (RESET, IN1, CLK: in std_logic; > OUT1: out std_logic); > > --Declare the Xilinx_GSR attribute and use it to remove the > --RESET signal from the synthesized Xilinx netlist > attribute Xilinx_GSR: boolean; > attribute Xilinx_GSR of RESET: signal is true; > > end USE_GSR; > > Now, when I read this, I sent an e-note to Xilinx Tech Support that > asked the following question: > > "Given the example of USE_GSR above, does this mean that I have to > declare the attribute Xilinx_GSR in EVERY module that's not the top > level?" > > The answer that came back was: > > "Xilinx Answer 1376 refers to the GSR (or power up reset) i.e. if the > GSR is triggered every thing is reset not just the Flip Flop. > > In this case it depends if you want to be able to control when the > flip flop is reset or only have it reset at power up. If you only > want the ff to be reset at power up, then yes remove the reset > signal. If you want to be able to control when the ff is reset (i.e. > reset just that flip flop) then you need to keep the reset signal in > your code. > > In response to your second question no you do not need to declare the > Xilinx_GSR attribute in every lower level module. Having it declared > once at the top level is enough." > > Note the last sentence: "Having it declared once at the top level is > enough." This, of course, contradicts the tech note. Or maybe it > doesn't. Perhaps what the tech note should have said was that the > attribute needs to be placed in the top-level entity. This is especially confusing to me, since I was told that you don't need that attribute at all. The backend tools supposedly recognize the duplication of the signal and remove the routed net. I do put the attribute in all of my VHDL code however. "Trust, but Verify". > Regarding simulation, I was referred to the Synopsys Design Guide. > Now, I'm not sure how relevant that guide is if I'm using the Metamor > synthesizer. > -- Rick Collins rickman@XYwriteme.com remove the XY to email me.Article: 11247
Hello everybody. I have a question concerning asynchronous logic.
It seems that an advantage exists if using this circuit as a
fundamental building block for asynchronous circuits, e.g. CPUs
that would require no clock (and operate at very high speed).
Is the circuit pictured here a good candidate for experiments in
asynchronous logic?
RESET * * *
- - - - - - - -* *
Tpd=4ns * 4ns *O- - + - - - - - -
+ - -* * |
| * * * |
+ - -|- - - - - - - - +
| + - - - - - - +
| |
| * * * |
+ - - - -* * |
SET * 4ns *O- +
- - - - - - - -* *
Tpd=8ns * * *
"Sequential or Combinatorial?"
-----------------------------------------------
http://www2.whidbey.net/~beattidp/
Douglas Beattie Jr.
Student of Computer Science
Student of Electronics Engineering Technology
Skagit Valley College, Whidbey Branch
Whidbey Island, Washington State, U.S.A.
Article: 11248
beattidp@whidbey.net (Douglas Beattie Jr.) writes:
> Hello everybody. I have a question concerning asynchronous logic.
> It seems that an advantage exists if using this circuit as a
> fundamental building block for asynchronous circuits, e.g. CPUs
> that would require no clock (and operate at very high speed).
You'd do well to research the state of the art first. Possible
starting points (with further links) are:
http://lenkkari.cs.tut.fi/~async/
http://maveric0.uwaterloo.ca/amulet/async/index.html
http://www.stud.ifi.uio.no/~perk/async.html
Not to diminish your excitement, but at some point you'll have to
synchronize between signals in your asynchronous CPU. This is not
only time-consuming and hence reduces the speed, but it also rids you
of some of the claimed advantages with regards to power consumption.
Achim Gratz.
--+<[ It's the small pleasures that make life so miserable. ]>+--
WWW: http://www.inf.tu-dresden.de/~ag7/{english/}
E-Mail: gratz@ite.inf.tu-dresden.de
Phone: +49 351 463 - 8325
Article: 11249Hello to integrate a VHDL simulator to a hardware board the following VHDL code was given . I regrette ,but I have never used these attribute commands before.Does anyone know exactly what this piece of code does ? Thank you very much in advanced, Benjamin email : www.bonics@hotmail.com library synopsys ;use synopsys.attributes.all; library ieee ; use ieee.std_logic_1164.all; library std; use std_textio.all; entity CLI_PLD is generic (delay : time := 10 ns; n :integer :=32; m :integer :=16; ttf_file :string :="design.ttf"); port ( clk,reset,enable :in std_logic; input : in std_logiv_vector(n-2 downto 0); ouputs : oout std_logic_vector (m-1 downto 0)); end CLI_PLD ; architecture cli of CLI_PLD is attribute FOREIGN CLI : architecture is "SYNOPSYS:CLI"; attribute CLI_ELABORATE of CLI : architecture is "cpld_open"; attribute CLI_EVALUATE of CLI : architecture is "cpld_eval"; attribute CLI_ERROR of CLI : architecture is "cpld_error"; attribute CLI_CLOSE of CLI : architecture is "cpld_close"; attribute CLI_PIN of CLK :signal is CLI_EVENT ; attribute CLI_PIN of ENABLE :signal is CLI_EVENT ; attribute CLI_PIN of RESET :signal is CLI_EVENT ; attribute CLI_PIN of INPUTS :signal is CLI_PASSIVE ; attribute CLI_PIN of OUTPUTS :signal is CLI_PASSIVE ; begin -- empty ,since this stuff is hidden in the c code end cli ; any clu about wha thtis is supposed to do ? Thanks . -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member Forum
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z