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DJ, you have yourself a couple of learning curves to climb. First, being a newbie to VHDL, you've got a language to learn. There are many nuances in the coding style that can greatly affect the circuit implementation. Second, being a newbie at FPGAs you need to learn the architecture then design your logic to fit the architecture. Finally, there are the FPGA tools which in some cases can be a bit of a bear until you've done a couple designs (and the low cost versions of the tools frequently don't come with any support). I might suggest trying first with schematic entry rather than VHDL, as the schematic entry gives more control over the design, and you don't have to worry about how your coding style will synthesize into the logic (expecting flames from the HDL bigots). Altera FPGAs are a bit of an exception, because their structure makes them less sensitive to placement and their tools resynthesize a schematic anyway (unless you set them up correctly for WYSIWYG). Don't take that as an endorsement for Altera though, their structure also puts them at a disadvantage in a number of high performance designs. As far as the design goes, you should have no problem putting the sync logic, DRAM control, memory management etc on even the smaller FPGAs. At higher resolutions, you'll want to use SGRAM (a dual port DRAM with a high speed shift register on one port) for the video memory. The palette is probably better left to a RAMDAC, as the memory for a 256 color palette would have to be off chip. The random access required to the palette, combined with the pixel clock rate make off-chip palette memory dicey at best, and then you still need a triple DAC to get the analog outputs. The interface to the RAMDAC can be done in the FPGA. Most of the FPGA vendors now offer low cost introductory tools that will place & route their smaller devices. Most of these contain some form of schematic entry, and a few contain an HDL entry tool. A video controller is not particularly demanding, and is certainly possible in the FPGAs from any of the vendor families. You might consult Steve Knapp's page at http://www.optimagic.com for a listing of low cost tools, links to the vendor's pages and data sheets and lots of other good stuff. BTW, if you use one of the SRAM based FPGAs such as xilinx, atmel, or altera 6,8 or 10K you can do a separate design for each resolution and just reload the part to change resolutions. Doing that saves quite a bit of logic that would otherwise be needed to change the counter lengths and other parameters. Result is a smaller and cheaper part. Since you will be connecting to a 80186, let the processor take care of configuring the FPGA and worrying about the program storage. Good luck, and welcome to the 'unreal' world of FPGAs. Dj wrote: > Ok OK OK : ) > > So I just implement one vga in traditional way so I use pcb and > logic logic logic ..............ok > My simple vga just functioning in 13h mode 320x200 256colors > witch is the only mode that I need on my 80186 board. > So one day I see that I can copy all to one fpga chip but I am > newbbbbbbbbbbbbbbie on vhdl language. > Maybe after all I can implement sync controll, dram refresch and palete > logic just on one fpga? > > For now I stady vhdl from my book OK. > And finaly I want to experiment with all this but I dont know whitch > fpga I have to use for start and is there some shareware or cheap > vhdl compiler for a poor man. > > Thank > > ps > Shhhhhhhhhhh don't tell anybody that I write about "real" and "unreal" > components. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 11676
[newsgroups adjusted]
z80@ds2.com (Peter) writes:
> I suggested to Xilinx (at some seminar years ago) that they should use
> FLASH for the config. It would have all the advantages of SRAM, and be
> nonvolatile. No good reason was given to me for not using FLASH.
Well shame on them for bailing on your question, but there is a
reason.
> I think they don't like mixing EEPROM cells with their normal fast
> logic. This is also why it is very hard to find ASIC CPU cores with
> EEPROM.
You can find it if you look in the right places. But decently fast
EEPROM on top of an existing ASIC technology requires the addition of
at least three masks and another poly layer plus a whole slew of
manufacturing problems to be solved before yield comes anywhere near
the original process. On the design side, at least for fast EEPROM
you need stable references (bandgap) and charge pumps to produce the
programming voltage. That is not exactly run-of-the-mill CMOS stuff.
It's also hard to keep the original transistor parameters while adding
EEPROM (not impossible, just really hard). Most customers aren't
prepared to cough up the price differential and go for the external
EEPROM route wherever possible. One other thing to note is that SRAM
is infinitely often reprogrammable, while EEPROM is not. Flash in
some instantiations is a particularly bad offender here with some
parts spec'ed at less than 1000 erase cycles. This would probably not
be a problem for most designs, but Xilinx would lose those where it
is, probably along with some of the others. And last but not least,
it's much easier to read out a powered down EEPROM than an SRAM, which
would probably worry much more people.
Achim Gratz.
--+<[ It's the small pleasures that make life so miserable. ]>+--
WWW: http://www.inf.tu-dresden.de/~ag7/{english/}
E-Mail: gratz@ite.inf.tu-dresden.de
Phone: +49 351 463 - 8325
Article: 11677http://jenna4sex.fsn.net/ WE HAVE A BRAND NEW SITE THAT YOU WILL LOVE. THERE ARE 4 GIRLS LIVING IN A HOUSE WITH CAMERAS IN EVREY ROOM. SEE THEM DO EVERYTHING YOU CAN IMAGINE. IT IS ALL FREE TAKE A PEEK. http://jenna4sex.fsn.net/ http://jenna4sex.fsn.net/ U]uPath: ix.netcom.com!su-news-hub1.bbnplanet.com!la-news-feed1.bbnplanet.com!news.bbnplanet.com!news.netgate.net.nz!news.xtra.co.nz!not-for-mailArticle: 11678
Hi!
I had that problem using gallileo, too. My solution is that you has to
make the enable signal to the PAD and the enable signal from the PAD to
the internal bus.
Example:
entity top is
port (
tripad : inout std_logic;
);
architecture rtl of top is
signal en_in: boolean;
signal enint1, enint2: boolean;
signal triint: std_logic;
begin
--this will generate int. TBUF's
triint <= "somesignal1" when enint1 else
'Z';
triint <= "somesignal2" when enint2 else
'Z';
--this will make the in/out PAD (and a TBUF on the input side).
triint <= tripad when en_in else
'Z';
tripad <= triint when (not en_in) else
'Z';
end
I has not check the code for synbtax errors:)
Best Regards
--
Soren Larsen
Logic Development
Niels Jernes Vej 10
9220 Aalborg
Denmark
mailto:sl@novi.dk
phone: +45 9635 2868
fax: +45 9635 4599
mobile: +45 2142 4146
Daniel T. Schwager wrote:
> Hi together,
>
> i have to design a VHDL-based FPGA which
> have to contact an uC-Databus (DB0..DB15).
> In my design, there's an FPGA internal tristate
> bus named "db".
> My problem is, that i don't know how to connect
> a bidirectional and tristate bus "db" to the FPGA pads.
> Should i use some library-objects like "ibuf16" ?
>
> Maybe somebody has an example-vhdl code for solving this
> "small" problem !
>
> regards
>
> Danny
>
> P.S.: i use the Xilinx Foundation Express Software and
> the Synopsys FPGA-Express. The FPGA is a Xilinx Spartan
> Chip (XC10)
> --
> ------------------------------------------------------------
> DTS Computer Schwager, Am Schnarrenberg 1, D-70376 Stuttgart
> Tel: +49-711-5094390 Fax: +49-711-5094391
> WEB: http://www.dts-s.de/ email: schwager@dts-s.de
Article: 11679I was wondering, if anyone could tell me what a divide-by-six Jonson counter is and to what it is used? Sincerely Reza BohraniArticle: 11680
Reza Bohrani wrote: > > I was wondering, if anyone could tell me what a divide-by-six Jonson counter > is and to what it is used? > > Sincerely > Reza Bohrani Johnson Counters are also known as 'Twisted Ring' counters. They are circular D registers, with a Single inversion. The advantage is no decoding glitches, and high speed. The disadvantage is more registers for a count modulus Normally, a design also includes logic to ripple out illegal states, which are possible in twisted Ring counters > /4 Look at the 4017 data, for a more detailed discussion. - jg -- ======= Manufacturers of Serious Design Tools for uC and PLD ========= = Specialists in Development tools for C51 cored controllers = mailto:DesignTools@xtra.co.nz Subject : Selc51ToolsArticle: 11681
A johnson counter is a ring counter (A shift register counter whose feedback is the last register inverted). Three flip-flops make a divide by six which produces this sequence 000 001 011 111 110 100 000 There are two illegal states, 010 and 101. Good design practice includes a trap to capture and escape from the illegal condition. The johnson counter is useful where high count speeds are required (simple feedback means low propagation delays and simple routing). These counters also have the advantage of producing a glitch free symmetric (50% duty) output once per cycle on each of the bits. These outputs are separated by equal phase angles, so the johnson counter is nice for generating split phase clocks Reza Bohrani wrote: > I was wondering, if anyone could tell me what a divide-by-six Jonson counter > is and to what it is used? > > Sincerely > Reza Bohrani -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 11682
One useful utility that I've used with Xilinx parts converts the MCS-format PROM file into a data byte or 'C' records for easy inclusion with your other source code. The utility is called MAKESRC and its available for both the PC and workstations. It's buried on the Xilinx web site at http://www.xilinx.com/techdocs/htm_index/utils_prom.htm along with some other bitstream-related utilities. ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- Daniel T. Schwager wrote in message <35E86279.E4804D2A@dts-s.de>... >Wade D. Peterson wrote: >> >> jcvilleneuve@hotmail.com wrote: >> >> >Hello there!!! >> >> >Is anybody has used something else than a PROM for the configuration cycle of >> >their FPGA (example direct CPU to fpga)? >> >> Yep. It works pretty good too. Did it with a Xilinx part once. I >> had to 'hack into' their bitstream file to do it, though. Wrote up a >> program to create a 'C' array file from the Xilinx bitstream file >> (automatically), and then downloaded it to the FPGA part from a CPU at >> boot-up time. >> > >Hi Wade, > >i wrote such a code also (Xilinx Foundation Base). My perl >script converts the hex-FPGA file to a C-File. > >I use the xilinx-Spartan FPGA's. The download routine >does work correct (CRC is OK), but if i try to >verify my FPGA design whith the READBACK-Option, about >100Bits are not correct. I thinks my verify-function is >not correct. Yould you email me your verify-function ?? > >regards > >Danny > > >-- >------------------------------------------------------------ >DTS Computer Schwager, Am Schnarrenberg 1, D-70376 Stuttgart >Tel: +49-711-5094390 Fax: +49-711-5094391 >WEB: http://www.dts-s.de/ email: schwager@dts-s.deArticle: 11683
Hello, Can somebody help me with a name of an software program, thats supports HSM features on a CD Jukebox. Thank you in advance! MartijnArticle: 11684
>The Zilog SCC has an interesting digital PLL. Yes, I have always been looking for the schematic of that particular design. Would be VERY useful. -- Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 11685
In article <cg1edmyoy.fsf@ite127.inf.tu-dresden.de>, Achim Gratz writes: > is, probably along with some of the others. And last but not least, > it's much easier to read out a powered down EEPROM than an SRAM, which > would probably worry much more people. I think it's easier to record a bitstream walking through inter-IC tracks than to open up a chip and "read" EEPROM cell contents. The first I can do at home, the latter requires $M equipment.Article: 11686
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Check the different solutions at http://associatedpro.com There are several
FPGA solutions there.
Reza Bohrani wrote:
> I am new to to world of FPGA and would like to now which vendor to choose.
> We have Actel, Altera, Xilinx, Lucent ... and many more. Can anyone please
> tell me which one is the cheapest, the "best"?
> Sincerely
> Reza
--
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Richard Schwarz, President
Associated Professional Systems Inc. (APS)
email: richard@associatedpro.com
web site: http://www.associatedpro.com
Phone: 410-569-5897
Fax: 410-661-2760
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
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Article: 11687
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Here are some suggestions:
Synopsys FPGA Express
Synplicity
Exemplar
Accolade Peak Vhdl
Very good deals can be had for Synopsys and Accolade (Metamor) from:
http://www.associatedpro.com
Reza Bohrani wrote:
> Which pc-based synthesis tool is the best on the market. I have heard of
> Synplify; is that a good tool or should I go for Leonardo or are there other
> good tools?
--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
Richard Schwarz, President
Associated Professional Systems Inc. (APS)
email: richard@associatedpro.com
web site: http://www.associatedpro.com
Phone: 410-569-5897
Fax: 410-661-2760
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
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Article: 11688
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Either will work. Synopsys may give you warnings, but the code will still work.
I've used it there. However, if your synthesis tool provides their own convert
functions, I reccomend using them. the CONV_INTEGER for SYNOPSYS works fine,
and if you are using numeric_std so does to_integer(); Synopsys cannot use
numeric_std due to the lack of support for aliases. This will or has changed (I
think) in the later releases.
Mark Purcell wrote:
> Thanks. I have tried this type of approach, but I think the synthesis part
> may have trouble, and my compiler didn't like it much either! I've recently
>
> started to use CONV_INTEGER to do this and so far it seems OK.
>
> Regards,
>
> Mark.
>
> Remove NOSPAM_ from email address.
>
> Wade D. Peterson <peter299@maroon.tc.umn.edu> wrote in article
> <6q8k4i$nqm$1@news1.tc.umn.edu>...
>
> >----------------------------------------------------------------------
> >-- Module name: INTRCONV.VHD
> >--
> >-- Description: Package converts INTEGER to STD_LOGIC_VECTOR and
> >-- vice-versa.
> >--
> >-- History: Project complete: APR 28, 1998 WD Peterson
> >--
> >----------------------------------------------------------------------
>
> <snipped for brevity>
--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
Richard Schwarz, President
Associated Professional Systems Inc. (APS)
email: richard@associatedpro.com
web site: http://www.associatedpro.com
Phone: 410-569-5897
Fax: 410-661-2760
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
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Article: 11689I am writing a VHDL model to be synthesized and compiled using OrCAD Express. The model synthesizes but when I try to compile I get two errors that are going to cause me a lot of trouble. 1) It says that it cant compile a while loop 2) It says that it cant compile multiple wait statements in the one process. Are these standard VHDL restrictions or is it just an OrCAD restriction? Is there any easy way to get around these probs? TIA Phil.Article: 11690
Hi everyone... We designed MicroMouse with VHDL. This is implemented on Two FPGA (Altera Flex10K10-4). All functions are designed with VHDL. Currently it runs... and trace simple maze. We're plan to implement more algorithms that trace Complex Maze... Visit our hopage.... http://csvlsi.kyunghee.ac.kr Mouse Picture... http://vlsi2.kyunghee.ac.kr/vhdl/Document/MicroMouse/Mouse_Top.jpg ------------------------------------------- ilho kook goodkook@csvlsi.kyunghee.ac.kr http://www.csvlsi.kyunghee.ac.kr http://vlsi2.kyunghee.ac.kr -------------------------------------------Article: 11691
Phillip Cook <cook-pa@eelab.usyd.edu.au> writes: > I am writing a VHDL model to be synthesized and compiled using > OrCAD Express. The model synthesizes but when I try to compile > I get two errors that are going to cause me a lot of trouble. > > 1) It says that it cant compile a while loop > > 2) It says that it cant compile multiple wait statements in the > one process. > > Are these standard VHDL restrictions or is it just an OrCAD > restriction? Is there any easy way to get around these probs? > There is no restriction in VHDL. However in VHDL there is nothing said about HOW to synthesize OR even it is synthesisable it all. There are synthesis tools that accept multiple wait statements in a single process (of course with restrictions, like waiting on the same signal and edge of that signal). Also WHILE/FOR LOOP is supported by some tools. But many synthesis tools will not support it. That is a reason why there is a working group of the IEEE (1076.6) defining a subset of VHDL. "This standard defines a way of writing VHDL that guarentees the interoperability of VHDL descriptions between any register transfer level synthesis tools that comply to this standard". You find more information about this group on www.eda.org/siwg Egbert MolenkampArticle: 11692
Phillip Cook wrote: > I am writing a VHDL model to be synthesized and compiled using > OrCAD Express. The model synthesizes but when I try to compile > I get two errors that are going to cause me a lot of trouble. > > 1) It says that it cant compile a while loop > > 2) It says that it cant compile multiple wait statements in the > one process. > > Are these standard VHDL restrictions or is it just an OrCAD > restriction? Is there any easy way to get around these probs? > > TIA > Phil. Thats' no VHDL but a synthesis tool restriction. You have to convert your code manually like that (see CHDL'93 for detailed implementaiton) process begin wait until clk = '1'; -- w0 p1( .. ); wait until clk = '1'; -- w1 p2( .. :; end process; process type state_type is ( w0 , w1 ); variable state_var : state_type := w0; begin wait until clk = '1'; case state_var is when w0 => p1( .. ); state_var := w1; when w1 => p2( .. ); state_var := w0; end case; end process; That pronciple also works for branches and while-loops with waits. Hope this helps , WolfgangArticle: 11693
molenkam@cs.utwente.nl (Bert Molenkamp) wrote: > Phillip Cook <cook-pa@eelab.usyd.edu.au> writes: > > I am writing a VHDL model to be synthesized and compiled using > > OrCAD Express. The model synthesizes but when I try to compile > > I get two errors that are going to cause me a lot of trouble. > > > > 1) It says that it cant compile a while loop > > > > 2) It says that it cant compile multiple wait statements in the > > one process. > > > > Are these standard VHDL restrictions or is it just an OrCAD > > restriction? Is there any easy way to get around these probs? > > There is no restriction in VHDL. However in VHDL there is nothing > said about HOW to synthesize OR even it is synthesisable it all. > > There are synthesis tools that accept multiple wait statements in > a single process (of course with restrictions, like waiting on the > same signal and edge of that signal). Also WHILE/FOR LOOP is > supported by some tools. But many synthesis tools will not support > it. If you want your code to be synthesizable (is there such a word?) and portable between tools then you should avoid using WHILE and FOR loops unless they are repeated a fixed number of times (which makes using a WHILE fairly pointless). Also you should avoid waits of all types except WAIT UNTIL clock'EVENT AND clock = '1'; which is normaly easier to do with an IF anyway. Writing code for synthesis is quite different from writing code for simulation, you can't use any of the realy useful commands. Andrew -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member ForumArticle: 11694
Phillip Cook wrote: > > I am writing a VHDL model to be synthesized and compiled using > OrCAD Express. The model synthesizes but when I try to compile > I get two errors that are going to cause me a lot of trouble. > > 1) It says that it cant compile a while loop > > 2) It says that it cant compile multiple wait statements in the > one process. > > Are these standard VHDL restrictions or is it just an OrCAD > restriction? Is there any easy way to get around these probs? > > TIA > Phil. -- Let me throw in my two cents worth. I would say you are making two mistakes. The first (and least important) is that you need to get some good references on how to program VHDL for synthesis. I just spent about 6 months coming up this learning curve and it is not easy. I said you should get good references, the problem is that I don't think there are any good easy references. I believe that VHDL for synthesis is much harder to learn than any programming language I have ever worked with. Part of the problem is that each vendor implements his own subset of the language for synthesis and the tools work differently with similar code. So you won't be able to find a universal reference like you can with 'C' or Pascal. Figure that you will have to take a couple of months extra to develop your skills. The second mistake you are making (in my opinion) is using the Orcad tool set. I started using Orcad 7.2. I spend many hours on the phone with support until I finally threw in the towel and got the Xilinx Foundation tools. Now my project is back on schedule and almost done. I have received the new release 9.0 from Orcad, but I haven't opened it and may well not. They told me that they might be switching VHDL tools with this release, so I might give it another try. But their product support has been very, very bad and many people on this newsgroup will echo my comments. You might seriously consider switching now rather than waiting until the middle of your project like I did. Rick Collins redsp@XYusa.net remove the XY to email me.Article: 11695
gang, Is there an easy way to constrain the Xilinx implementation tools to NOT use certain pins when choosing pinouts? I'm using an XC4005E part w/VHDL and Foundation 1.4. On my design, one of my input pins is a reset line, connected to STARTUP and GSR. I'm using a parallel EPROM to store my configuration. The place-and-route tools decided that it was a good idea to my reset line on one of the configuration EPROM's data lines. Since the reset input is always being driven by something, I have a problem. There are other signals similarly assigned that I want to make sure are not driven by the configuration process. Any thoughts? -andy -- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatories apeters@noao.edu.NOSPAMArticle: 11696
I wrote in article <01bdd5de$7e6f6ed0$4601fc8c@shootingstar>... > gang, > > Is there an easy way to constrain the Xilinx implementation tools to > NOT use certain pins when choosing pinouts? > > I'm using an XC4005E part w/VHDL and Foundation 1.4. On my design, > one of my input pins is a reset line, connected to STARTUP and GSR. > I'm using a parallel EPROM to store my configuration. > > The place-and-route tools decided that it was a good idea to my reset > line on one of the configuration EPROM's data lines. Since the reset > input is always being driven by something, I have a problem. There > are other signals similarly assigned that I want to make sure are not > driven by the configuration process. > > Any thoughts? > Never mind. I found it. CONFIG PROHIBIT = <pin num>; in the .ucf file. Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatories apeters@noao.edu.NOSPAMArticle: 11697
ÀÌÇ念 wrote: > Hello, > > I'm looking for xilinx tool, foundation. > > If any one have that tool(evaluation version, OK), please post the > tool. > > thank you Try one of the national distributors like Marshall (they have web sites). The eval is cheep or maybe even free!Article: 11698
For the FPGA stuff I would suggest you look at the Xiling 95xx CPLDs. They are fairly inexpensive and the s/w is available in student form for about $99. This would definitely be the way to go. I'm not sure about the interface (Schematics or VHDL ?). Schematics would probably be present though, so at least you would be able to enter your design. Dj wrote in message <6s9vvc$g73$1@server-b.cs.interbusiness.it>... > >Ray Andraka ha scritto nel messaggio <35DCC871.9D08A46C@ids.net>... >>Dj wrote: >> >>> I am New on fpga programming and I try to implement >>> simple video interface whitch I already do it with real componets, is >there >>> somebody can help me with some >>> very simple examples. >> >> Soo, FPGA's aren't real components?? Shhh, don't tell my clients! >>As far as your problem, can you be more specific. I doubt anyone is going >to >>post a complete video controller design as an example. >> >>-- >>-Ray Andraka, P.E. >>President, the Andraka Consulting Group, Inc. >>401/884-7930 Fax 401/884-7950 >>email randraka@ids.net >>http://users.ids.net/~randraka >> >> > >Ok OK OK : ) > >So I just implement one vga in traditional way so I use pcb and >logic logic logic ..............ok >My simple vga just functioning in 13h mode 320x200 256colors >witch is the only mode that I need on my 80186 board. >So one day I see that I can copy all to one fpga chip but I am >newbbbbbbbbbbbbbbie on vhdl language. >Maybe after all I can implement sync controll, dram refresch and palete >logic just on one fpga? > >For now I stady vhdl from my book OK. >And finaly I want to experiment with all this but I dont know whitch >fpga I have to use for start and is there some shareware or cheap >vhdl compiler for a poor man. > >Thank > >ps >Shhhhhhhhhhh don't tell anybody that I write about "real" and "unreal" >components. > > > >Article: 11699
Philips Digital Entertainment Group (DEG), is a newly formed group located in Palo Alto, CA, that has been recently structured to focus on the design and development of consumer electronics including such product lines as Digital TV, Internet TV, and home entertainment systems. An outgrowth of Philips Electronics in the Netherlands, DEG is well supported financially, technically, and will be taking advantage of excellent sales and marketing channels previously developed for other Philips Electronics product lines. As a result of forming this new group, we have an immediate need for a Software Architect. This individual will define, design, and describe the software architecture in modular, easy-to-maintain and extendible parts; works closely with the Software Team Leader and is technically responsible for implementing the required functionality; ensure the consistency and efficient integration of the separate modules of (Senior) Software Engineers in modular, easy-to-maintain and extendible software that meets the product specification; guides the Software Engineers in the design and implementation of the detailed design of modules; determines the required HIS in close consultation with hardware experts; maintains contacts with colleagues elsewhere within Philips; is abreast of and/or participates in standards; contributes to the organizational policy in the software field; and keeps abreast of technical developments in own professional field and maintains contacts with other R&D centers. Experience Preferred/Required · A minimum of 8 years of experience in the design and implementation of commercial software systems. · Demonstrable experience creating and completing major projects and systems, ideally within the consumer electronics business. · Broad knowledge and experience of hardware and software interfaces. · Current with external software developments within the industry. · Experienced working with project teams. · Specific knowledge of relevant design methods, architectural frameworks, and other software technologies etc.: e.g. UML, COM/OLE, JAVA, HTML, WinCE, pSOS Experience in audio/video technologies represents a significant advantage. This posting is for a full time position. For immediate consideration forward/email your resume to: PDEG Staffing Consultant RQSource@aol.com -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member Forum
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