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Hi everybody,
I am working on the FPGA implementation of an encryption device that
needs a fast 32_bit integer multiplier(the multiplication is in MOD(2^32))
as a key component in its data_path. I have tried with a behavioral VHDL code
for the multiplier, but it results in a delay of around 200 ns, once i try to
generate the netlist using the Synopsys tools with FPGAs as the target
libraries.
The VHDL code for the multiplier is as follows :
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.RC6_types.all;
entity MULTIPLY is
port(A : in word;
B : in word;
C : out word);
end MULTIPLY;
architecture BEHAVIORAL of MULTIPLY is
begin
MULTIPLY : process(A,B)
variable C_V : signed(63 downto 0);
begin
C_V := signed(A) * signed(B);
C <= std_logic_vector(C_V(31 downto 0));
end process MULTIPLY;
end BEHAVIORAL;
I would really appreciate, if someone could help me out in this
respect!!
Thanks,
Mohsin Riaz
Box#59,
Faculty Of Engineering,
Memorial University Of Newfoundland,
St. John's,Newfoundland,
A1B3X5,Canada.
email:mohsin@engr.mun.ca
Web:www.engr.mun.ca/~mohsin
Article: 12076Rickman <spamgoeshere4@yahoo.com> writes: > Zoltan Kocsi wrote: > ...snip... > > I think the antifuse faces technological problems instead. The antifuse, > > as far as I know, requires technologycal steps for those tungsten plugs > > other than the normal chip manufactoring process. This makes it inherently > > Someone correct me if I am wrong, but I thought that the links were low > conductance poly-si, rather than tungsten, and were blown shorted when > programmed. Isn't this why they are called "anti-fuse"? I looked it up in the book. If nothing else helps ... :-) The Quicklogic antifuse (Vialink) is amorphous Si. On its one side, there's a metalisation layer. On its other side there's that tungsten plug which connects the antifuse to the other metal layer via the oxide between the two metal layers. The Actel 'SPLICE' antifuse has a poly Si on the top, an n+ Si on the bottom and a oxide-nitride-oxide (ONO) dielectric layer (the antifuse itself) in between. Zoltan -- +------------------------------------------------------------------+ | ** To reach me write to zoltan in the domain of bendor com au ** | +--------------------------------+---------------------------------+ | Zoltan Kocsi | I don't believe in miracles | | Bendor Research Pty. Ltd. | but I rely on them. | +--------------------------------+---------------------------------+Article: 12077
Check with the vendor to see what they can provide. I know for
a fact that Xilinx includes LogiCORE blocks that are pre-made
blocks. One is a multiplier with variable bit-fields. I don't
know that they have an optimized one for mod(2^N), but you can
check.
In any case, the Xilinx ones are pipelined. They have a latency
of something like 3-6 cycles depending on the size of the inputs.
The cycle time is pretty good like several tens of MHz. Again,
this depends on the arguments, process (3.3v or 5v), and speed
rating of the device.
I wouldn't recommend a synthesized multiplier.
Cheers,
Jake
Mohsin Riaz <mohsin@engr.mun.ca> writes:
>Hi everybody,
>I am working on the FPGA implementation of an encryption device that
>needs a fast 32_bit integer multiplier(the multiplication is in MOD(2^32))
>as a key component in its data_path. I have tried with a behavioral VHDL code
>for the multiplier, but it results in a delay of around 200 ns, once i try to
>generate the netlist using the Synopsys tools with FPGAs as the target
>libraries.
>The VHDL code for the multiplier is as follows :
>library IEEE;
>use IEEE.std_logic_1164.all;
>use IEEE.std_logic_arith.all;
>use work.RC6_types.all;
>entity MULTIPLY is
> port(A : in word;
> B : in word;
> C : out word);
>end MULTIPLY;
>architecture BEHAVIORAL of MULTIPLY is
>begin
> MULTIPLY : process(A,B)
> variable C_V : signed(63 downto 0);
> begin
> C_V := signed(A) * signed(B);
> C <= std_logic_vector(C_V(31 downto 0));
> end process MULTIPLY;
>end BEHAVIORAL;
> I would really appreciate, if someone could help me out in this
>respect!!
>Thanks,
>Mohsin Riaz
>Box#59,
>Faculty Of Engineering,
>Memorial University Of Newfoundland,
>St. John's,Newfoundland,
>A1B3X5,Canada.
>email:mohsin@engr.mun.ca
>Web:www.engr.mun.ca/~mohsin
--
janovetz@uiuc.edu | Once you have flown, you will walk the earth with
University of Illinois | your eyes turned skyward, for there you have been,
| there you long to return. -- da Vinci
PP-ASEL | http://www.ews.uiuc.edu/~janovetz/index.html
Article: 12078Thanks to everyone who responded to my question. CLBs seem to be the way to go. ---Joel KolstadArticle: 12079
Hey Rick, If you're not careful pretty soon you're going to steal Peter Alfke's title of "most useful Usenet person on comp.arch.fpga." :-) Rickman wrote in message <3606694C.58F2FF33@yahoo.com>... >This will work for patterns where there are no duplicate words. However >if you have a pattern of, say, "A B C A B D" Then if you fail on your >match with 'D', you still need to compare to 'C' to determine if you >have a new starting match rather than going back to the beginning every >time. This can be a little tricky to analyze. Back when I was in high school, I wrote a terminal program for the Commodore 64 (all in assembly). At the time the popular thing was chat lines (although they were all hosted by single computers -- this was before the Internet was so widespread!). People were having great fun writing "auto greet" routines that would trigger on the message the chat line provided (e.g., "RickMan has entered the room") and respond back with various messages (e.g., "Hi RickMan!"). I decided to write my own routine, and was very satisfied with myself that mine took your trigger keyword and then used a state machine to decide, character by character, if the text was matching or not. Doing this made my trigger words somewhat limited compared to other peoples terminal programs that compared the incoming text to the _entire_ trigger string on _every single character_, but I was proud that mine was so much more efficient than theirs were! >In one of my graduate level logic classes we covered "string >recognizers" which is what you have here. If you want to design for the >general case and allow repeat entries in your match table, you will have >to make your design a little fancier. Hmm... good point... I hadn't considered that. Thanks for the tips! ---JoelArticle: 12080
> > >A johnson counter is a ring counter (A shift register counter whose feedback is > > >the last register inverted). Three flip-flops make a divide by six which > > >produces this sequence > > >000 > > >001 > > >011 > > >111 > > >110 > > The beauty of a ring counter vs. a binary or gray counter is that not > only can it be decoded glitch free, any single state or any set of > consecutive states can be decoded with a single two input AND gate. So > it requires very minimal decoding logic for many applications. Just remember, when creating a Twisted Ring / Johnson Counter, to allow for the 'alias' instances, as these things can be stable, with a variety of patterns in them. eg a 4 long RING counter ideally is 4 Low, 4 Hi, but can stably clock 1010101010101, and 11001100110011001100 - and imagine the downstream problems that can cause :-) - jgArticle: 12081
Compare architectures.
FPGA technology lets you experiment with CPU design.
Check out:
http://www.dnai.com/~jfox/fpgakit.htm
Simon
Article: 12082Any good reference material on "Metastability".Thanx,Saju -------------------------------------------------------------------- Posted using Reference.COM http://WWW.Reference.COM FREE Usenet and Mailing list archive, directory and clipping service --------------------------------------------------------------------Article: 12083
The Programmable Logic Jump Station (www.optimagic.com) maintains a list of links to free or low-cost FPGA/CPLD software at http://www.optimagic.com/lowcost.html. ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- adria.bofill wrote in message <360A69E4.951F73D7@imag.fr>... >I am a newbie in vhdl-fpga. > >Does Anyone know free/shareware for fpga design? > >Thanx > >Adria BofillArticle: 12084
The Programmable Logic Jump Station at http://www.optimagic.com contains some of the information that you are looking for. You can find a complete list of device vendors at http://www.optimagic.com/companies.html. Likewise, you can find a fairly comprehensive list of software vendors supporting FPGAs/CPLDs at http://www.optimagic.com/software.hmtl. Some of the other questions, such as I/O, number of metal levels, density, etc., will require that you visit the various vendor sites. ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- Peter wrote in message <36084F87.52B9691A@hotmail.com>... >Could anyone point me in the right direction as to where I could get >some broad information about FPGAs? > I have searched the web to no avail and require information such as >performance, software, gate length, number of metal levels, density, >I/O, speed, turn time and cost. >Any help on this matter would be sincerely appreciated. >Article: 12085
Joel Kolstad wrote: > > Hey Rick, > > If you're not careful pretty soon you're going to steal Peter Alfke's title > of "most useful Usenet person on comp.arch.fpga." :-) Thanks Joel, my pleasure. -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 12086
I would not advise using synthesis to generate your multiplier. Instead use a pre-placed core. Synthesis doe not have the smarts to do a good placement, nor does it do a very good job at using the FPGA resources. You might look at the multipliers page (http://users.ids.net/~randraka/multipli.htm) on my website for a discussion on multiplication in FPGAs. The problem with synthesizing a multiplier is the synthesis will infer a row ripple array structure, which is well suited for 2 input logic. The FPGA resources favor a structure constructed around partial products and adder trees. Unless you specifically instantiate this structure (or instantiate as a logic core), you'll get a slow multiplier. Even with the correct structure, correct placement is critical to performance. Again, the logic cores will give you the correct placement for best performance. So you look in the core library and discover there is no 32x32 multiplier. What to do? Read over my multiplier page again on the section about partial products. You can combine lower radix multipliers to obtain the desired size using this technique. If your multiplier is signed, you will have to account for the sign (which I haven't gotten around to addressing on my page). The easiest way to work through the sign is by reinterpreting the 2's complement msb meaning as negative 2^n. Thus an eight bit 2'sc number has bit weights -256,128,64,32,16,8,4,2,1. Then when computing the partial products take into account the negative bit weights. Mohsin Riaz wrote: > Hi everybody, > > I am working on the FPGA implementation of an encryption device that > needs a fast 32_bit integer multiplier(the multiplication is in MOD(2^32)) > as a key component in its data_path. I have tried with a behavioral VHDL code > for the multiplier, but it results in a delay of around 200 ns, once i try to > generate the netlist using the Synopsys tools with FPGAs as the target > libraries. > > The VHDL code for the multiplier is as follows : > > library IEEE; > use IEEE.std_logic_1164.all; > use IEEE.std_logic_arith.all; > use work.RC6_types.all; > entity MULTIPLY is > port(A : in word; > B : in word; > C : out word); > end MULTIPLY; > > architecture BEHAVIORAL of MULTIPLY is > > begin > MULTIPLY : process(A,B) > variable C_V : signed(63 downto 0); > begin > C_V := signed(A) * signed(B); > C <= std_logic_vector(C_V(31 downto 0)); > end process MULTIPLY; > end BEHAVIORAL; -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 12087
Hello everyone! I am working on an I2C controller to be placed in an FPGA and I will appreciate any valuable information. Tank you! Ovi -- ************************************************************ Ovidiu Lupas TimTeh Electronics Ltd. e-mail : ovilup@hotmail.com home e-mail : ovilup@mail.dnttm.ro phone : 40-56-121951 work e-mail : lupas@timteh.dnttm.ro phone/fax : 40-56-198943 ************************************************************Article: 12088
V8.3 changed the default PROM device. Convert the project .SOF file to .POF and select the EPC1 as the target PROM. Good Luck. Nicolas Matringe wrote in message <35F4D9FD.89AEFEFD@dot.com.fr>... >Hello >The problem has already been mentionned 1 or 2 months ago. >I can't manage to program an Altera PROM EPC1 with the DataIO ChipWriter >Someone at DAtaIO told me this problem appeared with designs compiled >with Max+ v8.2 and that I should use an *older* version (I'm a bit >puzzled here. I hope he meant newer) However, I use Max+ v8.3Article: 12089
Juergen Otterbach wrote: > > Dear FPGA and VHDL users, > please let me know if you heard about problems using the Altera DSP Kit > to design a FIR filter in FLEX10K. Please let me know from what I have > to be aware. Yes. A project I was involved in used this package on a FLEX10K series. We had two identical parallel 64 tap FIR filters which caused major headaches. Sometimes they worked, then if you made a change in the design which had nothing to do with the filter implementation, then they would stop working. Altera could not help since they wanted our design to try and repeat the problem which we were not prepared to do. Solution: Write your own FIR filter, its not really that difficult. We did and the problem vanished. WaltArticle: 12090
On Fri, 25 Sep 1998 09:32:51 -0500, "Dan Parent" <dparent@itis.com> wrote: ... >concern I had with the CPLD is the 5volt logic output only reaches >aproximately 3.7 to 4volts due to a diode drop. No negative side effects >have been detected in the product's logic levels yet but we have only >produced about 500 units. We may be switching to an Atmel or Altera >solution on the next pcb to overcome the voltage problem. > You might want to check the altera or atmel data books before making any changes. I believe altera only gaurantees 2.4 volts for a logic high depending, of course, on its load. This is for a 5 volt, flex 10k device and meets the requirements of driving cmos/ttl logic (i think). If you really want to make sure you're meeting the level requirements of your load device, you might want to look into using open drain outputs with pull-ups. OTH, I can't think of any 5 volt devices I've met that wouldn't take a 3.7 to 4 volts as a logic high. Good luck, Tim.Article: 12091
>I am working on an I2C controller to be placed in an FPGA and I will >appreciate any valuable information. > If you're using Altera devices there's an I2C module on the freecore webpage that might do what you need. I'll look up the url if you're interested. (I haven't used this lpm myself, I've only seen it -- it is well documented though). Tim.Article: 12092
Hi Eric, We do take up such projects, being a consulting company focussing specifically in VLSI Design and EDA solutions. Are you lookign for some outside help where we can come in on a contract basis and help you in the project ? Please let me know. Our company is Spike Technologies, Inc and we are based in Milpitas, CA. We have very good skills is design FPGAs, ASICs and conversion of FPGA to ASIC. If our skillsets interest you, please visit our web site at www. spiketech.com and call Sri at (408)945.0354 Ext. 105 Thanks - Sri Eric Edwards <ese002@news9.exile.org> wrote in article <slrn6vm144.k5k.ese002@spica.exile.org>... > We are in the process of a major rework of an aging ASIC design that has > been moderately reworked before. Given the magnitude of the changes, > and the fact the base design is not completely understood, we are > considering doing an FPGA first. And as the only member of the team > with any FPGA experience, they're looking at me. > > The trouble is, the design is filled with gated clocks and complicated > logicly divided clocks. There are also a small but non-trivial number > of more blatantly asynchronous design features. My FPGA experience is > limited was with almost purely synchronous designs. This was > deliberate. But this time I don't have that option. What I would like > to know is: How bad is it? And, is it really worth doing? Some points > of how to handle the gated clocks would be helpful too. > > -- > Real courtesy requires human effort and understanding. > Never let your machine or your habit send courtesy copies. >Article: 12093
Hi Gary, I am responding from Spike Technologies, Inc. to your message for ASIC jobs+work We are a consulting company offering precisely Design/Verification/Implementation services in ASIC/FPGA design, EDA Software Development and Cell & Library Development. We have 90 employees worldwide with 50 in the US and the rest in our engineering center in India. We would be interested in working with yourselves. For more information about ourselves, please visit our web site at www.spiketech.com and contact Sri on (408)945.0354 Ext. 105 Thanks - Sri For further information Garynlang <garynlang@aol.com> wrote in article <19980923204955.09176.00001033@ng141.aol.com>... > > We have several job opportunities in Phoenix > (nice quite, no crime, low living cost city in Arizona) > for ASIC/FPGA people at a $600 mil. IC design > company. And we need CAD SW people as well. > Position: Design engineer, will be responsible for the > design and development of low power high speed products > based upon embedded RISC and DSP cores. > Requirements: > BSEE, MSEE, (university degree) > 2++ year experience (the more the better), English language > skill. > Pls. send your TXT resume as an EMAIL TXT only > (pls do not send MS-WORD document). > We provide US work visa for 4,8+ years. > Laslo and Gary > > > Gary N. Lang > Vice President of ACD,Inc. > E-mail: garynlang@aol.com > http://www.acdcon.com/ >Article: 12094
Hello Lothar, We offer the following services and have expertise in-house (a)ASIC/FPGA design, verification & implementation services. (b) EDA Software solutions (c) Cell & Library Development We have 90 employees world-wide and 50 engineers in our US Design center and the rest in our engineering center in India. Please let me know if there are any opportunities we could address and bring in our expertise in this area. Thanks - Sri (408)945.0354 Ext. 105Article: 12095
Hi all: I need samples for VHDL, that must add 3 std_logic_vector(9 downto 0); what is the fastest mothed? thanks John HuangArticle: 12096
In article <6uo4jl$rjk$1@orthanc.reference.com>, saju@wipinfo.soft.net wrote: >Any good reference material on "Metastability".>>Thanx,>Saju > > > -------------------------------------------------------------------- > Posted using Reference.COM http://WWW.Reference.COM > FREE Usenet and Mailing list archive, directory and clipping service > -------------------------------------------------------------------- Take a look at http://www.cypress.com/pub/appnotes/pldmeta.pdfArticle: 12097
Are you sure you are providing all the power and gnd pins correctly ? Are you exceeding the total current specifications ? Ie the current drawn by the VCC pins is less than the datasheet specifications ? What about the Dynamic current consumption when you are switching a load of outputs ? Just some thoughts for you. Leprechaun wrote in message <6ue1f8$cpd@ustsu10.ust.hk>... >Hi all, > >I am using Xilinx XC4028XL-1-PG299 to implement a circuit. The utilization >is 100 % (all 1024 CLBs are used). After I download the circuit, I use a >IMS Tester to test the chip. >I found that for some output pin assignment, my circuit works well, but >for another, it just gives wrong result or just no result (all outputs >stay zero). > >I've done post-sim using the .sdf and .vhd files generated by M1 in synopsys >and the it works well (not any glitch problems ) and the timing >requirement for my circuit is not tight at all. > >does anyone have the same experience? I've already spent 2 weeks time in >debugging this problem but don't have any idea up till now..... > >Thanks a lot. > >Rgds, > >Oliver >Article: 12098
John Huang wrote: > Hi all: > I need samples for VHDL, that must add 3 std_logic_vector(9 downto 0); > what is the fastest mothed? Depends on your target. For an ASIC, the fastest method is probably a wallace tree with some form of fast look-ahead carry. For three inputs, however, I'm not sure the Wallace tree will buy much. In Xilinx FPGAs, the ripple carry is much faster than any carry look-ahead schemes for the bit widths you are looking at (assuming you care about clock latency), so a simple adder tree is fastest...assuming your HDL code makes use of the carry logic and places the logic accordingly. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 12099
> Any good reference material on "Metastability". Are you looking for general conceptual information or numbers for actual devices? -- These are my opinions, not necessarily my employers.
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