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hello, I'm looking for a evalation (free) version of Synario to use with Atmel's ATF1508. Does anybody know where I can get it? -- Amir Manasterski amirm@_ NOSPAM ibm.net / amirm@_ NOSPAM larc.usp.br USP - University of Sao Paulo - Brazil.Article: 11776
-----Original Message----- From: Peter Alfke [SMTP:Peter.Alfke@xilinx.com] Sent: Tuesday, September 08, 1998 4:44 PM To: Yarbrough, Howard Subject: Re: Xilinx CLPD Craig Yarbrough wrote: > > > From my experience, you're best off going with a 14-bit down counter > with a terminal count that synchronously resets the counter and > enables > the master clock to clock whatever it is that you're driving. > .....snip I do not see any need for first converting from decimal to binary. In a CPLD, it is as easy to implement a BCD counter as it is to implement a binary counter. It may be some work to write the equations, and there may not be the appropriate library element readily available, but there is no fundamental problem with the direct BCD counter implementation. Peter Alfke, Xilinx Applications ----------------------------------------------------------------------- Peter, I made a couple of assumtions here: 1. I assumed the application was high-speed, so I picked an application that could readily access an RPM. 2. I assumed that the user wouldn't mind the extra overhead of converting BCD-to-binary. I'm used to working with your 4000E 125k+ gate count devices! ; ) If area is more of a concern that speed, then you're right. By all means draw up some K-maps and save the extra CLBs. - CraigArticle: 11777
I am receiving excellent responses: THANKS. Does anyone know of a $100 programming device?Article: 11778
Found one for about $220. Does anyone have any comments about this model? http://www.needhams.com/emp10.htm Raymond Chiu wrote: > I am receiving excellent responses: THANKS. > > Does anyone know of a $100 programming device?Article: 11779
If you are interesting, here are a few web pages: (some browsers need the www prefix, which was omitted) http://www.vantis.com http://www.altera.com http://www.xilinx.com Mike added: http://www.latticesemi.com Another to check out: http://www.cypress.com -- Phil Hays "Irritatingly, science claims to set limits on what we can do, even in principle." Carl SaganArticle: 11780
Stuart Clubb wrote: > > For VHDL, might I suggest VHDLCover from TransEDA? > > www.transeda.com > > for Scandinavia, the local representative is Hardi Electronics > I've looked briefly at VHDLCover, and it is the alternative we're considering right now. But I'm sure there are other tools out there as well. Has anybody used anything else? Hans-Erik -- Hans-Erik Floryd Telephone: +46 31 747 00 00 Ericsson Microwave Systems AB Direct: +46 31 747 65 86 Airborne Radar Division Telefax: +46 31 27 10 19 Hans-Erik.Floryd@emw.ericsson.seArticle: 11781
In article <6t3uht$f2p1@serv1.uspnet.usp.br>, "Amir Manasterski" <amirm@larc.usp.br> wrote: > hello, Hi, > I'm looking for a evalation (free) version of Synario to use with Atmel's > ATF1508. > Does anybody know where I can get it? Synario offers a free download of the Atmel CPLD kit for version 4.1. vhich includes you AFT1508 device. But this means you need to have (buy) the Synario basic package. The obvius way would be to ask your local representative (or if you dont have any ask Synario for the nearest contact person) for a free evaluation of the product. Possibly a special disconunt for educational use. The home page is www.synario.com The email is edasales@synario.com > -- > Amir Manasterski > amirm@_ NOSPAM ibm.net / amirm@_ NOSPAM larc.usp.br > USP - University of Sao Paulo - Brazil. -- Matija In chaos all things are possible. Matija Milostnik, RDHW, IskraTEL, Ljubljanska 24a, SI-4000 Tel: +386 64 27 2125, Fax: +386 64 221 552, Email: milostnik@iskratel.si www.IskraTEL.si: Building the world of telecommunications -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member ForumArticle: 11782
Philip Freidin wrote: > Hi Bruce. Your need for a register file is a common one, and as you have > found out, it can take a lot of resources. While you offer eternal > gratitude for anyone who offers advice, I suspect that your constraints of > not being able to change the device type will preclude me from this > treasure. It is also a shame that you have spent several weeks on this. > > The underlying primitives that an FPGA offers you can constrain your > design. In your case, the need for two read ports restricts you to a > flipflop as your primitive, bacause the FPGA you are using does not offer > anything any bigger that is dual ported. The dual ported nature of a > flipflop is that you can write to it any time you want (with a clock), > and you can read it any time you want ( with muxes, for arrays). The EABs > are not dual ported, so they dont help much, unless you can clock them at > twice your cycle rate. If you want to write to the register file as well, > then even faster clocking will be needed. > > If a memory supports at least two ports, one read and one write, then > register files of 1xW, NxR are possible by writing to all memories at the > same time and to the same address, but reading from independent > addresses. The EABs can't do this in a single cycle in the devices you are > using. > > Given my Xilinx centric view of the world, let me show you what I believe > is the right tool for the job: The XC4000E, or EX, or XL. > > These devices have a dual ported primitive that supports 1 port that can > read or write in one cycle, and one port that is read only. The primitive > is a memory of 16 bits, so the mux you need for read (and the decode > logic need for write) are part of the primitive. Size wise, it is as big > as one of your LC's. (in Xilinx terminology, half a CLB) You are right except that the 16 bits dual-ported RAM you describe is not half a CLB but one full CLB. Catalin BaetoniuArticle: 11783
The dataio chiplab (is it the same as yours?) has a bugfix for programming the EPC1 proms instead of destroying them. I assume you need this fix too. The people at dataio should be able to help you. Nicolas Matringe wrote in message <35F4D9FD.89AEFEFD@dot.com.fr>... >Hello >The problem has already been mentionned 1 or 2 months ago. >I can't manage to program an Altera PROM EPC1 with the DataIO ChipWriter >Someone at DAtaIO told me this problem appeared with designs compiled >with Max+ v8.2 and that I should use an *older* version (I'm a bit >puzzled here. I hope he meant newer) However, I use Max+ v8.3 > >Any idea? > >Nicolas MATRINGE DotCom SA >Conception électronique 16 rue du Moulin des Bruyères >Tel: 00 33 1 46 67 51 00 92400 COURBEVOIE >Fax: 00 33 1 46 67 51 01 >Mail reply : remove one dot from the address (guess which :-)Article: 11784
This week's Tech Note was written by Peter Alfke from Xilinx. It describes how to avoid the difficulties that can arise when newer high-speed parts are used in older designs. www.edtn.com/pld Murray Disman EditorArticle: 11785
Marc Verhoeven wrote: > The dataio chiplab (is it the same as yours?) has a bugfix for programming > the EPC1 proms instead of destroying them. I assume you need this fix too. > The people at dataio should be able to help you. In fact it's a ChipWriter portable. We had a reply from data-io and they said that they are aware of this problem and working on a patch. As the prom is the same as before, the problem is only to convert the new EPC1 source file format to old. I don't think it needs a year ! What kind of patch do you have for chiplab ? Thank you for any help. Yves Le Henaff DotCom SAArticle: 11786
In article <35F675B8.CE453E46@spam.com> Catalin <no@spam.com> writes: >Philip Freidin wrote: > >> ... most of my article not reproduced, cos' you've already seen it ... >> >> These devices have a dual ported primitive that supports 1 port that can >> read or write in one cycle, and one port that is read only. The primitive >> is a memory of 16 bits, so the mux you need for read (and the decode >> logic need for write) are part of the primitive. Size wise, it is as big >> as one of your LC's. (in Xilinx terminology, half a CLB) > >You are right except that the 16 bits dual-ported RAM you describe is not half a >CLB but one full CLB. >Catalin Baetoniu Yep. Got to keep me honest: 16 x 16, 1xW, 1xR, Simultaneous R and W to diff addr 32 LC's or 16 CLBs 16 x 16, 1xW, 2xR, Simultaneous R and W to diff addr 64 LC's or 32 CLBs 16 x 16, 1xW, 3xR, Simultaneous R and W to diff addr 96 LC's or 48 CLBs 16 x 16, 1xW, 4xR, Simultaneous R and W to diff addr 128 LC's or 64 CLBs PhilipArticle: 11787
On Mon, 31 Aug 1998 04:11:38 GMT, mzenier@netcom.com (Mark Zenier)
wrote:
>Since what they are doing is feeding random crap into the configuration
>of a boardfull of FPGAs, and then using a scoring function to act as
>the selection, and then using the genetic algorithm to select flavors
>of the random crap that work better according to the scoring function,
>you end up with a set of bits that does unknown things in the FPGAs.
>It's not working as a digital circuit. There's no clock provided to
>the FPGA. Operation depends on circuit strays, and will only work
>in a 10 degree C temperature range.
>
>Sounds like a great way to build a phase of the moon detector. And
>scare the pants off of anybody that has to do a reliability audit.
It depends upon your genetic operators. 'Standard' operators, which
work on the genotype (bit string) without regard for its semantically
encoded phenotype ('organism', circuit, etc.) will likely do as you
describe. However, semantically aware operators (which incorporate
design rules) should produce 'good' circuits (at least, circuits which
do not violate design rules). I think this is a very promising
long-term research area, especially if general approach can be found
for translating phenotypic semantic constraints into genotypic
syntactic ones. Or am I obfuscating? ;-)
------------------------------------------------------------------------
Stuart W. Card, Chief Scientist & Vice-Pres., Critical Technologies Inc.
Suite 400 Technology Center, 4th Floor 1001 Broad Street, Utica NY 13501
315-793-0248 FAX -9710 <stu@critical.com> http://www.critical.com
Article: 11788Raymond Chiu wrote: > > Found one for about $220. Does anyone have any comments about this > model? > > > > Does anyone know of a $100 programming device? You might like to use some in-system-programmable parts, and not buy the programmer. One poster said he used a Lattice part (1016 has free dev kit) in a 44plcc package. He put a test-clip on the IC to get to the four pins needed for re-programming. In most cases the programming lead just connects to the PC printer port.Article: 11789
I think You can use PROHIBIT constraint. I havve not used it but it should work. Syntax im .ucf file: PROHIBIT=location1, location2, ... , locationn ; Good Luck Richard John Andy Peters wrote: > > gang, > > Is there an easy way to constrain the Xilinx implementation tools to > NOT use certain pins when choosing pinouts? > > I'm using an XC4005E part w/VHDL and Foundation 1.4. On my design, > one of my input pins is a reset line, connected to STARTUP and GSR. > I'm using a parallel EPROM to store my configuration. > > The place-and-route tools decided that it was a good idea to my reset > line on one of the configuration EPROM's data lines. Since the reset > input is always being driven by something, I have a problem. There > are other signals similarly assigned that I want to make sure are not > driven by the configuration process. > > Any thoughts? > > -andy > > -- > Andy Peters > Sr. Electrical Engineer > National Optical Astronomy Observatories > apeters@noao.edu.NOSPAMArticle: 11790
I've used Needham EMP (I don't recall model 10 or 20 or whatever), it worked well (on a Lattice 16v8), and the device support list included a wide variety of manufacturers and devices. - John Raymond Chiu wrote: > Found one for about $220. Does anyone have any comments about this > model? > > http://www.needhams.com/emp10.htm > > Raymond Chiu wrote: > > > I am receiving excellent responses: THANKS. > > > > Does anyone know of a $100 programming device?Article: 11791
Q: Lets say I were going to use a Xilinx Spartan XCS40 in a design.
That would probably mean I would use the XC17S40 SPROM.
How would you keep anyone who want to from cloning your design?
I don't see any mention of security in the Xilinx pages. How do you
load your FPGA without exposing your loadable image to hardware
hackers?
TIA
Eric
Article: 11792I've got an EMP20 that I've been pretty happy with. It uses personality modules to set up the connections for various PLDs. The module is nothing more than a printed circuit card (no components) about the same size as a SIMM. It comes with three that cover common PROMs and PLDs (22V10s are covered). I had to buy a module for something at one point (either a PIC processor or an Atmel serial EEPROM). The module prices are kind of steep, but the flexibility can't be found at a better price. You may also need a device adapter, as the programmer has a dip socket. The adapters can be purchased from emulation technology for most any package. John L. Smith wrote: > I've used Needham EMP (I don't recall model 10 or 20 or whatever), > it worked well (on a Lattice 16v8), and the device support > list included a wide variety of manufacturers and devices. > - John > -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 11793
Hello !
Where can find (Zilog)Z80 simulation Modle ?
Thank you.
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Article: 11794Sorry, I don't have the exact information anymore, because I'm working at another place now. On the data-io web-pages I found the last version for the chipwriter (it doesn'd look like a chiplab): The version mentioned there is recent, so maybe you need that one.... ---> Version 3.037 Released: 02-JUL-98 (from www.data-io.com)Article: 11795
> Sorry, I don't have the exact information anymore, because I'm working at > another place now. > > On the data-io web-pages I found the last version for the chipwriter (it > doesn'd look like a chiplab): > The version mentioned there is recent, so maybe you need that one.... > > ---> Version 3.037 Released: 02-JUL-98 > > (from www.data-io.com) The guy at Data-IO support told last week that they had no solution yet :-( Ans I have already downloaded the latest update. Thanks Nicolas MATRINGE DotCom SA Conception électronique 16 rue du Moulin des Bruyères Tel: 00 33 1 46 67 51 00 92400 COURBEVOIE Fax: 00 33 1 46 67 51 01 mail reply : remove one dot from the address (guess which :-)Article: 11796
In article <35EF011E.FF110D31@secsm.org>, YongKook Kim <likepunk@secsm.org> writes:
>> I'd like to implement a fast I/O pin configuration on
>>ALTERA's Flex10k20RC208-3
>> but I couldn't assign that logic option on it.
>> I choosed 'Assign -> Logic option -> Node Name-> Individual
>>logic option -> Fast I/O'.
>> But at the floor plan editor, and *.rpt file says that it
>>was not implemented on IOE.
>> My VHDL description is bleow. How can I make above possible?
Fast I/O refers to registered outputs, ie. implement the register driving the
output in the IOC cell of said pin.
>> library ieee;
>> use ieee.std_logic_1164.all;
>>
>> entity tri_bus is
>> port( CLK,dir: in std_logic;
>> b_inout : inout std_logic_vector(31 downto 0);
>> b_out : out std_logic_vector(31 downto 0);
>> b_in : in std_logic_vector(31 downto 0));
>> end tri_bus;
>>
>> architecture a of tri_bus is
>>
>> begin
>>
>> process(dir,b_in,b_inout)
>> begin
>>
>> if dir='0' then -- Input from Bidirectional port to Local
>>port
>> b_inout <= (others =>'Z');
>> B_OUT <= B_INOUT;
>> else -- Output Local port to Bidirectional
>>port
>> B_INOUT <=B_IN;
>> end if;
These are both combinatorial outputs and so 'Fast I/O' is irrelevant.
The tri-state function can only be instantiated in the IOC cell. You will not
have to do anything special, Maxplus2 will do it for you.
BTW. if B_OUT is to be tri-stated you'll have to assign that after the 'else'
statement as well. Also, because it has no assignment in the 'else' clause
it will be inferred as a latch. You may not want this, and latches cannot be
assigned to IOCs any way.
>>
>> end process;
>>
>> end a;
Hope this helps.
--
Regards,
Brent Hayhoe.
Nortel plc., Tel: +44 (0)1279-402937
Harlow Laboratories, London Road, Fax: +44 (0)1279-439636
Harlow, Essex, CM17 9NA, U.K. Email: hayhoe@nortel.co.uk
or: hayhoe@nortel.ca
Article: 11797
Hello, this is my first posting in these groups:
I need a VHDL or schematic model for a permutation generator of
integers.
I use the Xilinx M1 software, and I´m trying to implement a genetic
algorithm over an X4010E.
Thanks.
--
___________________________________________________
Jose Antonio Moreno Zamora
Profesor Dpto. Informatica
Universidad de Extremadura
Escuela Politecnica
Avda. Universidad, s/n. 10071-Caceres (SPAIN)
Tf/Fax: +34-27-257267 E-mail: joseanmo@unex.es
___________________________________________________
Article: 11798For a research project we want to partition an already tech-mapped circuit to 4 XC4013E devices. We are using the Alliance M1.3 software set. We figured out it should be possible to place&route the circuits and generate configuration data by running the latter two phases of the flow manager. This seems possible, but we need to supply the data in .ncd format. 1. Does anybody know how the .ncd format works? 2. Assuming I have a correct .ncd file, what other files do I need to set up in order to let flow manager do the job? Xilinx Guru's out there? pv.Article: 11799
Eric W Braeden wrote: > Q: Lets say I were going to use a Xilinx Spartan XCS40 in a design. > That would probably mean I would use the XC17S40 SPROM. > How would you keep anyone who want to from cloning your design? > I don't see any mention of security in the Xilinx pages. How do you > load your FPGA without exposing your loadable image to hardware > hackers? > > TIA > > Eric Hi Eric, There is no way to do what you ask with SRAM based FPGAs. While reverse engineering of the FPGA design is hard (at least in the Xilinx case), simple duplication of the bitstream is easy. No matter what FPGA configuration method you use the loadable image will be exposed on the part pins at startup. A simple logic analyzer is all you need to capture it. One solution to your problem could be the use of a small (and cheap) EPLD, something like Xilinx XC9536 or Vantis MACH111SP which can be protected against readback and make the FPGA design work only in the presence of this EPLD. And remember, there is no absolute copy protection scheme - all you can do is make copying hard enough to deter would be hackers. Catalin Baetoniu
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