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I happen to have dropped by http://www.despotovic.net and I couldn't believe what I saw. A complete case online with over 48 pictures, 3 police reports and more!!! Regards. P.S.- The website address is http://www.despotovic.netArticle: 11951
Rickman wrote:
> Philip Freidin wrote:
> ...snip...
> > Here are the two scenarios:
> > 1) Turn off is faster than turn on: The parasitic capacitance on the
> > the output node will hold the level till the second fet turns on.
> > There is no static current drawn on this node so there is no motivation
> > for it to change to the other level. The load is either another
> > similar mux, or the high impedance of an inverter.
> > 2) Turn off is slower than turn on: Since both paths have the same value,
> > for a short while (sub nanosecond) both sides of the mux drive the
> > output with the same value.
>
> For case 1, you will have both glitch free and contention free
> operation. But in case 2, how do you prevent contention when the two
> paths have different values?
>
> ...snip...
> > All the above information is pubicly available. With some effort, you can
> > actually find out a lot about the detailed internals of these devices,
> > because of the very large number of patents that have been filed by all
> > the FPGA companies. To see the gory details of the above, there are many
> > patents that show the detailed schematics. An example would be 5,566,123,
> > but there are many others. My favorite site for this is
>
> Public perhaps. But rather than dig through patents (which may or may
> not be implemented in a given device), it would be very nice if Xilinx
> (and others) made answers to questions like this easily available on
> their web sites. I couldn't find anything after doing a search at
> Xilinx.
here's some information from quicklogic, 1994 databook, p. 2-10:
Glitch-free switching of the multiplexer is ensured as the internal
capacitance
of the circuit maintains enough charge to hold the output in a steady
state
during input transitions.
rk
Article: 11952On Sun, 20 Sep 1998 17:09:24 -0700, "Joel Kolstad" <Joel.Kolstad@USA.Net> wrote: >Instead of using the wide edge decoders, one could use CLBs. Since each CLB >has two four input LUTs, each CLB one could do 4 bits worth of a comparison >(...against some register's compare value that a microcontroller could write >to). Multiple CLBs outputs could then be ANDed together in another CLB to >generate the match output. So by my calculations, a 32 bit configurable >compare would require 9 CLBs. quick thought: the micro writes the compare data stream into a fifo. this gives you maximum density on the compare data. when you get a new word into your device, just pop one word out of the fifo, and compare it against your new input data - ie. you only need one comparator. this is much more efficient for long compares. the edge decoders probably wont give you a speed advantage, since you still have to do something with your compare answer once you've got it (and spartan doesn't have edge decoders anyway). evanArticle: 11953
Has Xilinx released an M1.5 developement system? I am on maitainance, and have not received anything. Tim Olmstead email : timolmst@cyberramp.net Visit the unofficial CP/M web site. MAIN SITE AT : http://cdl.uta.edu/cpm MIRROR AT : http://www.mathcs.emory.edu/~cfs/cpm EUROPEAN MIRROR AT : http://cws86.kyamk.fi/mirrors/cpm/Article: 11954
rk wrote, quoting from QuickLogic's data:
>
>Glitch-free switching of the multiplexer is ensured as the internal
>capacitance of the circuit maintains enough charge to hold the output
>in a steady state during input transitions.
Quicklogic's transparent latch macros make use of this property.
I have always taken it as implying that the mux is based on
pass-transistors so that Philip Freidin's analysis (earlier in this
thread) applies. Certainly it works just fine.
However, QuickLogic has only 2:1 muxes - much easier to be sure
you know what's going on in something that straightforward
than in a 5-input LUT!
Funny how QuickLogic gets so little exposure in this NG - in
many ways it's a very attractive architecture, and nowadays they
have reasonable densities - just that everyone loathes one-time
programmability, I suppose.
Jonathan Bromley
--
-----------------------------------------------------------------
Electronics is fun. If you want me to take it seriously,
call and we'll talk consultancy rates.
^^^^^^^^^^^^^^^^^
I got my knuckles rapped in another NG for this .sig, even though
I thought its frivolous intent was obvious. No advertising
is intended or implied.
-----------------------------------------------------------------
Article: 11955Rickman <spamgoeshere4@yahoo.com> writes: > Public perhaps. But rather than dig through patents (which may or may > not be implemented in a given device), it would be very nice if Xilinx > (and others) made answers to questions like this easily available on > their web sites. I couldn't find anything after doing a search at > Xilinx. The online help with Altera's Maxplus2 states the conditions under which changing inputs won't generate glitches. Somewhere in the section on avoiding glitches. It's pretty similar the the descriptions we've had here for Xilinx. I like the Altera online help. -- JamieArticle: 11956
Alexander Sherstuk <Sherstuk@amsd.com> wrote: > Please, take into account, that you can not just send a byte to RS-232 COM > port to load it into configuration. Indeed. I think what I want is an asynchronous to synchronous converter; it would take in the async serial line and out would come serial clock and serial data. Does such a thing exist? > An other method, which I prefer - using a small AT89C2051 microprocessor > chip, connected with RS-232 Transceiver chip (e.g. ADM203E) and > certainly, > with XILINX XC4000E chip. Indeed this is the other possibility. Hamish -- Hamish Moffatt, StudIEAust hamish@debian.org, hamish@moffatt.nu Student, computer science & computer systems engineering. 4th year, RMIT. http://hamish.home.ml.org/ (PGP key here) CPOM: [******* ] 73% "Note that in C++, as in life, friendship is not transitive" -- TC++3 manualArticle: 11957
In article <36038c3e.9188527@news.dial.pipex.com>, ems@nospam.riverside-machines.com wrote: > On Fri, 18 Sep 1998 17:56:49 +0100, Jonathan Bromley > <jsebromley@brookes.ac.uk> wrote: > > >As a follow-up, I would be extremely intrigued to hear views > >from experienced designers and employers about how successfully > >the universities provide (or not!) the right skill-set in > >fresh-from-college EE graduates. > > Very good point. In the last 15 years, I don't think that I have > *ever* met an EE (or any other) graduate who would be remotely useful > as a paid engineer ... Education is meant to give you the basic and to focus on the way of thinking, not the skills that you need to be used as "a paid engineer". As you mentioned below it will come eventually. > But, while we're on the subject of what you should actually teach an > undergraduate, I've noticed that a lot of courses now involve > something along the lines of learning some VHDL, learning some tools, > and doing a design in an FPGA. This is a complete waste of time, and I have to disagree strongly. In my undergraduate time, my first chip I designed was a full custom chip using tools that don't even exist nowadays. During this design I was able to understand much more of the theory that was given to me during classes. I also experienced a problem where I had to go and learn something that was not thought in class. I learned how to search for that information. This was indeed a lesson I would never had if I would have learned the basic with pencil and paper only. Having a simple project keeps the student focused. At the end of the project you can have a positive feedback, very important for the students. If the project fails, you learn how to handle defeat. Analyzing the cause of failure can be so much enlightening, a thing that in real life you don t have the time and luxury to afford. This two aspects are not directly technical topics, but in an educational environment are paramount for developing the skills needed in life. How much of your work is strictly technical and how much does involve creating visions, projects, determining what's possible and what not, choosing the right tool, selecting the right technology, view challenges, recognize obstacles. You can say that all of this comes with experience, but I am believe this is what you need and what a teacher has to teach. > is rather like teaching an author to use a typewriter - the skill > isn't in how you type, but what you type. I don't need a graduate who > knows how to drive Foundation/Max Plus/whatever - the tools will be > completely different in a couple of years. When I came to my first company I was seated in front of a CAD system of Mentor. I never have seen Mentor before. But thanks to my undergraduate project in half an hour I was able to start designing. What's the lesson here: I learned how to use such tools way back. At work I had only to adjust to the new environment. Even that the screen was different, the commands different, the graphic different, the handling different, etc... all of the basic stuff was here. Now imagine that a student would be taught how to do this all in paper, but has never seen a CAD system. > You might as well just teach them Word for Windoze. Grin.. But beside this. There are skills that a (person) graduate needs to know, regardless of what he does. e.g. typewriting or car driving or even using the phone. > What *would* be useful, however, is a > graduate who knows how to get a clock from one end of a PCB to > another, who knows how to build a state machine (clocked or otherwise) > using only a pencil and paper, and who can do some basic design with > 7400-series logic. But, of course, you don't need to spend three years > learning this - I did most of the basics in a few weeks while doing a > Physics degree. see above. Bye > Evan Matija In chaos all things are possible. Matija Milostnik, RDHW, IskraTEL, Ljubljanska 24a, SI-4000 Kranj, Slovenia Tel: +386 64 27 2125, Fax: +386 64 221 552, Email: milostnik@iskratel.si www.IskraTEL.si: Building the world of telecommunications -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member ForumArticle: 11958
Joel Kolstad wrote: > Another engineer at work wants to build a state machine that watches for a > particular sequence of words and then trigger an output. E.g., set an > output active after receiving 0x5555,0xaaaa,0x0000,0xffff in that particular > order. The compare sequence needs to be configurable by a microcontroller > (but only as an "offline" operation on a very occasional basis). He was > thinking of using the wide address decoders around the perimeter of the > XC4000 series FPGAs to do this decoding, but they have the obvious drawback > that reprogramming the compare sequence would require completely > reprogramming the FPGA. That would be acceptable, but our understanding is > that this isn't feasible since Xilinx doesn't publish the configuration > bitstream specification due to security concerns about copied designs. > > Instead of using the wide edge decoders, one could use CLBs. Since each CLB > has two four input LUTs, each CLB one could do 4 bits worth of a comparison > (...against some register's compare value that a microcontroller could write > to). Multiple CLBs outputs could then be ANDed together in another CLB to > generate the match output. So by my calculations, a 32 bit configurable > compare would require 9 CLBs. > > My questions are: > -- Am I correct about Xilinx's policy on the bitstream? I've read that some > parts of it actually are published -- would that include the wide edge > decoder configuration bits? > -- Assuming no, is there a better way to do this than what I've proposed in > the second paragraph? > -- How much slower will the CLB approach be than the wide edge decoder > approach? Joel, 1) I believe that Xilinx has indicated that they will give you info on bitstream format (but not all) if you sign a Non Disclosure Agreement. You can consult your sales rep. 2) I think your solution is much more feasible than the wide decoders. I don't think it is very practical to auto-modify the bitstream. Now watch for the flood of people that don't agree with this. 3) The wide decoder can be used in a design cycling around 10 ns or so (of course depending on the rest of the design around it). The CLB approach can be used at similar speeds if you use appropriate pipelining (a little harder perhaps, because of the FSM feedback involved). My suggestion would be a lot like Goran Bilski's post. A 32 bit comparator can be implemented just once (9 CLB's as you say) and use a RAM to hold your match coefficients. If your pattern size is fixed, you can simplify the FSM a bit, otherwise you need to use a counter to program the number of words in the pattern. The FSM will cycle through the words in the match RAM, reseting the state or count on a non-match. When you get a match on the last word of a pattern, you have found the sequence. This will work for patterns where there are no duplicate words. However if you have a pattern of, say, "A B C A B D" Then if you fail on your match with 'D', you still need to compare to 'C' to determine if you have a new starting match rather than going back to the beginning every time. This can be a little tricky to analyze. In one of my graduate level logic classes we covered "string recognizers" which is what you have here. If you want to design for the general case and allow repeat entries in your match table, you will have to make your design a little fancier. This affects the FSM only. Your comparator in the wide decoder can still be used. Let me know if you need more info on this. -- Rick Collins redsp@XYusa.net remove the XY to email me.Article: 11959
Hello folks, We were reworking a design on a board containing an old xc3030 Xilinx chip. In the mean time the xc3030 was substituted by Xilinx with the xc3030a or xc3030l. Lucent still does the original chips. Since the old boards still have the chip of the original families we would like to compile the design using the new Merged release, but doing a xc3030 compatible bitfile. The new SW does force you to chose a new family. In the Xilinx manual it states that the A and L families can use the old bitfiles. Now my question is: Can you force the M1.4 Xilinx SW to generate a xc3000 compatible bitstream, or are you stuck with the ancient apr of the Xact fame. Bye Matija In chaos all things are possible. Matija Milostnik, RDHW, IskraTEL, Ljubljanska 24a, SI-4000 Kranj, Slovenia Tel: +386 64 27 2125, Fax: +386 64 221 552, Email: milostnik@iskratel.si www.IskraTEL.si: Building the world of telecommunications -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member ForumArticle: 11960
In article <3606A335.66B@gecm.com> paul.wheeler@gecm.com writes: >Can anyone tell me which of the xilinx tools produces a .tsi file. I can >find no reference to it in the on-line documentation. The .tsi comes from PPR in the XactStep versions of the software. While it is one of the most useful files in doing robust synchronous design, there is no equivalent in the M1 tools. The closest equivalent in M1 is trce with the "-u" and "-v" option set, but not nearly as clear or complete. PhilipArticle: 11961
Rickman wrote: > > Joel Kolstad wrote: > > Another engineer at work wants to build a state machine that watches for a > > particular sequence of words and then trigger an output. E.g., set an > > output active after receiving 0x5555,0xaaaa,0x0000,0xffff in that particular > > order. The compare sequence needs to be configurable by a microcontroller > > (but only as an "offline" operation on a very occasional basis). He was > > thinking of using the wide address decoders around the perimeter of the > > XC4000 series FPGAs to do this decoding, but they have the obvious drawback > > that reprogramming the compare sequence would require completely > > reprogramming the FPGA. That would be acceptable, but our understanding is > > that this isn't feasible since Xilinx doesn't publish the configuration > > bitstream specification due to security concerns about copied designs. > > > > Instead of using the wide edge decoders, one could use CLBs. Since each CLB > > has two four input LUTs, each CLB one could do 4 bits worth of a comparison > > (...against some register's compare value that a microcontroller could write > > to). Multiple CLBs outputs could then be ANDed together in another CLB to > > generate the match output. So by my calculations, a 32 bit configurable > > compare would require 9 CLBs. > > > > My questions are: > > -- Am I correct about Xilinx's policy on the bitstream? I've read that some > > parts of it actually are published -- would that include the wide edge > > decoder configuration bits? > > -- Assuming no, is there a better way to do this than what I've proposed in > > the second paragraph? > > -- How much slower will the CLB approach be than the wide edge decoder > > approach? > > Joel, > > 1) I believe that Xilinx has indicated that they will give you info on > bitstream format (but not all) if you sign a Non Disclosure Agreement. > You can consult your sales rep. > > 2) I think your solution is much more feasible than the wide decoders. I > don't think it is very practical to auto-modify the bitstream. Now watch > for the flood of people that don't agree with this. > > 3) The wide decoder can be used in a design cycling around 10 ns or so > (of course depending on the rest of the design around it). The CLB > approach can be used at similar speeds if you use appropriate pipelining > (a little harder perhaps, because of the FSM feedback involved). > > My suggestion would be a lot like Goran Bilski's post. A 32 bit > comparator can be implemented just once (9 CLB's as you say) and use a > RAM to hold your match coefficients. If your pattern size is fixed, you > can simplify the FSM a bit, otherwise you need to use a counter to > program the number of words in the pattern. The FSM will cycle through > the words in the match RAM, reseting the state or count on a non-match. > When you get a match on the last word of a pattern, you have found the > sequence. > > This will work for patterns where there are no duplicate words. However > if you have a pattern of, say, "A B C A B D" Then if you fail on your > match with 'D', you still need to compare to 'C' to determine if you > have a new starting match rather than going back to the beginning every > time. This can be a little tricky to analyze. > > In one of my graduate level logic classes we covered "string > recognizers" which is what you have here. If you want to design for the > general case and allow repeat entries in your match table, you will have > to make your design a little fancier. > > This affects the FSM only. Your comparator in the wide decoder can still > be used. > > Let me know if you need more info on this. > > -- > > Rick Collins > > redsp@XYusa.net > > remove the XY to email me. You could implement using the Altera 10K family. You can use one Embedded Array Block (EAB) to store the pattern. You can then either design a uP interface or just store the required data through an init file. You could then design a state machine that sequences the data and does the compare with the received stream. One can configure the EABS right from a single bit to 32 bit. Depending on your speed and resource requirement decide on one. The EABS do not consume any logic resources and this allows one to add more functionality in the device. SundarArticle: 11962
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Greetings FPGAers Can anyone tell me which of the xilinx tools produces a .tsi file. I can find no reference to it in the on-line documentation. Cheers.Article: 11964
Hello All, Does anyone know any Verilog newsgroup? Please tell me if you know. Thank You Sam KungArticle: 11965
Have you try comp.lang.verilog? sph Sam Kung wrote in message <3606A4DB.791EDFEC@cmd.com>... >Hello All, >Does anyone know any Verilog newsgroup? >Please tell me if you know. > >Thank You >Sam Kung >Article: 11966
Sam Kung wrote: > Hello All, > Does anyone know any Verilog newsgroup? > Please tell me if you know. > > Thank You > Sam Kung Yes I do know. Oh wait, did you want to know the newsgroup name? It is: comp.lang.verilog regards Jerry EnglishArticle: 11967
I was told that it is released and the Foundation was shipping ahead of the Alliance release. I think they said something about having everything shipped by the end of September, but I may be thinking of the Viewlogic release. I was also told that a major bug fix for the 1.5 release was coming out at the end of September. I'm running a pre-release copy of the final build and there are a few problems, but the new tools are a big improvement. All in all, they don't seem to have come very far since the last time I used the tools (about 10 years ago). - SteveArticle: 11968
--------------A38C901243EA3C495B39EA34 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit http://www.ejob.com/lucent3.htm --------------A38C901243EA3C495B39EA34 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> <HTML> <B><FONT FACE="Arial,Helvetica"><FONT COLOR="#3333FF"><FONT SIZE=+3><A HREF="http://www.ejob.com/lucent3.htm">http://www.ejob.com/lucent3.htm</A></FONT></FONT></FONT></B></HTML> --------------A38C901243EA3C495B39EA34--Article: 11969
On Mon, 21 Sep 1998 14:56:40 GMT, milostnik@my-dejanews.com wrote: >This was indeed a lesson I would never had if I would have learned the >basic with pencil and paper only. my point was that a student should be able to do an FSM from first principles, rather than using a synthesiser. that's why i said 'pencil and paper'. >When I came to my first company I was seated in front of a CAD system >of Mentor. I never have seen Mentor before. But thanks to my undergraduate >project in half an hour I was able to start designing. And, if you hadn't learnt some now-extinct-tool in your undergraduate project, how long would it have taken to learn to drive mentor? A few days? A week? And *what* exactly were you able to start designing in half an hour? I think you're ignoring my basic point, which was that there's no point learning a tool, if you can't design anything anyway. Some obvious examples come up in these newsgroups. I remember one case recently, in another group, where an engineer with $100K software had to ask what a negative setup time was. What sort of manager would tie up a $100K investment with an engineer who didn't know what a setup time was? Not to mention a $1M ASIC? There are numerous other examples in the groups - people who don't understand the difference between designing for synthesis and simulation, and people asking how they can code up impossible bits of hardware. So, if you're going to learn anything at all, you should start by learning how to design, preferably with discrete, well-specified logic, such as 7400-series. This should be the point at which you learn what a negative setup time is. If your course is long enough, then it may be worthwhile going on to use a specific tool. EvanArticle: 11970
Hi, I'm trying to think of an efficient implementation of an max-function that finds the largest from 16 unsigned 8-bit numbers. The input format is not specified (I decide parallel binary, serial LSB first, serial MSB first). The max-function must signal which of its inputs was the largest and the value of that input. What can I do to mimise FPGA area used and maintain a continuous flow of input data? Is there anything clever I can do? At the moment I'm thinking in terms of a tree of two-input comparators and muxes perhaps pipelined. This may be too big. Does anyone have any ideas? Thanks, John Funnell Inputs: 1. 00010011 2. 00110110 3. 00111001 4. 01001101 5. 00001001 6. 00011110 7. 00001010 8. 01001101 9. 01011010 <- largest, max-function needs to report this value and location 10. 00101011 11. 00011011 12. 00010010 13. 00010001 14. 00000011 15. 00101010 16. 00010010Article: 11971
Thanks to all for the responses to this, obviously this potential problem has been addressed by the FPGA vendors. My apologies to Xilinx and others. Mark. Mark Purcell <map@dial.pipex.com> wrote in article <3602DEA7.1C47@dial.pipex.com>... > Wade D. Peterson wrote: > > <snip> > > The biggest problems that I've run into are (a) race conditions (often > > causing 'glitches'), (b) metastability (where flip-flops cause > > glitches or oscillate after a clock edge) and (c) the guarentee of > > timing constraints (where you don't have a clock to coordinate > > activity). > <snip> > > What about SRAM based FPGAs causing glitches? For example, a classic > combinatorial feedback loop like the following: > > OUT = START > # HOLD & OUT; > > may not work due to the gates themselves being implemented using SRAM > lookup tables. The output may glitch or even fail to latch at all (to > see this think what happens when the logic latches - once latched it > should be invariant to transitions on START, but since it's an SRAM > there is a settling time when OUT will be invalid as the new 'address' > is looked up. This invalid state is fed back causing more invalid > states). Also using gray coded signals and ORing them to form glitch > free outputs can also cause problems. SRAM based FPGAs such as Xilinx > 4000 type devices should be avoided if the design contains any > combinatorial logic that is to remain glitch free (this goes for clock > domain resynchronizing too if gray coded FIFO flags are decoded and used > for resynchronization). > > Mark. >Article: 11972
We haven't received M1.5 from Xilinx yet. Seems that the local Avnet/Hamilton-Hallmark & Xilinx office had received theirs about a week or two ago.... Any inputs? Thanks, BobArticle: 11973
Is it possible to implement a 2D-FFT on a image using an ALTERA FLEX 10K ? I am digitizing a camera input and can pass the data through a FPGA. The FPGA has internal ram and also external ram available for storage. Thanks....Article: 11974
Reza Bohrani wrote: > > When synthesising the design below, I receive a warning that input pin pul > is not needed. WHY!!!! > The idea of the design is to make a pulse four clock-cycles wide. Is there a > better way of doing it? A couple of comments: 1) Try putting an explicit "else" part (see below) to state the "self-loop" in state 0 2) Why is state a signal, why not make it a local variable inside the process, that should make it obvious that this is an internal state... > Sincerely > Reza > > library ieee; > use ieee.std_logic_1164.all; > > entity pulse is > port(pul : in std_logic; > clk, reset : in std_logic; > pulse_4times : out std_logic > ); > end pulse; > > architecture rtl of pulse is > signal state : integer range 0 to 7; > begin > process(clk) > begin > if clk'event and clk = '1' then > if reset = '1' then > state <=0; > else > case state is > when 0 => if pul = '1' then > state <= 1; > end if; else what ? may be the synthesizer is thinking else state <= 1, in that case it is removing "pul" > pulse_4times <= '0'; > > when 1 to 6 => pulse_4times <= '0'; > state <= state + 1; > when 7 => pulse_4times <= '0'; > state <= 0; > end case; > end if; > end if; > end process; > end rtl; BTW, to make this more optimal (depends on what your synthesis tool does..) try to "extract" some of the outputs to BEFORE the case statement, that way they would be the "default". Ciao! -Bassam. -- ____________________________________________________________________ Bassam Tabbara 211-150 Cory Hall EECS Department U.C. Berkeley Berkeley, CA 94720 Title: EECS Ph.D. Student Group: CAD (Hardware Software Co-design) Office: Cory Hall 550-B2 Phone: (510) 643-5187 Fax: (510) 643-5052 email: tbassam@ic.eecs.berkeley.edu tbassam@computer.org www: http://www.EECS.Berkeley.EDU/~tbassam ____________________________________________________________________
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