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Threads Starting May 2002
42689: 02/05/01: John Williams: XC4000 readback woes
42766: 02/05/02: Christian Plessl: Re: XC4000 readback woes
42798: 02/05/03: John Williams: Re: XC4000 readback woes
42811: 02/05/03: Christian Plessl: Re: XC4000 readback woes
42775: 02/05/02: Steve Casselman: Re: XC4000 readback woes
42694: 02/05/01: Vernon L. Stant: Xilinx MicroBlaze, Opinion?
42841: 02/05/04: emanuel stiebler: Re: Xilinx MicroBlaze, Opinion?
42848: 02/05/04: Vernon L. Stant: Re: Xilinx MicroBlaze, Opinion?
42861: 02/05/05: jerry1111: Re: Xilinx MicroBlaze, Opinion?
42947: 02/05/08: Petter Gustad: Re: Xilinx MicroBlaze, Opinion?
42966: 02/05/08: jerry1111: Re: Xilinx MicroBlaze, Opinion?
42698: 02/05/01: Austin Franklin: Spartan outputs to 3.3V DRAMs...
42699: 02/05/01: Austin Franklin: Re: Spartan outputs to 3.3V DRAMs...
42700: 02/05/01: Austin Franklin: Re: Spartan outputs to 3.3V DRAMs...
42714: 02/05/01: Austin Lesea: Re: Spartan outputs to 3.3V DRAMs...
42719: 02/05/01: Austin Franklin: Re: Spartan outputs to 3.3V DRAMs...
42720: 02/05/01: Austin Lesea: Re: Spartan outputs to 3.3V DRAMs...
42729: 02/05/01: Austin Franklin: Re: Spartan outputs to 3.3V DRAMs...
42722: 02/05/01: Peter Alfke: Re: Spartan outputs to 3.3V DRAMs...
42701: 02/05/01: Hassan Mourad: synthesis error
42703: 02/05/01: Alan Fitch: Re: synthesis error
42734: 02/05/01: Hassan Mourad: Re: synthesis error
42752: 02/05/02: Alan Fitch: Re: synthesis error
42702: 02/05/01: gianzi: How can I test a downloaded design?
42704: 02/05/01: Børge Strand: Xilinx: delete file problem
42705: 02/05/01: Johann Glaser: Re: Xilinx: delete file problem
42706: 02/05/01: Børge Strand: Re: Xilinx: delete file problem
42707: 02/05/01: Børge Strand: Re: Xilinx: delete file problem
42746: 02/05/01: Dennis McCrohan: Re: Xilinx: delete file problem
42965: 02/05/08: Børge Strand: Re: Xilinx: delete file problem
42708: 02/05/01: Russell: JTAG programmer (ick!)
42749: 02/05/02: Russell: Re: JTAG programmer (ick!)
42755: 02/05/02: Jens Frauenschlaeger: Re: JTAG programmer (ick!)
42774: 02/05/02: Steve Casselman: Re: JTAG programmer (ick!)
42762: 02/05/02: Werner Dreher: Re: JTAG programmer (ick!)
42709: 02/05/01: Ren: Newbie--Where to start learning?
42710: 02/05/01: Tim: Re: Newbie--Where to start learning?
42715: 02/05/01: Børge Strand: Re: Newbie--Where to start learning?
42725: 02/05/01: Bill Moyer: Re: Newbie--Where to start learning?
42814: 02/05/03: Ren: Re: Newbie--Where to start learning?
42816: 02/05/03: Felix Bertram: Re: Newbie--Where to start learning?
42822: 02/05/03: Al Williams: Re: Newbie--Where to start learning?
42718: 02/05/01: emanuel stiebler: usb 2.0 on FPGAs
42750: 02/05/02: Felix Bertram: Re: usb 2.0 on FPGAs
42723: 02/05/01: Kevin Brace: Duplicating IOB FFs Without I/O Pads Being Inserted in XST
42727: 02/05/01: Tim: Re: Duplicating IOB FFs Without I/O Pads Being Inserted in XST
42733: 02/05/01: Kevin Brace: Re: Duplicating IOB FFs Without I/O Pads Being Inserted in XST
42739: 02/05/01: sweir: Re: Duplicating IOB FFs Without I/O Pads Being Inserted in XST
42802: 02/05/02: Kevin Brace: Re: Duplicating IOB FFs Without I/O Pads Being Inserted in XST
43036: 02/05/09: Kevin Brace: Re: Duplicating IOB FFs Without I/O Pads Being Inserted in XST
43039: 02/05/10: Hal Murray: Checklist for tool sets
43307: 02/05/18: Rick Filipkiewicz: Re: Duplicating IOB FFs Without I/O Pads Being Inserted in XST
43315: 02/05/18: Kevin Brace: Re: Duplicating IOB FFs Without I/O Pads Being Inserted in XST
43319: 02/05/18: Ray Andraka: Re: Duplicating IOB FFs Without I/O Pads Being Inserted in XST
43321: 02/05/18: Hal Murray: Re: Duplicating IOB FFs Without I/O Pads Being Inserted in XST
43323: 02/05/18: Kevin Brace: Re: Duplicating IOB FFs Without I/O Pads Being Inserted in XST
43332: 02/05/19: Rick Filipkiewicz: Re: Duplicating IOB FFs Without I/O Pads Being Inserted in XST
43333: 02/05/19: Kevin Brace: Re: Duplicating IOB FFs Without I/O Pads Being Inserted in XST
42803: 02/05/02: Jeff Mock: Re: Duplicating IOB FFs Without I/O Pads Being Inserted in XST
43034: 02/05/09: Kevin Brace: Re: Duplicating IOB FFs Without I/O Pads Being Inserted in XST
43076: 02/05/13: Jerzy Gbur: Re: Duplicating IOB FFs Without I/O Pads Being Inserted in XST
43180: 02/05/15: Kevin Brace: Re: Duplicating IOB FFs Without I/O Pads Being Inserted in XST
42724: 02/05/01: Philipper CHAGNY: free core DSTN LCD controller VHDL?
42732: 02/05/01: Henry: Can not get define_multicycle_path to work.
42738: 02/05/01: Ken McElvain: Re: Can not get define_multicycle_path to work.
42799: 02/05/02: Henry: Re: Can not get define_multicycle_path to work.
42743: 02/05/01: Jay: Vertex 2 IOB- unwanted flops inside
42745: 02/05/01: Kevin Brace: Re: Vertex 2 IOB- unwanted flops inside
42793: 02/05/02: Jay: Re: Vertex 2 IOB- unwanted flops inside
42800: 02/05/02: Ken McElvain: Re: Vertex 2 IOB- unwanted flops inside
42786: 02/05/02: spyng: Re: Vertex 2 IOB- unwanted flops inside
42754: 02/05/02: Mark McMahon: Xilinx Download Cable III
42757: 02/05/02: Jens Frauenschlaeger: Re: Xilinx Download Cable III
42765: 02/05/02: Tuomo Auer: Re: Xilinx Download Cable III
42776: 02/05/02: Falk Brunner: Re: Xilinx Download Cable III
42768: 02/05/02: Werner Dreher: Re: Xilinx Download Cable III
42777: 02/05/02: Greg Neff: Re: Xilinx Download Cable III
42801: 02/05/02: russell: Re: Xilinx Download Cable III
42756: 02/05/02: Aki Suihkonen: machine constraints for NIOS in gcc?
42767: 02/05/02: Prashant: Modelsim testbench problems
42769: 02/05/02: VhdlCohen: Re: Modelsim testbench problems
42788: 02/05/02: D2fabrizio: new website for TimingAnalyzer
42804: 02/05/02: Kevin Brace: How can I get rid of I/O pads from a netlist generated by XST?
42806: 02/05/03: Utku Ozcan: Re: Modelsim 5.6 problem
42810: 02/05/03: <dainis@saftehnika.com>: PDH MUX (E2,E3) and frame (E1,T1,E2 ...) based device VHDL examples
42855: 02/05/05: Xilinx FAE from Insight SANKET: Re: PDH MUX (E2,E3) and frame (E1,T1,E2 ...) based device VHDL examples
42859: 02/05/05: Falk Brunner: Re: PDH MUX (E2,E3) and frame (E1,T1,E2 ...) based device VHDL examples
42815: 02/05/03: Theron Hicks: LVPECL question?
42856: 02/05/05: Xilinx FAE from Insight SANKET: Re: LVPECL question?
42819: 02/05/03: Theron Hicks: VCCO vs. VCCINT on spartan2e
42820: 02/05/03: Theron Hicks: Re: VCCO vs. VCCINT on spartan2e
42824: 02/05/03: Manfred Kraus: DDR SDRAM controller for VIRTEX-II
42825: 02/05/03: Jeff: Hard macro with Xilinx
42827: 02/05/03: Bryan: Re: Hard macro with Xilinx
42834: 02/05/04: Tsoi Kuen Hung: Re: Hard macro with Xilinx
42886: 02/05/06: Jeff: Re: Hard macro with Xilinx
42889: 02/05/06: Russell: Re: Hard macro with Xilinx
42890: 02/05/06: Stephan Neuhold: Re: Hard macro with Xilinx
42894: 02/05/06: Tsoi Kuen Hung: Re: Hard macro with Xilinx
42829: 02/05/03: Jeff Wallace: CAN EVERYONE PLEASE READ THIS!! - FEEDBACK APPRECIATED!!
42830: 02/05/03: Jay: Xilinx 2GB limit... something has to be done
42831: 02/05/03: Jan Gray: Re: Xilinx 2GB limit... something has to be done
42833: 02/05/04: Hal Murray: Re: Xilinx 2GB limit... something has to be done
42847: 02/05/04: Jan Gray: Re: Xilinx 2GB limit... something has to be done
42832: 02/05/04: Tim: Re: Xilinx 2GB limit... something has to be done
42838: 02/05/04: <hamish@cloud.net.au>: Re: Xilinx 2GB limit... something has to be done
42849: 02/05/04: Petter Gustad: Re: Xilinx 2GB limit... something has to be done
42850: 02/05/04: Keith R. Williams: Re: Xilinx 2GB limit... something has to be done
42853: 02/05/05: Petter Gustad: Re: Xilinx 2GB limit... something has to be done
42896: 02/05/06: Austin Lesea: Re: Xilinx 2GB limit... something has to be done
42932: 02/05/07: David Hawke: Re: Xilinx 2GB limit... something has to be done
42956: 02/05/08: <hamish@cloud.net.au>: Re: Xilinx 2GB limit... something has to be done
42958: 02/05/08: Stephan Neuhold: Re: Xilinx 2GB limit... something has to be done
42835: 02/05/03: sympatico: Pointer processor
42844: 02/05/04: Falk Brunner: Re: Pointer processor
42840: 02/05/04: Martin E.: SelectRAM and DCM
42857: 02/05/05: Xilinx FAE from Insight SANKET: Re: SelectRAM and DCM
42858: 02/05/05: Falk Brunner: Re: SelectRAM and DCM
42870: 02/05/05: Martin E.: Re: SelectRAM and DCM
42871: 02/05/06: Peter Alfke: Re: SelectRAM and DCM
42869: 02/05/05: Martin E.: Re: SelectRAM and DCM
42878: 02/05/05: Xilinx FAE from Insight SANKET: Re: SelectRAM and DCM
42842: 02/05/04: Iain Waugh: Setting max skew in Xilinx software...
42843: 02/05/04: Falk Brunner: Re: Setting max skew in Xilinx software...
42846: 02/05/04: Lau, James: FPGA SOPC solution with MobileUne
42851: 02/05/04: russell: RPM binding
42852: 02/05/04: Sumeet: State Machine output assignment
42860: 02/05/05: Xilinx FAE from Insight SANKET: Re: State Machine output assignment
42862: 02/05/05: russell: Re: State Machine output assignment
42885: 02/05/06: newman: Re: State Machine output assignment
42863: 02/05/05: strong: a modelsim problem
42892: 02/05/06: Prashant: Re: a modelsim problem
43014: 02/05/09: Robert O. Taniman: Re: a modelsim problem
42866: 02/05/05: Stephen Williams: Bug in Xilinx DCM.v simulation model
42872: 02/05/06: Peter Alfke: Re: Xilinx IOBUF?
42873: 02/05/05: John Larkin: Re: Xilinx IOBUF?
42874: 02/05/06: Peter Alfke: Re: Xilinx IOBUF?
42877: 02/05/05: John Larkin: Re: Xilinx IOBUF?
42887: 02/05/06: Loi Tran: Re: Xilinx IOBUF?
42891: 02/05/06: Peter Alfke: Re: Xilinx IOBUF?
42895: 02/05/06: John Larkin: Re: Xilinx IOBUF?
42876: 02/05/05: Shane: VirtexII : Reserving IO Pins as inputs
42881: 02/05/06: Stephan Neuhold: Re: VirtexII : Reserving IO Pins as inputs
42893: 02/05/06: Stephan Klauke: Re: VirtexII : Reserving IO Pins as inputs
43011: 02/05/09: m0: Re: VirtexII : Reserving IO Pins as inputs
42882: 02/05/06: Anthony Ellis: PCI-32/Spartan II Pin Outs?
42883: 02/05/06: Stephan Neuhold: Re: PCI-32/Spartan II Pin Outs?
42899: 02/05/06: Kevin Brace: Re: PCI-32/Spartan II Pin Outs?
42900: 02/05/06: Kevin Brace: Re: PCI-32/Spartan II Pin Outs?
42884: 02/05/06: Itsaso Zuazua: SOPC solutions applications
42898: 02/05/06: sanjay parekh: virtex2: clk via clk buf to BRAM
42904: 02/05/06: Falk Brunner: Re: virtex2: clk via clk buf to BRAM
42901: 02/05/06: Nahum Barnea: clock multiplication in xilinx
42902: 02/05/06: Austin Lesea: Re: clock multiplication in xilinx
42928: 02/05/07: Falk Brunner: Re: clock multiplication in xilinx
42931: 02/05/07: Austin Lesea: Re: clock multiplication in xilinx
42934: 02/05/07: Falk Brunner: Re: clock multiplication in xilinx
42935: 02/05/07: Austin Lesea: Re: clock multiplication in xilinx
43005: 02/05/09: Philippe Robert: Re: clock multiplication in xilinx
43018: 02/05/09: Austin Lesea: Re: clock multiplication in xilinx
42903: 02/05/06: Falk Brunner: Re: clock multiplication in xilinx
42905: 02/05/06: Roger King: max 7000
42906: 02/05/06: ******: Re: max 7000
42908: 02/05/06: Roger King: Re: max 7000
42911: 02/05/07: Jim Granville: Re: max 7000
42910: 02/05/06: Alex Rast: Opinions on FPGA cores - best for a commercial project?
42912: 02/05/06: John Larkin: Re: Opinions on FPGA cores - best for a commercial project?
42914: 02/05/06: Assaf Sarfati: Re: Opinions on FPGA cores - best for a commercial project?
42917: 02/05/07: Kevin Brace: Re: Opinions on FPGA cores - best for a commercial project?
42916: 02/05/07: Kevin Brace: Re: Opinions on FPGA cores - best for a commercial project?
42918: 02/05/07: Victor Schutte: Re: Opinions on FPGA cores - best for a commercial project?
43052: 02/05/10: Alex Rast: Re: Opinions on FPGA cores - best for a commercial project?
43054: 02/05/10: Nicholas Weaver: Re: Opinions on FPGA cores - best for a commercial project?
43085: 02/05/13: Alex Rast: Re: Opinions on FPGA cores - best for a commercial project?
42938: 02/05/08: Guy Schlacter: Re: Opinions on FPGA cores - best for a commercial project?
42959: 02/05/08: Austin Lesea: Re: Opinions on FPGA cores - best for a commercial project?
42991: 02/05/09: Alex Rast: Re: Opinions on FPGA cores - best for a commercial project?
42949: 02/05/08: Petter Gustad: Re: Opinions on FPGA cores - best for a commercial project?
43009: 02/05/09: Phil Connor: Re: Opinions on FPGA cores - best for a commercial project?
43109: 02/05/14: Petter Gustad: Re: Opinions on FPGA cores - best for a commercial project?
42913: 02/05/06: Theron Hicks (Terry): LVPECL clock: which inputs?
42915: 02/05/06: Gaurav: FPGA in Storage
42919: 02/05/07: Noddy: Timing Scores
42925: 02/05/07: <hamish@cloud.net.au>: Re: Timing Scores
42930: 02/05/07: Peter Young: Re: Timing Scores
42933: 02/05/07: Jason T. Wright: Re: Timing Scores
43944: 02/06/06: Russ Panneton: Re: Timing Scores
42922: 02/05/07: Dirk =?iso-8859-1?Q?S=FCtterlin?=: Xilinx System Generator Simulation Problems
42924: 02/05/07: Roger King: OP-AMP in FPGA
42926: 02/05/07: Jonathan Bromley: Re: OP-AMP in FPGA
42987: 02/05/08: Mikeandmax: Re: OP-AMP in FPGA
43006: 02/05/09: Jonathan Bromley: Re: OP-AMP in FPGA
42927: 02/05/07: luigi funes: Re: OP-AMP in FPGA
42988: 02/05/09: Jim Granville: Re: OP-AMP in FPGA
42936: 02/05/07: Petter Gustad: RocketIO simulations, ISE 4.2iSP2 GT_SWIFT simulation
43119: 02/05/14: Brian Philofsky: Re: RocketIO simulations, ISE 4.2iSP2 GT_SWIFT simulation
43417: 02/05/21: Petter Gustad: Re: RocketIO simulations, ISE 4.2iSP2 GT_SWIFT simulation
42937: 02/05/07: barbara feledziak: Found a new interpreted language
42939: 02/05/07: Sramana Mitra: MIT Entrepreneurship Panel - EDA and Beyond: Funding and Industry Trends
42940: 02/05/08: John Williams: State machine synthesis
42942: 02/05/08: Kevin Brace: Re: State machine synthesis
43690: 02/05/29: sandeep: Re: State machine synthesis
42943: 02/05/08: sweir: Re: State machine synthesis
42945: 02/05/08: Phil Connor: Re: State machine synthesis
43001: 02/05/09: John Williams: Re: State machine synthesis
43065: 02/05/11: Robert O. Taniman: Re: State machine synthesis
43071: 02/05/13: John Williams: Re: State machine synthesis
43118: 02/05/14: Renaud Pacalet: Re: State machine synthesis
43616: 02/05/27: Phil Connor: Re: State machine synthesis
43633: 02/05/28: Phil Connor: Re: State machine synthesis
43726: 02/05/31: Robert O. Taniman: Re: State machine synthesis
42963: 02/05/08: Ralf Hildebrandt: Re: State machine synthesis
43742: 02/05/31: Mike Treseler: Re: State machine synthesis
42941: 02/05/07: Gaurav: Cellular Base stations
42944: 02/05/08: Eyal Shachrai: DDR reference design
42957: 02/05/08: Spam Hater: Re: DDR reference design
42998: 02/05/09: bob elkind: Re: DDR reference design
43000: 02/05/08: Eyal Shachrai: Re: DDR reference design
43047: 02/05/10: Spam Hater: Re: DDR reference design
42946: 02/05/08: golchehreh sohrab: unused I/O(Vref)
42948: 02/05/08: =?iso-8859-1?Q?Pawe=B3?= J. Rajda: JTAG 5V tollerance...?
42951: 02/05/08: Laurent Gauch: Re: JTAG 5V tollerance...?
42961: 02/05/08: Austin Lesea: Re: JTAG 5V tollerance...?
43004: 02/05/09: =?iso-8859-1?Q?Pawe=B3?= J. Rajda: Re: JTAG 5V tollerance...?
43017: 02/05/09: Austin Lesea: Re: JTAG 5V tollerance...?
43019: 02/05/09: Peter Alfke: Re: JTAG 5V tollerance...?
42952: 02/05/08: Falk Brunner: Re: JTAG 5V tollerance...?
43020: 02/05/09: rickman: Re: JTAG 5V tollerance...?
43021: 02/05/09: Austin Lesea: Re: JTAG 5V tollerance...?
42950: 02/05/08: Dr. Andy Nisbet: FPGA Development Boards for Xilinx Virtex II 2V6000 & HandelC Support
42953: 02/05/08: H.L: PAR warnings and errors
42955: 02/05/08: <hamish@cloud.net.au>: Re: PAR warnings and errors
43003: 02/05/09: H.L: Re: PAR warnings and errors
43048: 02/05/10: <hamish@cloud.net.au>: Re: PAR warnings and errors
42954: 02/05/08: Tullio Grassi: bug in XST ?
42970: 02/05/08: Kevin Brace: Re: bug in XST ?
43145: 02/05/14: Tullio Grassi: Re: bug in XST ?
42960: 02/05/08: gianzi: Problem when simulating post P&R, with SDF
42962: 02/05/08: michael m: Bit file format
42964: 02/05/08: sanjay parekh: trace report
42978: 02/05/08: John_H: Re: trace report
42967: 02/05/08: Børge Strand: VHDL: FIFO
42968: 02/05/08: Keith R. Williams: Re: VHDL: FIFO
42973: 02/05/08: Ray Andraka: Re: VHDL: FIFO
42971: 02/05/08: Vikram Pasham: Re: VHDL: FIFO
42977: 02/05/08: Paul Butler: Re: FIFO
42969: 02/05/08: m0: Re: "free" tools ... ?
42972: 02/05/08: Nicholas Weaver: Xilinx Design Language (xdl) documentation?
42974: 02/05/08: Theron Hicks: "easter egg" in FPGA design?
43028: 02/05/09: Ray Andraka: Re: "easter egg" in FPGA design?
43032: 02/05/10: Simon Gornall: Re: "easter egg" in FPGA design?
43037: 02/05/10: Ray Andraka: Re: "easter egg" in FPGA design?
42975: 02/05/08: Paul Smith: PCI bus software for Xilinx PCI core
42979: 02/05/08: Hal Murray: Re: PCI bus software for Xilinx PCI core
43025: 02/05/09: Kevin Brace: Re: PCI bus software for Xilinx PCI core
43026: 02/05/09: Stephen Williams: Re: PCI bus software for Xilinx PCI core
43029: 02/05/09: Steve Casselman: Re: PCI bus software for Xilinx PCI core
43049: 02/05/10: Paul Smith: Re: PCI bus software for Xilinx PCI core
43081: 02/05/13: Iwo Mergler: Re: PCI bus software for Xilinx PCI core
42976: 02/05/08: Kevin Brace: Does an EDIF schematic editor exist?
42992: 02/05/09: Russell: Re: Does an EDIF schematic editor exist?
42995: 02/05/09: Steve Casselman: Re: Does an EDIF schematic editor exist?
42980: 02/05/08: rickman: Timing of XC2S200E-6FG456C compared to XC2S200E-6FG456I
42981: 02/05/08: John_H: Re: Timing of XC2S200E-6FG456C compared to XC2S200E-6FG456I
42983: 02/05/08: Peter Alfke: Re: Timing of XC2S200E-6FG456C compared to XC2S200E-6FG456I
42982: 02/05/08: Peter Alfke: Re: Timing of XC2S200E-6FG456C compared to XC2S200E-6FG456I
42985: 02/05/08: John_H: Re: Timing of XC2S200E-6FG456C compared to XC2S200E-6FG456I
42989: 02/05/08: Peter Alfke: Re: Timing of XC2S200E-6FG456C compared to XC2S200E-6FG456I
42997: 02/05/08: rickman: Re: Timing of XC2S200E-6FG456C compared to XC2S200E-6FG456I
43016: 02/05/09: Austin Lesea: Re: Timing of XC2S200E-6FG456C compared to XC2S200E-6FG456I
42984: 02/05/08: Steve Charlwood: Transistor Counts for Xilinx FPGAs
42986: 02/05/08: Austin Lesea: Re: Transistor Counts for Xilinx FPGAs
42990: 02/05/08: Peter Alfke: Re: Transistor Counts for Xilinx FPGAs
43031: 02/05/09: glen herrmannsfeldt: Re: Transistor Counts for Xilinx FPGAs
43060: 02/05/11: B. Joshua Rosen: Re: Transistor Counts for Xilinx FPGAs
42994: 02/05/09: Tim: Re: Transistor Counts for Xilinx FPGAs
42993: 02/05/09: Russell: More C things
42996: 02/05/09: Jim Granville: Re: More C things
43033: 02/05/09: russell: Re: More C things
43040: 02/05/10: glen herrmannsfeldt: Re: More C things
42999: 02/05/08: Venu: Issue with X_SUH (using 4.1 sp 3)
43117: 02/05/14: Brian Philofsky: Re: Issue with X_SUH (using 4.1 sp 3)
43002: 02/05/08: Edzel: Eliminating Hierarchy in Xilinx XST
43023: 02/05/09: Kevin Brace: Re: Eliminating Hierarchy in Xilinx XST
43072: 02/05/12: Edzel: Re: Eliminating Hierarchy in Xilinx XST
43073: 02/05/12: Kevin Brace: Re: Eliminating Hierarchy in Xilinx XST
43075: 02/05/13: Edzel: Re: Eliminating Hierarchy in Xilinx XST
43177: 02/05/15: Kevin Brace: Re: Eliminating Hierarchy in Xilinx XST
43007: 02/05/09: satya: Reconfigurable FPGAs
43008: 02/05/09: Antonio: A special Thanks to :
43027: 02/05/09: Ray Andraka: Re: A special Thanks to :
43010: 02/05/09: Shane Mulligan: Have you designed a PCI/Ethernet Adapter using a HDL?
43013: 02/05/09: Carl Daniel: Re: Have you designed a PCI/Ethernet Adapter using a HDL?
43542: 02/05/23: Shane Mulligan: Re: Have you designed a PCI/Ethernet Adapter using a HDL?
43022: 02/05/09: Kevin Brace: Re: Have you designed a PCI/Ethernet Adapter using a HDL?
43035: 02/05/10: Phil Hays: Re: Have you designed a PCI/Ethernet Adapter using a HDL?
43046: 02/05/10: Victor Schutte: Re: Have you designed a PCI/Ethernet Adapter using a HDL?
43012: 02/05/09: m0: Re: VirtexII : Reserving IO Pins as inputs
43015: 02/05/09: H.L: Virtex -E LVDS pins' rules
43024: 02/05/09: Dan Fabrizio: Announce: TimingAnalyzer Program Update
43030: 02/05/09: Robert Binkley: Xilinx Documentation Survey
43044: 02/05/10: Luis Cupido: altera 7000's
43053: 02/05/11: Jim Granville: Re: altera 7000's
43045: 02/05/10: K PRASAD: timing violations in fpgas
43529: 02/05/22: Tullio Grassi: Re: timing violations in fpgas
43535: 02/05/23: Search for knowledge: Re: timing violations in fpgas
43051: 02/05/10: Rodney, Everard [CAR:CN31:EXCH]: Automated Amplify Flow
43055: 02/05/11: Przemyslaw Wegrzyn: Adders in Xilinx XC4000
43056: 02/05/11: David R Brooks: Re: Adders in Xilinx XC4000
43058: 02/05/11: Romans: [Xilinx] EEPROM recommendation
43080: 02/05/13: Verleye Frank: Re: [Xilinx] EEPROM recommendation
43059: 02/05/11: Maciek: dual port fifo
43061: 02/05/11: Russell: Re: dual port fifo
43062: 02/05/11: Falk Brunner: Re: dual port fifo
43063: 02/05/11: Maciek: Re: dual port fifo
43066: 02/05/11: Peter Alfke: Re: dual port fifo
43067: 02/05/12: Paul Baxter: Re: dual port fifo
43070: 02/05/12: Naohiko Shimizu: Announce:GPLed 6502 IP core
43163: 02/05/15: Micah Dowty: Re: Announce:GPLed 6502 IP core
43074: 02/05/12: MegaPowerStar: reconfigurable FPGAs
43077: 02/05/13: Kiren Tanna: JVM using FPGAs
43078: 02/05/13: Christian Plessl: Re: JVM using FPGAs
43079: 02/05/13: Theo: Virtex-II DCM Frequency Synthesis
43087: 02/05/13: Austin Lesea: Re: Virtex-II DCM Frequency Synthesis
43082: 02/05/13: Micah Dowty: Architecture for high-level reconfigurable computing
43086: 02/05/13: Neil Franklin: Re: Architecture for high-level reconfigurable computing
43130: 02/05/14: Micah Dowty: Re: Architecture for high-level reconfigurable computing
43137: 02/05/14: Nicholas Weaver: Re: Architecture for high-level reconfigurable computing
43142: 02/05/14: Neil Franklin: Re: Architecture for high-level reconfigurable computing
43144: 02/05/14: Micah Dowty: Re: Architecture for high-level reconfigurable computing
43175: 02/05/15: Neil Franklin: Re: Architecture for high-level reconfigurable computing
43088: 02/05/14: Jim Granville: Re: Architecture for high-level reconfigurable computing
43089: 02/05/14: John Williams: Re: Architecture for high-level reconfigurable computing
43097: 02/05/14: Tim: Re: Architecture for high-level reconfigurable computing
43090: 02/05/13: Steve Casselman: Re: Architecture for high-level reconfigurable computing
43106: 02/05/14: Phil Hays: Re: Architecture for high-level reconfigurable computing
43107: 02/05/14: Buddy Smith: Re: Architecture for high-level reconfigurable computing
43110: 02/05/14: Johann Glaser: Re: Architecture for high-level reconfigurable computing
43108: 02/05/14: news.bellatlantic.net: Re: Architecture for high-level reconfigurable computing
43134: 02/05/14: Steve Casselman: Re: Architecture for high-level reconfigurable computing
43150: 02/05/14: Tim: Re: Architecture for high-level reconfigurable computing
43179: 02/05/15: glen herrmannsfeldt: Re: Architecture for high-level reconfigurable computing
43211: 02/05/16: Bryan: Re: Architecture for high-level reconfigurable computing
43140: 02/05/14: Micah Dowty: Re: Architecture for high-level reconfigurable computing
43091: 02/05/14: John Williams: Re: Architecture for high-level reconfigurable computing
43092: 02/05/13: Peter Alfke: Re: Architecture for high-level reconfigurable computing
43094: 02/05/13: Nicholas Weaver: Re: Architecture for high-level reconfigurable computing
43096: 02/05/13: Nicholas Weaver: Re: Architecture for high-level reconfigurable computing
43098: 02/05/14: Tim: Re: Architecture for high-level reconfigurable computing
43100: 02/05/14: Jim Granville: Re: Architecture for high-level reconfigurable computing
43103: 02/05/14: Peter Alfke: Re: Architecture for high-level reconfigurable computing
43113: 02/05/14: Keith R. Williams: Re: Architecture for high-level reconfigurable computing
43125: 02/05/14: Peter Alfke: Re: Architecture for high-level reconfigurable computing
43128: 02/05/14: Keith R. Williams: Re: Architecture for high-level reconfigurable computing
43132: 02/05/14: Peter Alfke: Re: Architecture for high-level reconfigurable computing
43141: 02/05/14: Keith R. Williams: Re: Architecture for high-level reconfigurable computing
43162: 02/05/15: Eric Smith: Life Support (was Re: Architecture for high-level reconfigurable computing)
43139: 02/05/14: Nicholas Weaver: Re: Architecture for high-level reconfigurable computing
43159: 02/05/14: Keith R. Williams: Re: Architecture for high-level reconfigurable computing
43147: 02/05/15: Jim Granville: Re: Architecture for high-level reconfigurable computing
43148: 02/05/14: Austin Lesea: Re: Architecture for high-level reconfigurable computing
43154: 02/05/15: Jim Granville: Re: Architecture for high-level reconfigurable computing
43167: 02/05/15: Austin Lesea: Re: Architecture for high-level reconfigurable computing
43187: 02/05/16: Jim Granville: Re: Architecture for high-level reconfigurable computing
43193: 02/05/15: Keith R. Williams: Re: Architecture for high-level reconfigurable computing
43229: 02/05/16: Keith R. Williams: Re: Architecture for high-level reconfigurable computing
43247: 02/05/17: Tim: Re: Architecture for high-level reconfigurable computing
43258: 02/05/17: Peter Alfke: Re: Architecture for high-level reconfigurable computing
43264: 02/05/17: Tim: Re: Architecture for high-level reconfigurable computing
43248: 02/05/17: Hal Murray: Re: Architecture for high-level reconfigurable computing
43104: 02/05/14: Nicholas Weaver: Re: Architecture for high-level reconfigurable computing
43112: 02/05/14: Rick Filipkiewicz: Re: Architecture for high-level reconfigurable computing
43157: 02/05/15: <samg@codenet.net>: Re: Architecture for high-level reconfigurable computing
43168: 02/05/15: Austin Lesea: Re: Architecture for high-level reconfigurable computing
43171: 02/05/15: Rick Filipkiewicz: Re: Architecture for high-level reconfigurable computing
43174: 02/05/15: Austin Lesea: Re: Architecture for high-level reconfigurable computing
43207: 02/05/16: Austin Lesea: Got to get those decimals in the right place on the slide rule .....
43135: 02/05/14: Steve Casselman: Re: Architecture for high-level reconfigurable computing
43158: 02/05/15: <samg@codenet.net>: Re: Architecture for high-level reconfigurable computing
43138: 02/05/14: Neil Franklin: Re: Architecture for high-level reconfigurable computing
43095: 02/05/14: John Williams: Re: Architecture for high-level reconfigurable computing
43373: 02/05/20: m0: Re: Architecture for high-level reconfigurable computing
43474: 02/05/22: Micah Dowty: Re: Architecture for high-level reconfigurable computing
43083: 02/05/13: Sean: Neverending ISA bus interface drama, Spartan-II
43084: 02/05/13: Peter Alfke: Re: Neverending ISA bus interface drama, Spartan-II
43099: 02/05/14: Rick Filipkiewicz: Re: Neverending ISA bus interface drama, Spartan-II
43102: 02/05/14: Ray Andraka: Re: Neverending ISA bus interface drama, Spartan-II
43105: 02/05/14: Peter Alfke: Re: Neverending ISA bus interface drama, Spartan-II
43116: 02/05/14: Sean: Re: Neverending ISA bus interface drama, Spartan-II
43129: 02/05/14: Rick Filipkiewicz: Re: Neverending ISA bus interface drama, Spartan-II
43131: 02/05/14: Iwo Mergler: Re: Neverending ISA bus interface drama, Spartan-II
43093: 02/05/13: Trampus Richmond: New Nios Developer Community Started
43101: 02/05/13: emanuel stiebler: 50 mA sink
43121: 02/05/14: John_H: Re: 50 mA sink
43124: 02/05/14: Peter Alfke: Re: 50 mA sink
43225: 02/05/16: Jay: Re: 50 mA sink
43111: 02/05/14: jetmarc: Bus arbiter with low latency
43153: 02/05/14: Jay: Re: Bus arbiter with low latency
43114: 02/05/14: Johan Eriksson Thelin: LGPL 32bits RISC CPU Core
43115: 02/05/14: Bert Wibble: Driving high speed external devices from an FPGA
43120: 02/05/14: Mike Treseler: Re: Driving high speed external devices from an FPGA
43123: 02/05/14: Hal Murray: Re: Driving high speed external devices from an FPGA
43126: 02/05/14: Peter Alfke: Re: Driving high speed external devices from an FPGA
43152: 02/05/14: Jay: Re: Driving high speed external devices from an FPGA
43303: 02/05/18: Adrian: Re: Driving high speed external devices from an FPGA
43363: 02/05/20: Bert Wibble: Re: Driving high speed external devices from an FPGA
43369: 02/05/20: Austin Lesea: Re: Driving high speed external devices from an FPGA
43411: 02/05/21: Bert Wibble: Re: Driving high speed external devices from an FPGA
43451: 02/05/21: Noddy: Re: Driving high speed external devices from an FPGA
43455: 02/05/21: Austin Lesea: Re: Driving high speed external devices from an FPGA
43456: 02/05/21: Falk Brunner: Re: Driving high speed external devices from an FPGA
43122: 02/05/14: Marcus Bednara: Virtex2 placement problem
43275: 02/05/17: Martin: Re: Virtex2 placement problem
43749: 02/06/01: MikeJ: Re: Virtex2 placement problem
43127: 02/05/14: Hal Murray: Anyody else get spam about "FPGA Video Seminar"?
43318: 02/05/18: Kevin Brace: Re: Anyody else get spam about "FPGA Video Seminar"?
43355: 02/05/20: m0: Re: Anyody else get spam about "FPGA Video Seminar"?
43133: 02/05/14: Ted Bronson: Altera/Quartus II: unconditional loop?
43136: 02/05/14: Mike Treseler: Re: Altera/Quartus II: unconditional loop?
43143: 02/05/14: Dines Justesen: Re: Altera/Quartus II: unconditional loop?
43155: 02/05/14: Ted Bronson: Re: Altera/Quartus II: unconditional loop?
43156: 02/05/14: Mike Treseler: Re: Altera/Quartus II: unconditional loop?
43170: 02/05/15: Kevin Neilson: Re: Altera/Quartus II: unconditional loop?
43182: 02/05/15: Kevin Neilson: Re: Altera/Quartus II: unconditional loop?
43183: 02/05/15: Tim: Re: Altera/Quartus II: unconditional loop?
43185: 02/05/15: Dines Justesen: Re: Altera/Quartus II: unconditional loop?
43188: 02/05/15: Davis Moore: Re: Altera/Quartus II: unconditional loop?
43146: 02/05/14: Tullio Grassi: verilof parameter and XST
43366: 02/05/20: Steven Elzinga: Re: verilof parameter and XST
43149: 02/05/14: C.W. THomas: Please help me figure out serial prom problem
43164: 02/05/15: Utku Ozcan: Re: Please help me figure out serial prom problem
43151: 02/05/14: William L Hunter Jr: Heat Sink/Fan for XC2V3000-4BF957
44419: 02/06/19: Patrick: Re: Heat Sink/Fan for XC2V3000-4BF957
43165: 02/05/15: Nagaraj: Processor interface to memory mapped FPGA
43166: 02/05/15: Laurent Gauch: Re: Processor interface to memory mapped FPGA
43172: 02/05/15: Mauricio Lange: PCI Board Project
43173: 02/05/15: Micah Dowty: Re: PCI Board Project
43176: 02/05/15: Falk Brunner: Re: PCI Board Project
43292: 02/05/18: Josep Duran: Re: PCI Board Project
43181: 02/05/15: Kevin Brace: Re: PCI Board Project
43189: 02/05/15: Austin Franklin: Re: PCI Board Project
43205: 02/05/16: Mauricio Lange: Re: PCI Board Project
43217: 02/05/16: Falk Brunner: Re: PCI Board Project
43272: 02/05/17: Kevin Brace: Re: PCI Board Project
43342: 02/05/19: Austin Franklin: Re: PCI Board Project
43344: 02/05/19: Kevin Brace: Re: PCI Board Project
43445: 02/05/21: Austin Franklin: Re: PCI Board Project
43449: 02/05/21: Kevin Brace: Re: PCI Board Project
43238: 02/05/17: Hal Murray: Re: PCI Board Project
43239: 02/05/17: Stephan Neuhold: Re: PCI Board Project
43259: 02/05/17: Austin Franklin: Re: PCI Board Project
43261: 02/05/17: Stephan Neuhold: Re: PCI Board Project
43276: 02/05/17: Austin Franklin: Re: PCI Board Project
43178: 02/05/15: Brad: xilinx foundation 2.1 RPC problem on win2000
43196: 02/05/16: sweir: Re: xilinx foundation 2.1 RPC problem on win2000
43294: 02/05/18: Lorenzo Lutti: Re: xilinx foundation 2.1 RPC problem on win2000
43184: 02/05/15: the Geez: Re: Exemplar in ISE
43190: 02/05/15: Kamal Patel: Re: Exemplar in ISE
43186: 02/05/15: Loi Tran: WEBPack 4.1 - vhdl modules in schematics?
43192: 02/05/15: Kamal Patel: Re: WEBPack 4.1 - vhdl modules in schematics?
43194: 02/05/16: vandam: PCMCIA interface Logic Between PCMCIA LAN Card and ARM CPU....
43197: 02/05/16: Joze Dedic: Re: PCMCIA interface Logic Between PCMCIA LAN Card and ARM CPU....
43195: 02/05/15: Theron Hicks (Terry): output rise and fall time for Spartan2E??
43209: 02/05/16: Austin Lesea: Re: output rise and fall time for Spartan2E, but don't talk about IBIS??
43222: 02/05/16: Theron Hicks (Terry): Re: output rise and fall time for Spartan2E, but don't talk about IBIS??
43224: 02/05/16: Austin Lesea: Re: output rise and fall time for Spartan2E, but don't talk about IBIS??
43226: 02/05/16: Theron Hicks (Terry): Re: output rise and fall time for Spartan2E, but don't talk about IBIS??
43198: 02/05/16: Dany: XAPP173 BUG
43199: 02/05/16: Joze Dedic: SPARTAN II - Master serial mode configuration problem
43202: 02/05/16: C.W. THomas: Re: SPARTAN II - Master serial mode configuration problem
43219: 02/05/16: jakab tanko: Re: SPARTAN II - Master serial mode configuration problem
43214: 02/05/16: Thorsten Trenz: Re: SPARTAN II - Master serial mode configuration problem
43200: 02/05/16: H.L: Virtex-E interconnection
43203: 02/05/16: Ray Andraka: Re: Virtex-E interconnection
43208: 02/05/16: H.L: Re: Virtex-E interconnection
43201: 02/05/16: Matjaz Finc: Nios 32bit - simulation problem
43390: 02/05/20: Alan Calac: Re: Nios 32bit - simulation problem
43204: 02/05/16: Wim Peeters: extend jtag downloadcable
43210: 02/05/16: Luis Cupido: Re: extend jtag downloadcable
43230: 02/05/17: Leo Havmøller: Re: extend jtag downloadcable
43466: 02/05/21: Endric Schubert: Re: extend jtag downloadcable
43628: 02/05/28: Wim Peeters: Re: extend jtag downloadcable
43670: 02/05/29: Noddy: Re: extend jtag downloadcable
43206: 02/05/16: Philippe Robert: XC95108+XC4036EX
43212: 02/05/16: Joze Dedic: Re: Bidirectional DONE?
43213: 02/05/16: Austin Lesea: Re: Bidirectional DONE?
43310: 02/05/18: cfk: Re: Bidirectional DONE?
43317: 02/05/18: Hal Murray: Re: Bidirectional DONE?
43215: 02/05/16: Jan Ziak: What properties has FPGA?
43244: 02/05/17: Jan Ziak: Re: What properties has FPGA?
43246: 02/05/17: Hal Murray: Re: What properties has FPGA?
43461: 02/05/21: Jan Ziak: Re: What properties has FPGA?
43463: 02/05/22: Jim Granville: Re: What properties has FPGA?
43464: 02/05/21: Peter Alfke: Re: What properties has FPGA?
43469: 02/05/21: John_H: Re: What properties has FPGA?
43482: 02/05/22: Jan Ziak: Re: What properties has FPGA?
43484: 02/05/22: Jim Granville: Re: What properties has FPGA?
44164: 02/06/12: Paul: Re: What properties has FPGA?
43254: 02/05/17: John_H: Re: What properties has FPGA?
43257: 02/05/17: Peter Alfke: Re: What properties has FPGA?
43270: 02/05/17: Ray Andraka: Re: What properties has FPGA?
43218: 02/05/16: Don Teeter: Articles on FPGA-based design validation / verification?
43220: 02/05/16: Traveler: Need Help on FPGA and Spiking Neurons
43227: 02/05/16: rickman: Re: Need Help on FPGA and Spiking Neurons
43268: 02/05/17: Ray Andraka: Re: Need Help on FPGA and Spiking Neurons
43279: 02/05/17: Traveler: Re: Need Help on FPGA and Spiking Neurons
43296: 02/05/18: Ray Andraka: Re: Need Help on FPGA and Spiking Neurons
43322: 02/05/18: Traveler: Re: Need Help on FPGA and Spiking Neurons
43327: 02/05/18: rickman: Re: Need Help on FPGA and Spiking Neurons
43335: 02/05/19: Simon Gornall: Re: Need Help on FPGA and Spiking Neurons
43381: 02/05/20: Traveler: Re: Need Help on FPGA and Spiking Neurons
43389: 02/05/20: rickman: Re: Need Help on FPGA and Spiking Neurons
43441: 02/05/21: Traveler: Re: Need Help on FPGA and Spiking Neurons
43314: 02/05/18: Micah Dowty: Re: Need Help on FPGA and Spiking Neurons
43223: 02/05/17: Douglas Miller: Timing constraints on internal signals
43245: 02/05/17: Jerzy Gbur: Re: Timing constraints on internal signals
43228: 02/05/16: Frank: Circuit design for Altera ACEX development board
43325: 02/05/19: Matt van de Werken: Re: Circuit design for Altera ACEX development board
43231: 02/05/16: Jeff Mock: Spartan2 on a Compact Flash card
43241: 02/05/17: Laurent Gauch: Re: Spartan2 on a Compact Flash card
43392: 02/05/20: rickman: Re: Spartan2 on a Compact Flash card
43394: 02/05/21: Jim Granville: Re: Spartan2 on a Compact Flash card
43232: 02/05/16: Mauricio Lange: PCI target with FPGA question
43237: 02/05/17: Stephan Neuhold: Re: PCI target with FPGA question
43260: 02/05/17: Austin Franklin: Re: PCI target with FPGA question
43273: 02/05/17: Kevin Brace: Re: PCI target with FPGA question
43233: 02/05/17: Patrik Eriksson: Accessing TAP registers from within the FPGA (VirtexII)
43234: 02/05/17: Phil Hays: HardPath
43252: 02/05/17: Austin Lesea: Re: HardPath
43299: 02/05/18: Phil Hays: Re: HardPath
43301: 02/05/18: Nicholas Weaver: Re: HardPath
43311: 02/05/18: Phil Hays: Re: HardPath
43320: 02/05/19: Jim Granville: Re: HardPath
43345: 02/05/20: Phil Hays: Re: HardPath
43358: 02/05/20: Austin Lesea: Re: HardPath
43477: 02/05/22: Phil Hays: Re: HardPath
43499: 02/05/22: Austin Lesea: Re: Testing Philosophy
43298: 02/05/18: John Larkin: Re: HardPath
43235: 02/05/17: jfh: LOCKED signal of a DLL in a Virtex device questions
43253: 02/05/17: Austin Lesea: Re: LOCKED signal of a DLL in a Virtex device questions
43236: 02/05/16: Anjan: interfacing dspand fpga
43240: 02/05/17: Allan Herriman: Re: Reading GSR signal of Spartan-II
43242: 02/05/17: Roman MORAWEK: Problem with Xilinx ISE 4.2i map
43256: 02/05/17: Kamal Patel: Re: Problem with Xilinx ISE 4.2i map
43249: 02/05/17: sweir: Re: Reading GSR signal of Spartan-II
43284: 02/05/17: Theron Hicks (Terry): Re: Reading GSR signal of Spartan-II
43337: 02/05/19: Ray Andraka: Re: Reading GSR signal of Spartan-II
43349: 02/05/20: Allan Herriman: Re: Reading GSR signal of Spartan-II
43399: 02/05/21: Ray Andraka: Re: Reading GSR signal of Spartan-II
43250: 02/05/17: Russell: RPMs
43267: 02/05/17: Ray Andraka: Re: RPMs
43283: 02/05/17: russell: Re: RPMs
43297: 02/05/18: Ray Andraka: Re: RPMs
43331: 02/05/19: russell: Re: RPMs
43336: 02/05/19: Ray Andraka: Re: RPMs
43341: 02/05/20: Russell: Re: RPMs
43343: 02/05/19: russell: Re: RPMs
43424: 02/05/21: <hamish@cloud.net.au>: Re: RPMs
43251: 02/05/17: Greg: Spartan II Proto. Board
43377: 02/05/20: engr: Re: Spartan II Proto. Board
43910: 02/06/06: Dan: Re: Spartan II Proto. Board
43950: 02/06/07: Spam Hater: Re: Spartan II Proto. Board
43262: 02/05/17: rickman: SDRAM pricing
43269: 02/05/17: Matt H: Re: SDRAM pricing
43274: 02/05/17: rickman: Re: SDRAM pricing
43280: 02/05/17: <amolitor-at@visi-dot-com.com>: Re: SDRAM pricing
43281: 02/05/17: Jerry Avins: Re: SDRAM pricing
43282: 02/05/18: <amolitor-at@visi-dot-com.com>: Re: SDRAM pricing
43328: 02/05/18: rickman: Re: SDRAM pricing
43330: 02/05/19: <amolitor-at@visi-dot-com.com>: Re: SDRAM pricing
43338: 02/05/19: rickman: Re: SDRAM pricing
43339: 02/05/19: Rick Filipkiewicz: Re: SDRAM pricing
43288: 02/05/17: Herman Oosthuysen: Re: SDRAM pricing
43329: 02/05/18: rickman: Re: SDRAM pricing
43370: 02/05/20: John_H: Re: SDRAM pricing
43423: 02/05/21: Jim Thomas: Re: SDRAM pricing
43425: 02/05/21: Rick Filipkiewicz: Re: SDRAM pricing
43553: 02/05/23: rickman: Re: SDRAM pricing
43263: 02/05/17: <shparekh@yahoo.com>: virtex 2 block rams
43265: 02/05/17: Falk Brunner: Re: virtex 2 block rams
43266: 02/05/17: Peter Alfke: Re: virtex 2 block rams
43277: 02/05/17: Rick Filipkiewicz: Re: virtex 2 block rams
43286: 02/05/17: <shparekh@yahoo.com>: Re: virtex 2 block rams
43289: 02/05/18: Hal Murray: Re: virtex 2 block rams
43291: 02/05/18: Rick Filipkiewicz: Re: virtex 2 block rams
43300: 02/05/18: <shparekh@yahoo.com>: Re: virtex 2 block rams
43302: 02/05/18: Hal Murray: Re: virtex 2 block rams
43304: 02/05/18: Rick Filipkiewicz: Re: virtex 2 block rams
43271: 02/05/17: Ray Andraka: Re: virtex 2 block rams
43368: 02/05/20: John_H: Re: virtex 2 block rams
43278: 02/05/17: Scott Schlachter: Re: Reading GSR signal of Spartan-II
43470: 02/05/21: Brian Philofsky: Re: Reading GSR signal of Spartan-II
43285: 02/05/18: Len Chisholm: Building a relaxation oscillator with a Xilinx 9536XL
43287: 02/05/18: Jim Granville: Re: Building a relaxation oscillator with a Xilinx 9536XL
43589: 02/05/24: Frank Wirtz: Re: Building a relaxation oscillator with a Xilinx 9536XL
43290: 02/05/18: Falk Brunner: P&R times
43473: 02/05/22: Phil Hays: Re: P&R times
43531: 02/05/23: Phil Hays: Re: P&R times
43538: 02/05/23: <hamish@cloud.net.au>: Re: P&R times
43603: 02/05/26: Jay: Re: P&R times
43635: 02/05/28: Ray Andraka: Re: P&R times
43293: 02/05/18: Allan Herriman: Re: Reading GSR signal of Spartan-II
43295: 02/05/18: Theron Hicks (Terry): Re: Reading GSR signal of Spartan-II
43305: 02/05/18: Adrian: Signal Fan-out
43312: 02/05/18: Peter Alfke: Re: Signal Fan-out
43450: 02/05/21: Noddy: Re: Signal Fan-out
43306: 02/05/18: cfk: button & 3 LED's
43316: 02/05/18: Ray Andraka: Re: button & 3 LED's
43334: 02/05/19: Rick Filipkiewicz: Re: button & 3 LED's
43365: 02/05/20: John_H: Re: button & 3 LED's
43398: 02/05/21: Ray Andraka: Re: button & 3 LED's
43438: 02/05/21: Peter Alfke: Re: button & 3 LED's
43442: 02/05/21: John_H: Re: button & 3 LED's
43448: 02/05/21: Ray Andraka: Re: button & 3 LED's
43308: 02/05/18: Songqing Zhang: Xilinx 4000XLA-8: is 4 stages of logic ok?
43309: 02/05/18: Songqing Zhang: Re: Xilinx 4000XLA-8: is 4 stages of logic ok?
43354: 02/05/20: ae: Re: Xilinx 4000XLA-8: is 4 stages of logic ok?
43384: 02/05/20: Peter Alfke: Re: Xilinx 4000XLA-8: is 4 stages of logic ok?
43386: 02/05/20: Songqing Zhang: Re: Xilinx 4000XLA-8: is 4 stages of logic ok?
43515: 02/05/22: ae: Re: Xilinx 4000XLA-8: is 4 stages of logic ok?
43324: 02/05/19: Kevin Neilson: Slice Usage Per Module
43346: 02/05/20: Utku Ozcan: Re: Slice Usage Per Module
43340: 02/05/19: Pete Dudley: Rounding Accumulator
43396: 02/05/21: Ray Andraka: Re: Rounding Accumulator
43680: 02/05/29: Steve Casselman: Re: Rounding Accumulator
43347: 02/05/20: Kelvin XCJ: Difference between Altera and Xilinx.
43348: 02/05/20: stefaan vanheesbeke: Re: Difference between Altera and Xilinx.
43397: 02/05/21: Ray Andraka: Re: Difference between Altera and Xilinx.
43514: 02/05/22: Arash Salarian: Re: Difference between Altera and Xilinx.
43350: 02/05/20: Rick Filipkiewicz: Disti web sites
43371: 02/05/20: russell: Re: Disti web sites
43391: 02/05/20: rickman: Re: Disti web sites
43351: 02/05/20: Richard B. Katz: 2002 MAPLD: Registration Open, Call for Papers, and Announcements
43352: 02/05/20: Alex Clapperton: Foundation 1.5
43353: 02/05/20: Jake: Upgrade to ISE4.1/4.2 ?
43356: 02/05/20: Kamal Patel: Re: Upgrade to ISE4.1/4.2 ?
43817: 02/06/03: Brian: Re: Upgrade to ISE4.1/4.2 ?
43357: 02/05/20: Derren Crome: Using Impact with XCR5064 coolrunner?
43383: 02/05/21: Jim Granville: Re: Using Impact with XCR5064 coolrunner?
43385: 02/05/20: Neil Glenn Jacobson: Re: Using Impact with XCR5064 coolrunner?
43433: 02/05/21: Arthur: Re: Using Impact with XCR5064 coolrunner?
43462: 02/05/22: tim simpson: Re: Using Impact with XCR5064 coolrunner?
43359: 02/05/20: Marcel: How to generate fractional-N clock ?
43360: 02/05/20: Austin Lesea: Re: How to generate fractional-N clock ?
43361: 02/05/20: Marcel: Re: How to generate fractional-N clock ?
43367: 02/05/20: Austin Lesea: Re: How to generate fractional-N clock ?
43372: 02/05/20: John_H: Re: How to generate fractional-N clock ?
43400: 02/05/21: Allan Herriman: Re: How to generate fractional-N clock ?
43362: 02/05/20: John_H: Re: How to generate fractional-N clock ?
43374: 02/05/20: John_H: Re: How to generate fractional-N clock ?
43380: 02/05/20: Jeff Mock: Re: How to generate fractional-N clock ?
43402: 02/05/21: Allan Herriman: Re: How to generate fractional-N clock ?
43420: 02/05/21: Marc Randolph: Re: How to generate fractional-N clock ?
43544: 02/05/23: John_H: Re: How to generate fractional-N clock ?
43562: 02/05/24: Allan Herriman: Re: How to generate fractional-N clock ?
43563: 02/05/24: Brian Drummond: Re: How to generate fractional-N clock ?
43364: 02/05/20: Jonny: Request: PCI to ISA Firewire and USB2.0 Advice Please
43376: 02/05/20: Eyal Shachrai: virtex II : CLB with two clocks
43378: 02/05/20: John_H: Re: virtex II : CLB with two clocks
43379: 02/05/20: stefaan vanheesbeke: fpga cpu
43407: 02/05/21: Victor Schutte: Re: fpga cpu
43408: 02/05/21: Jim Granville: Re: fpga cpu
43447: 02/05/21: Janusz Raniszewski: Re: fpga cpu
43776: 02/06/02: rickman: Re: fpga cpu
43791: 02/06/03: jerry1111: Re: fpga cpu
43813: 02/06/03: rickman: Re: fpga cpu
43840: 02/06/04: jerry1111: Re: fpga cpu
43801: 02/06/03: stefaan vanheesbeke: Re: fpga cpu
43841: 02/06/04: jerry1111: Re: fpga cpu
43850: 02/06/04: Rick Filipkiewicz: Re: fpga cpu
43851: 02/06/04: jerry1111: Re: fpga cpu
43989: 02/06/08: Janusz Raniszewski: Re: fpga cpu
43485: 02/05/22: Matthias Dyer: Re: fpga cpu
43503: 02/05/22: Jan Gray: Re: fpga cpu
43530: 02/05/22: Greg Comeau: Re: fpga cpu
43382: 02/05/20: Tom Hawkins: Synchronous Single Clock Designs
43393: 02/05/20: rickman: Re: Synchronous Single Clock Designs
43415: 02/05/21: =?ISO-8859-1?Q?L=E4hteenm=E4ki?= Jussi: Re: Synchronous Single Clock Designs
43426: 02/05/21: Peter Alfke: Re: Synchronous Single Clock Designs
43427: 02/05/21: Austin Lesea: Re: Synchronous Single Clock Designs
43435: 02/05/21: Rick Filipkiewicz: Re: Synchronous Single Clock Designs
43437: 02/05/21: John_H: Re: Synchronous Single Clock Designs
43439: 02/05/21: Austin Lesea: Re: Synchronous Single Clock Designs
43436: 02/05/21: Softley, C.: Re: Synchronous Single Clock Designs
43458: 02/05/21: Kai Harrekilde-Petersen: Re: Synchronous Single Clock Designs
43475: 02/05/22: Hal Murray: Re: Synchronous Single Clock Designs
43432: 02/05/21: Rick Filipkiewicz: Re: Synchronous Single Clock Designs
43595: 02/05/25: Fabio G.: Re: Synchronous Single Clock Designs
43619: 02/05/27: gosensgo@goober_lumictech.com: Re: Synchronous Single Clock Designs
43428: 02/05/21: Tom Hawkins: Re: Synchronous Single Clock Designs
43454: 02/05/21: Austin Franklin: Re: Synchronous Single Clock Designs
43479: 02/05/22: =?ISO-8859-1?Q?L=E4hteenm=E4ki?= Jussi: Re: Synchronous Single Clock Designs
43387: 02/05/20: Prashant: Power Consumption scaling factor
43388: 02/05/20: Austin Lesea: Re: Power Consumption scaling factor
43395: 02/05/20: Andy McDaniel: Any suggestions?
43401: 02/05/21: John Williams: Addressable shift register
43403: 02/05/21: Nicholas Weaver: Re: Addressable shift register
43404: 02/05/21: John Williams: Re: Addressable shift register
43405: 02/05/21: Peter Alfke: Re: Addressable shift register
43406: 02/05/21: John Williams: Re: Addressable shift register
43660: 02/05/28: Jim Hwang: Re: Addressable shift register
43663: 02/05/29: John Williams: Re: Addressable shift register
43664: 02/05/29: sweir: Re: Addressable shift register
43667: 02/05/29: Russell: Re: Addressable shift register
43668: 02/05/29: John Williams: Re: Addressable shift register
43681: 02/05/29: Mike Treseler: Re: Addressable shift register
43409: 02/05/21: James Zaiter: i need help getting started with fpgas
43419: 02/05/21: Russell: Re: i need help getting started with fpgas
43483: 02/05/22: Rick Filipkiewicz: Re: i need help getting started with fpgas
43488: 02/05/22: Laurent Gauch: Re: i need help getting started with fpgas
43492: 02/05/22: Al Williams: Re: i need help getting started with fpgas
43511: 02/05/22: Ray Andraka: Re: i need help getting started with fpgas
43410: 02/05/21: Jerzy Gbur: Off topic - a little
43412: 02/05/21: Joerg Schneide: Xilinx WP test vectors in Jedec file
43434: 02/05/21: Arthur: Re: Xilinx WP test vectors in Jedec file
43457: 02/05/21: Joerg Schneide: Re: Xilinx WP test vectors in Jedec file
43413: 02/05/21: Peter: Altera FPGA (EPM7256AETC100-5) programming
43510: 02/05/22: Ben Twijnstra: Re: Altera FPGA (EPM7256AETC100-5) programming
43414: 02/05/21: Felix Bertram: Ann: Spartan-IIE development board
43416: 02/05/21: Geiger Hope: military/industrial FPGA device suggestion request
43418: 02/05/21: me: Configuration Blues
43421: 02/05/21: Evgeny Shamin: RS232 a utility for debugging serial data transfers between devices.
43422: 02/05/21: Cyrille de Brébisson: Shift register or state machine
43430: 02/05/21: Falk Brunner: Re: Shift register or state machine
43431: 02/05/21: John_H: Re: Shift register or state machine
43443: 02/05/21: Peter Alfke: Re: Shift register or state machine
43429: 02/05/21: Eyal Shachrai: virtex II : DCM phases
43440: 02/05/21: Austin Lesea: Re: virtex II : DCM phases
43444: 02/05/21: Christopher Saunter: 5V differential -> Virtex 2
43446: 02/05/21: Austin Lesea: Re: 5V differential -> Virtex 2
43452: 02/05/21: Rick Filipkiewicz: Re: 5V differential -> Virtex 2
43453: 02/05/21: Austin Lesea: Re: 5V differential -> Virtex 2
43536: 02/05/23: Christopher Saunter: Re: 5V differential -> Virtex 2
43459: 02/05/21: Kevin Brace: XST since ISE 4.x can actually generate an EDIF netlist!!!
43460: 02/05/21: Rick Filipkiewicz: Re: XST since ISE 4.x can actually generate an EDIF netlist!!!
43465: 02/05/21: Kevin Brace: Re: XST since ISE 4.x can actually generate an EDIF netlist!!!
43468: 02/05/21: Rick Filipkiewicz: Re: XST since ISE 4.x can actually generate an EDIF netlist!!!
43471: 02/05/21: Kevin Brace: Re: XST since ISE 4.x can actually generate an EDIF netlist!!!
43467: 02/05/22: Jim Granville: Re: XST since ISE 4.x can actually generate an EDIF netlist!!!
43679: 02/05/29: Michael Rhotert: Re: XST since ISE 4.x can actually generate an EDIF netlist!!!
43899: 02/06/05: Falk Brunner: Re: XST since ISE 4.x can actually generate an EDIF netlist!!!
43939: 02/06/06: Michael Rhotert: Re: XST since ISE 4.x can actually generate an EDIF netlist!!!
43938: 02/06/06: Michael Rhotert: Re: XST since ISE 4.x can actually generate an EDIF netlist!!!
43472: 02/05/22: Przemyslaw Wegrzyn: Aldec Active-HDL 5.1 + Xilinx ISE 4.1 - how to simulate ?
43490: 02/05/22: Paul Baxter: Re: Aldec Active-HDL 5.1 + Xilinx ISE 4.1 - how to simulate ?
43506: 02/05/22: Przemyslaw Wegrzyn: Re: Aldec Active-HDL 5.1 + Xilinx ISE 4.1 - how to simulate ?
43508: 02/05/22: Ray Andraka: Re: Aldec Active-HDL 5.1 + Xilinx ISE 4.1 - how to simulate ?
43522: 02/05/22: Przemyslaw Wegrzyn: Re: Aldec Active-HDL 5.1 + Xilinx ISE 4.1 - how to simulate ?
43476: 02/05/22: Kevin Neilson: Cross Probing in Xilinx Floorplanner Quirky
43478: 02/05/22: Mitchell Crago: Xilinx Serial IO Data rates
43487: 02/05/22: Laurent Gauch: Re: Xilinx Serial IO Data rates
43500: 02/05/22: Austin Lesea: Re: Xilinx Serial IO Data rates
43480: 02/05/22: Mitchell Crago: Xilinx configuration times
43481: 02/05/22: Mitchell Crago: Re: Xilinx configuration times
43504: 02/05/22: Austin Lesea: Re: Xilinx configuration times
43516: 02/05/22: Peter Alfke: Re: Xilinx configuration times
43486: 02/05/22: Steffen Thieringer: 50Mhz driven - Overheat by Program?
43495: 02/05/22: Ray Andraka: Re: 50Mhz driven - Overheat by Program?
43512: 02/05/22: Nicholas Weaver: Re: 50Mhz driven - Overheat by Program?
43520: 02/05/22: Tim: Re: 50Mhz driven - Overheat by Program?
43489: 02/05/22: Angus Thompson: Routing in a 6200-like sea of gates
43518: 02/05/22: Peter Alfke: Re: Routing in a 6200-like sea of gates
43521: 02/05/22: Nicholas Weaver: Re: Routing in a 6200-like sea of gates
43524: 02/05/22: Neil Franklin: Re: Routing in a 6200-like sea of gates
43491: 02/05/22: Grégory HERMANT: xc2v-6000 FF1152 orcad symbol ???
43532: 02/05/22: Assaf Sarfati: Re: xc2v-6000 FF1152 orcad symbol ???
43533: 02/05/23: Hal Murray: Re: xc2v-6000 FF1152 orcad symbol ???
43493: 02/05/22: ChristopheGuelff: We need people with good knowledge about FPGA
43494: 02/05/22: Ray Andraka: Time for a new computer. Suggestions?
43498: 02/05/22: Paul Baxter: Re: Time for a new computer. Suggestions?
43502: 02/05/22: Johann Glaser: Re: Time for a new computer. Suggestions?
43507: 02/05/22: Ray Andraka: Re: Time for a new computer. Suggestions?
43540: 02/05/23: <hamish@cloud.net.au>: Re: Time for a new computer. Suggestions?
43550: 02/05/23: Ray Andraka: Re: Time for a new computer. Suggestions?
43552: 02/05/23: Tim: Re: Time for a new computer. Suggestions?
43555: 02/05/23: Nicholas Weaver: Re: Time for a new computer. Suggestions?
43557: 02/05/24: Ray Andraka: Re: Time for a new computer. Suggestions?
43558: 02/05/24: Nicholas Weaver: Re: Time for a new computer. Suggestions?
43561: 02/05/24: Klaus-Guenter Leiss: Re: Time for a new computer. Suggestions?
43560: 02/05/24: Hal Murray: Re: Time for a new computer. Suggestions?
43583: 02/05/24: rickman: Re: Time for a new computer. Suggestions?
43585: 02/05/24: Nicholas Weaver: Re: Time for a new computer. Suggestions?
43587: 02/05/24: Ray Andraka: Re: Time for a new computer. Suggestions?
43712: 02/05/30: Nicholas Weaver: Re: Time for a new computer. Suggestions?
43745: 02/05/31: Ray Andraka: Re: Time for a new computer. Suggestions?
43775: 02/06/02: rickman: Re: Time for a new computer. Suggestions?
43594: 02/05/25: Ulf Samuelsson: Re: Time for a new computer. Suggestions?
43505: 02/05/22: Ulf Samuelsson: Re: Time for a new computer. Suggestions?
43513: 02/05/22: Nicholas Weaver: Re: Time for a new computer. Suggestions?
43599: 02/05/25: Duane Clark: Re: Time for a new computer. Suggestions?
43496: 02/05/22: svhb: inverse engeneering on XC3020.
43509: 02/05/22: Ray Andraka: Re: inverse engeneering on XC3020.
43497: 02/05/22: Jerre: stability/timing problem on reset
43752: 02/06/01: MikeJ: Re: stability/timing problem on reset
43501: 02/05/22: Noddy: PROM programming
43517: 02/05/22: Kevin Neilson: Virtex2 Carry Chains Slow? (Tciny)
43519: 02/05/22: Kevin Neilson: Re: Virtex2 Carry Chains Slow? (Tciny)
43523: 02/05/22: Przemyslaw Wegrzyn: Xilinx STARTUP and PADS problems
43582: 02/05/24: Steven Elzinga: Re: Xilinx STARTUP and PADS problems
43525: 02/05/22: Kevin Neilson: Inferring BlockROMs
43526: 02/05/22: Kevin Neilson: Re: Inferring BlockROMs
43527: 02/05/22: Steven Elzinga: Re: Inferring BlockROMs
43528: 02/05/22: akandel: Free emulator
43534: 02/05/23: H.L: Xilinx chip scope: Comments
43556: 02/05/24: Rick Filipkiewicz: Re: Xilinx chip scope: Comments
43592: 02/05/25: H.L: Re: Xilinx chip scope: Comments
43602: 02/05/26: Jay: Re: Xilinx chip scope: Comments
43669: 02/05/29: H.L: Re: Xilinx chip scope: Comments
43763: 02/06/01: H.L: chipscope: Tips to get more speed
43537: 02/05/23: Eyal Shachrai: virtex II : FDDRRSE instantiation
43543: 02/05/23: Steven Elzinga: Re: virtex II : FDDRRSE instantiation
43539: 02/05/23: Salman Sheikh: Altera 10K30A240C-1
43621: 02/05/27: Tuomo Auer: Re: Altera 10K30A240C-1
43541: 02/05/23: Joe: Xact Design Editor 5.1 or later needed!
43545: 02/05/23: Jeff: Xilinx proprietary format?
43547: 02/05/23: Kevin Neilson: Re: Xilinx proprietary format?
43683: 02/05/29: Steve Casselman: Re: Xilinx proprietary format?
43685: 02/05/29: Nicholas Weaver: Re: Xilinx proprietary format?
43546: 02/05/23: Kevin Neilson: Re: FPGA, VHDL : RAM initialization
43548: 02/05/23: Mike Treseler: Re: FPGA, VHDL : RAM initialization
43549: 02/05/23: Ray Andraka: Re: FPGA, VHDL : RAM initialization
43551: 02/05/23: noman: FPGA and VHDL: question about RAM initialization
43566: 02/05/24: Jacky Renaux: Re: FPGA and VHDL: question about RAM initialization
43567: 02/05/24: Jacky Renaux: Re: FPGA and VHDL: question about RAM initialization
43568: 02/05/24: gianzi: Re: FPGA and VHDL: question about RAM initialization
43574: 02/05/24: Ray Andraka: Re: FPGA and VHDL: question about RAM initialization
43554: 02/05/24: John Williams: XC4000 series pin compatability
43605: 02/05/27: Andreas Wassatsch: Re: XC4000 series pin compatability
43559: 02/05/23: Frank Scherler: JTAG ICE or programmer
43581: 02/05/24: Laurent Gauch: Re: JTAG ICE or programmer
43682: 02/05/29: Steve Casselman: Re: JTAG ICE or programmer
43564: 02/05/24: Utku Ozcan: Re: Small FIFOs in Spartan
43577: 02/05/24: John_H: Re: Small FIFOs in Spartan
43565: 02/05/24: Philippe Robert: SDRAM controler for Virtex-II
43569: 02/05/24: Laurent Gauch: Re: SDRAM controler for Virtex-II
43578: 02/05/24: Laurent Gauch: Re: SDRAM controler for Virtex-II
43596: 02/05/25: Spam Hater: Re: SDRAM controler for Virtex-II
43597: 02/05/25: Antonio Pasini: Re: SDRAM controler for Virtex-II
43570: 02/05/24: Manfred Muecke: SOPC for machine vision
43571: 02/05/24: Laurent Gauch: Re: SOPC for machine vision
43572: 02/05/24: Manfred Muecke: Re: SOPC for machine vision
43604: 02/05/27: Victor Schutte: Re: SOPC for machine vision
43608: 02/05/27: Manfred Muecke: Re: SOPC for machine vision
43639: 02/05/28: Ray Andraka: Re: SOPC for machine vision
43575: 02/05/24: Falk Brunner: Re: Small FIFOs in Spartan
43576: 02/05/24: kjhales: Targeting Virtex with WebPack
43579: 02/05/24: m0: Re: FPGA, VHDL : RAM initialization
43610: 02/05/27: Martin: Re: FPGA, VHDL : RAM initialization
43666: 02/05/29: Patrik Eriksson: Re: FPGA, VHDL : RAM initialization
43580: 02/05/24: D Brown: Xilinx Pull Ups/Dpwns
43584: 02/05/24: gosensgo@goober_lumictech.com: Re: Xilinx Pull Ups/Dpwns
43586: 02/05/24: George Un-Spam Schmitt: Xilinx "Real PCI-X" core capabilities
43588: 02/05/24: rickman: IO simulations
43638: 02/05/28: Austin Lesea: Re: IO simulations
43727: 02/05/31: rickman: Re: IO simulations
43732: 02/05/31: Austin Lesea: Re: IO simulations
43741: 02/05/31: Steve Casselman: Re: IO simulations
43744: 02/05/31: Austin Lesea: Re: IO simulations
43748: 02/05/31: Steve Casselman: Re: IO simulations
43756: 02/06/01: Russell: Re: IO simulations
43591: 02/05/25: Geiger Hope: evaluation boards for virtex
43606: 02/05/27: Felix Bertram: Re: evaluation boards for virtex
43593: 02/05/25: Ulf Samuelsson: Re: Small FIFOs in Spartan
43613: 02/05/27: Børge Strand: Re: Small FIFOs in Spartan
43620: 02/05/27: Falk Brunner: Re: Small FIFOs in Spartan
43871: 02/06/04: Ray Andraka: Re: Small FIFOs in Spartan
43792: 02/06/03: Ulf Samuelsson: Re: Small FIFOs in Spartan
43598: 02/05/25: Neil Steiner: Documentation on XDL reports?
43600: 02/05/26: Kevin Brace: How can I create an encrypted netlist for Altera?
43609: 02/05/27: Rene Tschaggelar: Re: How can I create an encrypted netlist for Altera?
43623: 02/05/27: Petter Gustad: Re: How can I create an encrypted netlist for Altera?
43627: 02/05/28: Kevin Brace: Re: How can I create an encrypted netlist for Altera?
43695: 02/05/29: Joe: Re: How can I create an encrypted netlist for Altera?
43877: 02/06/05: Kevin Brace: Re: How can I create an encrypted netlist for Altera?
43601: 02/05/26: Dan Fabrizio: automatically generate timing diagrams
43607: 02/05/26: Nahum Barnea: footprint competabilty in virtex-II devices
43624: 02/05/27: Marc Randolph: Re: footprint competabilty in virtex-II devices
43611: 02/05/27: Muthu: Why there is no clear signal in BRAM?
43617: 02/05/27: Muzaffer Kal: Re: Why there is no clear signal in BRAM?
43753: 02/06/01: MikeJ: Re: Why there is no clear signal in BRAM?
43612: 02/05/27: Georg Heinrich: ALtera SOPC Builder
43615: 02/05/27: Prager Roman: Re: ALtera SOPC Builder
43688: 02/05/29: Fabio G.: Re: ALtera SOPC Builder
43721: 02/05/31: Prager Roman: Re: ALtera SOPC Builder
43777: 02/06/02: Fabio G.: Re: ALtera SOPC Builder
43814: 02/06/03: Jesse Kempa: Re: ALtera SOPC Builder
43880: 02/06/05: Prager Roman: Re: ALtera SOPC Builder
44152: 02/06/12: Noel Klonsky: Re: ALtera SOPC Builder
43614: 02/05/27: Dan Fabrizio: request for vcd and Symphony 1.5 lst files
43618: 02/05/27: Utku Ozcan: Re: static vs gate-level timing analysis
43622: 02/05/27: Hanks Lee: XC95288 Programming
43631: 02/05/28: Laurent Gauch: Re: XC95288 Programming
43625: 02/05/28: John Williams: avoiding resynthesis
43637: 02/05/28: Ray Andraka: Re: avoiding resynthesis
43657: 02/05/29: John Williams: Re: avoiding resynthesis
43626: 02/05/27: Kannan G: Re: DIP4 error in Payload Contro Word in SPI4, phase2 frame.
43629: 02/05/28: Ken Mac: Do I have metastability issues?
43733: 02/05/31: John_H: Re: Do I have metastability issues?
43878: 02/06/05: Ken Mac: Re: Do I have metastability issues?
43893: 02/06/05: John_H: Re: Do I have metastability issues?
43915: 02/06/06: Ken Mac: Re: Do I have metastability issues?
43929: 02/06/06: John_H: Re: Do I have metastability issues?
43953: 02/06/07: Ken Mac: Re: Do I have metastability issues?
43902: 02/06/05: Jay: Re: Do I have metastability issues?
43918: 02/06/06: Ray Andraka: Re: Do I have metastability issues?
43975: 02/06/07: Rick Filipkiewicz: Re: Do I have metastability issues?
43982: 02/06/07: John_H: Re: Do I have metastability issues?
43984: 02/06/07: Austin Lesea: Re: Do I have metastability issues?
43985: 02/06/07: John_H: Re: Do I have metastability issues?
43987: 02/06/07: Austin Lesea: Re: Do I have metastability issues?
43988: 02/06/08: John_H: Re: Do I have metastability issues?
43986: 02/06/07: Rick Filipkiewicz: Re: Do I have metastability issues?
43992: 02/06/08: Ray Andraka: Re: Do I have metastability issues?
43995: 02/06/08: Hal Murray: Re: Do I have metastability issues?
44010: 02/06/09: Ray Andraka: Re: Do I have metastability issues?
43630: 02/05/28: haiyan: xc2v-6000 BF957 orcad symbol !!!!!
43632: 02/05/28: yin wang: Strange error message from MaxPlus II !
43640: 02/05/28: Martin Thompson: Re: Strange error message from MaxPlus II !
43636: 02/05/28: Ray Andraka: Re: XACT - Xilinx design editor for a 2018 design desperately needed ...
43641: 02/05/28: ae: Timing Analyzer lockups
43645: 02/05/28: Kevin Neilson: Re: Timing Analyzer lockups
43656: 02/05/29: Utku Ozcan: Re: Timing Analyzer lockups
43764: 02/06/01: <hamish@cloud.net.au>: Re: Timing Analyzer lockups
43644: 02/05/29: samlin: How to add delay in fpga(spartan)?
43743: 02/05/31: Falk Brunner: Re: How to add delay in fpga(spartan)?
43747: 02/05/31: to ja: Re: How to add delay in fpga(spartan)?
43937: 02/06/06: Jay: Re: How to add delay in fpga(spartan)?
43648: 02/05/28: H.L: Virtex CLKDLLHF output
43649: 02/05/28: ae: Daisy Chain synchronization option
43671: 02/05/29: Philippe Robert: LOC constraint
43672: 02/05/29: Daniel =?ISO-8859-1?Q?Han=27czewski?=: Xilinx Foundation schematic multi-sheet problem.
43686: 02/05/29: Caleb Hess: Re: Xilinx Foundation schematic multi-sheet problem.
43674: 02/05/29: Gerard: Re: XACT - Xilinx design editor for a 2018 design desperately needed ...
43675: 02/05/29: Nagaraj: place and route simulation time
43677: 02/05/29: Utku Ozcan: Re: place and route simulation time
43694: 02/05/29: Jeff Mock: Re: place and route simulation time
43702: 02/05/30: Kim Enkovaara: Re: place and route simulation time
43714: 02/05/30: Duane Clark: Re: place and route simulation time
43692: 02/05/29: newman: Re: place and route simulation time
43710: 02/05/30: Falk Brunner: Re: place and route simulation time
43718: 02/05/30: William Wallace: Re: place and route simulation time
43737: 02/05/31: Falk Brunner: Re: place and route simulation time
43765: 02/06/01: Allan Herriman: Re: place and route simulation time
43766: 02/06/01: Nicholas Weaver: Re: place and route simulation time
43774: 02/06/02: Allan Herriman: Re: place and route simulation time
43783: 02/06/03: Ray Andraka: Re: place and route simulation time
43797: 02/06/03: Allan Herriman: Re: place and route simulation time
43815: 02/06/03: Ken Morrow: Re: place and route simulation time
43861: 02/06/04: Falk Brunner: Re: place and route simulation time
43872: 02/06/04: Ray Andraka: Re: place and route simulation time
43873: 02/06/05: Allan Herriman: Re: place and route simulation time
43684: 02/05/29: <s>: DCM partial reconfiguration
43691: 02/05/29: Austin Lesea: Re: DCM partial reconfiguration
43687: 02/05/29: Eyal Shachrai: virtex 2 : DCM divided clock
43698: 02/05/29: Marc Randolph: Re: virtex 2 : DCM divided clock
43703: 02/05/30: Austin Lesea: Re: virtex 2 : DCM divided clock
43696: 02/05/29: Chris Lewis: Director of FPGA Design - New York City
43757: 02/05/31: Austin Franklin: Re: Director of FPGA Design - New York City
43697: 02/05/29: wuqiang: about Configure FLEX10K10 with 89c51
43707: 02/05/30: Falk Brunner: Re: about Configure FLEX10K10 with 89c51
43730: 02/05/31: wuqiang: Re: about Configure FLEX10K10 with 89c51
43713: 02/05/30: Jay: Re: about Configure FLEX10K10 with 89c51
43729: 02/05/31: wuqiang: Re: about Configure FLEX10K10 with 89c51
43699: 02/05/29: Rajat Karol: Engineering Samples for free?
43716: 02/05/30: Speedy Zero Two: Re: Engineering Samples for free?
43717: 02/05/30: William Wallace: Re: Engineering Samples for free?
43724: 02/05/31: Hal Murray: Re: Engineering Samples for free?
43740: 02/05/31: Leon Heller: Re: Engineering Samples for free?
43750: 02/06/01: Nicholas Weaver: Re: Engineering Samples for free?
43751: 02/06/01: MikeJ: Re: Engineering Samples for free?
43700: 02/05/30: Ulises Hernandez: Can we edit an RBT Configuration file for a Xilinx FPGA?
43701: 02/05/30: Philip Freidin: Re: Can we edit an RBT Configuration file for a Xilinx FPGA?
43852: 02/06/04: Ulises Hernandez: Re: Can we edit an RBT Configuration file for a Xilinx FPGA?
43711: 02/05/30: Steve Casselman: Re: Can we edit an RBT Configuration file for a Xilinx FPGA?
43715: 02/05/30: Darren Gnanapragasam: VIRTEX-E XCV405E Orcad schematic required
43890: 02/06/05: m0: Re: VIRTEX-E XCV405E Orcad schematic required
43719: 02/05/30: Rich LeGrand: Atmel and IDS 7.5
43722: 02/05/31: Russell: Re: Nets in multiple schematics?
43725: 02/05/31: Nicolas Matringe: Lattice .ldf to VHDL help
43728: 02/05/31: jetmarc: LFSR with 2^n instead of (2^n)-1
43731: 02/05/31: Dilip V. Sarwate: Re: LFSR with 2^n instead of (2^n)-1
43738: 02/05/31: John Savard: Re: LFSR with 2^n instead of (2^n)-1
43736: 02/05/31: Falk Brunner: Re: LFSR with 2^n instead of (2^n)-1
43739: 02/05/31: John_H: Re: LFSR with 2^n instead of (2^n)-1
43755: 02/05/31: jetmarc: Re: LFSR with 2^n instead of (2^n)-1
43758: 02/05/31: John_H: Re: LFSR with 2^n instead of (2^n)-1
43746: 02/05/31: newman: Re: LFSR with 2^n instead of (2^n)-1
43754: 02/06/01: David R Brooks: Re: LFSR with 2^n instead of (2^n)-1
43760: 02/06/01: Rick Filipkiewicz: Re: LFSR with 2^n instead of (2^n)-1
43734: 02/05/31: Kamal Patel: Re: Nets in multiple schematics?
43759: 02/05/31: lktan: communication between two RC100
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