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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Threads Starting Jun 1997
6536: 97/06/01: Djimm2: In circuit programming of flash --->JTAG?
6539: 97/06/02: David R Brooks: Re: In circuit programming of flash --->JTAG?
6557: 97/06/02: Djimm2: Re: In circuit programming of flash --->JTAG?
6541: 97/06/02: bob elkind: NT4 and EECAD applications, and SP3
6542: 97/06/02: Rune Bĉverrud: Dear all Altera CPLD designers!
6568: 97/06/03: Pelican: test
6572: 97/06/03: Eric Fleischman: ECL FPGA Demo at DAC
6586: 97/06/04: Tim Forcer: Re: ECL FPGA Demo at DAC
6573: 97/06/03: Eric Fleischman: New High-Speed FPGA - Demo at DAC
6575: 97/06/03: Scott A. Hauck: FPGA'98 Call For Papers
6576: 97/06/03: Alexandru Seibulescu: Best value for Verilog Simulation!
6577: 97/06/03: Jackie Meyer: Memory workshop, San Jose
6583: 97/06/04: Mark Johnson: Re: Memory workshop, San Jose
6594: 97/06/04: Del Cecchi: Re: Memory workshop, San Jose
6579: 97/06/03: Jinan Lou: Your recommendation needed
6581: 97/06/03: Dr. Endric Schubert: Re: Your recommendation needed
6612: 97/06/05: Christopher Puff: Re: Your recommendation needed
6580: 97/06/04: <rajesh@comit.com>: Alternate Verilog FAQ : New release
6595: 97/06/04: Ram Prabhakar: Re: Alternate Verilog FAQ : New release
6587: 97/06/04: <elvis@dcs.rhbnc.ac.uk>: Ripp10 Board
6588: 97/06/04: Barry Rising: RIPP10 Board: Correct EMAIL Address
6589: 97/06/04: David G. Stork: Summer Student Job
6590: 97/06/04: John Cooley: + Last Year's (1996) DAC Trip Report +
6591: 97/06/04: Cyril Muller: XILINX CONFIGUTATION CRCs
6592: 97/06/04: Philip Freidin: Re: XILINX CONFIGUTATION CRCs
6593: 97/06/04: Adam J. Elbirt: The Advanced FPGA Design Demonstration at DAC
6603: 97/06/04: Dr. Endric Schubert: Re: The Advanced FPGA Design Demonstration at DAC
6597: 97/06/04: Ivan Hamer: PCI how to
6634: 97/06/07: Austin Franklin: Re: PCI how to
6635: 97/06/07: Steve Casselman: Re: PCI how to
6636: 97/06/08: Austin Franklin: Re: PCI how to
6649: 97/06/09: Steve Casselman: Re: PCI how to
6643: 97/06/09: Gareth Baron: Re: PCI how to
6644: 97/06/09: Georg Acher: Re: PCI how to
6645: 97/06/09: Mike Kelly: Re: PCI how to
6664: 97/06/11: Austin Franklin: Re: PCI how to
6669: 97/06/11: Carlos Stahr: Re: PCI how to
6601: 97/06/04: Karl Kristianson: FS: CADKEY '97 -100+ Available- Save $HUNDRED's EACH!!!
6605: 97/06/05: Jan Muska: NEED YOUR HELP - IN RETURN COULD WIN FREE ANTI-VIRUS SOFTWARE
6608: 97/06/05: Linda Boyd: Qualis Verilog Training
6609: 97/06/05: Linda Boyd: Qualis VHDL Training
6610: 97/06/05: <asklfdlsjd@>: Send thousands of Posting to the Newsgroups at once with Mailloop
6618: 97/06/05: robert bible: Don't Design With Altera Parts... Altera Obsolete Parts
6641: 97/06/08: William E. Lenihan III: Re: Don't Design With Altera Parts... Altera Obsolete Parts
6690: 97/06/14: Steven Knapp: Re: Don't Design With Altera Parts... Altera Obsolete Parts
6691: 97/06/15: John McDougall: Re: Don't Design With Altera Parts... Altera Obsolete Parts
6681: 97/06/13: Ray Bowden: Re: Don't Design With Altera Parts... Altera Obsolete Parts
6685: 97/06/13: Ray Andraka: Re: Don't Design With Altera Parts... Altera Obsolete Parts
6692: 97/06/15: Terry Harris: Re: Don't Design With Altera Parts... Altera Obsolete Parts
6621: 97/06/06: Hans Tiggeler: Actel Designer Series 3.1 and NT 4.0?
6623: 97/06/06: Adam J. Elbirt: Re: Actel Designer Series 3.1 and NT 4.0?
6627: 97/06/06: Rich K.: Re: Actel Designer Series 3.1 and NT 4.0?
6624: 97/06/06: Dag Magne Ulvang: flex10k100
6628: 97/06/06: <gajhkajh@usa.net>: Cash Grant
6640: 97/06/08: Richard B. Katz: fpga usage by capacity
6642: 97/06/09: Andreas Wassatsch: readback on xc40xx ?
6646: 97/06/09: Jeffrey M. Arnold: Re: readback on xc40xx ?
6657: 97/06/10: Andreas Wassatsch: Re: readback on xc40xx ?
6697: 97/06/16: Dr. Endric Schubert: Re: readback on xc40xx ?
6651: 97/06/09: Dave Ingram: Re: readback on xc40xx ?
6647: 97/06/09: Pedro Merino Gonzalez: XC6200 Gate Count
6648: 97/06/09: Phil Short: Re: XC6200 Gate Count
6650: 97/06/09: Tim Warland: Re: XC6200 Gate Count
6652: 97/06/09: Steve Casselman: Re: XC6200 Gate Count
6653: 97/06/09: <richard_steinman@cmagroup.com>: Job-Upstate NY; Senior Engineer; FPGA; Altera
6654: 97/06/09: Karl Kristianson: FS: CADKEY '97 (8.0) -100+ Available- Save $HUNDRED's EACH!!!
6658: 97/06/10: Stephan Gick: ATMEL 17Cxxx ISP function
6659: 97/06/10: koen Gadeyne: Re: ATMEL 17Cxxx ISP function
6660: 97/06/10: Udi Finkelstein: Re: ATMEL 17Cxxx ISP function
6661: 97/06/10: Glen Rosendale: Re: ATMEL 17Cxxx ISP function
6662: 97/06/10: Werner Dreher: Re: ATMEL 17Cxxx ISP function
6693: 97/06/16: Klaus-Guenter Leiss: Re: ATMEL 17Cxxx ISP function ( no change of RESET/_OE )
6666: 97/06/10: Martin Mason: Re: ATMEL 17Cxxx ISP function
6670: 97/06/12: Erwin Oertli: Re: ATMEL 17Cxxx ISP function
6663: 97/06/10: Brandon Unger: SUN AND SGI FOR SALE
6668: 97/06/11: Paul Hatcher: XC1700 programming algorithm
6671: 97/06/12: Steven K. Knapp: Re: XC1700 programming algorithm
6672: 97/06/12: Robin M. Morneault: FPGA Opportunities
6673: 97/06/12: Robin M. Morneault: FPGA Opportunities
6674: 97/06/12: Robin M. Morneault: Test/Development Engineer, FPGA
6675: 97/06/12: Robin M. Morneault: Sr. System Simulation Engineer,FPGA
6676: 97/06/12: Robin M. Morneault: Engineer, FPGA
6677: 97/06/12: Jacob W Janovetz: Power consumption (Xilinx FPGA) questions
6678: 97/06/13: Tom Burgess: Re: Power consumption (Xilinx FPGA) questions
6679: 97/06/13: John Kramer: Re: Power consumption (Xilinx FPGA) questions
6688: 97/06/14: Peter: Re: Power consumption (Xilinx FPGA) questions
6686: 97/06/13: Ray Andraka: Re: Power consumption (Xilinx FPGA) questions
6682: 97/06/13: Brian P Hunter: Verilog Simulation and Synthesis for FPGA Devices
6689: 97/06/14: Giuliano Cardinali: Re: Verilog Simulation and Synthesis for FPGA Devices
6783: 97/06/27: Adrian Aichner: Re: Verilog Simulation and Synthesis for FPGA Devices
6846: 97/07/02: Martin Vorbach: Verilog Simulation and Synthesis for FPGA Devices
6792: 97/06/28: Robert M. Münch: Verilog Simulation and Synthesis for FPGA Devices
6812: 97/06/30: Veli-Matti Karppinen: Re: Verilog Simulation and Synthesis for FPGA Devices
6844: 97/07/02: Robert M. Münch: Verilog Simulation and Synthesis for FPGA Devices
6892: 97/07/07: P Nibbs: Re: Verilog Simulation and Synthesis for FPGA Devices
6912: 97/07/08: Martin Vorbach: Verilog Simulation and Synthesis for FPGA Devices
6914: 97/07/08: Robert M. Münch: Verilog Simulation and Synthesis for FPGA Devices
6845: 97/07/02: Martin Vorbach: Verilog Simulation and Synthesis for FPGA Devices (VeriBests Bug
6835: 97/07/01: Greg Brown: Re: Verilog Simulation and Synthesis for FPGA Devices
6843: 97/07/02: Robert M. Münch: Verilog Simulation and Synthesis for FPGA Devices
6854: 97/07/02: Jean-Michel Vuillamy: Re: Verilog Simulation and Synthesis for FPGA Devices
6870: 97/07/04: Robert M. Münch: Verilog Simulation and Synthesis for FPGA Devices
6683: 97/06/13: Karl Kristianson: FS: CADKEY '97 (8.0)-100+ Available- Save $HUNDRED's EACH!!!
6684: 97/06/13: <ch794@freenet.buffalo.edu>: FPGA-like chip
6687: 97/06/13: Joseph H Allen: 100MHz SDRAMs with Xilinx?
6726: 97/06/19: Kim Hofmans: Re: 100MHz SDRAMs with Xilinx?
6722: 97/06/19: Wen-King Su: Re: 100MHz SDRAMs with Xilinx?
6727: 97/06/19: Brad Taylor: Re: 100MHz SDRAMs with Xilinx?
6728: 97/06/20: Stuart Clubb: Re: 100MHz SDRAMs with Xilinx?
6694: 97/06/16: Executive Search: San Diego, Ca.--MTS-FPGA Field Applications Engineer-Recruiter
6695: 97/06/16: Brian Heber: Help: Interfacing a Xilinx 4k to a microprocessor
6709: 97/06/18: Eric Jay Crabill: Re: Help: Interfacing a Xilinx 4k to a microprocessor
6713: 97/06/18: Jacob W Janovetz: Re: Help: Interfacing a Xilinx 4k to a microprocessor
6732: 97/06/20: <aaps@erols.com>: Re: Help: Interfacing a Xilinx 4k to a microprocessor
6696: 97/06/16: Austin Franklin: PCMCIA CardBus controller...
6749: 97/06/23: John Solo: Re: PCMCIA CardBus controller...
6698: 97/06/16: Simon Bacon: XCHECKER Download to Xilinx 9500 CPLDs
6699: 97/06/16: Eric Ryherd: Re: XCHECKER Download to Xilinx 9500 CPLDs
6706: 97/06/17: Gerhard Hoffmann: Re: XCHECKER Download to Xilinx 9500 CPLDs
6736: 97/06/20: Christian Schaefer: Re: XCHECKER Download to Xilinx 9500 CPLDs
6789: 97/06/27: Daniel Jones: Re: XCHECKER Download to Xilinx 9500 CPLDs
6715: 97/06/18: Ruth Mayeda: Re: XCHECKER Download to Xilinx 9500 CPLDs
6700: 97/06/17: Austin Franklin: PC Keyboard Controller in a Xilinx...
6717: 97/06/18: Ray Andraka: Re: PC Keyboard Controller in a Xilinx...
6701: 97/06/17: Ho Siu Hung: DES cracker project
6707: 97/06/17: Keith Outwater: Re: DES cracker project
6738: 97/06/21: Robb Cole: Re: DES cracker project
6702: 97/06/17: H. Ploog: How to (xilinx)?
6703: 97/06/17: Clay Gloster, Jr.: Java and Giga Ops FPGA Boards
6734: 97/06/20: Steven Guccione: Re: Java and Giga Ops FPGA Boards
6762: 97/06/25: Philip James-Roxby: Re: Java and Giga Ops FPGA Boards
6704: 97/06/17: John Cooley: ++ Trolling For DAC Dirt & Voices From The Dark Side ++
6705: 97/06/17: Karl Kristianson: FS: CADKEY '97 (8.0)-100+ Available- Save $HUNDRED's EACH!!!
6719: 97/06/19: harvey hanig: Re: FS: CADKEY '97 (8.0)-100+ Available- Save $HUNDRED's EACH!!!
6708: 97/06/17: Greg Quintana: PCI interfaces
6710: 97/06/18: John Kramer: test - don't read
6711: 97/06/18: John Kramer: test - don't read
6712: 97/06/18: Bulent UNALMIS: HELP: FOR 6000 SERIES
6729: 97/06/20: Wong Man Kit: Re: HELP: FOR 6000 SERIES
6714: 97/06/18: Nacho: Help, FPGA Information
6716: 97/06/18: Ray Andraka: Re: Help, FPGA Information
6720: 97/06/19: Kardos, Botond: Re: Help, FPGA Information
6718: 97/06/19: Marinos J. Yannikos: APS-X84 - recommended?
6733: 97/06/20: <aaps@erols.com>: Re: APS-X84 - recommended?
6806: 97/06/29: David Buckley: Re: APS-X84 - recommended?
6721: 97/06/19: Nicholas C. Weaver: Building Homebrew Tools for Xilinx 4K
6723: 97/06/19: Kardos, Botond: Flex 8000 confuguartion question - DCLK pin
6724: 97/06/19: Ilija Hadzic: Re: Flex 8000 confuguartion question - DCLK pin
6730: 97/06/20: Kardos, Botond: Re: Flex 8000 confuguartion question - DCLK pin
6725: 97/06/19: Zeev Yelin: Actel HDL cores - request for information
6737: 97/06/20: Karl Kristianson: FS: CADKEY '97 (8.0)-100+ Available- Save $700.00 EACH!!!
6739: 97/06/21: Steve Casselman: DES Cracked
6740: 97/06/22: Charles Stevens: SW updates for Sunshine EXPRO 80 programmer & a LCC44 adapter
6741: 97/06/22: Gray Creager: @@ finding data sheets and chipmaker websites (403 valid sites currently) @@
6742: 97/06/23: Djimm2: Gerhard Hoffmann... my own download program
6743: 97/06/23: Linda Boyd: Qualis Verilog Training
6744: 97/06/23: Linda Boyd: Qualis VHDL Training
6745: 97/06/23: Khalid Alotaibi: Netlist file EDIF
6746: 97/06/23: Henry Selvaraj: Logic Synthesis and AI - Special Session - Final CFP
6747: 97/06/23: Jens Ginzel: looking for FPGA to access VMEBus
6748: 97/06/23: Jonas Thor: Help: Two's complement multiplier in ORCA FPGA
6752: 97/06/24: Stuart Clubb: Re: Help: Two's complement multiplier in ORCA FPGA
6750: 97/06/23: Bharat Kurani: Need Good IC Schematics to Chip Layout Engineer
6751: 97/06/24: Stephen: Query: Anyone ever install Xilinx Foundation on a Jaz drive? If so how?
6753: 97/06/24: <david.surphlis@gecm.com>: lattice / synario and smatmodels
6754: 97/06/24: Hakan Thyr: ASIC/FPGA in Boston?
6755: 97/06/24: Deependra Talla: universities offering real-time
6756: 97/06/24: <aaps@erols.com>: Re: FPGA prototype board
6771: 97/06/26: Stephen D. Scott: Re: FPGA prototype board
6757: 97/06/25: Erik Lins: Asynchronous Peripheral Download Mode, Probs
6761: 97/06/25: Steve Gross: Re: Asynchronous Peripheral Download Mode, Probs
6781: 97/06/27: Philip Freidin: Re: Asynchronous Peripheral Download Mode, Probs
6776: 97/06/26: Peter Alfke: Re: Asynchronous Peripheral Download Mode, Probs
6818: 97/06/30: Peter Alfke: Re: Asynchronous Peripheral Download Mode, Probs
6758: 97/06/25: Gianpaolo Scassellati: Info on VHDL
6759: 97/06/25: David Bishop: Re: Info on VHDL
6772: 97/06/26: Stephen D. Scott: Re: Info on VHDL
6821: 97/06/30: Steven K. Knapp: Re: Info on VHDL
6760: 97/06/25: SALIX Technologies - Dan Simpkins: Are Xilinx 4000XL I/O's truly 5V tolerant?
6764: 97/06/25: Tom Burgess: Re: Are Xilinx 4000XL I/O's truly 5V tolerant?
6787: 97/06/27: Peter Alfke: Re: Are Xilinx 4000XL I/O's truly 5V tolerant?
6788: 97/06/27: Phil Short: Re: Are Xilinx 4000XL I/O's truly 5V tolerant?
6791: 97/06/28: Tom Burgess: Re: Are Xilinx 4000XL I/O's truly 5V tolerant?
6860: 97/07/02: Peter Alfke: Re: Are Xilinx 4000XL I/O's truly 5V tolerant?
6884: 97/07/06: Tom Burgess: Re: Are Xilinx 4000XL I/O's truly 5V tolerant?
6802: 97/06/29: Richard B. Katz: Re: Are Xilinx 4000XL I/O's truly 5V tolerant?
6816: 97/06/30: <husby@fnal.gov>: Re: Are Xilinx 4000XL I/O's truly 5V tolerant?
6763: 97/06/25: Anthony Marchini: Intel PLD programmer
6765: 97/06/25: Steve Martindell: FPGA prototype board
6766: 97/06/25: Jacob W Janovetz: Re: FPGA prototype board
6769: 97/06/26: Joseph H Allen: Re: FPGA prototype board
6777: 97/06/26: David R Brooks: Re: FPGA prototype board
6778: 97/06/26: <aaps@erols.com>: Re: FPGA prototype board
6774: 97/06/26: Leon Heller: Re: FPGA prototype board
6775: 97/06/26: Philip Freidin: Re: FPGA prototype board
6790: 97/06/28: Steve Casselman: Re: FPGA prototype board
6822: 97/06/30: Steven K. Knapp: Re: FPGA prototype board
6851: 97/07/02: S.Perri: Re: FPGA prototype board
6767: 97/06/25: Karl Kristianson: FS: CADKEY '97 (8.0)-100+ Available- Save $700.00 EACH!!!
6773: 97/06/26: <asd>: Tight Teen Snatch * teen1.jpg
6779: 97/06/27: Daniel Elftmann: PCI
6780: 97/06/27: Rune Bĉverrud: Generating Sine/Cosine digitally
6784: 97/06/27: Brian Drummond: Re: Generating Sine/Cosine digitally
6786: 97/06/27: Ray Andraka: Re: Generating Sine/Cosine digitally
6903: 97/07/07: Marc 'Nepomuk' Heuler: Re: Generating Sine/Cosine digitally
6905: 97/07/08: Joel W. Kolstad: Re: Generating Sine/Cosine digitally
6906: 97/07/08: Rune Bĉverrud: Re: Generating Sine/Cosine digitally
6911: 97/07/08: Ralph Reinhold: Re: Generating Sine/Cosine digitally
6916: 97/07/08: Ray Andraka: Re: Generating Sine/Cosine digitally
6917: 97/07/09: Rune Bĉverrud: Re: Generating Sine/Cosine digitally
6921: 97/07/09: Rune Bĉverrud: Re: Generating Sine/Cosine digitally
6934: 97/07/10: Tom Burgess: Re: Generating Sine/Cosine digitally
6927: 97/07/09: M Sweger: Re: Generating Sine/Cosine digitally
6929: 97/07/09: Terry Harris: Re: Generating Sine/Cosine digitally
6918: 97/07/09: M. Spicker: Re: Generating Sine/Cosine digitally
6920: 97/07/09: Stephen R. Synakowski: Re: Generating Sine/Cosine digitally
6949: 97/07/14: -Bodnar,B.L.: Re: Generating Sine/Cosine digitally
6951: 97/07/14: Ray Andraka: Re: Generating Sine/Cosine digitally
6923: 97/07/09: Henry F. (Hank) McCall: Re: Generating Sine/Cosine digitally
6937: 97/07/10: Glenn Fasnacht: Re: Generating Sine/Cosine digitally
6981: 97/07/18: Peter Alfke: Re: Generating Sine/Cosine digitally
6782: 97/06/27: <asdofjasd>: Young cheerleader fucking and sucking cock
6785: 97/06/27: Usenet Admin: Help!!
6793: 97/06/28: Tom Burgess: Re: Help!!
6795: 97/06/28: Roger: Re: Help!!
6794: 97/06/28: Peter: Programming Xilinx 3k/4k in C ?
6810: 97/06/30: A.Williams: Re: Programming Xilinx 3k/4k in C ?
6796: 97/06/28: TJ: Smart Card Design and Interface. How?
6798: 97/06/28: "Paul E. Bennett": Re: Smart Card Design and Interface. How?
6799: 97/06/28: Andrew DeWeerd: Re: Smart Card Design and Interface. How?
6804: 97/06/29: Olav Woelfelschneider: Re: Smart Card Design and Interface. How?
6808: 97/06/29: Chris Hills: Re: Smart Card Design and Interface. How?
6811: 97/06/30: Gregor Glawitsch: Re: Smart Card Design and Interface. How?
6814: 97/06/30: Ray Andraka: Re: Smart Card Design and Interface. How?
6885: 97/07/06: Karen: Re: Smart Card Design and Interface. How?
6823: 97/06/30: PicInfo: Re: Smart Card Design and Interface. How?
6881: 97/07/06: Adam Anderson: Re: Smart Card Design and Interface. How?
6899: 97/07/07: Lee Mitchell: Re: Smart Card Design and Interface. How?
6800: 97/06/28: Viktor Kesler: HELP with mcALLPROG
6803: 97/06/29: Joseph H Allen: fast scopes: how?
6813: 97/06/30: Bill Sloman: Re: fast scopes: how?
6832: 97/07/01: Frank Miles: Re: fast scopes: how?
6862: 97/07/03: Bill Sloman: Re: fast scopes: how?
6866: 97/07/03: Joseph H Allen: Re: fast scopes: how?
6933: 97/07/10: Roy McCammon: Re: fast scopes: how?
6940: 97/07/11: <sloman@sci.kun.nl>: Re: fast scopes: how?
6941: 97/07/11: Mike: Re: fast scopes: how?
6872: 97/07/04: Paul Baxter: Fast sampling techniques. Was: Fast scopes, How?
6874: 97/07/04: Joseph H Allen: Re: Fast sampling techniques. Was: Fast scopes, How?
6876: 97/07/05: Tom Burgess: Re: Fast sampling techniques. Was: Fast scopes, How?
6882: 97/07/05: Mike: Re: Fast sampling techniques. Was: Fast scopes, How?
6889: 97/07/06: Garritt: Re: Fast sampling techniques. Was: Fast scopes, How?
6879: 97/07/05: bob elkind: Re: fast scopes: how?
6902: 97/07/07: Joseph H Allen: Re: fast scopes: how?
6922: 97/07/09: Henry F. (Hank) McCall: Re: fast scopes: how?
6930: 97/07/09: Jon Goguen: Re: fast scopes: how?
6928: 97/07/09: A William Sloman: Re: fast scopes: how?
6865: 97/07/03: Bob Myers: Re: fast scopes: how?
6805: 97/06/29: Reetinder P. S. Sidhu: EDIF for Xilinx tools
6827: 97/07/01: Frank Gilbert: Re: EDIF for Xilinx tools
6869: 97/07/04: Philip James-Roxby: Re: EDIF for Xilinx tools
6809: 97/06/30: <ASE1000@1stfamily.com>: World Wide Free Internet Access .
6815: 97/06/30: Rod Leiting: Xilinx XACT question
6825: 97/07/01: Austin Franklin: Re: Xilinx XACT question
6817: 97/06/30: Patrick n' Nicole Miller: Development Proposals
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Compare FPGA features and resources
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