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I need information on Actel HDL cores, specifically the 8259 and 8254 which I have to integrate in an A1280A chip. are they "Silicon Proven" ? What HDL abstraction level? is it RTL or gate level ? How easy are they to "degenerate" to specific modes used in the system ( and save a few gate there, a few FF there and maybe squeeze an additional peripheral in it). Do they come with a test fixture, synthesis scripts. ? Any special terms & condidtions, Any "combat proven experience" will much appreciated and shared in the future. thx Zeev ************************************************************************** Zeev Yelin Solution Architect - Spectrum Services Cadence Design Systems(ISRAEL) Tel. (972)9-9-511-799 Car(972)-52-772-584 Fax. (972)9-9-511-796 Free Ron Arad - Israeli Navigator, held prisoner since 1986, His condition & whereabouts unknown. *****************************************************************************Article: 6726
In article <EBqKos.1A2@world.std.com>, jhallen@world.std.com (Joseph H Allen) writes: > I want to connect 4 SDRAMs (in a 2M x 32 configuration) to a XC40XXE in such > a way that I can do a full speed 100MHz continual write to the SDRAMs (reads > can be slow). All signals will come from the fpga including data, address, > control and clock. All signals except clock will use the pad flip flops. > Each data line originates from another fpga input pin, and goes through only > a single CLB (and it can use that CLB's flip flop as a pipeline register). > The data rate and SDRAM clock will be 100MHz. The SDRAMs are 3.3V parts and > the xilinx is 5V, but with TTL output levels. > > Has anyone tried this? Did it work? 100MHz seems fast for the control > logic, but no state machines actually have to go at that rate (only 50MHz or > maybe less). The data paths do have to work though. > It should work. At the moment I'm working on a 106Mhz Fibre channel encoder/ decoder (XC4010E-2) driving a channel transceiver vsc7125. The data rate and the vsc7125 is 106Mhz.Most of the State machines run at 53Mhz. 50% of the Xilinx works at a speed of 106Mhz, so it gets very hot. With some tricks, the setup and hold time of the VSC7125 are met. kind regards, Hofmans Kim R&D Hardware Engineer Nieuwevaart 153, B9000 Gent BelgiumArticle: 6727
Wen-King Su wrote: >> The data rate and SDRAM clock will be 100MHz. The SDRAMs are 3.3V >>parts and the xilinx is 5V, but with TTL output levels. >> Has anyone tried this? Did it work? 100MHz seems fast for the >>control logic, but no state machines actually have to go at that rate >>(only 50MHz or maybe less). The data paths do have to work though. > > Your problem will be with "TTL output levels". There is no guarantee > that it will not source a significant amount of current at VOH = 3.3V > forward biased drop of the protection diode on the SDRAM's pads. Actually, the problem of significant current will only occur if the 5 volt supply is at 5.5V and the 3.3V supply is at 3.0 V. I've forgotten the details, but Xilinx has an app note about this. I don't believe uncontrolled current begins to flow until there are 4 diode drops (2.4v) between the two supplies. If you are creating the 3.3V supply yourself with a regulator you should be fine.Article: 6728
On 19 Jun 97 16:13:21 CET, kho@phobos.gent.bg.barco.com (Kim Hofmans) wrote: >It should work. At the moment I'm working on a 106Mhz Fibre channel encoder/ >decoder (XC4010E-2) driving a channel transceiver vsc7125. The data rate >and the vsc7125 is 106Mhz.Most of the State machines run at 53Mhz. >50% of the Xilinx works at a speed of 106Mhz, so it gets very hot. >With some tricks, the setup and hold time of the VSC7125 are met. How hot? What is the power consumption? How will you cool it? What ambiant temperature is it safe to (in the package)? StuartArticle: 6729
Bulent UNALMIS (unalmis@club-internet.fr) wrote: : I want to use 6000 family of lattice or equvalent fpga of another : companys. : Can you suggest any hardware and software devolopment tools for this : serie. I have used Lattice 6k family before. You have two options. 1. pDS 3.0 from Lattice. - boolean entry with Lattice and TTL macro. - with ispDOWNLOAD to program the device 2. WorkView 7.3.1 or Pro Series 6.1 from ViewLogic + ispDS+ 5.0 fitter (from Lattice) - schematic (+ VHDL) entry - functional and timing simulation - with ispDPWNLOAD to prgram the device Hope this can help you. For detail, I think you can visti Lattice's homepage and the URL is http://www.latticesemi.com. -- Wong Man Kit 1996 M.Sc. Graduate Department of Elecrtrical and Electronic Engineering Hong Kong University of Science and TechnologyArticle: 6730
Ilija Hadzic wrote: > > Kardos, Botond (kardos@mail.matav.hu) wrote: > : has anyone experience with the Passive Paralell Active configuration > : of the Flex 8000 devices ? > > I guess you mean Passive Parallel Asynchronous (not Active) ? > Sorry for the typo of course it wanted to be Passive Parallel Asynchronous. > I would rather guess that it has to do with the device options. Make sure > that the the device option "Enable DCLK output in user mode" is checked > before the compilation. That's exactly what I've done. And there's a circuit with an APU configured FPGA where it works, and there's one with a PPA configured chip where it doesn't. Strange, isn't it ? My next guess is that MaxPlus II (version 6.2) makes some errors (maybe another config option which one I'm not aware of or maybe a bug). I'm currently trying to find a software problem but with no efforts yet. So thanks Ilija and I'd appreciate any other hint, Botond -- Kardos, Botond - at Innomed Medical Ltd. in Hungary eMail: kardos@mail.matav.hu phone/fax: (0036 1) 351-2934 fax: (0036 1) 321-1075Article: 6731
Once the VHDL files have been successfully analysed by Speedwave, you should get a "VHDL Architecture" and "VHDL Entity" menu pick when you press the left hand mouse key over the symbol. In article <01bc55fb$be1daf60$504116c4@anthonye>, Anthony <aelogic@iafrica.com> writes >I have just upgraded to Workview 7.31. I have run their tutorials for >creating symbols >from VHDL and placed those symbols in a schematic. When selecting the >symbols and invoking the pop-up menu the "push-vhdl" etc. options are not >available. I understood from the literature that one could push into the >symbol and bring up the source code for editing. Is this so?. What >attributes are missing so that the PUSH options are unavailable. > >Thanks Tony. -- William WhiteArticle: 6732
Brian Heber wrote: > > I'm trying to interface a TMS320C5x with a Xilinx 4k FPGA and > I'm looking for anyone who might have done something similar. > All I want to be able to do (at the moment) is to send a 16 > bit message to the FPGA and/or read a 16 bit message from the > FPGA. > > Does anyone have schematics and code on how to do this? If > not, some other friendly advice would be greatly appreciated. > > Thanks > > Brian Heber Brian, The details involve setting up a decode select line of some sort , a write/read line and an address and data bus. Then you simply write to the fpga and have it store the command or act accordingly. Some VHDL code which does this from the PC ISA bus is available at: http://www.erols.com/aaps Press the VHDL Lab button and it will take you to the VHDL/FPGA tutorial pages. Hope this helps :)Article: 6733
Marinos J. Yannikos wrote: > > Is the APS-X84 kit as good as it looks on http://www.erols.com/aaps/ ? > I'd like to experiment a bit with various algorithms and this looks as if > it would suffice, while the price does not hurt much. However, since I'm > new to FPGAs, I'm not at all sure I can tell. Any comments would be much > appreciated. > > Thanks, > -nino Marinos, I am not at all unbiased but we have sold dozens of these kits in the last several months, and gotten only rave reviews. I have never gotten even one complaint, (except that at one point we ran out and had a delivery delay of about 2 weeks). The kits are just as they seem --a great value-- We are in the midst of developing low cost SRAM, FIFO and AD/DA modules which plug in to the top of the X84 boards connectors, and allow for various scenarios to be tried with the board. We are proud to have sold our X84 products to Universities and large conpanies like ITT, 3M, Texas Instruments, and Hewlett Packard. But the bulk of our kits have been sold to individual engineers who are new to FPGAs, or are either starting thier own side business or want unrestricted access to their own kits. APS is committed to supporting these kits with tech notes and low cost support modules to encourage and promote FPGA coding. Hopefully some who are avid readers of this newsgroup will chime in and give you a more unbiased view. Feel free to contact me with any questions you have concering these kits. Richard Schwarz, President Associated Professional Systems(APS)Article: 6734
See http://www.vcc.com/ They have a Xilinx 6200-based board that has full Java support and does remote access pretty painlessly. Comes with WebScope, a remote debug tool, also implemented in Java. -- Steve -- 6/20/97Article: 6735
timolmst@cyberramp.net wrote: : >It would be very helpful for those of us with homegrown tools, who are : >considering a move from XNF to EDIF, if Xilinx would publish a : >specification of how to emit EDIF for Xilinx tools, e.g. how to target : >specific device features, specify timespecs, placement constraints, etc. : >That is, don't repeat the XNF experience where the information was : >available only under NDA or through "reverse engineering" of : >otherwise-generated XNF. : >Perhaps such a EDIF-for-Xiilnx specification is available, but I haven't : >yet received an update since 6.0 and it doesn't appear to be on the Xilinx : >website. : You probably won't. Xilinx has historicly considered this information : to be propietary. There's no secret. The tools want to see an EDIF file containing Xilinx unified libraries. The libraries are documented in our Libraries Guide and also the attributes that we will accept. EDIF is a standard and is fairly well documented. SteveArticle: 6736
Gerhard Hoffmann wrote: > I second that. I think that Xcheckers can have LatchUp effects > if you don't apply power to your prototype before turning > on your pc. Sometimes there are situations where it simply > does not work. I found that it then draws more current ( i > remember something like an extra 150 mA ) and heats up a bit. We have a Xchecker connection between our prototype (two XC4005) and a Sun workstation that is never shut down. We sometimes experienced a problem when the prototype consumed about 1A (!) after power on. Normal power consumption of the circuit is 100-200mA. If this happens, downloading the design via Xchecker is not possible. We have to switch the power off and on again several times until it works again. Bis dann, Christian. -- PGP: pgp-public-keys@keys.de.pgp.net Subj: GET 0x73036211 Fingerprint: 33 20 99 54 66 C1 1C 32 D9 C1 BC F8 53 AF E4 C6Article: 6737
FS: CADKEY '97 (8.0)-100+ Available- Save $700.00 EACH!!! A new copy of Cadkey '97 is selling on the street for $1,195. To guarantee updates for the next year costs $350 more, bringing it up to $1,545 total! We have available over 100 NEW copies of Cadkey 6.0 on CD for DOS in unopened, shrinkwrapped boxes with all manuals & documentation; which can be upgraded to Cadkey '97, INCLUDING the year's worth of free updates, for the street price of $595. That's $950 LESS than the normal street price! Or, maybe Cadkey 6.0 has enough power for you with no upgrade at all! (Cadkey '97 is basically Cadkey 8.0) We're selling these for $250 each, so you save $700 over the normal street price of Cadkey '97! ($1,545 minus $595 upgrade price minus our price of $250 equals $700 savings!) If you would like more info on Cadkey 97, here's Cadkey 97's Web page: http://www.cadkey.com/cadkey/index.htm Thanks! Karl Kristianson DreamQuestArticle: 6738
Ho Siu Hung <eg_hsh@stu.ust.hk> wrote in article > We planned to buy lots of FPGA for parallel processing, but we need to > make sure that we are not buying the wrong one. How can we make sure that > a VHDL program can fit into one FPGA? Counting number of gates/CLB or > some other stuff? Is there a clear cut solution for that? What you need to do is to understand about how many flops you will need to implement your design (or at least one slice of the parallel process). Once you have that number in mind, you can decide what size (generally) of FPGA you need. The next consideration is what system speeds you need to run at. Xilinx parts have a history of adding a significant amount of delays to a circuit in wiring. (I once had a Xilinx part take > 50 ns to route a wire from a flop Q output to a flop D input with no logic between them!). I have set a rule of doubling the function generator propagation time plus the flop setup time and using that number to determine how many function generators I can tolerate between latches. So you may end up having to pipeline your design heavily to make it work, depending on the system clock rate. Once you have considered these numbers, you can arrive at a CLB count, and from that you can make an educated guess as to the size Xilinx you will need. Hope this helps a bit.. Robb ColeArticle: 6739
RSA's 56-bit DES challenge has been broken see http://www.rsa.com/des for details. -- Steve Casselman, President Virtual Computer Corporation http://www.vcc.comArticle: 6740
Does the company that manufacturers Sunshine series of programmers still exist? The last software update that I have been able to obtain was version 8.40.00. Are there highers versions than this one. I would like to program Atmel AT17C65 with the Expro 80. I am also looking for the wiring to match the ADP-EPM7032 adapter to program Altera 7032 (LCC44) from the Expros 40 pin DIP. Any help os appreciated. Thanks Charles ----------------------------------------------------------------------------- Charles Stevens c.stevens@ieee.org => cstevens@iafrica.com Box 782094 Sandton. Tel/Fax: (+2711) 468 2311 South Africa, 2146. Cell: 083 255 4906Article: 6741
Just a reminder to everyone. I have been compiling a semiconductor manufacturer website listing (and making it available to other engineers on the web) for about 2 years now. I used to post it to sci.electronics every so often in the past, but it has gotten way too big for that. There are 403 companies on the list currently. These are chipmakers, so if you can't find the data sheet that you need because you don't know the manufacturer's website, try my listing. Bookmark it and tell your co-workers. I try to keep it the most up-to-date and useful listing of chipmakers anywhere on the web (by constantly searching for new URLs before most others find them) and it is now widely used by a lot of people. The following categories exist among my "engineering" subpages. - Semiconductor URLs (Brief listing) - Semiconductor URLs (Verbose listing; includes product categories) - New Semiconductor URLs - Missing Semiconductor URLs - Motivations - 25 Best Semiconductor Websites - 25 Worst Semiconductor Websites - Engineering Humor try it out, I think you'll find it to be quite useful. Let me know what you think. The URL is: http://www.scruznet.com/~gcreager The website is best viewed in a frames environment, but there are "back doors" for getting to these pages if your browser doesn't support frames. === Also, PCB-Quote and Mitronics are helping me in this endeavor by running unobtrusive ads on my webpages. PCB-Quote can be your one stop shop for quoting the fabrication and assembly of your PCBs. Mitronics is an independent stocking distributor. If these services are of interest, then please follow their banner links and let them know you heard about them through Gray's Semiconductor Pages :-) === Gray CreagerArticle: 6742
Hallo Gerhard! > Since i don't want to power down my pc whenever i play with > the prototype, i now use my own download program and the > printer port. I have exatly the same problem. I need also to download some info through the printerport via the "Xchecker" back and forth. I was going to write this program. Could you help me on that? Danke Jimmy D.Article: 6743
Qualis Design Corporation has released the Fall schedule for our many
hands-on, application-focused courses in Verilog- and VHDL-based design.
Our courses are like no other -- just take a look at our lineup:
Verilog System Design
---------------------
Introductory:
High Level Design Using Verilog (5 days)
System Verification Using Verilog (5 days)
Verilog for Board-Level Design (5 days)
Elite:
ASIC Synthesis and Verification Strategies Using Verilog (5 days)
Advanced Techniques Using Verilog (3 days)
Verilog Synthesis
-----------------
Introductory:
Verilog for Synthesis: A Solid Foundation (5 days)
Elite:
ASIC Synthesis Strategies Using Verilog (3 days)
Behavioral Synthesis Strategies Using Verilog (3 days)
For more info on our suite of HDL classes, to review our Fall schedule,
or if you're interested in an on-site class, check out our web site at
http://www.qualis.com or call Michael Horne on our hotline at 888.644.9700.
Qualis Design Corporation
8705 SW Nimbus Suite 118
Beaverton OR 97008 USA
Ph: +1.503.644.9700 Fax: +1.503.643.1583
http://www.qualis.com
Copyright (c) 1997 Qualis Design Corporation
Article: 6744
Qualis Design Corporation has released the Fall schedule for our many
hands-on, application-focused courses in VHDL- and Verilog-based design.
Our courses are like no other -- just take a look at our lineup:
VHDL System Design
------------------
Introductory:
High Level Design Using VHDL (5 days)
System Verification Using VHDL (5 days)
VHDL for Board-Level Design (5 days)
Elite:
ASIC Synthesis and Verification Strategies Using VHDL (5 days)
Advanced Techniques Using VHDL (3 days)
VHDL Synthesis
--------------
Introductory:
VHDL for Synthesis: A Solid Foundation (5 days)
Elite:
ASIC Synthesis Strategies Using VHDL (3 days)
Behavioral Synthesis Strategies Using VHDL (3 days)
For more info on our suite of HDL classes, to review our Fall schedule,
or if you're interested in an on-site class, check out our web site at
http://www.qualis.com or call Michael Horne on our hotline at 888.644.9700.
Qualis Design Corporation
8705 SW Nimbus Suite 118
Beaverton OR 97008 USA
Ph: +1.503.644.9700 Fax: +1.503.643.1583
http://www.qualis.com
Copyright (c) 1997 Qualis Design Corporation
Article: 6745Hi All In one part of my work, I want to generate EDIF file as an input to XACT6000 Please, where can I find a EDIF syntax, or any documentation for EDIF structure... Thanks in advance Khalid AlotaibiArticle: 6746
ICCIMA'98
International Conference on Computational Intelligence and
Multimedia Applications 9-11 February 1998
Monash University, Gippsland Campus, Churchill, Australia
F I N A L C A L L F O R P A P E R S
The International Conference on Computational Intelligence and
Multimedia Applications will be held at Monash University on 9-11
February 1998.
The conference will include sessions on theory, implementation
and applications, as well as the non-technical areas of challenges in
education and technology transfer to industry. There will be both
oral and poster sessions. Accepted full papers will be included in
the proceedings to be published by World Scientific. Keynote
speakers at the conference will include:
Prof. Russell C. Eberhart
Executive Director, Advanced Vehicle Technology Institute
Purdue School of Engineering and Technology
Indiana Univ. Purdue Univ. Indianapolis
USA
Dr Adam Kowalczyk
Telstra Research Laboratories
Melbourne, Australia
Special Sessions:
Artificial Intelligence and Logic Synthesis: intelligent
algorithms for logic synthesis; functional decomposition
in machine learning, pattern recognition, knowledge discovery
and logic synthesis;evolutionary and reconfigurable computing
with FPGAs. Chair: Lech Jozwiak, Eindhoven University,
Netherlands.
Multimedia Information Retrieval: segmentation of audio, image and
video; feature extraction and representation; semi-automatic text
annotation techniques; indexing structure; query model and retrieval
methods; feature similarity measurement; system integration issues;
prototype systems and applications. Chair: Guojun Lu, Monash
University, Australia.
Conference Topics Include (but not limited to):
Artificial Intelligence
Artificial Neural Networks
Artificial Intelligence and Logic Synthesis
Functional decomposition
Pattern Recognition
Fuzzy Systems
Genetic Algorithms
Intelligent Control
Intelligent Databases
Knowledge-based Engineering
Learning Algorithms
Memory, Storage and Retrieval
Multimedia Systems
Formal Models for Multimedia
Interactive Multimedia
Multimedia and Virtual Reality
Multimedia and Telecommunications
Multimedia Information Retrieval
Important Dates:
Submission of papers received latest on: 7 July 97
Notification of acceptance: 19 September 97
Camera ready papers & registration received by: 24 October 97
Submission of Papers
Papers in English reporting original and unpublished research
results and experience are solicited. Electronic submission of
papers via e-mail in postscript or Microsoft Word for Windows format
directly to the General Chair are acceptable and encouraged for the
refereeing process. If not submitting an electronic version, please
submit three hard copy originals to the General Chair. Papers for
refereeing purposes must be received at the ICCIMA 98 secretariat
latest by 7 July 1997. Notification of acceptance will be mailed by
19 September 1997.
Page Limits
Papers for refereeing should be double-spaced and must include an
abstract of 100-150 words with up to six keywords.
The accepted papers will need to be received at the ICCIMA 98
secretariat by 24 October 1997 in camera ready format. A final
preparation format for the camera-ready papers will be provided upon
notification of acceptance. Camera ready papers exceeding 6 pages
(including abstract, all text, figures, tables and references etc.)
will be charged an extra fee per page in excess to the normal
registration.
Evaluation Process
All submissions will be refereed based on the following criteria by
two reviewers with appropriate background.
originality
significance
contribution to the area of research
technical quality
relevance to ICCIMA 98 topics
clarity of presentation
Referees report will be provided to all authors.
Check List
Prospective authors should check that the following items are
attached and guidelines followed while submitting the papers for
refereeing purpose.
* The paper and its title page should not contain the name(s) of
the author(s), or their affiliation
* The paper should have attached a covering page containing
the following information:
-title of the paper
-author name(s), Affiliation, mail and e-mail addresses,
phone
and fax numbers
-Conference topic area
-up to six keywords
* The name, e-mail, phone, fax and postal address of the contact
person should be attached to the submission
General Chair:
Henry Selvaraj
Gippsland School of Computing
& Information Technology
Monash University,
Churchill, VIC, Australia 3842
Henry.Selvaraj@fcit.monash.edu.au
Phone: +61 3 9902 6665
Fax: +61 3 9902 6842
International Programme Committee:
Abdul Sattar, Griffith University, Australia
Andre de Carvalho, University of Sao Paulo, Brazil
Bob Bignall, Monash University, Australia
Brijesh Verma, Griffith University, Australia (Programme Chair)
Dinesh Patel, Surrey University, UK Henry Selvaraj, Monash
University, Australia Hyunsoo Lee, University of Yonsei, Korea Jan
Mulawka, Warsaw University of Technology, Poland Jong-Hwan Kim,
Korea Advanced Institute of Science & Technology, Korea Lech
Jozwiak, Eindhoven Univ. of Tech, Netherlands Margaret
Marek-Sadowska, University of California, USA Marek Perkowski,
Portland State University, USA Michael Bove, MIT Media Laboratory,
USA Mikio Takagi, University of Tokyo, Japan Nagarajan Ramesh,Tencor
Instruments, USA Ramana Reddy, West Virginia University, USA Regu
Subramanian, Nanyang Tech University, Singapore Sargur Srihari,
State University of New York, USA Shyam Kapur, James Cook
University, Australia Sourav Kundu, Kanazawa University, Japan S.
Srinivasan, IIT, Madras, India Subhash Wadhwa, IIT, Delhi, India
Tadeusz Luba, Warsaw University of Technology, Poland Vishy Karri,
University of Tasmania, Australia Xin Yao, University of New South
Wales, Australia
International Liaison
Asian Liaison:
Regu Subramanian, Network Technology Research
Centre, Nanyang Technological University, Singapore
U.S. Liaison:
Marek Perkowski, Portland State University, USA
European Liaison:
Tadeusz Luba, Warsaw University of Technology,
Poland
Organising Committee:
Bob Bignall, Monash University, Australia
Baikunth Nath, Monash University, Australia
Vishy Karri, University of Tasmania, Australia
Syed M. Rahman, Monash University, Australia
Bala Srinivasan, Monash University,Australia
Cheryl Brickell, Monash University, Australia
Andy Flitman, Monash University, Australia
Lindsay Smith, Monash University, Australia
Further Information:
Conference Email :
iccima98@fcit.monash.edu.au
Conference WWW Page:
http://www-gscit.fcit.monash.edu.au/~iccima98
Article: 6747Hello, I have to design a VME-card, which should carry a Dual-Ported RAM, that should be accessible from other VME-cards. The card that has to be designed has only slave-function, but should be able to create Interrupts. Does anybody know about a FPGA that is ready to use for this task? (maybe with a little auxillary logic) JensArticle: 6748
Hi! I'm trying do design a two's complement combinational multiplier in a ORCA 2Cxx series FPGA. The tools I'm using are Synopsys Design compiler and FPGA compiler. When I instatiate Synopsys DW multiplier FPGA compiler doesn't map to any ORCA macros, thus the design is not optimal (?). I expected that FPGA compiler would map the design to FPUs in either multiplier mode or adder mode but it doesn't... I have no problem with unsigned multiplers or other designware components. I guess this is becuase there are no ORCA macros for two's complement multipliers...- If so, could anyone please give me a hint how to best implement a two's complement multiplier in ORCA FPGA? Thanks, Jonas Thor -------------------------- Jonas Thor University of Technology Lulea, Sweden i93-jtr@sm.luth.seArticle: 6749
Yes, TI makes one chip, 32-bit, with code for many systems. Austin Franklin wrote in article <01bc7a82$0a3cb8a0$27cab7c7@drt1>... >Hi, > >Anyone know of a PCMCIA controller that does CardBus and is NOT a PCI >peripheral? > >Thank you, > >Austin Franklin >darkroom@ix.netcom.com > >
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