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Paul, if you want the performance and asynchronous behavior that you mention, you must make a decision on a specific architecture. At the 50+ MHz performance level, you need a true dual-port RAM, you cannot fake it with multiplexed addresses. I wrote an app note on this subject, it's XAPP051, appropriately called "Synchronous and Asynchronous FIFO Designs". If you intend to use it, send me e-mail and I'll tell you a few new tricks. ( I was the driving force behind the Fairchild 3341, the industy's first FIFO in 1972, a quarter century ago ). In an asynchronous FIFO, there is no known phase or frequency relationship between the read and the write clock. The difficulty lies in the reliable generation of the control signals FULL and EMPTY ( the rest is trivial ). Slow designs you can do in a generic fashion, but for really high performance, you need to decide on a particular manufacturer's part and development system. Luckily the decision often narrows down to only a few contenders, sometimes only one. Near the end of the alphabet. :-) Peter Alfke, Xilinx ApplicationsArticle: 7351
Have anyone more than I had any problems with the Microchip 24LC164 (I2C EEPROM 2k*8)? As I have detected, it responds not only to the I2C address that I have choosen (1001xxxr) but also to 0110xxxr. I have tested the same type of device from Thomson, Xicor and Atmel and it is only the Microchip device that acts this way. I also changed the device address (by changing the A1 pin) to 1011xxxr but its still responds to address 0110xxxr too. I have had som contact with Microchip, but they neither confirms or denies. Is this a bug in the 24LC164? Normally it is of no problem, but if I want to use a device that actually uses the address 0110xxxr I would get a conflict on the address using the 24LC164 device. Has anyone seen the same behaviour?? /Anders SandgrenArticle: 7352
Joseph, > So which mode should we use delay or nodelay? I would guess that a card on > a bus should use nodelay (short setup time, more than 0ns hold time), but a > chip on a motherboard should use delay (large setup time, no hold time). According to the data book, DELAY is the mode you want to use. It supposedly requires 7ns setup and 0ns hold. > Why would XACT give more conservative numbers for this? What additional > assumptions do the "massaged" numbers make- there should be no variable > routing estimates for global clock to IOB FFs? Is a narrower temperature > window perhaps being assumed? I don't know what the exact (no pun intended) numbers are, but they e-mailed me a PERL script called 'model_io' that I had to run on the simulation .xnf file. This script changed the INFF setup and hold values to be 7setup and 0 hold so I could pass simulation.... What the claim was is as follows: "Run the model_io Perl script, (model_io version 2.01 or higher should be used). This corrects known conservative modeling values for the setup/ hold and clock-to-output timing of the I/O flip-flops. The Perl script provides the guaranteed data book values in the final .xnf file (see the XC4000E Technical Data data sheet). The Perl program version 5.00 or higher is required to execute the model_io script," So, no, it is not temperature related, as it shouldn't be. My understanding is that the numbers used in the speed files is 'conservative'....and does not match the data book values. Note the data book 'guaranteed' values require the use of a primary global clock, and it obviously must be direct. Alas, though I have this nice script, all I know now is my design passes a 7ns setup and 0ns hold time simulation....but still doesn't work in the system with the one bridge - 21152-AA. Argh! AustinArticle: 7353
I'm tempted to load my PCI controller FPGA configuration (Xilinx bit-stream) over the PCI bus. One way is to broadcast the bitstream to all slots- a simple descrete circuit looks for writes to read-only configuration space registers and latches some of the address bits. The latched bits become the cclk and din lines for the configuration data. Now this circuit never drives the devsel# (or any other) line, so the write will eventually just terminate after 6 cycles. This is so slow that the circuit can be seperated from the bus with, say, 100 ohm resistors- so it won't load the bus and the signals can also go to the FPGA without violating the spec. This happens way after the PCI bios does memory mapping, so you have to do the memory mapping on your own. (Actually the PCI bios should provide a memory remapping call for just this purpose). Now we just need a standard so that several people can have their FPGA boards in the bus: maybe you have to broadcast the vendor and device IDs before the bit-stream. -- /* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */ int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0) +r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2 ]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}Article: 7354
It would be really nice if PCI controller FPGAs could be configured over the PCI bus. One way of doing it is to use configuration writes with the fpga data encoded in the address. A simple circuit looks for these configuration writes and latches the address. The circuit doesn't drive idsel# (or any other line), but timeout occurs anyway after 6 cycles- the address is guarenteed to get through, however. The circuit could be added onto the PCI lines which already go to the FPGA through large resistors, so as not to violate the spec. To configure the FPGA, you write the bitstream to each slot which appears empty in succession until your card appears. The main problem with this scheme is that your card won't appear until after the PCI bios has assigned addresses. Thus you have to do the memory mapping on your own (there should be a call for this in the PCI BIOS...). Another problem is that a standard needs to be made to prevent you from configuring other people's PCI cards: Two of the address bits are needed for this: one bit enables shifting in of the other bit into a vendor ID shift register. The configuration data is only accepted when the correct ID has been loaded into the register. The shift register could be optionally longer (the required vendor ID must be shifted in last for this to work), so that the vendors can differentiate between cards using their own scheme, without requiring a 40 bit register. I want this circuit to be as simple as possible, so that it can be done with descrete logic and you can make cards without any programmed devices. So what do you think? Should we make a standard? I'm going to try this circuit on a card I'm making (and leave space for the Xilinx prom in case there's a problem :-). I know I can get it to work on a PC- I'm not sure how easy it is to access configuration space in other systems though. -- /* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */ int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0) +r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2 ]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}Article: 7355
In a previous article jhallen@world.std.com (Joseph H Allen) writes: : ;It would be really nice if PCI controller FPGAs could be configured over the :PCI bus. One way of doing it is to use configuration writes with the fpga ;data encoded in the address. Why not just do it through JTAG.Article: 7356
I'm currently using a serial PROM for FPGA loading . This device is programmed with a file in the MCS (intel86) format. As we're going to transfer to S/W dowload of this file, we need to know the exact format of this file in order to extract the respective data, to be tranformed into a S/W driver. Does anyone know this format , or where it could be found ?Article: 7357
In article <5u7v21$5d8@neptune.myri.com>, Wen-King Su <wen-king@myri.com> wrote: >In a previous article jhallen@world.std.com (Joseph H Allen) writes: >: >;It would be really nice if PCI controller FPGAs could be configured over the >:PCI bus. One way of doing it is to use configuration writes with the fpga >;data encoded in the address. >Why not just do it through JTAG. I don't know anything about JTAG or JTAG on the PC. Is it board by board addressable? I'll have to learn more about it. -- /* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */ int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0) +r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2 ]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}Article: 7358
> The circuit could be added onto the PCI > lines which already go to the FPGA through large resistors, so as not to > violate the spec. You will have more than one load in that particular slot, which is a violation of the spec. Just routing the signal through a resistor does not change the number of actual loads. There is also a maximum trace length spec, and a maximum capacitance spec. Also, routing the signal through a resistor changes the rise and fall times of that signal...and may cause setup and/or hold time violations.... Austin Franklin darkroom@ix.netcom.comArticle: 7359
AS OF 8/31/97, THERE ARE 436 COMPANIES ON THIS LIST!! -- IMPORTANT NEWS FOR USERS OF GRAY'S SEMICONDUCTOR URL PAGES the only URLs that now work for accessing my site are as follows: http://www.scruznet.com/~gcreager http://www.scruznet.com/~gcreager/brief.htm (non-frame brief listing) http://www.scruznet.com/~gcreager/verbose.htm (non-frame verbose listing) -- Now, just a reminder to everyone... I have been compiling a semiconductor manufacturer website listing (and making it available to other engineers on the web) for over 2 years now. I used to post it to sci.electronics every so often in the past, but it has gotten way too big for that. There are 436 companies on the list currently. These are chipmakers who market chips under their own names, so if you can't find the data sheet that you need because you don't know the manufacturer's website, try my listing. Bookmark it and tell your co-workers!! I try to keep it the most up-to-date and useful listing of chipmakers anywhere on the web (by constantly searching for new URLs before most others find them) and it is now widely used by a lot of people. The following categories exist among my "engineering" subpages. - Semiconductor URLs (Brief listing) - Semiconductor URLs (Verbose listing; includes product categories) - New Semiconductor URLs - Missing Semiconductor URLs - Motivations - 25 Best Semiconductor Websites - 25 Worst Semiconductor Websites - Engineering Humor try it out, I think you'll find it to be quite useful. Let me know what you think. Again, the URL is: http://www.scruznet.com/~gcreager The website is best viewed in a frames environment, but there are "back doors" for getting to these pages if your browser doesn't support frames. Thanks for all the support everyone has given me in this endeavor! :-) Gray Creager -- ******************** PLEASE NOTE ********************* To respond to me, remove "no.spam.to." from the e-mail address reported above. Sorry for this inconvenience. ****************************************************** Gray Creager http://www.scruznet.com/~gcreager ******************************************************Article: 7360
In article <01bcb632$b7b9d300$35a8b8cd@drt1>, Austin Franklin <dark4room@ix.netcom.com> wrote: >> The circuit could be added onto the PCI lines which already go to the >> FPGA through large resistors, so as not to violate the spec. >Just routing the signal through a resistor does not change the number of >actual loads. There is also a maximum trace length spec, and a maximum >capacitance spec. The bus has a certain impedance: say 25 ohms (typical for a loaded bus). A load seperated from the bus through a big resistor R (even if that load is a transmission line) is going to have its effect reduced by 25/R. Suppose you can model the line on the circuit side of the resistor as a distributed capacitance of 15pF. If R is 100 ohms, the bus will see it as 3.75 pF. Of course, you want the resistors to be as close as possible to the short connection between the bus and the PCI controller (FPGA). >Also, routing the signal through a resistor changes the rise and fall times >of that signal...and may cause setup and/or hold time violations.... This is a more difficult problem. You want the resistors to be as small as you can get away with, all of the resistors to be equal in value (especially the one on the clock line), and the lines between the resistors and the configuration circuit to be as equal in length (and in every other characteristic) as possible. With a 100ohm resistor and 15pF load, the risetime is going to be no faster than 5ns. Since the window is only 7ns, the input capacitances have to be as matched as possible, since differences will effect skew to a greater degree than usual. You can actually pull off things like this. The best one I've seen so far is a cheap Cirrus Logic PCI VGA card. It cost only $27! How many PCI cards have you seen for only $27? They get it that cheap because it's only a two layer board (with only four chips total). A two layer board for PCI? Impossible and out of spec. you say! Well actually it is possible: the reason the PCI bus wants you to have a ground plain on your cards is to reduce inductive coupling. The return current part of an AC signal is the lowest impedance ground path from the destination of the signal to the bus (for DC it's the lowest resistance ground path). This incidentally is why you are supposed to decouple the 3.3V lines even if you don't need 3.3V: they provide more AC grounds. When you have a ground plain, this path is usually the part of the ground plain right under the signal trace. Without a ground plain, it's the loop made by the nearest ground trace and the signal trace. Unfortunately these loops are physically big and loops from other signals which share the common ground trace are right on top of each other, so there is crosstalk in the form of inductive coupling (which is additive if all the signal lines transition at the same time). So how do they get away with only two-layers on the VGA card? Well the strength of the inductive coupling also depends on the magnitude of the current through the loop. So... you guessed it... they put 50ohm series resistors on most of the signal lines (they did the 32 data bus lines). I also have a slightly older Cirrus Logic PCI VGA card: it also is only 4 chips, but it's a four layer board. It was more than double the price of this one (around $65 I think). -- /* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */ int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0) +r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2 ]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}Article: 7361
Ilan Ron <iron@radnet.co.il> wrote in article <3408F0C3.5503@radnet.co.il>... | I'm currently using a serial PROM for FPGA loading . | This device is programmed with a file in the MCS (intel86) format. | As we're going to transfer to S/W dowload of this file, we need to know | the exact format of this file in order to extract the respective data, | to be tranformed into a S/W driver. | | Does anyone know this format , or where it could be found ? | There is a utility available on the Xilinx web site that converts an Intel MCS file into the file format that you specify. For example, you can create data-byte statements for assembly code, C data structures, etc. There is a UNIX version ('makesrc.tar.Z') and a PC version ('makesrc.zip'). The download also includes some simple documentation. Also, for reference, you may want to look at the C source code provided on their web site ('dn_ld.zip'). However, this is for downloading a Xilinx bit file instead of an MCS file but the idea is the same. -- Steven Knapp OptiMagic(tm) Logic Design Solutions E-mail: sknapp @ optimagic.com Programmable Logic Jump Station: http://www.optimagic.comArticle: 7362
Sorry, I had drain bamage on the last posting. I forgot to include the full path names. Here we go again: There is a utility available on the Xilinx web site that converts an Intel MCS file into the file format that you specify. For example, you can create data-byte statements for assembly code, C data structures, etc. There is a UNIX version ('ftp://ftp.xilinx.com/pub/utilities/prom/makesrc.tar.Z') and a PC version ('ftp://ftp.xilinx.com/pub/utilities/prom/makesrc.zip'). The download also includes some simple documentation. Also, for reference, you may want to look at the C source code provided on their web site ('ftp://ftp.xilinx.com/pub/utilities/prom/dn_ld.zip'). However, this is for downloading a Xilinx bit file instead of an MCS file but the idea is the same. -- Steven Knapp OptiMagic(tm) Logic Design Solutions E-mail: sknapp @ optimagic.com Programmable Logic Jump Station: http://www.optimagic.comArticle: 7363
CELEBRATE A YEAR OF ACHIEVEMENT 1997 VSI FALL WORLDWIDE MEMBER MEETING October 3, 1997 (after the Embedded Systems Conference) Santa Clara, Calif. Free for members $150 for non-members JOIN US -- to see the progress of the working groups and begin to reap the benefits for system-level ICs. This meeting will begin the discussions of VSI specifications with members and with the industry. Keynote Speaker: Anant Agrawal Vice president and general manager of the performance products group, Sun Microsystems Microelectronics Division. The program runs from 9:00 until 4:00pm when parallel sessions for each of the six DWGs will begin, ending at 5:30pm. The YEAR OF ACHIEVEMENT party begins at 5:30pm. Don't miss it. You are invited to send as many representatives as you wish. The DWG break-out sessions at 4:00pm will be: --Design Implementation and Verification --High-level System Design --IP Protection --Mixed-Signal --On-chip Buses --Manufacturing Related Test. Please register in advance, by fax or email. The fax registration form can be downloaded here. Contact the VSI Alliance at: 15495 Los Gatos Boulevard, Los Gatos, CA 95032, USA phone: 1-408-356-8800 fax: 1-408-356-9018 email: nancy@vsi.org. Venue Santa Clara Marriott 2700 Mission College Blvd., Santa Clara, Calif. By special arrangement, a limited number of hotel rooms are available at the Marriott at a rate of $149, single or double occupancy per night. For reservations, call 1-800-228-9290 or 1-408-327-6808. Mention the "VSI Meeting";. The special priced rooms are available on the nights of October 2nd and 3rd. You must make reservations by September 11 to get this rate. Individuals are responsible for their own billing arrangements with the hotel. please register as soon as possible and indicate which DWG breakout session you expect to attend -- so we can make plans for a good meeting. Best regards, Stan Baker Executive Director, VSI AllianceArticle: 7364
Anyone have a clue, what is the simplest and most reliable means for exporting post-compile pinouts from Altera's MAX+II to OrCad or Protel, for generating a schematic symbol for board design? There must be a simple solution, since this is otherwise a horribly tedious, error-prone, and repetitive task. Thank you for your help! -- Bob Elkind **************************************************************** Bob Elkind mailto:eteam@aracnet.com 7118 SW Lee Road part-time fax number:503.357.9001 Gaston, OR 97119 cell:503.709.1985 home:503.359.4903 ****** Video processing, R&D, ASIC, FPGA design consulting *****Article: 7365
<snip> > You can actually pull off things like this. The best one I've seen so far > is a cheap Cirrus Logic PCI VGA card. It cost only $27! How many PCI cards > have you seen for only $27? <snip> > I also have a slightly older Cirrus Logic PCI VGA card: it also is only 4 > chips, but it's a four layer board. It was more than double the price of > this one (around $65 I think). Intel (who was a major player in the creation of the PCI spec) violates the spec. all the time. One prime example is their PCI Ethernet cards....they remove the unused pins from the PCI connector...which is clearly a violation of the spec. Look at pictures of their PCI NICs in any CDW, Insight, PC Complete etc. catalog... Many PCI cards on the market violate the spec, yet they still 'appear' to work. Working is not a very good test of PCI compliance. I 'believe' the scheme you have described does not meet the letter of the spec. I do not have the time to do a detailed analysis of it....but I would suggest you do before you decide to do this in a production board. For a prototype, it may work fine. Austin Franklin darkroom@ix.netcom.comArticle: 7366
I have read a few articles and papers about asynchronous design styles. All approaches make assumptions about delays (e.g. wire delays are significantly shorter than gate delays or a forked wire will have equal delays on both ends or even stronger requirements) or add too much overhead (ack/req-protocols for every register and function) or are not efficiently to implement on a typical FPGA architecture like the Xilinx family of FPGAs (e.g. the C-Element seem to be expensive). So I fear that there is no way to specify an asynchronous circuit with a high-level language like VHDL which is fed into optimizing tools like Synopsys and XACT. Instead the designer or the CAD tool has to control the placement and routing to make an asynchronous design. I would appreciate any hints on literature about asynchronous high-level design with FPGAs, if this is possible at all. The most promising approach seems to me "burst-mode asynchronous controllers" by Steven Mark Nowick, but I'm not yet sure if this is applicable to my problem or to FPGAs at all. Christian. -- PGP: pgp-public-keys@keys.de.pgp.net Subj: GET 0x73036211 Fingerprint: 33 20 99 54 66 C1 1C 32 D9 C1 BC F8 53 AF E4 C6Article: 7367
In article <01bcb7a4$227517f0$35a8b8cd@drt1>, Austin Franklin <darkroo4m@ix.netcom.com> wrote: >Many PCI cards on the market violate the spec, yet they still 'appear' to >work. Working is not a very good test of PCI compliance. I 'believe' the >scheme you have described does not meet the letter of the spec. I do not >have the time to do a detailed analysis of it....but I would suggest you do >before you decide to do this in a production board. For a prototype, it >may work fine. Well of course I'm still going to leave pads for the Xilinx prom. Also the resistors are basically going to be right on top of the lines between the bus and the FPGA, so if they're not in, there are no stubs. This is a low volume vertical market product (as most FPGA designs are) anyway. One the positive side, 74ACT chips only have 4pF input capacitance and much better setup time requirements than the FPGA, so the resistors can be pretty big. Without the vendor ID detector, the circuit is only four standard chips. The clock line has to go to three of them though, so it needs a smaller resistor or has to be buffered. -- /* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */ int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0) +r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2 ]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}Article: 7368
Hello, I'm looking for some info/parts to do the job of interpolating and decimating a US/Euro HDTV digital stream. In the past I've used the Raytheon TMC2242 to do this on CCIR streams. any suggestions? chad.Article: 7369
I have previously mentioned a Xilinx App Note on synchronous and asynchronous FIFOs, available on the Xilinx web page as XAPP051. Here is an improvement, better called a fix, that makes the coding of the address counters truly Grey, and thus avoids any glitches. I apologize for the format, the logic looks ugly in its ASCII form, but in the 4-input look-up-tables it is very simple and compact. If anybody has a problem, send me e-mail. If you don't use XAPP051, ignore this long posting. Peter Alfke, Xilinx Applications ================================= Asynchronous FIFO Here is an improvement to XAPP051: “Synchronous and asynchronous FIFO designs”. The decoding of Full and Empty, shown in Figure 4, can generate glitches, because the 4-bit address counters have more than one simultaneous transition. ( The two upper and the two lower address bits are individually Grey-coded, but over the whole address, there are two bit changes at every quadrant border.) This can easily be changed as shown below. This change affects only Figure 3. Since each counter bit is driven by a 4-input function generator, the count sequence can be freely adjusted. New count sequence for read and write counters: 3210 0000 0010 0011 0001 1001 1000 1010 1011 1111 1101 1100 1110 0110 0111 0101 0100 0000 etc The true hardware cost of this improved design is identical to the original design: Each counter fits into two CLBs. D0= ( Q1 •Q0 ) + ( Q1•Q2bar ) + ( Q1•Q3bar) + ( Q0•Q2bar•Q3bar ) D1 =( Q0bar •Q3 ) + ( Q0bar•Q2bar ) + ( Q0bar•Q1) + ( Q1•Q2bar•Q3 ) D2 = ( Q2 •Q3 ) + ( Q2•Q1 ) + ( Q2•Q0) + ( Q0•Q1•Q3 ) D3 = ( Q3 •Q1bar ) + ( Q3•Q2bar ) + ( Q3•Q0 ) + ( Q0•Q1bar•Q2bar ) ========================================= Figure 7: 32--deep FIFO, Read Counter or Write Counter 43210 00000 00010 00011 00001=A, an auxiliary signal, used in the equations below 00101 00100 00110 00111=A 10111 10101 10100 10110=A 10010 10011 10001 10000=A 11000 11010 11011 11001=A 11101 11100 11110 11111=A 01111 01101 01100 01110=A 01010 01011 01001 01000=A A = ( Q1 XNOR Q2 ) AND ( Q0 XOR ( Q3 XOR Q4 )) D0 = ( Q1 AND Abar ) OR ( Q0 AND A ) D1 = ( Q0bar AND Abar ) OR ( Q1 AND A ) D2 = [( Q3 XNOR Q4 ) AND A ] OR (Q2 AND Abar) D3 = {[( Q2 AND Q3 ) OR ( Q2bar AND Q4 ) ] AND A } OR ( Q3 AND Abar) D4 ={[(Q2 AND Q3bar ) OR ( Q2bar AND Q4 )] AND A } OR (Q4 AND Abar ) ======================= Figure 10: 64--deep FIFO, Read Counter or Write Counter 543 210 000 000 000 001 000 101 000 100 000 110 000 111 000 011 000 010=A, an auxiliary signal used in the equations below 001 010 001 000 001 001 001 101 001 100 001 110 001 111 001 011=A 101 011 101 010 101 000 101 001 101 101 101 100 101 110 101 111=A 100 111 100 011 100 010 100 000 100 001 100 101 100 100 100 110=A 110 110 110 111 110 011 110 010 110 000 110 001 110 101 110 100=A 111 100 111 110 111 111 111 011 111 010 111 000 111 001 111 101=A 011 101 011 100 011 110 011 111 011 011 011 010 011 000 011 001=A 010 001 010 101 010 100 010 110 010 111 010 011 010 010 010 000=A A= ( Q1 XOR Q4 ) AND ( Q0 XNOR Q3 ) AND ( Q2 XNOR Q5 ) D0 = [( Q1 XNOR Q2 ) AND Abar ] OR ( Q0 AND A ) D1 ={ [(Q0bar AND Q2) OR ( Q0 AND Q1 )] AND Abar} OR ( Q1 AND A) D2 = {[(Q0 AND Q1bar)OR( Q0bar AND Q2)] AND Abar}OR(Q2 AND A) D3 = [( Q4 XNOR Q5 ) AND A ] OR ( Q3 AND Abar ) D4 = {[(Q3bar AND Q5) OR ( Q3 AND Q4 )] AND A} OR ( Q4 AND Abar) D5 = {[(Q3 AND Q4bar)OR( Q3bar AND Q5)] AND A}OR(Q5 AND Abar) ================================= Summary: This improves the address count sequence for 16, 32, and 64--deep FIFOs, so that only one counter bit changes at any transition. This avoids all spurious decoding glitches that might affect the asynchronous detection of FULL and EMPTY. This version increase the CLB count only for the 64-address counters by one CLB, and it does not affect any of the control structures. For any questions, please send e-mail to: peter@xilinx.comArticle: 7370
Are you sick of all the Home Business hype? Most of them are either too expensive or so complicated that you can't explain them to other people. Are you ready for a simple Home Business that makes sense? A business that doesn't monopolize all of your time. That requires No: Stocking, Selling or Delivery. No: billing or collections. No: complicated paperwork. No: employees to pay. No: contracts to sign, you can quit any time. There is a one time $29 enrollment. There is never any new money spent after that. If you decide that this business is not for you simply return the business kit within 60 days for a full refund. Tens of thousands of people have been able to make this their full time business in a reasonably short amount of time. This is not "get rich quick." This is a highly reputable company that opened in 1985. I will send you details on this company when you e-mail me for information. God forbid, but if something should happen where you couldn't work or a loved one became ill and you had to stay home to care for them, would you be able to? Would your company keep paying you? Nobody likes to think about these things, but they do happen. And unless you have great insurance you may want to consider this business. You've nothing to lose by asking for information. I'll be happy to send it to you. The fact is, if you are trading time for money your income is temporary, ( even if you own the company.) The average person works from paycheck to paycheck with little or nothing left over to save or invest. This business can help you break the paycheck to paycheck cycle. For information email me at rramsey36@aol.com or rgr@freedomnet.comArticle: 7371
Peter Alfke <peter@xilinx.com> wrote in article <3406BCBE.42F0169C@xilinx.com>... > > Slow designs you can do in a generic fashion, but for really high > performance, you need to decide on a particular manufacturer's part and > development system. Luckily the decision often narrows down to only a > few contenders, sometimes only one. Near the end of the alphabet. > :-) > > Peter Alfke, Xilinx Applications > > interesting to note that there a lot of parts at each of the two ends of the alphabet. then again, i guess you said 'near' the end not 'at' the end ;) rkArticle: 7372
I know, I know, your supposed to instantiate memgen components but ... Exemplar's Leonardo claims to be able to infer single port RAM in 4000e devices. Has anyone been able to make this work. I sent my test code in to exemplar and they couldn't make it work with version 4.03 (what I have) but claim lots of people do it with this version. Is this true ? Anybody out there make this work? I'll attach my test code which they don't understand why it doesn't work. (I'm currently working the support issue, we buy our licenses from Mentor so Exemplar doesn't want to help.) Thanks, -- ______________________________________________________________ Allan Redenbaugh allan@ti.com Raytheon TI Systems voice : (972) 575-7764 P.O. Box 869305 M/S 8454 fax : (972) 575-6965 Plano, TX 75086 ______________________________________________________________ LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.all; PACKAGE vdm IS subtype Vid_Type is signed (11 DOWNTO 0); END vdm; LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE work.vdm.ALL; ENTITY test IS PORT (clk : IN std_logic; addr : IN integer RANGE 3 DOWNTO 0; data_A : IN Vid_Type; data_B : IN Vid_Type; data_C : IN Vid_Type; data_D : IN Vid_Type; dout_A : OUT Vid_Type; dout_B : OUT Vid_Type; dout_C : OUT Vid_Type; dout_D : OUT Vid_Type ); ATTRIBUTE clock_node : boolean; ATTRIBUTE clock_node OF clk : SIGNAL IS true; END test; ARCHITECTURE synth OF test IS TYPE Mem_Word IS ARRAY (3 DOWNTO 0) OF Vid_Type; SIGNAL mem_A, mem_B, mem_C, mem_D : Mem_Word; SIGNAL we : bit; BEGIN we <= '1'; write_proc: PROCESS(clk) BEGIN IF clk'event AND clk = '1' THEN IF we = '1' THEN mem_A(addr) <= data_A; mem_B(addr) <= data_B; mem_C(addr) <= data_C; mem_D(addr) <= data_D; END IF; END IF; END PROCESS; dout_A <= mem_A(addr); dout_B <= mem_B(addr); dout_C <= mem_C(addr); dout_D <= mem_D(addr); END;Article: 7373
Uwe Bonnes wrote: > > In comp.lang.vhdl Kevin Bush <kevin.bush@minc.com> wrote: > : ANNOUNCEMENT: > > : MINC is now offering a full-featured VHDL synthesis engine for $495. > : VHDL EASY(tm) is VHDL-93 and IEEE 1076 compliant and uses a combination > : of > : proprietary and industry standardsynthesis and optimization > : methodologies > : including: > > Is it available for Linux? > > -- > Uwe Bonnes bon@elektron.ikp.physik.th-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- VHDL EASY is currently available for Windows 95 and Windows NT, although we are considering Linux. We still need to look at the impact on our GUI, etc. What other EDA type tools are available on Linux? Kevin Bush, MINC kevin.bush@minc.comArticle: 7374
SNUG '98 Call For Papers ------------------------------ WHAT: Eighth Annual Synopsys Users Group (SNUG '98) WHEN: March 11th-13th WHERE: Double Tree Inn, San Jose, CA (formerly the Red Lion Inn) An Invitation to Contribute SHARE Your Experiences! The success of a user's group depends on the active participation of users who are willing to share their experiences with others. If you have information on High-Level Design methodology or experiences with Synopsys tools that would be of interest to other users, you are encouraged to present in one of the sessions described below. Preliminary User Breakout Sessions These sessions are always the hit of the conference. Hear Synopsys users' experience on specific topics. Each user breakout session will consist of three presentations, twenty-five minutes each, with another five minutes for questions and answers. Preliminary topics include: *Synthesis/Design Productivity Strategies, experiences, and best practices for design productivity with an emphasis on synthesis. Automation and Optimization techniques for synthesis. *High-Level Verification Verification strategies covering design for test and system-level verification. Users share experiences in developing a test bed to verify the combined hardware and software systems. Design for test strategies for complex, large designs. *Higher Levels of Abstraction / Behavioral Synthesis This sessions covers real-world experiences in making the transition to high-level design. Topics include the methodology for top-down design, behavioral synthesis, & high-level techniques for DSP design. *Deep Submicron / Large Designs Concentrating on the unique challenges of submicron and large designs. Sessions provide experience with automating scripts for submicron, special techniques for managing wireloading, floorplanning, and non-linear delay modeling. *Makefiles/Synthesis Scripting This is a popular session that was added to SNUG last year to address the increased effort to automate and extend the synthesis process through scripting. The session includes case studies by users that have taken advantage of the power of Make and Perl drive synthesis iterations and to extend DC Shell. *Configuration Management Management of files and directory structures is a big key toward design success. This session will explore approaches or methods like MAKE used to manage the complex designs of today. *Design Reuse This session includes a practical methodology for design reuse based on real-world experience. Issues and guidelines are explored. *FPGA Synthesis This year a new session will be added that will focus directly on synthesis of FPGAs. Tricks and techniques used for designing and synthesizing FPGAs will be presented. Experiences with FPGA Express will also be included. To present your experiences with a contribution in an user session, please forward a summary or brief description of your idea to the conference Technical Committee, (snug_tech@synopsys.com), by October 1, 1997. You will be notified of your acceptance shortly afterwards. A Technical Committee member will work with each author to develop and review the paper and presentation. Please review the Author's kit posted on the Synopsys web site for details on paper format and structure. Final drafts are due by January 5, 1998. Final papers are due for publication in the SNUG proceedings by February 2, 1998. A Preliminary SNUG '98 Schedule Wednesday, March 11th Morning 1/2 day Tutorial Sessions Afternoon Industry related Panel Discussion Evening R&D Cocktail Party /Synopsys New Product Demos Thursday, March 12th Morning Executive Status Morning/Afternoon User Breakout Sessions Evening Cocktail Party / Vendor Fair Friday, March 13th Morning 1/2 day Tutorial Sessions Who to Contact Should you wish to discuss your potential contribution, please feel free to contact your local Synopsys applications engineering manager or the SNUG'98 Technical Committee via email at: snug_tech@synopsys.com All email sent to this alias will be reflected to User Group Technical Chairperson and the Technical Committee. These addresses are NOT for basic information on attending the conference itself. Don Mills, Renae Cunningham, SNUG '98 User Chairman SNUG '98 Synopsys Program Manager 640 North 2200 West 700 E. Middlefield Road MS F1-J12 Mtn. View, CA. 94043 Salt Lake City, UT Fax: 415-965-2539 Phone: 801-594-3270 renae@synopsys.com donald.r.mills@lmco.com =========================================================================== Trapped trying to figure out a Synopsys bug? Want to hear how 5459 other users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)! !!! "It's not a BUG, jcooley@world.std.com /o o\ / it's a FEATURE!" (508) 429-4357 ( > ) \ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys, _] [_ Verilog, VHDL and numerous Design Methodologies. Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222 Legal Disclaimer: "As always, anything said here is only opinion."
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