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Anyone have any information on doing a PC Keyboard controller (ala 8042?) in a Xilinx? Any information would be appreciated. Austin Franklin darkroom@ix.netcom.comArticle: 6701
Hello everybody, We are a group of undergraduates students doing this project from scratch :>. We have got some books on topics like VHDL and DES, and now we are facing with the uncertainty question - what material / instruments we need for testing and implementation? (A Xilinx 4000 series FPGA will cost more than US$100, and we don't have the money for _try and error_.) At hand now we have the following stuff: 1. Synosis 2. 1 Xilinx 4003 FPGA + corresponding programming tools 3. Reference on DES algorithm We planned to buy lots of FPGA for parallel processing, but we need to make sure that we are not buying the wrong one. How can we make sure that a VHDL program can fit into one FPGA? Counting number of gates/CLB or some other stuff? Is there a clear cut solution for that? If you have some experience or suggestions on that topic, please help. :> ------------------------------------------------------------------------------- | Best Regards, +--------+ | Campus: eg_hsh@stu.ust.hk | | David Ho | ¦ó²Ðºµ | | cshosh@cs.ust.hk | | Ho Siu Hung +--------+ | Home: david.ho@cb.yonet.org | | University of Science and Technology | Poly U: tc404321@hkpucc.polyu.edu.hk | | Computer Engineering Year II(CPEG) =======================================| -------------------------------------------------------------------------------Article: 6702
Hi, we are trying to map a (running) design from the xc4000 to xc4000e. We are using a clk-pin. Unfortunaly synopsys maps an unconstraint clk to one of these SGCK's. BUT we want to use PGCK, so we have to place a BUFGP in our top-level-modul. So far so well. Now we have changed all our references from xc4000 to xc4000e. While elaborating the warning 'can't find the architecture BUFGP(FTGS) in the library xc4000e' comes out. Is there a replacement of BUFGPs to xxx in the xc4000e-lib or do we have to include the xc4000-lib also? ========================================================== EMail: mailto:hp@e-technik.uni-rostock.de www: http://www-md.e-technik.uni-rostock.de/ma/hp/hp.htm Hagen Ploog University of Rostock Tel.: (++49 +381) 4983534 Institute of AM and CS (EE-Dep.) Fax.: (++49 +381) 4981126 Richard-Wagner Str. 31 18119 Rostock-Warnemuende GermanyArticle: 6703
I am attempting to communicate with a Giga Ops FPGA board using Java and am starting from ground zero. Please post information requested below: 1) Do yo actually think that it is possible to communicate with an FPGA board connected to a PC on the internet using java from a remote site? 2) Do you know of any persons (send email and/or telephone numbers) that may know anything about this? 3) Can java code be written to read/write specific memory locations on a remote machine? Clay Gloster gloster@eos.ncsu.eduArticle: 6704
TROLLING FOR USER DAC DIRT!
---------------------------
It's once again that time of year, folks! For those of you who went
to last week's DAC in Anaheim, I'd like to ask you for your impressions
for the Fifth Annual ESNUG/DAC Awards. Please write me what you thought
(and, yes, you'll be ANONYMOUS.) What did you think was the best/worst/
whatever DAC party, and why? Technically what was the most interesting EDA
product/tool you saw on the DAC floor and why? The worst? The <make your
own category> product? What was the biggest lie you heard from an EDA
salesman and why? What was the best personal quote? The best/worst/
whatever DAC panel/paper/talk and why? Which vendor had the best DAC
booth and/or floor show? The worst? The stupidest? The most content-free?
What were the hottest EDA tools you saw from the Big Five (Cadence, Mentor,
Synopsys, ViewLogic, Avant!)? What did they offer that was lame? What
were the hottest EDA tools you saw from the smaller EDA vendors? What was
lame? What's the most interesting thing you saw in a NDA suite?
.... AND CALLING ON THE DARK SIDE, TOO!
----------------------------------------
Since turnabout is fair play, I like to add some voices from the "Dark
Side" (the EDA vendors themselves) about what *they* saw in the customers
at this year's DAC. Of course, you'll also be anonymous, too! What is
your most troublesome customer story? What was the most outrageous
customer request you got at DAC? Did the customer get it? Whose products
do you wish you were selling? Whose are glad you're not selling? What
was the most ridiculous claim you saw an EDA vendor try to make at DAC?
"John, I Just Wrote This Trip Report..."
----------------------------------------
Yes, if you wrote a trip report and would rather just forward that to
me, cool! I take the Keeping-My-Anonymous-Sources-Anonymous business very
seriously. What I'm seeking are real impressions about the industry -- not
saying who had these impressions. Please! Tell me what you saw and what
you thought about it!
- John Cooley
Part Time EDA Consumer Advocate
Full Time ASIC, FPGA & EDA Design Consultant
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 5409 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
Article: 6705FS: CADKEY '97 (8.0)-100+ Available- Save $HUNDRED's EACH!!! Hello! A new copy of Cadkey '97 is selling on the street for $1,195. To guarantee updates for the next year costs $350 more, bringing it up to $1,545 total! We have available over 100 NEW copies of Cadkey 6.0 on CD for DOS in unopened, shrinkwrapped boxes with all manuals & documentation; which can be upgraded to Cadkey '97, INCLUDING the year's worth of free updates, for the street price of $595. That's $950 LESS than the normal street price! Or, maybe Cadkey 6.0 has enough power for you with no upgrade at all! (Cadkey '97 is basically Cadkey 8.0) We're selling these for best offer, one or all, so please send your best offer on out to us! If you would like more info on Cadkey 97, here's Cadkey 97's Web page: http://www.cadkey.com/cadkey/index.htm Thanks! Karl Kristianson DreamQuestArticle: 6706
Eric Ryherd wrote: > We had a lot of problems donwloading to XC4000 parts. > Often we had to download 2 or 3 times and it would eventually > work (we sometimes had to power cyle too). > Never got an explanation from Xilinx but the newest > HardwareDebugger does seem to work quite reliably via I second that. I think that Xcheckers can have LatchUp effects if you don't apply power to your prototype before turning on your pc. Sometimes there are situations where it simply does not work. I found that it then draws more current ( i remember something like an extra 150 mA ) and heats up a bit. My whole population of 3 Xcheckers shows this behaviour. It seems to depend somewhat on the RS232 port. Since i don't want to power down my pc whenever i play with the prototype, i now use my own download program and the printer port. So, if you have Xchecker trouble, try the proper power up sequence. Maybe it helps. Gerhard -- Gerhard Hoffmann dk4xp remove the nospam from my email address.Article: 6707
: We are a group of undergraduates students doing this project from scratch : :>. We have got some books on topics like VHDL and DES, and now we are : facing with the uncertainty question - what material / instruments we need : for testing and implementation? (A Xilinx 4000 series FPGA will cost more : than US$100, and we don't have the money for _try and error_.) : : At hand now we have the following stuff: : : 1. Synosis : 2. 1 Xilinx 4003 FPGA + corresponding programming tools : 3. Reference on DES algorithm : : We planned to buy lots of FPGA for parallel processing, but we need to : make sure that we are not buying the wrong one. How can we make sure that : a VHDL program can fit into one FPGA? Counting number of gates/CLB or : some other stuff? Is there a clear cut solution for that? : Ho - Here are a few suggestions: 1. See if you can locate a paper written on the subject of DES attack using ASICS. I had a copy once, but I can't find it :( It has a lot of good info. I *think* it was written by someone at BNL. 2. Get a VHDL simulator (maybe you already have it as a part of Synposys?) and use it to simulate your system before you start building anything. You can model each FPGA in VHDL and use a structural VHDL netlist to tie the VHDL models of the FPGAs together. You cab also model other parts of your system such as RAM in VHDL as well. If you write "RTL" VHDL and use conservative design techniques (synchronous logic), you should be able to go from the VHDL model stage to the synthesized design stage without too much trouble. 3. To figure out if the logic will fit into you FPGA, the ultimate sure fire way is to actually synthesize the design and try to route the design. A few iterations will get you to the point where you'll know about how much will fit into your devices. 4. Be sure to talk to your CAE tool vendors (Synopsys, Xilinx) about getting access to application notes and design examples. Synopsys, for example, has the solv-it help system which is full of useful stuff on logic systhesis. It sounds like a neat project with lots of opportunity for fame and glory! :) Good luck! Regards, Keith -- Keith Outwater Primex Aerospace Company (formerly Olin Aerospace Company) P.O. Box 97009 Redmond, WA 98073-9709 (425) 885-5010 x6606Article: 6708
I am looking for PCI interface devices and/or fpga cores. does anyone have a list of such parts? -- Greg Quintana M/S 3USQ Hewlett-Packard Company Santa Rosa Systems Division 1400 Fountaingrove Pkwy Santa Rosa, CA 95403 Voice (707)577-2460 Fax (707)577-5644 Internet gregq@sr.hp.comArticle: 6709
Brian Heber (lnusdyt1.zzvczs@gmeds.com) wrote: : I'm trying to interface a TMS320C5x with a Xilinx 4k FPGA and : I'm looking for anyone who might have done something similar. I put together a project using an MC68340 and an XC4005 where the processor configures the FPGA using slave parallel mode and then communicates with it over the processor bus. I can send you a photocopy of the board schematics/FPGA design/software if you think it would help you out. Eric CrabillArticle: 6710
testArticle: 6711
testArticle: 6712
Hello, I want to use 6000 family of lattice or equvalent fpga of another companys. Can you suggest any hardware and software devolopment tools for this serie. Thanks.Article: 6713
crabill@leland.Stanford.EDU (Eric Jay Crabill) writes:
>Brian Heber (lnusdyt1.zzvczs@gmeds.com) wrote:
>: I'm trying to interface a TMS320C5x with a Xilinx 4k FPGA and
>: I'm looking for anyone who might have done something similar.
>I put together a project using an MC68340 and an XC4005 where the
>processor configures the FPGA using slave parallel mode and then
>communicates with it over the processor bus. I can send you a
>photocopy of the board schematics/FPGA design/software if you
>think it would help you out.
>Eric Crabill
I have a XC4006 on a 68360 bus, and a 4028XL on a DSP56302 bus.
I program them through GPIO outputs from the 68360 (6 pins a piece).
The beauty of these things is that the interface is completely
flexible.
Basically, all you have to connect are address, data, Read/Write.
This depends on the processor, though. Some (like the 68360 and 56302)
have programmable address decoders on chip so you don't need to
decode all the address lines.
Cheers,
Jake
--
janovetz@coewl.cen.uiuc.edu| Once you have flown, you will walk the earth with
University of Illinois | your eyes turned skyward, for there you have been,
| there you long to return. -- da Vinci
PP-ASEL | http://www.cen.uiuc.edu/~janovetz/index.html
Article: 6714I must do a work about 'FPGA Aplications' at my University, and I know only a little about FPGAs. Please, if any of you could send some general (not too high level) information about this topic (FPGA and FPGA aplications) I'd be very grateful.I`ve search at Xilinx web-page, but it`s a little complex. Thanks in advance NachoArticle: 6715
Simon Bacon wrote:
>
> Does anyone know how to use an XCHECKER cable to reliably download a
> configuration to a Xilinx 9600 CPLD?
>
> The Xilinx documentation is perfectly clear on how to do it, but
> it doesn't work reliably, as Xilinx acknowledge. Frequently, it
> doesn't work at all.
An EZTAG patch has recently been developed to fix this problem.
Basically, the patched version will download a new bitstream to
the FPGA inside the XChecker pod.
You can find this patch at ftp://ftp.xilinx.com/pub/swhelp/cpld/ .
It sounds like you are using a PC, so the file you want to
download is eztag_pc.zip (HP and Sun versions are also available.)
> I am posting because Xilinx tech support
> cannot or will not answer email.
I was unable to locate a Technical Support case in your name.
The manager of our support center in the UK will be contacting you
soon to help discover what happened with this issue.
--
=====================================================================
/ /\/ Ruth Mayeda E-mail: ruth.mayeda@xilinx.com
\ \ Applications Engineer Tel: 1-800-255-7778
/ / Xilinx, Inc. Fax: 1-408-879-4442
\_\/\ 2100 Logic Drive Web: http://www.xilinx.com
San Jose, CA 95124
=====================================================================
Article: 6716Nacho wrote: > > I must do a work about 'FPGA Aplications' at my University, and I > know only a little about FPGAs. Please, if any of you could send some > general (not too high level) information about this topic (FPGA and FPGA > aplications) I'd be very grateful.I`ve search at Xilinx web-page, but > it`s a little complex. > > Thanks in advance > > Nacho FPGAs are essentially an array of uncommitted logic cells which the designer can define and connect to produce arbitrary logic functions. In a way the fpga is canvas on which the designer can do his craft....Well, OK, with the architectural limitations, it is a little more akin to a coloring book. (Of course, once you know the limitations, you can use the limitations to your advantage). The logic cells vary in complexity and function. Some of the "fine grain" devices have many cells that can only implement logic functions with 2 or 3 inputs, while others use fewer more complex cells with as many as a dozen or more inputs. The cells themselves may be look up tables where the inputs are essentially address lines to a small memory, and the output is the data from the memory. The stored data is patterned to realize the desired logic function. Normally the data is written to these look up cells only when the device is programed or configured. Some of the devices permit the logic to modify the data, thus providing a memory function in the array. Other arrays use combinations of logic consisting of multiplexors or and-or type arrays controlled by a configuration program to realize the logic (this is typically true of the fine grain architectures) The interconnect between logic cells is a combination of metal wires and any one of several types of programmable switches between wire segments. The switches may be fuses, anti-fuses, or pass transistors. The vast majority of FPGAs are currently used to gather random logic into a single chip. While this is not a very interesting application, it is where the bulk of the devices are used. Recently, there has been more interest in using the FPGA as a processing element in signal processing and computing (I have been involved in this end since around 1990). These applications are becoming more popular mostly because of the increased density of the FPGA devices. Some of the applications I've used FPGAs for include: Video display controllers, Radar signal processors (quadrature demodulation, correlation, magnitude processing [cartesian to polar conversion], complex noise generation-gamma and gaussian distributions, hardware sorting, FIR and matched filtering, quadrature numerically controlled oscillators), image processing including feature recognition and pattern matching, smart card readers, keyboard controllers, audio processors (filtering, tone generation) and communication interfaces. As you can see, some of the applications get to be pretty interesting. -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://www.ids.net/~randrakaArticle: 6717
Austin Franklin wrote: > > Anyone have any information on doing a PC Keyboard controller (ala 8042?) > in a Xilinx? > > Any information would be appreciated. > > Austin Franklin > darkroom@ix.netcom.com Austin, It's actually pretty simple. The hardest part is getting your hands on the interface spec. I did a keyboard controller a few years back in part of a 3042A (I think that's what it was) that interfaced a membrane keypad and a barcode reader to a PC keyboard port. Unfortunately, I don't have the design details anymore on it (I don't own that design). Get a hold of "PC Keyboard Design" by Gary J. Konzak and put out by Annabooks (ISBN 0-929392-12-4). It is has a fairly complete description of the interface protocol and electrical considerations. It also discusses debounce and key scanning, but is slanted at a microcontroller implementation (like the 8042). For debounce in hardware, you need to make a state machine that samples the key matrix multiple times after it detects a closure. A decent debounce restarts a timer each time it sees a transition on the key row/column then reads the value from the row/column when the timer expires. A simple controller can just drive rows and stop when it senses a closure at the column, then resample some time later. The resulting row/column combination corresponds to the pressed key. If you want multiple key rollover and elimination of phantom keys you need to get a little more creative (requires continuing scan, storage for multiple row read values and some logic to deduce which columns are phantoms. phantoms are best deduced by driving the row and column alternately). The 8042 sends a unique key press and a unique key release code for each key. Hope this helps. -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://www.ids.net/~randrakaArticle: 6718
Is the APS-X84 kit as good as it looks on http://www.erols.com/aaps/ ? I'd like to experiment a bit with various algorithms and this looks as if it would suffice, while the price does not hurt much. However, since I'm new to FPGAs, I'm not at all sure I can tell. Any comments would be much appreciated. Thanks, -ninoArticle: 6719
Karl Kristianson wrote: > > FS: CADKEY '97 (8.0)-100+ Available- Save $HUNDRED's > EACH!!! > > Hello! > > snip > > We have available over 100 NEW copies of Cadkey 6.0 > on CD for DOS in unopened, shrinkwrapped boxes with > all manuals & documentation; which can be upgraded > to Cadkey '97, INCLUDING the year's worth of free > updates, for the street price of $595. > > That's $950 LESS than the normal street price! > > SNIP > Karl Kristianson > DreamQuest THIS IS BULLSHIT! This jerk is trying to sell obsolete software for the original price. Most resellers of out-of-date software offer heavy discounts. DON'T DO ANY BUSINESS WITH THIS RIPOFF ARTIST! --Article: 6720
Nacho wrote: > > I must do a work about 'FPGA Aplications' at my University, and I > know only a little about FPGAs. Please, if any of you could send some > general (not too high level) information about this topic (FPGA and FPGA > aplications) I'd be very grateful.I`ve search at Xilinx web-page, but > it`s a little complex. > > Thanks in advance > > Nacho Hi Nacho, I'm much lazier than Ray so I give you only a link. Try looking at http://www.vcc.com/fpga.html#fpga for an overwiev, or http://www.mrc.uidaho.edu/fpga/fpga.html for other FPGA related sites (thers's a link to Ray's home page too). Cheers, Botond -- Kardos, Botond - at Innomed Medical Ltd. in Hungary eMail: kardos@mail.matav.hu phone/fax: (0036 1) 351-2934 fax: (0036 1) 321-1075Article: 6721
Does anyone have expericence brewing custom tools for Xilinx 4K? Also, is there information on the EDIF output needed for this? (I have the XNF information, but I'd rather use EDIF since XNF is going to be obsoleted). -- Nicholas C. Weaver "Trouble will come in its own time. It always nweaver@cs.berkeley.edu does. But that is tomorrow. Give me http://www.cs.berkeley.edu/~nweaver/ today and I will be happy." It is a tale, told by an idiot, full of sound and fury, .signifying nothing.Article: 6722
;In article <EBqKos.1A2@world.std.com>, jhallen@world.std.com (Joseph H Allen) writes: : I want to connect 4 SDRAMs (in a 2M x 32 configuration) to a XC40XXE in such ; a way that I can do a full speed 100MHz continual write to the SDRAMs (reads : can be slow). All signals will come from the fpga including data, address, ; control and clock. All signals except clock will use the pad flip flops. : Each data line originates from another fpga input pin, and goes through only ; a single CLB (and it can use that CLB's flip flop as a pipeline register). : The data rate and SDRAM clock will be 100MHz. The SDRAMs are 3.3V parts and ; the xilinx is 5V, but with TTL output levels. : ; Has anyone tried this? Did it work? 100MHz seems fast for the control : logic, but no state machines actually have to go at that rate (only 50MHz or ; maybe less). The data paths do have to work though. Your problem will be with "TTL output levels". There is no guarantee that it will not source a significant amount of current at VOH = 3.3V + forward biased drop of the protection diode on the SDRAM's pads.Article: 6723
Hi, has anyone experience with the Passive Paralell Active configuration of the Flex 8000 devices ? I have an EPF8282ALC84-4 and a Hitachi H8/3048F uC in a design. The uC configures the FPGA via PPA, everything seems to be fine, nCONF_DONE goes high. In user mode every pin of the FPGA I've tested works as expected. So everything's OK except for one tiny thing: I just can't make the DCLK pin drive out the internal clock signal. I've managed to do it earlier with the APU configuration but in this case the DCLK pin simply goes high and does nothing. The problem is that in the current stage of my design I'm not sure whether the proper signals travel on the data bus during configuration. Could this problem with the DCLK pin indicate that something's wrong with the configuration, or is it normal, that after a PPA process the DCLK pin stucks to Vcc ? (The DCLK pin is left unconnected in the PPA and also in the APU design.) Thx for any help in advance, Botond -- Kardos, Botond - at Innomed Medical Ltd. in Hungary eMail: kardos@mail.matav.hu phone/fax: (0036 1) 351-2934 fax: (0036 1) 321-1075Article: 6724
Kardos, Botond (kardos@mail.matav.hu) wrote: : has anyone experience with the Passive Paralell Active configuration : of the Flex 8000 devices ? I guess you mean Passive Parallel Asynchronous (not Active) ? : expected. So everything's OK except for one tiny thing: I just can't : make the DCLK pin drive out the internal clock signal. I am not using the DCLK output, but driven by your note, I've just hooked the scope to that pin and it seems to work for me (I am using EPF8636ALC84-4 device). I get the square wave freq. ca. 2.7MHz : Could this problem with the DCLK pin indicate that something's wrong : with the configuration, or is it normal, that after a PPA process the : DCLK pin stucks to Vcc ? I would rather guess that it has to do with the device options. Make sure that the the device option "Enable DCLK output in user mode" is checked before the compilation. hope this helps, Ilija
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Compare FPGA features and resources
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