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Rod, > > I have been doing a Xilinx XC4013E PCI design using the PCI Logicore. I > have been doing the design as a mixed schematic/VHDL design. Most of my > memory elements and FIFOs internal to the FPGA are done in the > Xilinx/Viewlogic schematic models and I create the controls to these > using VHDL. I have been functionally simulating my VHDL using the > Viewlogic Fusion/Speedwave VHDL functional simulator. I have > functionally simulated my design and it seems to be working quite well. Using VHDL (or any HDL for that matter) to try to get 33MHz out of a Xilinx design is quite a chore....I would sure like to know if you were able to do it... It would also be nice if you could report to this group how the Logicore (whether it is just target, or is also a master) worked for you. Mind you, it may look good in simulation, but it would be better to hear if it worked after testing it out with bridge chips, and different motherboards etc. Thanks, Austin Franklin darkroom@ix.netcom.comArticle: 6826
Hi there,
Could any body tell me what are at the moment the larger devices of the
40xxE and 40xxEX series available. I now a 4025 is very much in use,
but I would like to know if the higher gate count devices like
4036EX, 4044EX, ... are already easy to get, and if they are already
supported by tools like Synopsys-fpga compiler ??
Do you know if there exists pin-compatible versions of the larger ones
to the 4025E or 4036EX ?? If my design-modules don't fit in one, I
could try to get a higher density part without making a new board ?
Does any body know if prototype boards with at least 4 to 6 of these
large devices are available (with the possibility to add some glue
logic to them) ?
Thanks.
--
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Article: 6827Reetinder P. S. Sidhu wrote: > > Hi > > I've just started using FPGAs (XC6200) for my research and I > would appreciate any advice on the following problem. > > I'm working with simple and regular designs but require > complete control over place and route. So it seems better (and > cheaper) to work at (or close to) the EDIF level rather than use an > expensive HDL or schematic tool. > > So is there any place where I can get info on the EDIF subset > understood by Xilinx tools, esp. XACT 6000? Please send an email copy > while replying. Thanks in advance. Hello! Unfortunately I can't help with the EDIF subset, but there is an alternative. You can use "velab" to convert structural VHDL to EDIF. You can find Velab here: http://www.xilinx.com/apps/6200.htm This may satisfy your needs. Look at the examples included in the archive. By the way, I would be interested in the EDIF subset as well. So if you can get some information, please send me an email. ____________________________________________________________________ Frank Gilbert | University of Kaiserslautern mailto:gilbert@informatik.uni-kl.de | Dept. of Computer ScienceArticle: 6828
Anyone use Xchecker 5.2.0 and XChecker Download Cable DLC4 with NT 4.0? Thanks, Austin Franklin darkroom@ix.netcom.com to reply to this post, remove the number from the reply address...Article: 6829
Hello all,
Does someone know something about previous work which has been done
in Natural Language Processing(NLP) using FPGA's ?
While Image Processing algorithms are implemented in FPGA's ...are there
NLP alg. implemented in FPGA's ?
thanx a lot
Christian
Article: 6830
Hello all,
Does someone know something about previous work which has been done
in Natural Language Processing(NLP) using FPGA's ?
While Image Processing algorithms are implemented in FPGA's ...are there
NLP alg. implemented in FPGA's ?
thanx a lot
Christian
Article: 6831Fault-Simulation - Turbo Fault High Performance Fault Simulator: TurboFault combines high performance, versatility and accuracy. It is highly competitive with hardware accelerators for classical test fault grading. It supports synchronous and asynchronous designs at the gate-level, including tri-state gates, latches, flip-flops, single and multi-port RAMS, complex bus resolution functions, and USER Defined primitives (UDPs). TurboFault reads Verilog gate-level netlists, and will also read Standard Delay Format (SDF) timing files. Advanced Cached-Concurrent Algorithm: Turbofault utilizes a new algorithm optimed for today's computer hardware that maximizes the simulation power of workstations. Syntest Cached-Concurrent algorithm eliminates needless operations and with new Fast Queque technology combines the best of unit delay and cycle-based capabilities. No other fault simulator, hardware or software, matches the performance of TurboFault. TurboFault makes fault simulation an integral design tool for generating a quality manufacturing test set. TurboFault supports single timing delay for simulation accuracy and flexibility, without sacrificing speed. TurboFault is the fastest concurrent fault simulator based on the latest advances in cycle-based simulation technology. It simulates even *faster* than existing expensive hardware accelerated fault simulators. Fault simulation also consumes memory very quickly, so memory management is critical. TurboFault combines efficient memory management with special fault handling resulting in low memory consumption. To hear more of Turbo-Fault, please send an e-mail to Suzanne@world.std.com, please send us your company name, your name and fax #. Thanks! The staff at Syntest Technology. *ATPG* *Boundry Scan* *RAM BIST* *Design for test services* *Training* *TurboFault Simulation* *IDDQ* *Testability Analysis* -------------------------------------------------------/-/-/-/-/-/-Article: 6832
In article <5p81b8$41k$1@wnnews.sci.kun.nl>, Bill Sloman <sloman@sci.kun.nl> wrote: >In article <ECIqFs.16J@world.std.com>, jhallen@world.std.com (Joseph H Allen) says: >> >> >>In some fast digital scopes they increase the vertical resolution of >>repetitive signals by sampling at random different times during each period, >>and "filling in" more holes on the screen as time goes on. Thus if you have >>an ADC with a 2GHz bandwidth but only a 100MHz sample rate and low sample >>jitter, you can still effectively sample at 2GHz. I guess I'd call this resolution in time, not voltage... >>So my question is... how do they accurately time these "random" samples? Are >>they sythesized (perhaps with a counter or shift register running at 2GHz), >>are they timed (with a counter running at 2GHz and use some other method of >>generating random clocks for the ADC), or do they use delay lines with >>selected taps or timing vernier chips? > >I believe Hewlett-Packard described their system in the Hewlett-Packard >Journal, many years ago. Contact HP and see if you can get a reprint. > >>Does anyone know? Are there chips that I can buy which accept a trigger >>input and which generate these timing pulses available? Do they use >>discrete ECL? Do they have custom chips? > >I don't know of any timing chips which would really do the whole job >that you are asking for. The Analog Device AD9500 and AD9501 are >effectively digitally programmable monostables which might serve as a >beginning, and the Motorola MC100E195/6 are digitally programmable >delay lines with a range of 2nsec. > >The oscilloscope manufacturers definitely use their own custom chips - >TriQuint was originally the Tektronix in-house chip source. When designing >such systems, there are real advantages to using balanced signals >and current-steering logic for interconects, so there is a preference >for ECL over TTL and CMOS in the vicinity of the input. > >I've done a similar sort of system, with systematically interleaved >sampling, for a stroboscopic electron microscope. We use a mixture >of Gigabit Logic GaAs and 100k ECL with a small admixture of discrete >components. E-mail me if you want more details. I'm not sure how Tek et al. do it these days, but remember than random sampling has been done for many years before GaAs or ECL ICs were available. The usual technique is to have a fast ramp generator which starts on a trigger event, and is stopped by an internal clock. The amplitude of the fast ramp is then a measure of time offset. So long as the triggering events and internal clock are not in time sync, one can fill up a display window for repetitive waveforms after enough trigger events have occurred. For example, with care, you can get subnanosecond resolution of relative time using LS-speed logic and some discrete analog circuitry. Long before ICs were available, random sampling made it possible to view waveforms with bandwidths in the low GHz range. Obviously I've left out many details. If you can find a copy of one of the old Tek books written on their circuit designs (often available in university engineering libraries) you could find out a lot more. I don't know of any commercially available ICs that do all the work for you. There may be more direct digital approaches if your needs are not all that great, by running extremely fast clocks and counters, but to this analog guy it seems a gross way of doing things. -frank Disclaimer: yeah, I designed one of these for Tek for one of their 7K scopes; haven't worked for them for many years now.Article: 6833
I want to do revision control with Altera. In order to archive, what files need to be saved? I think I need the .tdf file, which is the original source, as well as the .cnf file. Are these two alone sufficient to completely recreate the design?Article: 6834
>one favorite i left off before is using johnson twisted ring counters and >using appropriate combinations of taps for glitchless state machine >decodes. Yes, I know somebody who really likes those. Spends days working them out... :) Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiserve.com.Article: 6835
Robert M. Münch wrote: > > > -----Original Message----- > > From: hunterbp@magellan.Colorado.EDU (Brian P Hunter) > > [SMTP:hunterbp@magellan.Colorado.EDU] > > Posted At: Friday, June 13, 1997 9:54 PM > > Posted To: fpga > > Conversation: Verilog Simulation and Synthesis for FPGA Devices > > Subject: Verilog Simulation and Synthesis for FPGA Devices > > > > These are the vendors I'm looking at right now: > > Synario with FPGA Express > > VeriBest with FPGA Express (from right here in Boulder!) > > ViewLogic's ViewDraw, VCS, and FPGA Express > > > > Can anyone here sway me in the right direction? Thanks in advance! > > > > > [Robert M. Münch] Yes, don't use Veribest! Their programs are a > collection of bugs! Nothing works! We tried the synthesis and their > optimizer is real good -> you won't get any signal in the result if you > are lucky and the program doens't crash your machine! Try Synopsis FPGA > Express and VCS. > > Robert M. Muench > SCRAP EDV-Anlagen GmbH, Karlsruhe, Germany > > ==> Private mail : r.m.muench@ieee.org <== > ==> ask for PGP public-key <== An interesting collection of comments, especially given that you recommend FPGA Express which is the same synthesis tool we OEM. Please contact me with specifics of what you have encountered, and I will address any issues you may have. "Nothing works" is a gross oversimplification as we have lots of very satisfied customers and gives me nothing to work with you on. -- Greg Brown gbrown@veribest.com VeriBest Incorporated 6101 Lookout Road Boulder, Colorado 80301 303.581.2327 http://www.veribest.comArticle: 6836
This is the "END" of the war! WilCoX, good good good!!! Joe Chan will agree with you! Yau Man Wai, Roger ICQ UIN:703065 The Hong Kong Polytechnic University Department of Electronic Engineering http://www.net.polyu.edu.hk/~rogeryauArticle: 6837
Sorry, send to wrong location!! Please remove it! sorry. Yau Man Wai, Roger ICQ UIN:703065 The Hong Kong Polytechnic University Department of Electronic Engineering http://www.net.polyu.edu.hk/~rogeryauArticle: 6838
Hi all -
I know this may be a pipe dream but...
Does anyone know of an "inexpensive" development system for the
Xilinx 3042A FPGA? It should have a socketed programmer with some
sort of interface for a serial/parallel port to a PC, schematic
capture (running on a PC), and potentially some sort of simulator
(also running on the PC).
I'm looking for an inexpensive way to develop these chips for use
on the IP-Xilinx IP module made by Greenspring for use in an embedded
system.
Any and all pointers to the right direction would be appreciated.
TIA
Dave
=====================================================
NOTE : The return address in the e-mail header is bogus to reduce spam.
The correct return address is starfire@pacbell.net
(eliminate the leading # symbol).
Article: 6839Well, after hours of trying to get my chip to download unsuccessfully...I spoke to one of the Xilinx FAEs...and he told me that basically Xchecker doesn't work with NT, I should use DOS/Win 95. I'm glad to find out that it wasn't my hardware....but now I'm a bit 'upset' that I have to reboot my NT machine to a DOS floppy just to download the Xilinx... Has anyone written a new downloader that will work with NT, or knows how to get Xchecker to work with NT....any help would be appreciated. Austin Franklin darkroom@ix.netcom.com to reply to this post, remove the number from the reply address... Austin Franklin <dark4room@ix.netcom.com> wrote in article <01bc8623$8eeb8bb0$34c220cc@drt3>... > Anyone use Xchecker 5.2.0 and XChecker Download Cable DLC4 with NT 4.0? > > Thanks, > > Austin Franklin > darkroom@ix.netcom.com > > to reply to this post, remove the number from the reply address... > > >Article: 6840
For anyone needing information on EDA tools and products, I highly reccomend Steven Knapp's Programmable Logic Jump Station site at: http:/optimagic.com This iste is really well done! -- _____________________________________________________ Richard Schwarz, President Associated Professional Systems Inc. (APS) 3003 Latrobe Court Abingdon, Maryland 21009 USA email: aaps@erols.com web site: http://www.erols.com/aaps Phone: 410-515-3883 or 410-290-3918 Fax: 410-661-2760 or 410-290-8146Article: 6841
-----BEGIN PGP SIGNED MESSAGE-----
Roger <roger@solaris.x86.org> wrote:
>This is the "END" of the war!
>WilCoX, good good good!!!
>Joe Chan will agree with you!
Of course!
Chan Kai Cho, Joe (³¯ Ä~ ¯ª)
B.A.(Hons) Computing Yr.4
The Hong Kong Polytechnic University
E-mail: joechan@poboxes.com
Homepage: http://www.net.polyu.edu.hk/~joechan/
... I'll never die, I'll never cry, you'll see ...
I'm Angry --- BEYOND
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Article: 6842Add the .acf file to your list, and probably the .fit file as well. Neal Becker <neal@ctd.comsat.com> wrote in article <u9yb7qa9i0.fsf@neal.ctd.comsat.com>... > I want to do revision control with Altera. In order to archive, what > files need to be saved? I think I need the .tdf file, which is the > original source, as well as the .cnf file. Are these two alone > sufficient to completely recreate the design? >Article: 6843
> -----Original Message----- > From: Greg Brown [SMTP:gbrown@veribest.com] > Posted At: Tuesday, July 01, 1997 9:27 PM > Posted To: fpga > Conversation: Verilog Simulation and Synthesis for FPGA Devices > Subject: Re: Verilog Simulation and Synthesis for FPGA Devices > > > [Robert M. Münch] Yes, don't use Veribest! Their programs are a > > collection of bugs! Nothing works! We tried the synthesis and their > > optimizer is real good -> you won't get any signal in the result if > you > > are lucky and the program doens't crash your machine! Try Synopsis > FPGA > > Express and VCS. > > > > Robert M. Muench > > SCRAP EDV-Anlagen GmbH, Karlsruhe, Germany > > > > ==> Private mail : r.m.muench@ieee.org <== > > ==> ask for PGP public-key <== > > An interesting collection of comments, especially given that you > recommend > FPGA Express which is the same synthesis tool we OEM. [Robert M. Münch] You have to say that this is for a maximum of some month (or maybe only some weeks now). We used your stuff some months ago and the NT version mostly crashed. And the Veribest optimizer is one of the best I saw: Something in -> no gate out!! Realy impressive. We lost about 6 weeks because we tried your stuff to long. After switching to Synopsys (even the Veribest guys found out that their own stuff is so buggy that the better way is to license it from Synopsys) and VCS we only have the normal minor problems. As Veribest is mostly a collection of tools from other vendors (except the PCB stuff) I see no reason why I should use Veribest, I better go with the original manufacturer... faster updates, better support, etc. > Please contact me with specifics of what you have encountered, and I > will address any issues you may have. "Nothing works" is a gross > oversimplification as we have lots of very satisfied customers and > gives me nothing to work > with you on. [Robert M. Münch] Specifics see above or call german support (they will know us!). Terms like: 'We have a lots of very satisfied customers' are only empty phrases from marketing and say nothing about a product. How much is a 'a lots'? Maybe 3 to 5? Depends on your company. We couldn't find anyone here in Germany who used the Synthesis stuff... I will hold my statement about Veribest: Don't use it for synthesis! Robert M. Muench SCRAP EDV-Anlagen GmbH, Karlsruhe, Germany ==> Private mail : r.m.muench@ieee.org <== ==> ask for PGP public-key <==Article: 6844
> -----Original Message----- > From: Veli-Matti Karppinen [SMTP:veli-matti.karppinen@fincitec.fi] > Posted At: Monday, June 30, 1997 12:16 PM > Posted To: fpga > Conversation: Verilog Simulation and Synthesis for FPGA Devices > Subject: Re: Verilog Simulation and Synthesis for FPGA Devices > > Aren't You mixing things now? VeriBest's synthesis part IS Synopsys's > FPGA Express, which You are recommending. [Robert M. Münch] As I said in my other posting: As we used/tried to use it they still had their own stuff 'running' which is/was totaly buggy! They told us that they now will use Synopsys and we might get a beta in some months. But why should I use it than? I use Synopsys directly. There is no reason to use a vendor who just license some tools from 3rd party companies where I can buy them directly (the only one I can guess is that Veribest wants to earn some $$, but sorry not ours). > > As far as I know people are > using it quite succesfully for FPGA synthesis. We are using front-end > and simulation tools from VB together with Synopsys Design Compiler > and > I would say that they don't contain more bugs than any other piece of > EDA software I've seen. [Robert M. Münch] Maybe I have to say that we are working with >80K Gates and are switching some designs to ASICs... so for little applications maybe it will work. > Of course I also would like to see a totally > bug-free one, but ... [Robert M. Münch] that's not the point. We asked them if they can handle our specification and they said: Yes! But they couldn't!! So we lost a lot of time and Veribest had its chance but missed it. If they now say: everything is better I don't believe them. Robert M. Muench SCRAP EDV-Anlagen GmbH, Karlsruhe, Germany ==> Private mail : r.m.muench@ieee.org <== ==> ask for PGP public-key <==Article: 6845
> Aren't You mixing things now? VeriBest's synthesis part IS Synopsys's > FPGA Express, which You are recommending. As far as I know people are > using it quite succesfully for FPGA synthesis. We are using front-end > and simulation tools from VB together with Synopsys Design Compiler > and > I would say that they don't contain more bugs than any other piece of > EDA software I've seen. Of course I also would like to see a totally > bug-free one, but ... > [M.Vorbach] Your right, NOW you use Synopsys FPGA-Express, after you tried to sell no-working scrap. We considered to buy VeriBest in 1Q97. We tested it for about 6 weeks and found out, that we wasted only our time. You use: - Simulator: Fintronic, which is a nice bug-collection. It hangs a lot of time and fails without warnings or error messages. - Synthesis: An FPGA-Tool from AT&T, which synthesises all, without any error or warning. BUT our ALTERA-FPGA-fitter found out, that no gate and not pin would be left after synthesis. Great tool. - VeriBest claim to be the number one in Windows NT tools, but their tools don´t look like NT4.0 and partially don´t work with NT4.0 - VeriBest support is the worst I ever found. The german office has no idea about synthesis or verilog (or VHDL). Another point of view is: Synopsys synthesis IS synopsys synthesis. This is the market leader and almost 100% compatible to the ASIC tool. Probably this is important! So I guess to any possible FPGA-synthesis user: Take SYNOPSYS FGPA-EXPRESS and order it directly at SYNOPSYS. Support is OK and the tool is almost stable and good! Or : VIEWLOGIC WORKVIEW OFFICE seems to be very good too! We use the VCS Verilog Simulator from Viewlogic and their new Waveform Tracer in the alpha(!) version! It works! Support is very good, the tools are stable (I found not any bug in the VCS, but there are some tiny in the old ViewTrace). They are NT4.0 compatible.Article: 6846
[M.Vorbach] Take this one: > ViewLogic's ViewDraw, VCS, and FPGA Express [M.Vorbach] Viewlogic has a good sopport and VCS is very, very good. I don´t know ViewDraw, but all other tools. Although I don´t like VeriBest, the schematic capture is OK! We use VeriBest Schematic Capture, VCS and FPGA-Express. The reason for prefering VeriBest in Schematic Capture is historical, we had to much old drawings, but else we would use ViewLogic too (I believe). >Article: 6847
--Article: 6848
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Article: 6849No problem, We can do that, but the proto-board we sell is for the 4000/5200 series. We do have some older boards which support the 3000 series boards, but you will have to contact me via email to request the information. D.F. Spencer wrote: > Hi all - > > I know this may be a pipe dream but... > > Does anyone know of an "inexpensive" development system for the > Xilinx 3042A FPGA? It should have a socketed programmer with some > sort of interface for a serial/parallel port to a PC, schematic > capture (running on a PC), and potentially some sort of simulator > (also running on the PC). > > I'm looking for an inexpensive way to develop these chips for use > on the IP-Xilinx IP module made by Greenspring for use in an embedded > system. > > Any and all pointers to the right direction would be appreciated. > > TIA > > Dave > > ===================================================== > NOTE : The return address in the e-mail header is bogus to reduce > spam. > The correct return address is starfire@pacbell.net > (eliminate the leading # symbol).
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