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Threads Starting Sep 2000
25239: 00/09/01: <segels@home.com>: Anybody Wanna Fuck My Virgin Whiteboy Ass?
25242: 00/09/01: Tomasz Brychcy: Error during synthesis
25245: 00/09/01: Rick Filipkiewicz: Re: Error during synthesis
25292: 00/09/05: Johan Petersson: Re: Error during synthesis
25246: 00/09/01: Rick Filipkiewicz: Xilinx Web pack ABEL tools
25252: 00/09/01: Jamie Sanderson: Virtex-E DLL Question
25253: 00/09/01: Paul Smith: Xilinx block Ram Verilog model
25254: 00/09/01: Ray Andraka: Re: Xilinx block Ram Verilog model
25256: 00/09/02: Austin Franklin: Re: Xilinx block Ram Verilog model
25257: 00/09/02: B. Joshua Rosen: Re: Xilinx block Ram Verilog model
25259: 00/09/02: Muzaffer Kal: Re: Xilinx block Ram Verilog model
25261: 00/09/03: Austin Franklin: Re: Xilinx block Ram Verilog model
25258: 00/09/02: Muzaffer Kal: Re: Xilinx block Ram Verilog model
25255: 00/09/01: Stuart J Adams: Spartan II Power Down Mode ??
25260: 00/09/03: Sammo Spud: OverClockers Direct
25265: 00/09/03: <jamil.khatib@pmail.net>: Win a free OpenTech cdrom
25266: 00/09/03: Anthony Tekatch: XC3000A Configuration data
25272: 00/09/04: Thomas Karlsson: Re: XC3000A Configuration data
25352: 00/09/07: Juan-Luis López Rodríguez: Re: XC3000A Configuration data
25271: 00/09/04: jeffrey j cook: FS: Xilinx XCV200-5PQ240, IDT 71V3558S/133PF
25273: 00/09/04: <news@rtrussell.co.uk>: Slow routing of PWR/GND (Virtex)
25276: 00/09/04: Johan Petersson: Re: Slow routing of PWR/GND (Virtex)
25279: 00/09/04: Ray Andraka: Re: Slow routing of PWR/GND (Virtex)
25286: 00/09/05: Johan Petersson: Re: Slow routing of PWR/GND (Virtex)
25290: 00/09/05: Ray Andraka: Re: Slow routing of PWR/GND (Virtex)
25319: 00/09/06: Rick Filipkiewicz: Re: Slow routing of PWR/GND (Virtex)
25351: 00/09/07: Rajeev Jayaraman: Re: Slow routing of PWR/GND (Virtex)
25285: 00/09/05: <news@rtrussell.co.uk>: Re: Slow routing of PWR/GND (Virtex)
25291: 00/09/05: Ray Andraka: Re: Slow routing of PWR/GND (Virtex)
25301: 00/09/05: Ray Andraka: Re: Slow routing of PWR/GND (Virtex)
25302: 00/09/05: <fjz001@email.mot.com>: Re: Slow routing of PWR/GND (Virtex)
25307: 00/09/06: Ray Andraka: Re: Slow routing of PWR/GND (Virtex)
25274: 00/09/04: Anthony Tekatch: Re: XC3000A Configuration data
25275: 00/09/04: Thomas Karlsson: Re: XC3000A Configuration data
25280: 00/09/04: Anthony Tekatch: Re: XC3000A Configuration data
25312: 00/09/06: Peter Schulz: Re: XC3000A Configuration data
25321: 00/09/06: <kolja@prowokulta.org>: Re: XC3000A Configuration data
25333: 00/09/06: Phil James-Roxby: Re: XC3000A Configuration data
25340: 00/09/07: <sulimma@my-deja.com>: Re: XC3000A Configuration data
25341: 00/09/07: <kolja@prowokulta.org>: Re: XC3000A Configuration data
25347: 00/09/07: Phil James-Roxby: Re: XC3000A Configuration data
25362: 00/09/08: <sulimma@my-deja.com>: Re: XC3000A Configuration data
25350: 00/09/07: glen herrmannsfeldt: Re: XC3000A Configuration data
25359: 00/09/07: John L. Smith: Re: XC3000A Configuration data
25364: 00/09/08: Ray Andraka: Re: XC3000A Configuration data
25282: 00/09/05: Ron: Model for 8101 - 8104
25306: 00/09/05: Eric Smith: Re: Model for 8101 - 8104
25308: 00/09/06: Ray Andraka: Re: Model for 8101 - 8104
25284: 00/09/05: <kolja@prowokulta.org>: XC4013 available
25288: 00/09/05: Ray Andraka: Re: XC4013 available
25297: 00/09/05: S. Ramirez: Re: XC4013 available
25314: 00/09/06: <kolja@prowokulta.org>: Re: XC4013 available
25293: 00/09/05: Dan: PCB design for Xilinx FPGAs
25298: 00/09/05: Seb C: DCT implementation using FpgA
25595: 00/09/15: Vincenzo Liguori: Re: DCT implementation using FpgA
25299: 00/09/05: Seb C: DCT implementation using FPGA
25365: 00/09/08: <kolja@prowokulta.org>: Re: DCT implementation using FPGA
25372: 00/09/08: Ray Andraka: Re: DCT implementation using FPGA
25412: 00/09/11: <sulimma@my-deja.com>: Re: DCT implementation using FPGA
25472: 00/09/12: Johan Petersson: Re: DCT implementation using FPGA
25300: 00/09/05: <rickballantyne@home.com>: ADV7185 & AVD7194
25303: 00/09/06: Daniel Nilsson: sowtware/programmer
25305: 00/09/05: Dave Vanden Bout: Re: sowtware/programmer
25304: 00/09/05: Joseph H Allen: Re: Mealy vs Moore FSM model
25313: 00/09/06: <eml@riverside-machines.com.NOSPAM>: Re: Mealy vs Moore FSM model
25322: 00/09/06: Ulf Samuelsson: Re: Mealy vs Moore FSM model
25327: 00/09/06: Andy Peters: Re: Mealy vs Moore FSM model
25339: 00/09/07: Ulf Samuelsson: Re: Mealy vs Moore FSM model
25323: 00/09/06: Joseph H Allen: Re: Mealy vs Moore FSM model
25399: 00/09/09: <rajkumar@gdatech.com>: Re: Mealy vs Moore FSM model
25309: 00/09/06: P: Program & Readback Spartan II from 188
25310: 00/09/06: Alexandr V Shuvalov: 3.3/2.5 voltage regulators
25315: 00/09/06: Leon Heller: Re: 3.3/2.5 voltage regulators
25316: 00/09/06: Rémi SEGLIE: Re: 3.3/2.5 voltage regulators
25326: 00/09/06: Andy Peters: Re: 3.3/2.5 voltage regulators
25331: 00/09/06: Alain Cloet: Re: 3.3/2.5 voltage regulators
25332: 00/09/06: Theron Hicks: Re: 3.3/2.5 voltage regulators
25343: 00/09/07: Austin Lesea: Re: 3.3/2.5 voltage regulators
25344: 00/09/07: rickman: Re: 3.3/2.5 voltage regulators
25348: 00/09/07: Alain Cloet: Re: 3.3/2.5 voltage regulators
25356: 00/09/07: Austin Lesea: Re: 3.3/2.5 voltage regulators
25375: 00/09/08: Austin Lesea: Re: 3.3/2.5 voltage regulators
25380: 00/09/09: rickman: Re: 3.3/2.5 voltage regulators
25394: 00/09/09: <eml@riverside-machines.com.NOSPAM>: Re: 3.3/2.5 voltage regulators
25421: 00/09/11: Austin Lesea: Re: 3.3/2.5 voltage regulators
25363: 00/09/08: Henryk Cieslak: Re: 3.3/2.5 voltage regulators
25368: 00/09/08: Austin Lesea: Re: 3.3/2.5 voltage regulators
25381: 00/09/09: rickman: Re: 3.3/2.5 voltage regulators
25422: 00/09/11: Austin Lesea: Re: 3.3/2.5 voltage regulators
25427: 00/09/11: rickman: Re: 3.3/2.5 voltage regulators
25617: 00/09/15: Austin Lesea: Re: 3.3/2.5 voltage regulators
25652: 00/09/16: rickman: Re: 3.3/2.5 voltage regulators
25715: 00/09/18: Austin Lesea: Re: 3.3/2.5 voltage regulators
25726: 00/09/18: rickman: Re: 3.3/2.5 voltage regulators
25346: 00/09/07: Andy Peters: Re: 3.3/2.5 voltage regulators
25337: 00/09/07: Alexandr V Shuvalov: Re: 3.3/2.5 voltage regulators
25311: 00/09/06: Tim: Cypress Delta39K availability
25358: 00/09/07: Eric Smith: Re: Cypress Delta39K availability
25317: 00/09/06: Peter Desmet: About XNF, EDIF and UCF
25320: 00/09/06: Thomas Karlsson: Re: About XNF, EDIF and UCF
25342: 00/09/07: Peter Desmet: Re: About XNF, EDIF and UCF
25345: 00/09/07: rickman: Re: About XNF, EDIF and UCF
25404: 00/09/10: Christian Mautner: Re: About XNF, EDIF and UCF
25328: 00/09/06: B. Joshua Rosen: Re: About XNF, EDIF and UCF
25318: 00/09/06: <erika_uk@my-deja.com>: floorplanning
25324: 00/09/06: Ray Andraka: Re: floorplanning
25349: 00/09/07: <husby@my-deja.com>: Re: floorplanning
25353: 00/09/07: Ray Andraka: Re: floorplanning
25354: 00/09/07: <husby@my-deja.com>: Re: floorplanning
25325: 00/09/06: <ed.moore@snellwilcox.com>: pcilogic celss
25397: 00/09/09: Duane: Re: pcilogic celss
25329: 00/09/06: Erik Brunvand: FPGA Express, Xilinx, and Powerview
25400: 00/09/09: Philip Freidin: Re: FPGA Express, Xilinx, and Powerview
25330: 00/09/06: Daniel Nilsson: DRAM controller
25334: 00/09/06: <uwuh@my-deja.com>: bga->dip?
25335: 00/09/06: Ray Andraka: Re: bga->dip?
25338: 00/09/07: Olaf Birkeland: Re: bga->dip?
25391: 00/09/09: <mhkohne@discordia.org>: Re: bga->dip?
25336: 00/09/08: <goodfolks@firmware.com>: 1A215966 Visio for Linux
25355: 00/09/07: <karenwlead@my-deja.com>: XC6K still alive ??
25360: 00/09/08: <craigm9203@my-deja.com>: Jobs at Xilinx
25361: 00/09/08: Stan Ramsden: ORCAD Xilin GSR
25366: 00/09/08: Ian Miller: test
25367: 00/09/08: Thomas Karlsson: How do I mix vhdl and verilog source files in Synplify?
25398: 00/09/09: <rkadam@my-deja.com>: Re: How do I mix vhdl and verilog source files in Synplify?
25432: 00/09/11: Stuart Clubb: Re: How do I mix vhdl and verilog source files in Synplify?
25447: 00/09/11: Phil Hays: Re: How do I mix vhdl and verilog source files in Synplify?
25474: 00/09/12: Johan Petersson: Re: How do I mix vhdl and verilog source files in Synplify?
25557: 00/09/13: Phil Hays: Re: How do I mix vhdl and verilog source files in Synplify?
25572: 00/09/14: Thomas Karlsson: Re: How do I mix vhdl and verilog source files in Synplify?
25369: 00/09/08: Jaap H. Mol: IEEE 754 Floating point VHDL functions / MATH package
25395: 00/09/09: <eml@riverside-machines.com.NOSPAM>: Re: IEEE 754 Floating point VHDL functions / MATH package
25370: 00/09/08: <mrtwisterz@020.co.uk>: Mr Twisterz needs you
25371: 00/09/08: Stuart Clubb: test
25373: 00/09/08: Andy Peters: VirtexE availability?
25377: 00/09/08: S. Ramirez: Re: VirtexE availability?
25390: 00/09/09: Mark Harvey: Re: VirtexE availability?
25392: 00/09/09: rickman: Re: VirtexE availability?
25506: 00/09/13: Mark Harvey: Re: VirtexE availability?
25653: 00/09/16: rickman: Re: VirtexE availability?
25401: 00/09/10: S. Ramirez: Re: VirtexE availability?
25430: 00/09/11: Andy Peters: Re: VirtexE availability?
25433: 00/09/11: S. Ramirez: Re: VirtexE availability?
25508: 00/09/13: Mark Harvey: Re: VirtexE availability?
25507: 00/09/13: Mark Harvey: Re: VirtexE availability?
25529: 00/09/13: S. Ramirez: Re: VirtexE availability?
25689: 00/09/17: Mark Harvey: Re: VirtexE availability?
25697: 00/09/18: S. Ramirez: Re: VirtexE availability?
25719: 00/09/18: Andy Peters: Re: VirtexE availability?
25431: 00/09/11: Andy Peters: Re: VirtexE availability?
25374: 00/09/08: Nestor: Numerically-Controlled Crystal Oscillator (NCXO) or Digitally-Controlled Crystal Oscillator (DCXO) Designs
25376: 00/09/08: Theron Hicks: Re: Numerically-Controlled Crystal Oscillator (NCXO) or
25411: 00/09/11: <kolja@prowokulta.org>: Re: Numerically-Controlled Crystal Oscillator (NCXO) or Digitally-Controlled Crystal Oscillator (DCXO) Designs
25378: 00/09/08: Rolie Baldock: Re: Numerically-Controlled Crystal Oscillator (NCXO) or Digitally-Controlled Crystal Oscillator (DCXO) Designs
25489: 00/09/12: Nestor: Re: Numerically-Controlled Crystal Oscillator (NCXO) or Digitally-Controlled Crystal Oscillator (DCXO) Designs
25383: 00/09/09: rickman: Re: Numerically-Controlled Crystal Oscillator (NCXO) or
25490: 00/09/12: Nestor: Re: Numerically-Controlled Crystal Oscillator (NCXO) or Digitally-Controlled Crystal Oscillator (DCXO) Designs
25498: 00/09/12: rickman: Re: Numerically-Controlled Crystal Oscillator (NCXO) or
25423: 00/09/11: Austin Lesea: Re: Numerically-Controlled Crystal Oscillator (NCXO) or
25428: 00/09/11: rickman: Re: Numerically-Controlled Crystal Oscillator (NCXO) or
25443: 00/09/11: Austin Lesea: Re: Numerically-Controlled Crystal Oscillator (NCXO) or
25450: 00/09/11: doug: Re: Numerically-Controlled Crystal Oscillator (NCXO) or Digitally-Controlled Crystal Oscillator (DCXO) Designs
25618: 00/09/15: Austin Lesea: Re: Numerically-Controlled Crystal Oscillator (NCXO) or
25451: 00/09/11: rickman: Re: Numerically-Controlled Crystal Oscillator (NCXO) or
25483: 00/09/12: Austin Lesea: Re: Numerically-Controlled Crystal Oscillator (NCXO) or
25448: 00/09/12: <eddy_bobby@my-deja.com>: Re: Numerically-Controlled Crystal Oscillator (NCXO) or Digitally-Controlled Crystal Oscillator (DCXO) Designs
25449: 00/09/12: <eddy_bobby@my-deja.com>: Re: Numerically-Controlled Crystal Oscillator (NCXO) or Digitally-Controlled Crystal Oscillator (DCXO) Designs
25379: 00/09/08: Tom Kerrigan: How many 4005s (4010s) does it take to make a general purpose CPU?
25382: 00/09/09: Ray Andraka: Re: How many 4005s (4010s) does it take to make a general purpose CPU?
25384: 00/09/09: rickman: Re: How many 4005s (4010s) does it take to make a general purpose CPU?
25385: 00/09/08: Tom Kerrigan: Re: How many 4005s (4010s) does it take to make a general purpose CPU?
25388: 00/09/09: Jan Gray: Re: How many 4005s (4010s) does it take to make a general purpose CPU?
25386: 00/09/09: Jan Gray: Re: How many 4005s (4010s) does it take to make a general purpose CPU?
25387: 00/09/09: Nicholas C. Weaver: Re: How many 4005s (4010s) does it take to make a general purpose CPU?
25393: 00/09/09: Ben Franchuk: Re: How many 4005s (4010s) does it take to make a general purpose CPU?
25407: 00/09/11: Michael Randelzhofer: Re: How many 4005s (4010s) does it take to make a general purpose CPU?
25409: 00/09/10: Bob Perlman: Re: How many 4005s (4010s) does it take to make a general purpose CPU?
25415: 00/09/11: B. Joshua Rosen: Re: How many 4005s (4010s) does it take to make a general purpose CPU?
25417: 00/09/11: rickman: Re: How many 4005s (4010s) does it take to make a general purpose CPU?
25424: 00/09/11: B. Joshua Rosen: Re: How many 4005s (4010s) does it take to make a general purpose CPU?
25429: 00/09/11: rickman: Nanoseconds and seasons
25438: 00/09/11: B. Joshua Rosen: Re: Nanoseconds and seasons
25439: 00/09/11: B. Joshua Rosen: Re: Nanoseconds and seasons
25445: 00/09/12: Keith R. Williams: Re: How many 4005s (4010s) does it take to make a general purpose CPU?
25413: 00/09/11: Gary Watson: Re: How many 4005s (4010s) does it take to make a general purpose CPU?
25416: 00/09/11: B. Joshua Rosen: Re: How many 4005s (4010s) does it take to make a general purpose CPU?
25425: 00/09/11: Rick Filipkiewicz: Re: How many 4005s (4010s) does it take to make a general purpose CPU?
25441: 00/09/11: B. Joshua Rosen: Re: How many 4005s (4010s) does it take to make a general purpose CPU?
25402: 00/09/09: B. Joshua Rosen: Re: How many 4005s (4010s) does it take to make a general purpose CPU?
25414: 00/09/11: Gary Watson: Re: How many 4005s (4010s) does it take to make a general purpose CPU?
25396: 00/09/09: Michael Daldrup: Tutorial for ABEl-HDL
25406: 00/09/10: Vikram Pasham: Re: Tutorial for ABEl-HDL
25403: 00/09/10: Thomas Falk: Clock skew in XILINX CPLD
25435: 00/09/11: John L. Smith: Re: Clock skew in XILINX CPLD
25442: 00/09/11: Rick Filipkiewicz: Re: Clock skew in XILINX CPLD
25502: 00/09/12: <tronsmith@my-deja.com>: Re: Clock skew in XILINX CPLD
25453: 00/09/12: Pinhas Krengel: Re: Clock skew in XILINX CPLD
25454: 00/09/12: Thomas Falk: Re: Clock skew in XILINX CPLD
25455: 00/09/12: Thomas Falk: Re: Clock skew in XILINX CPLD
25456: 00/09/12: Klaus Falser: Re: Clock skew in XILINX CPLD
25477: 00/09/12: S. Ramirez: Re: Clock skew in XILINX CPLD
25528: 00/09/13: S. Ramirez: Re: Clock skew in XILINX CPLD
25610: 00/09/15: Nial Stewart: Re: Clock skew in XILINX CPLD
25680: 00/09/17: S. Ramirez: Re: Clock skew in XILINX CPLD
25705: 00/09/18: Nial Stewart: Re: Clock skew in XILINX CPLD
25706: 00/09/18: S. Ramirez: Re: Clock skew in XILINX CPLD
25709: 00/09/18: Ray Andraka: Re: Clock skew in XILINX CPLD
25712: 00/09/18: Nial Stewart: Re: Clock skew in XILINX CPLD
25727: 00/09/18: Ray Andraka: Re: Clock skew in XILINX CPLD
25543: 00/09/13: S. Ramirez: Re: Clock skew in XILINX CPLD
25569: 00/09/14: S. Ramirez: Re: Clock skew in XILINX CPLD
25518: 00/09/13: Thomas Falk: Re: Clock skew in XILINX CPLD
25522: 00/09/13: Jim Granville: Re: Clock skew in XILINX CPLD
25531: 00/09/13: Thomas Falk: Re: Clock skew in XILINX CPLD
25547: 00/09/13: Rick Filipkiewicz: Re: Clock skew in XILINX CPLD
25563: 00/09/14: Thomas Falk: Re: Clock skew in XILINX CPLD
25405: 00/09/10: <erika_uk@my-deja.com>: virtex shape
25408: 00/09/11: S. Ramirez: Re: virtex shape
25446: 00/09/12: Keith R. Williams: Re: virtex shape
25492: 00/09/12: Johan Petersson: Re: virtex shape
25499: 00/09/12: rickman: Re: virtex shape
25521: 00/09/13: Bill Blyth: Re: virtex shape
25536: 00/09/13: <husby@my-deja.com>: Re: virtex shape
25545: 00/09/13: Ray Andraka: Re: virtex shape
25675: 00/09/17: Bill Lenihan: Re: virtex shape
25700: 00/09/17: John L. Smith: Re: virtex shape
25702: 00/09/18: Nicholas C. Weaver: Re: virtex shape
25768: 00/09/19: Peter Alfke: Re: virtex shape
25410: 00/09/11: Carl Rouse: Xilinx Student Edition 2.1 where?
25645: 00/09/15: default@user.com: Re: Xilinx Student Edition 2.1 where?
25698: 00/09/18: mousy: Re: Xilinx Student Edition 2.1 where?
25418: 00/09/11: <channing@21cn.com>: Problem of Virtex-E I/O
25419: 00/09/11: <channing@21cn.com>: Problem of Virtex-E I/O
25420: 00/09/11: <erika_uk@my-deja.com>: xilinx web site access
25436: 00/09/11: Lasse Langwadt Christensen: Re: xilinx web site access
25444: 00/09/12: mok: Re: xilinx web site access
25479: 00/09/12: Gary Watson: Re: xilinx web site access
25426: 00/09/11: Chris Anderson: Code distribution without loss of IP?
25437: 00/09/11: =?iso-8859-1?q?Andr=E9_Powell?=: Re: Code distribution without loss of IP?
25493: 00/09/12: Johan Petersson: Re: Code distribution without loss of IP?
25500: 00/09/12: rickman: Re: Code distribution without loss of IP?
25440: 00/09/11: <theshai@my-deja.com>: An online FPGA and CPLD course
25457: 00/09/12: Peter Hanely: Re: hardware compatibility and patent infringement
25599: 00/09/15: Nicholas C. Weaver: Re: hardware compatibility and patent infringement
25600: 00/09/15: Tom Moog: Re: hardware compatibility and patent infringement
25603: 00/09/15: Björn Lindgren: Re: hardware compatibility and patent infringement
25629: 00/09/15: Darin Johnson: Re: hardware compatibility and patent infringement
25639: 00/09/16: Ulf Samuelsson: Re: hardware compatibility and patent infringement
25654: 00/09/16: rickman: Re: hardware compatibility and patent infringement
25670: 00/09/16: Jon Kirwan: Re: hardware compatibility and patent infringement
25679: 00/09/17: Peter: Re: hardware compatibility and patent infringement
25677: 00/09/17: <bkk411@hotmail.com>: Re: hardware compatibility and patent infringement
25703: 00/09/18: Ulf Samuelsson: Re: hardware compatibility and patent infringement
25728: 00/09/18: rickman: Re: hardware compatibility and patent infringement
25745: 00/09/19: Darin Johnson: Re: hardware compatibility and patent infringement
25751: 00/09/19: Ulf Samuelsson: Re: hardware compatibility and patent infringement
25458: 00/09/12: Mostafa Halas: CPLD: Basic informations
25459: 00/09/12: Mostafa Halas: Re: CPLD: Basic informations
25494: 00/09/12: Johan Petersson: Re: CPLD: Basic informations
25594: 00/09/14: Mark Korsloot: Re: CPLD: Basic informations
25460: 00/09/12: Tomasz Brychcy: OUTs after synthesis?
25487: 00/09/12: Johan Petersson: Re: OUTs after synthesis?
25461: 00/09/12: Tomasz Brychcy: Simulation problem
25464: 00/09/12: Tomasz Brychcy: Odp: Simulation problem (attached files)
25634: 00/09/15: Mujtaba Hamid: Re: Simulation problem
25773: 00/09/20: <yuryws@my-deja.com>: Re: Simulation problem
25463: 00/09/12: Charles Wagner: unexpanded XU macros
25465: 00/09/12: Michael Warner: Is this practical?
25466: 00/09/12: K. Orthner: Re: Is this practical?
25468: 00/09/12: Ray Andraka: Re: Is this practical?
25470: 00/09/12: <kolja@prowokulta.org>: Re: Is this practical?
25480: 00/09/12: Ray Andraka: Re: Is this practical?
25523: 00/09/13: Michael Warner: Re: Is this practical?
25533: 00/09/13: Ray Andraka: Re: Is this practical?
25524: 00/09/13: Michael Warner: Re: Is this practical?
25534: 00/09/13: Ray Andraka: Re: Is this practical?
25552: 00/09/14: Lasse Langwadt Christensen: Re: Is this practical?
25554: 00/09/13: Ray Andraka: Re: Is this practical?
25467: 00/09/12: psisabel: MEMORY
25535: 00/09/13: <husby@my-deja.com>: Re: MEMORY
25538: 00/09/13: Hawker: Re: MEMORY
25469: 00/09/12: Jerry English: Anybody receiving Spartan II?
25478: 00/09/12: Gary Watson: Re: Anybody receiving Spartan II?
25471: 00/09/12: ABP: hardware compatibility and patent infringement
25482: 00/09/12: David Kessner: Re: hardware compatibility and patent infringement
25509: 00/09/13: Martin Usher: Re: hardware compatibility and patent infringement
25510: 00/09/13: Bill Pringlemeir: Re: hardware compatibility and patent infringement
25553: 00/09/14: Zoltan Kocsi: Re: hardware compatibility and patent infringement
25789: 00/09/20: Brian Drummond: Re: hardware compatibility and patent infringement
25562: 00/09/14: Ben Franchuk: Re: hardware compatibility and patent infringement
25637: 00/09/15: Sylvan Butler: Re: hardware compatibility and patent infringement
25578: 00/09/14: David Kessner: Re: hardware compatibility and patent infringement
25586: 00/09/14: david lindauer: Re: hardware compatibility and patent infringement
25628: 00/09/15: Everett M. Greene: Re: hardware compatibility and patent infringement
25585: 00/09/14: Robert Posey: Re: hardware compatibility and patent infringement
25593: 00/09/14: Al Arduengo: Re: hardware compatibility and patent infringement
25616: 00/09/15: Paul Hovnanian ®: Re: hardware compatibility and patent infringement
25630: 00/09/15: Darin Johnson: Re: hardware compatibility and patent infringement
25632: 00/09/15: Paul Hovnanian ®: Re: hardware compatibility and patent infringement
25638: 00/09/15: John L. Smith: Re: hardware compatibility and patent infringement
25642: 00/09/15: Eric Smith: Re: hardware compatibility and patent infringement
25655: 00/09/16: rickman: Re: hardware compatibility and patent infringement
25643: 00/09/16: Darin Johnson: Re: hardware compatibility and patent infringement
25657: 00/09/16: rickman: Re: hardware compatibility and patent infringement
25669: 00/09/16: Jon Kirwan: Re: hardware compatibility and patent infringement
25671: 00/09/17: Kevin Aylward: Re: hardware compatibility and patent infringement
25866: 00/09/23: George Neuner: Re: hardware compatibility and patent infringement
25867: 00/09/23: Kevin Aylward: Re: hardware compatibility and patent infringement
25558: 00/09/14: Austin Franklin: Re: hardware compatibility and patent infringement
25579: 00/09/14: David Kessner: Re: hardware compatibility and patent infringement
25584: 00/09/14: Darin Johnson: Re: hardware compatibility and patent infringement
25598: 00/09/14: Marc Warden: Re: hardware compatibility and patent infringement
25473: 00/09/12: Gary Cook: Using U_SET/HU_SET in RPM's in Xilinx
25476: 00/09/12: Tom Leacock: Virtex 1800 series ISP proms
25527: 00/09/13: Peter Schulz: Re: Virtex 1800 series ISP proms
25551: 00/09/13: Alun: Re: Virtex 1800 series ISP proms
25851: 00/09/22: <chadlamb@my-deja.com>: Re: Virtex 1800 series ISP proms
25887: 00/09/25: Peter Schulz: Re: Virtex 1800 series ISP proms
25484: 00/09/12: <barrytedstone@my-deja.com>: IEC1131-3 PLC Programming Standard
25485: 00/09/12: <barrytedstone@my-deja.com>: IEC1131-3 PLC Programming Standard
25491: 00/09/12: Richard Meester: flipflops/statemachine/fifos and timing
25495: 00/09/12: rickman: Re: flipflops/statemachine/fifos and timing
25513: 00/09/13: Richard Meester: Re: flipflops/statemachine/fifos and timing
25497: 00/09/12: Johan Petersson: Re: flipflops/statemachine/fifos and timing
25515: 00/09/13: Richard Meester: Re: flipflops/statemachine/fifos and timing
25501: 00/09/12: Hawker: ABEL trouble with XC95108 and Foundation 2.1i SPVI
25537: 00/09/13: Hawker: Re: ABEL trouble with XC95108 and Foundation 2.1i SPVI
25504: 00/09/12: Andy Peters: Complaint: Xilinx functional simulation libraries
25505: 00/09/13: K. Orthner: Re: Complaint: Xilinx functional simulation libraries
25514: 00/09/13: Ray Andraka: Re: Complaint: Xilinx functional simulation libraries
25517: 00/09/13: K. Orthner: Re: Complaint: Xilinx functional simulation libraries
25532: 00/09/13: Ray Andraka: Re: Complaint: Xilinx functional simulation libraries
25540: 00/09/13: Andy Peters: Re: Complaint: Xilinx functional simulation libraries
25511: 00/09/13: Joel Kolstad: Re: Complaint: Xilinx functional simulation libraries
25512: 00/09/13: K. Orthner: Re: Complaint: Xilinx functional simulation libraries
25516: 00/09/13: Tobias Stumber: Re: Complaint: Xilinx functional simulation libraries
25519: 00/09/13: K. Orthner: Re: Complaint: Xilinx functional simulation libraries
25776: 00/09/20: Joel Kolstad: Re: Complaint: Xilinx functional simulation libraries
25778: 00/09/20: K. Orthner: Re: Complaint: Xilinx functional simulation libraries
25788: 00/09/20: Ray Andraka: Re: Complaint: Xilinx functional simulation libraries
25796: 00/09/20: Andy Peters: Re: Complaint: Xilinx functional simulation libraries
25804: 00/09/21: Ray Andraka: Re: Complaint: Xilinx functional simulation libraries
25525: 00/09/13: <eml@riverside-machines.com.NOSPAM>: Re: Complaint: Xilinx functional simulation libraries
25541: 00/09/13: Andy Peters: Re: Complaint: Xilinx functional simulation libraries
25546: 00/09/13: <eml@riverside-machines.com.NOSPAM>: Re: Complaint: Xilinx functional simulation libraries
25556: 00/09/13: Andy Peters: Re: Complaint: Xilinx functional simulation libraries
25542: 00/09/13: Andy Peters: Re: Complaint: Xilinx functional simulation libraries
25548: 00/09/13: <eml@riverside-machines.com.NOSPAM>: Re: Complaint: Xilinx functional simulation libraries
25555: 00/09/13: Andy Peters: Re: Complaint: Xilinx functional simulation libraries
25566: 00/09/14: Rick Filipkiewicz: Re: Complaint: Xilinx functional simulation libraries
25526: 00/09/13: <news@rtrussell.co.uk>: Virtex 'shutdown' phenomenon
25539: 00/09/13: Hawker: Re: Virtex 'shutdown' phenomenon
25565: 00/09/14: <news@rtrussell.co.uk>: Re: Virtex 'shutdown' phenomenon
25574: 00/09/14: Hawker: Re: Virtex 'shutdown' phenomenon
25580: 00/09/14: Richard Dungan: Re: Virtex 'shutdown' phenomenon
25683: 00/09/17: Gary Watson: Re: Virtex 'shutdown' phenomenon
25544: 00/09/13: S. Ramirez: Re: Virtex 'shutdown' phenomenon
25549: 00/09/13: Rick Filipkiewicz: Re: Virtex 'shutdown' phenomenon
25587: 00/09/14: Dan: nice one Rick
25571: 00/09/14: Ben Franchuk: Re: Simon , decoupling caps
25635: 00/09/15: S. Ramirez: Re: Simon , decoupling caps
25659: 00/09/16: rickman: Re: Simon , decoupling caps
25665: 00/09/16: Bob Perlman: Re: Simon , decoupling caps
25682: 00/09/17: rickman: Re: Simon , decoupling caps
25783: 00/09/20: <eml@riverside-machines.com.NOSPAM>: Re: Simon , decoupling caps
25791: 00/09/20: Bob Perlman: Re: Simon , decoupling caps
25829: 00/09/22: <eml@riverside-machines.com.NOSPAM>: Re: Simon , decoupling caps
25667: 00/09/16: Hal Murray: Re: Simon , decoupling caps
25588: 00/09/14: Dan: Simon,Floating Inputs
25589: 00/09/14: Hawker: Re: Simon,Floating Inputs
25591: 00/09/14: S. Ramirez: Re: Simon,Floating Inputs
25602: 00/09/14: John L. Smith: Whoa, Noise on a digital output pin?, and Minor rant on XC9500 S/W, was
25612: 00/09/15: Hawker: Re: Whoa, Noise on a digital output pin?, and Minor rant on XC9500 S/W,
26109: 00/10/04: Jens Konig: Re: Whoa, Noise on a digital output pin?, and Minor rant on XC9500 S/W, was Re: Simon,Floating Inputs
26126: 00/10/05: Jim Granville: Re: Whoa, Noise on a digital output pin?, and Minor rant on XC9500 S/W, was Re: Simon,Floating Inputs
26148: 00/10/05: John L. Smith: Re: Whoa, Noise on a digital output pin?, and Minor rant on XC9500 S/W,
25590: 00/09/14: S. Ramirez: Re: Simon,Floating Inputs
25601: 00/09/15: Dan: Re: Simon,Floating Inputs
25608: 00/09/15: S. Ramirez: Re: Simon,Floating Inputs
25615: 00/09/15: S. Ramirez: Re: Simon,Floating Inputs
25619: 00/09/15: Dan: Simon , decoupling caps
25716: 00/09/18: Austin Lesea: Re: Simon,Floating Inputs
25530: 00/09/13: Rinux: sw
25550: 00/09/13: Mark Coles: emma/dy ssn
25559: 00/09/13: Richard B. Katz: MAPLD 2000 - Schedule Released and Final Registration
25561: 00/09/14: Ben Franchuk: Re: Guide to useing Atmel FPGA (at40k)
25605: 00/09/15: Paul Maddox: Re: Guide to useing Atmel FPGA (at40k)
25627: 00/09/15: Ray Andraka: Re: Guide to useing Atmel FPGA (at40k)
25640: 00/09/16: Ulf Samuelsson: Re: Guide to useing Atmel FPGA (at40k)
25564: 00/09/14: anup: Advertisement of a new e-Group/mailing list --
25567: 00/09/14: Michael Boehnel: Ethernet MII + bit ordering
25577: 00/09/14: <eml@riverside-machines.com.NOSPAM>: Re: Ethernet MII + bit ordering
25814: 00/09/21: Jamie Lokier: Re: Ethernet MII + bit ordering
25573: 00/09/14: Ben Franchuk: Re: MAX PLUS 2
25661: 00/09/17: gk7eong: Re: MAX PLUS 2
25575: 00/09/14: =?iso-8859-1?Q?J=F6rg?= Ritter: coregen or logiblox
25582: 00/09/14: Andy Peters: Re: coregen or logiblox
25576: 00/09/14: Paul Maddox: Guide to useing Atmel FPGA (at40k)
25581: 00/09/14: Ben Franchuk: Re: Adders in FPGA?
25583: 00/09/14: Andy Peters: FPGA Express Strikes Again!
25592: 00/09/14: S. Ramirez: Re: FPGA Express Strikes Again!
25609: 00/09/15: <eml@riverside-machines.com.NOSPAM>: Re: FPGA Express Strikes Again!
25625: 00/09/15: Ray Andraka: Re: FPGA Express Strikes Again!
25626: 00/09/15: Andy Peters: Re: FPGA Express Strikes Again!
25647: 00/09/16: <wq998@yahoo.com>: Re: FPGA Express Strikes Again!
25649: 00/09/16: Joel Kolstad: Re: FPGA Express Strikes Again!
25658: 00/09/16: Phil Hays: Re: FPGA Express Strikes Again!
25664: 00/09/16: <wq998@my-deja.com>: Re: FPGA Express Strikes Again!
26003: 00/09/30: Bill Lenihan: Re: FPGA Express Strikes Again!
26008: 00/09/30: <bob_42690@my-deja.com>: Re: FPGA Express Strikes Again!
25656: 00/09/16: Phil Hays: Re: FPGA Express Strikes Again!
25648: 00/09/16: Joel Kolstad: Re: FPGA Express Strikes Again!
25660: 00/09/16: rickman: Re: FPGA Express Strikes Again!
25765: 00/09/19: Vikram Pasham: Re: FPGA Express Strikes Again!
25795: 00/09/20: Andy Peters: Re: FPGA Express Strikes Again!
25596: 00/09/14: sergio oyaga: Boundary scan
25604: 00/09/15: David Miller: Re: Boundary scan
25798: 00/09/20: Alain Cloet: Re: Boundary scan
25597: 00/09/15: Jean-Paul Smeets: Xilinx PCI interface: buy the LogiCORE or do it yourself?
25611: 00/09/15: Francois DUSSAUGEY: Re: Xilinx PCI interface: buy the LogiCORE or do it yourself?
25606: 00/09/15: Marc Reinert: PCI-Tip? (for Xilinx Virtex/-E)
25607: 00/09/15: Lars Rzymianowicz: Re: PCI-Tip? (for Xilinx Virtex/-E)
25614: 00/09/15: Newsbrowser: Re: PCI-Tip? (for Xilinx Virtex/-E)
25774: 00/09/20: <yuryws@my-deja.com>: Re: PCI-Tip? (for Xilinx Virtex/-E)
25775: 00/09/20: <yuryws@my-deja.com>: Re: PCI-Tip? (for Xilinx Virtex/-E)
25613: 00/09/15: Richard Meester: timing constraints
25624: 00/09/15: Andy Peters: Re: timing constraints
25769: 00/09/20: Kang Liat Chuan: Re: timing constraints
25620: 00/09/15: <erika_uk@my-deja.com>: Physical Interpretation
25623: 00/09/15: Andy Peters: Re: Physical Interpretation
25633: 00/09/15: bob elkind: Re: Physical Interpretation
25641: 00/09/16: Muzaffer Kal: Re: Physical Interpretation
25621: 00/09/16: gk7eong: MAX PLUS 2
25622: 00/09/15: Andy Peters: Re: MAX PLUS 2
25662: 00/09/17: gk7eong: Re: MAX PLUS 2
25681: 00/09/17: rickman: Re: MAX PLUS 2
25690: 00/09/17: S. Ramirez: Re: MAX PLUS 2
25691: 00/09/17: rickman: Re: MAX PLUS 2
25694: 00/09/17: S. Ramirez: Re: MAX PLUS 2
25693: 00/09/17: Bob Perlman: Re: MAX PLUS 2
25695: 00/09/17: S. Ramirez: Re: MAX PLUS 2
25744: 00/09/18: Eric Smith: Xilinx software licensing (was Re: MAX PLUS 2)
25713: 00/09/18: Phil James-Roxby: Re: MAX PLUS 2
25631: 00/09/15: bob elkind: Re: MAX PLUS 2
25636: 00/09/15: Lawrence Peregrim: Virtex clock fanout
25685: 00/09/17: Michael Rhotert: Re: Virtex clock fanout
25721: 00/09/18: Alun: Re: Virtex clock fanout
25729: 00/09/18: rickman: Re: Virtex clock fanout
25733: 00/09/18: Hal Murray: Re: Virtex clock fanout
25784: 00/09/20: <eml@riverside-machines.com.NOSPAM>: Re: Virtex clock fanout
25644: 00/09/16: Russell Tessier: FPGA'2001 CFP: 2 weeks to deadline
25646: 00/09/15: default@user.com: Good FPGA prototyping boards?
25704: 00/09/18: Ulf Samuelsson: Re: Good FPGA prototyping boards?
25735: 00/09/18: Tim Boescke: Re: Good FPGA prototyping boards?
25736: 00/09/18: Tim Boescke: Re: Good FPGA prototyping boards?
25772: 00/09/19: default@user.com: Re: Good FPGA prototyping boards?
25650: 00/09/16: <shahzad2512@my-deja.com>: Adders in FPGA?
25672: 00/09/17: Peter Alfke: Re: Adders in FPGA?
25770: 00/09/20: Ray Andraka: Re: Adders in FPGA?
25663: 00/09/16: Duane Hague: Reassurance on Xilinx Sought
25666: 00/09/16: B. Joshua Rosen: Re: Reassurance on Xilinx Sought
25668: 00/09/16: Hal Murray: Re: Reassurance on Xilinx Sought
25676: 00/09/17: Pini: Re: Reassurance on Xilinx Sought
25711: 00/09/18: Ray Andraka: Re: Reassurance on Xilinx Sought
25717: 00/09/18: Bob Perlman: Re: Reassurance on Xilinx Sought
25865: 00/09/23: Peter: Re: Reassurance on Xilinx Sought
25870: 00/09/23: Ray Andraka: Re: Reassurance on Xilinx Sought
25673: 00/09/17: Dan: Are SpartanIIs in FG456 drop in replacements for Virtex FG456
25684: 00/09/17: Michael Rhotert: Re: Are SpartanIIs in FG456 drop in replacements for Virtex FG456
25687: 00/09/17: rickman: Re: Are SpartanIIs in FG456 drop in replacements for Virtex FG456
25688: 00/09/17: Nicholas C. Weaver: Re: Are SpartanIIs in FG456 drop in replacements for Virtex FG456
25696: 00/09/18: S. Ramirez: Re: Are SpartanIIs in FG456 drop in replacements for Virtex FG456
25701: 00/09/17: rickman: Re: Are SpartanIIs in FG456 drop in replacements for Virtex FG456
25732: 00/09/18: Hal Murray: Re: Are SpartanIIs in FG456 drop in replacements for Virtex FG456
25753: 00/09/19: S. Ramirez: Re: Are SpartanIIs in FG456 drop in replacements for Virtex FG456
25699: 00/09/18: K. Orthner: Re: Are SpartanIIs in FG456 drop in replacements for Virtex FG456
25708: 00/09/18: Ray Andraka: Re: Are SpartanIIs in FG456 drop in replacements for Virtex FG456
25674: 00/09/17: Hal Murray: Virtex-E: LVDS vs LVPECL
25755: 00/09/19: Tom Burgess: Re: Virtex-E: LVDS vs LVPECL
25678: 00/09/17: <sivakumar1974@my-deja.com>: post route timing simulation- help????
25686: 00/09/17: Walt: Freelance Designer Needed: Protel & FPGA
25730: 00/09/18: S. Ramirez: Re: Freelance Designer Needed: Protel & FPGA
25737: 00/09/18: Gregory C. Read: Re: Freelance Designer Needed: Protel & FPGA
25741: 00/09/19: S. Ramirez: Re: Freelance Designer Needed: Protel & FPGA
25800: 00/09/20: Ben Sanchez: Re: Freelance Designer Needed: Protel & FPGA
25743: 00/09/19: Ray Andraka: Re: Freelance Designer Needed: Protel & FPGA
25761: 00/09/19: <artaaron@my-deja.com>: Re: Freelance Designer Needed: Protel & FPGA
25771: 00/09/20: S. Ramirez: Re: Freelance Designer Needed: Protel & FPGA
25779: 00/09/20: K. Orthner: Re: Freelance Designer Needed: Protel & FPGA
25785: 00/09/20: <eml@riverside-machines.com.NOSPAM>: Re: Freelance Designer Needed: Protel & FPGA
25801: 00/09/20: Peter: Re: Freelance Designer Needed: Protel & FPGA
25805: 00/09/21: <mbmsv@my-deja.com>: Re: Freelance Designer Needed: Protel & FPGA
25812: 00/09/21: S. Ramirez: Re: Freelance Designer Needed: Protel & FPGA
25739: 00/09/18: Dan: Info seems incomplete and unrealistic
25754: 00/09/19: Hawker: PCB side of this
25760: 00/09/19: Ray Andraka: Re: PCB side of this
25740: 00/09/18: Dan: They put the 'Free' in freelance.
25692: 00/09/17: rickman: Xilinx Web Pack
25742: 00/09/19: <bob_42690@my-deja.com>: Re: Xilinx Web Pack
25749: 00/09/19: Tobias F. Garde: Re: Xilinx Web Pack
25752: 00/09/19: K. Orthner: Re: Xilinx Web Pack
25758: 00/09/19: rickman: Re: Xilinx Web Pack
25757: 00/09/19: rickman: Re: Xilinx Web Pack
25818: 00/09/21: Carl Rohrer: Re: Xilinx Web Pack
25848: 00/09/22: rickman: Re: Xilinx Web Pack
25707: 00/09/18: <khatib@ieee.org>: Bluetooth core??
25767: 00/09/19: Vikram Pasham: Re: Bluetooth core??
25863: 00/09/23: Lasse Langwadt Christensen: Re: Bluetooth core??
25710: 00/09/18: Mikhail Matusov: Looking for an Altera APEX eval board
25718: 00/09/18: Muzaffer Kal: Re: Looking for an Altera APEX eval board
25747: 00/09/19: Ernst Zwingenberger: Re: Looking for an Altera APEX eval board
25714: 00/09/18: Gary Watson: Safe voltage regulator for Xilinx XC2S150 part?
25738: 00/09/18: Austin Lesea: Re: Safe voltage regulator for Xilinx XC2S150 part?
25781: 00/09/20: Gary Watson: Re: Safe voltage regulator for Xilinx XC2S150 part?
25802: 00/09/20: Ray Andraka: Re: Safe voltage regulator for Xilinx XC2S150 part?
25810: 00/09/21: Gary Watson: Re: Safe voltage regulator for Xilinx XC2S150 part?
25815: 00/09/21: Dan: Re: Safe voltage regulator for Xilinx XC2S150 part?
25817: 00/09/21: Gary Watson: Re: Safe voltage regulator for Xilinx XC2S150 part?
25750: 00/09/19: <erika_uk@my-deja.com>: Re: Safe voltage regulator for Xilinx XC2S150 part?
25759: 00/09/19: rickman: Re: Safe voltage regulator for Xilinx XC2S150 part?
25722: 00/09/18: Alun: system-gates and system-bytes
25723: 00/09/18: <job_mine@my-deja.com>: Empoyment
25724: 00/09/18: DL: SoC VSIA meeting
25725: 00/09/18: DL: SoC VSIA Meeting
25746: 00/09/19: Arnd Sluiter: JTAG CPLD FPGA
25748: 00/09/19: K. Orthner: Re: JTAG CPLD FPGA
25849: 00/09/22: <chadlamb@my-deja.com>: Re: JTAG CPLD FPGA
25764: 00/09/19: <jing_pang@my-deja.com>: GPS design with xilinx board
25859: 00/09/23: Jonas Thor: Re: GPS design with xilinx board
25756: 00/09/19: Shai Gilat: An Online Course for CPLD and FPGA design
25780: 00/09/20: Philip Freidin: Re: An Online Course for CPLD and FPGA design
25822: 00/09/22: Dan: What a badly written advertisement EOM
25959: 00/09/27: prem: Re: An Online Course for CPLD and FPGA design
25961: 00/09/28: prem: Re: An Online Course for CPLD and FPGA design
25762: 00/09/19: <erika_uk@my-deja.com>: VHDL to SCHEMATIC
25763: 00/09/19: <erika_uk@my-deja.com>: Re: VHDL to SCHEMATIC
25790: 00/09/20: Eric Pearson: Re: VHDL to SCHEMATIC
25799: 00/09/20: <erika_uk@my-deja.com>: Re: VHDL to SCHEMATIC
25792: 00/09/20: Phil James-Roxby: Re: VHDL to SCHEMATIC
25794: 00/09/20: Jamie Sanderson: Re: VHDL to SCHEMATIC
25806: 00/09/21: spyng: Re: VHDL to SCHEMATIC
25766: 00/09/19: <jing_pang@my-deja.com>: GPS design with xilinx board
25777: 00/09/20: Charles Wagner: unexpanded XU macros
25782: 00/09/20: Reynald Pireyre: FPGA compiler abort 219
25797: 00/09/20: Vikram Pasham: Re: FPGA compiler abort 219
26005: 00/09/30: Bill Lenihan: Re: FPGA compiler abort 219
25786: 00/09/20: <eml@riverside-machines.com.NOSPAM>: Synthesiser comparisons (was: FPGA Express strikes again)
25803: 00/09/21: Ray Andraka: Re: Synthesiser comparisons (was: FPGA Express strikes again)
25954: 00/09/27: Andy Peters: Re: Synthesiser comparisons (was: FPGA Express strikes again)
26011: 00/09/30: Keith R. Williams: Re: Synthesiser comparisons (was: FPGA Express strikes again)
25787: 00/09/20: Josef Däubler: Placement and routing of Xilinx physical macro can't be locked
25793: 00/09/20: Martin.J Thompson: Re: Virtex 'shutdown' phenomenon
25811: 00/09/21: <petter@scimba.dolphinics.no>: Alliance 3.1i CAE Libs install hangs under Solaris
25821: 00/09/22: <bob_42690@my-deja.com>: Re: Alliance 3.1i CAE Libs install hangs under Solaris
25827: 00/09/22: <petter@scimba.dolphinics.no>: Re: Alliance 3.1i CAE Libs install hangs under Solaris
25842: 00/09/22: Paul Smith: Re: Alliance 3.1i CAE Libs install hangs under Solaris
25891: 00/09/25: <petter@scimba.dolphinics.no>: Re: Alliance 3.1i CAE Libs install hangs under Solaris
25813: 00/09/21: anup: Is Incremental Routing Supported in Xilinx -Foundation 3.1
25816: 00/09/21: Scott Thibault: Announce: Free HC11 CPU Core
25833: 00/09/22: <eml@riverside-machines.com.NOSPAM>: Re: Announce: Free HC11 CPU Core
25834: 00/09/22: Ray Andraka: Re: Announce: Free HC11 CPU Core
25835: 00/09/22: S. Ramirez: Re: Announce: Free HC11 CPU Core
25836: 00/09/22: Scott Thibault: Re: Announce: Free HC11 CPU Core
25843: 00/09/22: S. Ramirez: Re: Announce: Free HC11 CPU Core
25853: 00/09/22: Eric Braeden: Re: Announce: Free HC11 CPU Core
25856: 00/09/23: S. Ramirez: Re: Announce: Free HC11 CPU Core
25860: 00/09/23: <eddy_bobby@my-deja.com>: Re: Announce: Free HC11 CPU Core
26495: 00/10/18: M.B.: Re: Announce: Free HC11 CPU Core
25904: 00/09/26: yaohan: Re: Announce: Free HC11 CPU Core
25906: 00/09/26: S. Ramirez: Re: Announce: Free HC11 CPU Core
26487: 00/10/18: Joachim Strombergson: Re: Announce: Free HC11 CPU Core
26523: 00/10/19: Joachim Strombergson: More errata. (Was: Re: Announce: Free HC11 CPU Core)
25819: 00/09/21: John Fielden: Uart core?
25820: 00/09/21: Mikhail Matusov: Re: Uart core?
25823: 00/09/21: default@user.com: CORDIC COS/SIN with FPGA implementation
25857: 00/09/23: Ray Andraka: Re: CORDIC COS/SIN with FPGA implementation
25873: 00/09/23: default@user.com: Re: CORDIC COS/SIN with FPGA implementation
25875: 00/09/24: rickman: Re: CORDIC COS/SIN with FPGA implementation
25876: 00/09/24: Ray Andraka: Re: CORDIC COS/SIN with FPGA implementation
25937: 00/09/26: Netscape User: Re: CORDIC COS/SIN with FPGA implementation
25824: 00/09/21: Tomek: Category : tri state data bus
25892: 00/09/25: Johan Petersson: Re: Category : tri state data bus
25825: 00/09/21: Tomek: Category : Why CRs are cleared?
25828: 00/09/22: <eml@riverside-machines.com.NOSPAM>: Re: Category : Why CRs are cleared?
25826: 00/09/21: Tomek: Category : timinig testbench
25830: 00/09/22: Tomasz Brychcy: Is correct code?
25850: 00/09/22: Mujtaba Hamid: Re: Is correct code?
25893: 00/09/25: Johan Petersson: Re: Is correct code?
25831: 00/09/22: Henrik A. =?iso-8859-1?Q?S=F8rensen?=: Pack I/O Reg/Latches into IOBs
25837: 00/09/22: Carl Rohrer: Re: Pack I/O Reg/Latches into IOBs
25839: 00/09/22: Brian Philofsky: Re: Pack I/O Reg/Latches into IOBs
25844: 00/09/22: Vikram Pasham: Re: Pack I/O Reg/Latches into IOBs
26006: 00/09/30: Bill Lenihan: Re: Pack I/O Reg/Latches into IOBs
26012: 00/09/30: Rick Filipkiewicz: Re: Pack I/O Reg/Latches into IOBs
25832: 00/09/22: Stephen Ingram: Virtex: partial reconfiguration
25838: 00/09/22: Carl Rohrer: Re: Virtex: partial reconfiguration
25841: 00/09/22: Robert Posey: Multi-Arch, Moderately High performance VHDL FPGA Code?
25855: 00/09/23: Ray Andraka: Re: Multi-Arch, Moderately High performance VHDL FPGA Code?
25897: 00/09/25: Robert Posey: Re: Multi-Arch, Moderately High performance VHDL FPGA Code?
25894: 00/09/25: Johan Petersson: Re: Multi-Arch, Moderately High performance VHDL FPGA Code?
25845: 00/09/22: Carlhermann Schlehaus: memory interface trouble...
25846: 00/09/22: Mike Treseler: Re: memory interface trouble...
25847: 00/09/22: Peter Alfke: Re: memory interface trouble...
25854: 00/09/23: tim simpson: Re: memory interface trouble...
25868: 00/09/23: Carlhermann Schlehaus: Re: memory interface trouble...
25871: 00/09/24: Peter Alfke: Re: memory interface trouble...
25877: 00/09/24: Carlhermann Schlehaus: Re: memory interface trouble...
25881: 00/09/24: Peter Alfke: Re: memory interface trouble...
25882: 00/09/24: Carlhermann Schlehaus: Re: memory interface trouble...
25880: 00/09/24: Peter Alfke: Re: MAPLD
25869: 00/09/23: Carlhermann Schlehaus: Re: memory interface trouble...
25852: 00/09/22: James S.: Need Help: Xilinx FastCLK (XC4000XLA)
25858: 00/09/23: K.J. Seefried III: PDP-11
25861: 00/09/23: Daniel Nilsson: dp ram
25864: 00/09/23: Ray Andraka: Re: dp ram
25862: 00/09/23: ChenSongWei: Category : why is 0?
25916: 00/09/26: chsw: Re: Category : why is 0?
25872: 00/09/24: Barry Schneider: Looking for Long Island Verilog or VHDL designers
25874: 00/09/23: Guest Internet User: Xilinx Student Edition 2.1i with "Digital Design:Principles and
25879: 00/09/24: Jan Gray: Re: Xilinx Student Edition 2.1i with "Digital Design:Principles and Practices"
25900: 00/09/25: Anna Acevedo: Re: Xilinx Student Edition 2.1i with "Digital Design:Principles and
25911: 00/09/25: Guest Internet User: Re: Xilinx Student Edition 2.1i with "Digital Design:Principles and
25878: 00/09/24: Gary Watson: Paranoid...
25923: 00/09/26: Johan Petersson: Re: Paranoid...
25883: 00/09/25: Anoop Nannra: 20 bit to 64 bit bus conversion
25884: 00/09/24: David Forbes: Re: 20 bit to 64 bit bus conversion
25885: 00/09/25: K. Orthner: Re: 20 bit to 64 bit bus conversion
25896: 00/09/25: rickman: Re: 20 bit to 64 bit bus conversion
25886: 00/09/24: Neo Wei Thiam: FPGA for PCM coded DTMF transmission?
25889: 00/09/25: Ulf Samuelsson: Re: FPGA for PCM coded DTMF transmission?
25899: 00/09/25: rickman: Re: FPGA for PCM coded DTMF transmission?
25888: 00/09/25: Nial Stewart: Dual monitor display possible with modelsim on a PC?
25890: 00/09/25: Gary Watson: Re: Dual monitor display possible with modelsim on a PC?
25901: 00/09/25: Keith R. Williams: Re: Dual monitor display possible with modelsim on a PC?
25895: 00/09/25: Marc Battyani: Using the xilinx "pull-up to 5V" in VHDL
25909: 00/09/26: K. Orthner: Re: Using the xilinx "pull-up to 5V" in VHDL
25913: 00/09/26: Marc Battyani: Re: Using the xilinx "pull-up to 5V" in VHDL
25915: 00/09/26: Klaus Falser: Re: Using the xilinx "pull-up to 5V" in VHDL
25918: 00/09/26: Marc Battyani: Re: Using the xilinx "pull-up to 5V" in VHDL
25919: 00/09/26: K. Orthner: Re: Using the xilinx "pull-up to 5V" in VHDL
25920: 00/09/26: Marc Battyani: Re: Using the xilinx "pull-up to 5V" in VHDL
25942: 00/09/27: Klaus Falser: Re: Using the xilinx "pull-up to 5V" in VHDL
25912: 00/09/25: Steven: Re: Using the xilinx "pull-up to 5V" in VHDL
25914: 00/09/26: Marc Battyani: Re: Using the xilinx "pull-up to 5V" in VHDL
25902: 00/09/25: Eric Smith: Difference between Foundation Base and Foundation ISE Base Express?
25903: 00/09/25: rickman: Re: Difference between Foundation Base and Foundation ISE Base Express?
25978: 00/09/28: Carl Rohrer: Re: Difference between Foundation Base and Foundation ISE Base Express?
25905: 00/09/26: yaohan: Point to point core
25907: 00/09/26: Barry Schneider: Looking for ASIC,FPGA Designers
25908: 00/09/26: <shahzad2512@my-deja.com>: FEC in FPGAs?
26083: 00/10/03: Bill Wilkie: Re: FEC in FPGAs?
26090: 00/10/03: <erika_uk@my-deja.com>: Re: FEC in FPGAs?
25910: 00/09/26: <sivakumar1974@my-deja.com>: clock skew,,,,,,,DLL instantiation
25917: 00/09/26: Christophe Heyert: Coregen
25928: 00/09/26: Johan Petersson: Re: Coregen
26077: 00/10/03: Christophe Heyert: Re: Coregen
25921: 00/09/26: Richard Meester: Global clock buffers and secondary clock buffers.
25922: 00/09/26: Simon: Re: Global clock buffers and secondary clock buffers.
25929: 00/09/26: Richard Meester: Re: Global clock buffers and secondary clock buffers.
25930: 00/09/26: Simon: Re: Global clock buffers and secondary clock buffers.
25924: 00/09/26: SteVe: Re: Global clock buffers and secondary clock buffers.
25926: 00/09/26: Hanna Bruno: Re: Global clock buffers and secondary clock buffers.
25925: 00/09/26: Lars Rzymianowicz: Synopsys FPGA Compiler II on Solaris
25991: 00/09/29: =?iso-8859-1?Q?J=F6rg?= Ritter: Re: Synopsys FPGA Compiler II on Solaris
26169: 00/10/06: Lars Rzymianowicz: Re: Synopsys FPGA Compiler II on Solaris
26526: 00/10/19: =?iso-8859-1?Q?J=F6rg?= Ritter: Re: Synopsys FPGA Compiler II on Solaris
26527: 00/10/19: Georg Acher: Re: Synopsys FPGA Compiler II on Solaris
26559: 00/10/20: Lars Rzymianowicz: Re: Synopsys FPGA Compiler II on Solaris
26007: 00/09/30: Bill Lenihan: Re: Synopsys FPGA Compiler II on Solaris
25927: 00/09/26: Mike DeKoker: VirtexE readback via JTAG
25931: 00/09/26: Andy Peters: FPGA Express strikes again! Xilinx response
25933: 00/09/27: S. Ramirez: Re: FPGA Express strikes again! Xilinx response
25953: 00/09/27: Andy Peters: Re: FPGA Express strikes again! Xilinx response
25955: 00/09/28: <bob_42690@my-deja.com>: Re: FPGA Express strikes again! Xilinx response
26014: 00/09/30: Ray Andraka: Re: FPGA Express strikes again! Xilinx response
26017: 00/10/01: Muzaffer Kal: Re: FPGA Express strikes again! Xilinx response
26019: 00/10/01: Ray Andraka: Re: FPGA Express strikes again! Xilinx response
26043: 00/10/01: Rick Filipkiewicz: Re: FPGA Express strikes again! Xilinx response
26050: 00/10/02: Keith R. Williams: Re: FPGA Express strikes again! Xilinx response
26055: 00/10/02: Rick Filipkiewicz: Re: FPGA Express strikes again! Xilinx response
26062: 00/10/02: Andy Peters: Re: FPGA Express strikes again! Xilinx response
26070: 00/10/03: Keith R. Williams: Re: FPGA Express strikes again! Xilinx response
26073: 00/10/03: <bob_42690@my-deja.com>: Re: FPGA Express strikes again! Xilinx response
26075: 00/10/03: Keith R. Williams: Re: FPGA Express strikes again! Xilinx response
26076: 00/10/02: Phil Hays: Amplify experience, was: FPGA Express strikes again! Xilinx response
26091: 00/10/03: Ray Andraka: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26097: 00/10/03: Phil Hays: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26114: 00/10/04: Ray Andraka: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26140: 00/10/05: Jamie Lokier: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26153: 00/10/05: rickman: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26172: 00/10/06: Jamie Lokier: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26191: 00/10/08: Neil Franklin: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26193: 00/10/07: rickman: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26207: 00/10/08: Neil Franklin: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26209: 00/10/08: rickman: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26261: 00/10/10: Jamie Lokier: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26287: 00/10/10: Neil Franklin: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26326: 00/10/11: rickman: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26332: 00/10/11: Phil Hays: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26341: 00/10/12: Jamie Lokier: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26359: 00/10/13: rickman: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26379: 00/10/13: Jamie Lokier: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26347: 00/10/12: Andy Peters: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26349: 00/10/12: Jamie Lokier: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26360: 00/10/13: rickman: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26353: 00/10/13: Neil Franklin: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26361: 00/10/13: rickman: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26402: 00/10/15: Neil Franklin: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26403: 00/10/14: rickman: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26417: 00/10/15: Neil Franklin: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26422: 00/10/16: rickman: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26454: 00/10/16: Neil Franklin: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26405: 00/10/15: Jan Gray: 35 CLB 8-bit MCU
26406: 00/10/15: rickman: Re: 35 CLB 8-bit MCU
26215: 00/10/09: Zoltan Kocsi: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26262: 00/10/10: Jamie Lokier: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26260: 00/10/10: Jamie Lokier: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26197: 00/10/08: Andy Holt: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26198: 00/10/08: Hal Murray: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26234: 00/10/09: Andy Peters: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26246: 00/10/10: Kent Orthner: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26249: 00/10/10: Keith R. Williams: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26252: 00/10/10: Kent Orthner: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26289: 00/10/11: Neil Franklin: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26327: 00/10/11: rickman: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26348: 00/10/12: Andy Peters: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26362: 00/10/13: rickman: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26385: 00/10/13: Andy Peters: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26412: 00/10/15: Neil Franklin: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26416: 00/10/15: rickman: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26446: 00/10/16: Andy Peters: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26472: 00/10/17: Neil Franklin: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26356: 00/10/13: Keith R. Williams: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26322: 00/10/12: Keith R. Williams: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26324: 00/10/12: Kent Orthner: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26357: 00/10/13: Keith R. Williams: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26342: 00/10/12: Jamie Lokier: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26358: 00/10/13: Keith R. Williams: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26383: 00/10/13: Jamie Lokier: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26269: 00/10/10: Ray Andraka: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26280: 00/10/10: Andy Peters: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26323: 00/10/12: Keith R. Williams: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26284: 00/10/10: <eml@riverside-machines.com.NOSPAM>: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26285: 00/10/10: Jamie Lokier: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26297: 00/10/11: Ray Andraka: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26290: 00/10/11: Zoltan Kocsi: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26253: 00/10/10: Ray Andraka: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26265: 00/10/10: Jamie Lokier: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26281: 00/10/10: Andy Peters: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26303: 00/10/11: Jamie Lokier: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26305: 00/10/11: Hal Murray: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26309: 00/10/11: Jamie Lokier: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26314: 00/10/11: Andy Peters: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26458: 00/10/16: Ray Andraka: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26457: 00/10/16: Ray Andraka: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26263: 00/10/10: Jamie Lokier: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26272: 00/10/10: rickman: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26276: 00/10/10: Jamie Lokier: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26273: 00/10/10: rickman: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26154: 00/10/05: Ray Andraka: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26160: 00/10/06: Zoltan Kocsi: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26192: 00/10/08: Neil Franklin: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26194: 00/10/07: rickman: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26208: 00/10/08: Neil Franklin: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26210: 00/10/08: rickman: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26268: 00/10/10: Jamie Lokier: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26235: 00/10/09: Andy Peters: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26241: 00/10/09: rickman: Alternative hardware development tools Was: Amplify experience
26254: 00/10/10: Ray Andraka: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26267: 00/10/10: Jamie Lokier: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26266: 00/10/10: Jamie Lokier: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26292: 00/10/11: Zoltan Kocsi: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26298: 00/10/10: rickman: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26456: 00/10/16: Ray Andraka: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26464: 00/10/17: rickman: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26096: 00/10/04: Keith R. Williams: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26101: 00/10/03: Phil Hays: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26212: 00/10/09: Keith R. Williams: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26217: 00/10/08: Phil Hays: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26236: 00/10/09: Andy Peters: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26293: 00/10/10: Phil Hays: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26331: 00/10/11: Phil Hays: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26250: 00/10/10: Keith R. Williams: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26321: 00/10/12: Keith R. Williams: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26459: 00/10/16: Ray Andraka: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26482: 00/10/17: Phil Hays: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26484: 00/10/18: Ray Andraka: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26522: 00/10/18: Phil Hays: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26525: 00/10/19: Ray Andraka: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26025: 00/10/01: Keith R. Williams: Re: FPGA Express strikes again! Xilinx response
26190: 00/10/07: Stefan Ludwig: Re: FPGA Express strikes again! Xilinx response
26199: 00/10/08: Rick Filipkiewicz: Re: FPGA Express strikes again! Xilinx response
25932: 00/09/27: Daniel Nilsson: hdl
25934: 00/09/27: Jim Granville: Re: hdl
25938: 00/09/27: Daniel Nilsson: SV: hdl
25943: 00/09/27: Theron Hicks: Re: SV: hdl
25964: 00/09/28: Johan Petersson: Re: SV: hdl
25999: 00/09/29: Ben Franchuk: Look MOM ... No Hardware
26010: 00/09/30: Duane: Re: SV: hdl
25980: 00/09/28: Alun: Re: hdl
25946: 00/09/27: Phil James-Roxby: Re: hdl
25935: 00/09/26: chsw: Category : Subject
25965: 00/09/28: Johan Petersson: Re: Category : Subject
25936: 00/09/27: DL: VSIA System-Chip Update
25939: 00/09/27: Martin.J Thompson: Re: Simon , decoupling caps
25951: 00/09/27: <eml@riverside-machines.com.NOSPAM>: Re: Simon , decoupling caps
25952: 00/09/27: Austin Lesea: Re: Simon , decoupling caps
26155: 00/10/05: Bob Baman: Re: Simon , decoupling caps
26233: 00/10/09: Austin Lesea: Re: Simon , decoupling caps
25940: 00/09/27: Martin.J Thompson: Re: Synthesiser comparisons (was: FPGA Express strikes again)
25970: 00/09/28: Johan Petersson: Re: Synthesiser comparisons (was: FPGA Express strikes again)
25941: 00/09/27: Alan Horton: ABEL truth table for 8-1 Mux
25948: 00/09/27: rickman: Re: ABEL truth table for 8-1 Mux
25963: 00/09/28: Alan Horton: Re: ABEL truth table for 8-1 Mux
25968: 00/09/28: <eml@riverside-machines.com.NOSPAM>: Re: ABEL truth table for 8-1 Mux
25950: 00/09/27: Rick Filipkiewicz: Re: ABEL truth table for 8-1 Mux
25971: 00/09/28: Alan Horton: Re: ABEL truth table for 8-1 Mux (The solution)
25979: 00/09/29: Jim Granville: Re: ABEL truth table for 8-1 Mux (The solution)
25944: 00/09/27: Lee Weston: Preserving nets using Maxplus2 (9.5)
25949: 00/09/27: bob elkind: Re: Preserving nets using Maxplus2 (9.5)
25962: 00/09/28: Lee Weston: Re: Preserving nets using Maxplus2 (9.5)
25945: 00/09/27: John Kortink: Altera EPM3256ATC144 equivalents
25947: 00/09/27: Mike Treseler: Re: Altera EPM3256ATC144 equivalents
25956: 00/09/27: Yury Wolf-Sonkin: RE: timing constraints
25960: 00/09/28: Richard Meester: Re: timing constraints
25957: 00/09/28: <graham_moss@my-deja.com>: atmel verses altera
25969: 00/09/28: S. Ramirez: Re: atmel verses altera
25990: 00/09/29: Ulf Samuelsson: Re: atmel verses altera
26013: 00/09/30: Ray Andraka: Re: atmel verses altera
26015: 00/09/30: rickman: Re: atmel verses altera
26021: 00/10/01: Ray Andraka: Re: atmel verses altera
26023: 00/09/30: rickman: Re: atmel verses altera
26027: 00/10/01: Ray Andraka: Re: atmel verses altera
25958: 00/09/27: Netscape User: Synplicity vs Xilinx FPGA Express
25967: 00/09/28: S. Ramirez: Re: Synplicity vs Xilinx FPGA Express
25975: 00/09/28: Muzaffer Kal: Re: Synplicity vs Xilinx FPGA Express
25966: 00/09/28: Marc Battyani: FPGA Express pb
25973: 00/09/28: Mikhail Matusov: Re: FPGA Express pb
25974: 00/09/28: Marc Battyani: Re: FPGA Express pb
25976: 00/09/28: Klaus Falser: Re: FPGA Express pb
25977: 00/09/28: Marc Battyani: Re: FPGA Express pb
25972: 00/09/28: Kate Atkins: Xilinx clkdll not driven from IBUFG
25981: 00/09/29: ±è¾ç·¡_YLKIM: some question about synplify tool
25982: 00/09/29: S. Ramirez: Re: some question about synplify tool
26004: 00/09/30: Rick Filipkiewicz: Re: some question about synplify tool
25983: 00/09/29: <snyderkena@my-deja.com>: FPGA development on the cheap?
25984: 00/09/28: Dave Vanden Bout: Re: FPGA development on the cheap?
25985: 00/09/29: Wolfgang Loewer: Re: FPGA development on the cheap?
25986: 00/09/29: Ulf Samuelsson: Re: FPGA development on the cheap?
25987: 00/09/29: Ulf Samuelsson: Re: FPGA development on the cheap?
25988: 00/09/29: Ulf Samuelsson: Re: FPGA development on the cheap?
25989: 00/09/29: Ulf Samuelsson: Re: FPGA development on the cheap?
25992: 00/09/30: Tony Burch: Re: FPGA development on the cheap?
26034: 00/10/01: Aaron Holtzman: Re: FPGA development on the cheap?
25993: 00/09/29: Manfred Kraus: Xilinx Logicore Generator
25994: 00/09/29: Muzaffer Kal: Re: Xilinx Logicore Generator
25996: 00/09/29: Rick Filipkiewicz: Re: Xilinx Logicore Generator
25995: 00/09/29: Marc Battyani: Xilinx 2.1 to 3.1 pb
25998: 00/09/29: Marc Battyani: Re: Xilinx 2.1 to 3.1 pb
26000: 00/09/29: Andy Peters: Funny Message
26001: 00/09/30: S. Ramirez: Re: Funny Message
26002: 00/09/30: Ben Franchuk: Re: Xilinx Student Edition 2.1i first impressions
26046: 00/10/01: Netscape User: Re: Xilinx Student Edition 2.1i first impressions
26009: 00/09/30: kashjohal: Altera FPGA experts needed
26016: 00/09/30: S. Ramirez: Re: Altera FPGA experts needed
26030: 00/09/30: Netscape User: Re: Altera FPGA experts needed
26033: 00/10/01: S. Ramirez: Re: Altera FPGA experts needed
26035: 00/10/01: <bob_42690@my-deja.com>: Re: Altera FPGA experts needed
26089: 00/10/03: Steve Rencontre: Re: Altera FPGA experts needed
26036: 00/10/01: Jamie Lokier: Re: Altera FPGA experts needed
26024: 00/09/30: news.gate.net: Xilinx XC2018 Design tools
26029: 00/10/01: Ray Andraka: Re: Xilinx XC2018 Design tools
26054: 00/10/02: Dave Vanden Bout: Re: Xilinx XC2018 Design tools
26206: 00/10/08: Peter: Re: Xilinx XC2018 Design tools
26031: 00/09/30: Netscape User: Xilinx Student Edition 2.1i first impressions
26063: 00/10/02: Andy Peters: Re: Xilinx Student Edition 2.1i first impressions
26094: 00/10/03: Netscape User: Re: Xilinx Student Edition 2.1i first impressions
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