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Try this with Synplify Pro v6.0, running on an NT4 SP6 box. From the main menu, choose Help | License Agreement. You'll get a message box saying, "The topic does not exist. Contact your application vendor for an updated Help file. (129)" I guess they figured that no one reads license agreements... and since there ISN'T one ... hmmmm!!! -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d uArticle: 26001
See, you already need an upgrade! -Simon Ramirez, Consultant Synchronous Design, Inc. "Andy Peters n o a o [.] e d u>" <"apeters <"@> wrote in message news:8r3ahf$19hb$1@noao.edu... > Try this with Synplify Pro v6.0, running on an NT4 SP6 box. > > From the main menu, choose Help | License Agreement. > > You'll get a message box saying, "The topic does not exist. Contact > your application vendor for an updated Help file. (129)" > > I guess they figured that no one reads license agreements... > > and since there ISN'T one ... hmmmm!!! > > -- a > ---------------------------- > Andy Peters > Sr. Electrical Engineer > National Optical Astronomy Observatory > 950 N Cherry Ave > Tucson, AZ 85719 > apeters (at) n o a o [dot] e d u >Article: 26002
Netscape User wrote: > > Having used both XSE 1.3 and XSE 1.5 extensively, I feel compelled to > inform the world about my initial impressions of XSE 2.1i. But the big question is what specific chips and sizes are supported. Ben. -- "We do not inherit our time on this planet from our parents... We borrow it from our children." "Luna family of Octal Computers" http://www.jetnet.ab.ca/users/bfranchukArticle: 26003
a) No matter what synthesis tool I use, I don't pay too much attention to the timing estimates it produces (I just rely on what the post-P&R timing analysis says) because these estimates are based on wire-load models that are an average of hundreds of 'representative' designs that the tool vendor thinks are typical -- may or may not have any relationship to MY design. b) I agree Synlify (Synplicity) is head and tails better than FPGA Compiler II (Synopsys) ... and I just have plain Synplify, not Synplify Pro (yet). c) I just discovered that FPGA Compiler II's much-touted "behavioral retiming" -- i.e., shuffling combinatorial logic across register boundaries for faster pipelined designs -- DOES NOT EVEN WORK (ver 3.4, Synopsys claims it'll work in the next release). Since FPGA Compiler II is supposed to be more or less the same thing as FPGA Express, I'm curious if any FE users have experienced this, too. Comments, please. Joel Kolstad wrote: > <wq998@yahoo.com> wrote in message news:8pus5o$km1$1@nnrp1.deja.com... > > I am not rich, but do have FPGA Express v3.4 (with Foundation v3.1) and > > Synplicity Pro v6.0. Overall, I like to use Synplicity much more. Its > > schematic view and critical path analysis are very helpful. > > If you can believe it... in my experience it's timing estimates are pretty > far off. It tends to overestimate logic delay and underestimate route > delay. Our current design has a 53MHz clock running around, and meets PAR > timing just fine, even though Synplify claims the timing margin is -5.6ns. > Yeah, right. > > > The > > performance of systhersized results are almost always better than > > Synopsys. > > FPGA Express is pretty dismal. People who bitch about how buggy Microsoft's > operating systems are should try FPGA Express for awhile... > > > Only one design forced me to switch back to Synopsys. It has 12 > > 125MHz/16bit Serdes inputs (12 Rx clocks routing locally) across to a > > global 133MHz clock domain. Synplicity failed. > > [Cough] > > We've got an HP, I mean Agilent, HDMP-1536 running at fiber channel speeds. > The '1536 needs byte-wide data feed to it at 106.25MHz, and spits out 2 > bytes of data with two clocks 180 degrees out of phase. We had to build the > ROM32x1's ourselves to make timing. Synplify would have met the timing, but > the ROM it inferes exposes a bug in Xilinx PAR that causes PAR to error out. > Specifically, the 6B->5B decoder needs a 64 entry ROM, and the mux Synplify > builds to route the outputs of two ROM32x1's together causes the problem. > > ---Joel Kolstad -- ============================== William Lenihan lenihan3weNOSPAM@earthlink.net ==============================Article: 26004
"±è¾ç·¡_YLKIM" wrote: > I have r600 & r531. but I need r514 version. > > If you problem to send mail, let me know where is it. > > Thank you. > > PS: I tried for find r514 in synplicity web-site but i can't find. As a matter of interest why do you have to go back that far ? Is it a bug hunt ? The earliest copy I hold is 522a which I downloaded on 15/10/99 - nearly a year ago.Article: 26005
We've been using FPGA Compiler II (ver 3.4) successfully for a number of Virtex designs, but I recently inherited someone else's Verilog design that had a lot of poor coding constructs and not much in the way of heirarchy (10% of design in submodules, 90% in one giant top level module). When we try to synthesize this design on an UltraSparc with 1 Gbyte of RAM (our best machine) FCII dies and we get this Abort 219 message on the unix command line. I don't remember what Synopsys said or promised us about this problem ...... our ultimate solution: we went with Synplicity's tool, which synthesizes this design quite nicely in 90 seconds on a PC (Pentium III w/ 256 Mbyte RAM). Reynald Pireyre wrote: > HI > I use FPGA compiler II, (target xilinx) > All VHDL source has been compiled. > But during elaborating on Xilinx target, the soft crash. > And report file is not available , only "abort at 219" !!!! > You know this problem > thanks > reynald -- ============================== William Lenihan lenihan3weNOSPAM@earthlink.net ==============================Article: 26006
You should never have to instantiate Xilinx-specific I/O registers in the code to make this happen. As long as there is no combinatorial logic between pin & register and as long as the type (D-type w/ proper kind of reset/preset) of register is do-able in the IOB. What you must do though is push the registers into the IOB in the synthesis tool (see your synth tool documentation for the switch to do this) AND set the appropriate constraints and options in the Xilinx Alliance tool. Trying to do it with Alliance alone won't work -- the IOB-type-registers have to be there in the EDIF netlist first, and that's the job of your synthesis tool. "Henrik A. Sørensen" wrote: > Hey you all. > > I have a problem concerning mapping some of my regsters directly into IO > PADS. In my VHDL code, I have declared some registers - by the standard > process form for a register. Xilinx Design manager has also translated > my source edif file right, but implements the registers within CLB, even > though the Flip-flops output is connected directley to a output. I have > tried the Map option: Pack I/O registers/Latches into IOBs for Input and > output. But this option does NOT influence the mapping???? Is there some > way to indicate where a reister should be mapped whitin the source VHDL > code??? Or are there other guidelines?? > > Thanks in advance > > Henrik -- ============================== William Lenihan lenihan3weNOSPAM@earthlink.net ==============================Article: 26007
We have this problem when we use FCII via a PC telneting to a Sun
workstation. When we sit at the workstation itself, we don't have this
problem. Can't remember what Synopsys said about their future solution
for this ...... and we don't care: other problems steered us to
Synplicity, which works like a champ.
Lars Rzymianowicz wrote:
> Hi folks!
>
> We are using FC2 on SunOS5.8, with either CDE or KDE/Openwin.
> Everything works fine, except the Online Help. When clicking
> the Help -> Topics button, a winhelp process is started, but
> never shows up on the screen. FC2 then stalls forever...
> Has anyone seen this behavior? Workarounds?
>
> The README mentions some problems with the Online Help,
> but the -t or -f switches don't solve it.
>
> Any ideas?
>
> Lars
> --
> Address: University of Mannheim; B6, 26; 68159 Mannheim, Germany
> Tel: +(49) 621 181-2716, Fax: -2713
> email: larsrzy@{ti.uni-mannheim.de, atoll-net.de, computer.org}
> Homepage: http://mufasa.informatik.uni-mannheim.de/lsra/persons/lars/
--
==============================
William Lenihan
lenihan3weNOSPAM@earthlink.net
==============================
Article: 26008Last time I checked, one of the differentiators between FCII and FPGA Express was FPGA Express did not support redistribution of combinatorial logic across pipelines, it does not support DC shell scripting and the use of designware components, so by definition, reshuffling logic across register boundaries does not work with FPGA Express. Bob In article <39D59A0E.E802F52B@earthlink.net>, lenihan3weNOSPAM@earthlink.net wrote: > a) No matter what synthesis tool I use, I don't pay too much attention to the > timing estimates it produces (I just rely on what the post-P&R timing analysis > says) because these estimates are based on wire-load models that are an average > of hundreds of 'representative' designs that the tool vendor thinks are typical > -- may or may not have any relationship to MY design. > > b) I agree Synlify (Synplicity) is head and tails better than FPGA Compiler II > (Synopsys) ... and I just have plain Synplify, not Synplify Pro (yet). > > c) I just discovered that FPGA Compiler II's much-touted "behavioral retiming" > -- i.e., shuffling combinatorial logic across register boundaries for faster > pipelined designs -- DOES NOT EVEN WORK (ver 3.4, Synopsys claims it'll work in > the next release). Since FPGA Compiler II is supposed to be more or less the > same thing as FPGA Express, I'm curious if any FE users have experienced this, > too. Comments, please. > > Joel Kolstad wrote: > > > <wq998@yahoo.com> wrote in message news:8pus5o$km1 $1@nnrp1.deja.com... > > > I am not rich, but do have FPGA Express v3.4 (with Foundation v3.1) and > > > Synplicity Pro v6.0. Overall, I like to use Synplicity much more. Its > > > schematic view and critical path analysis are very helpful. > > > > If you can believe it... in my experience it's timing estimates are pretty > > far off. It tends to overestimate logic delay and underestimate route > > delay. Our current design has a 53MHz clock running around, and meets PAR > > timing just fine, even though Synplify claims the timing margin is - 5.6ns. > > Yeah, right. > > > > > The > > > performance of systhersized results are almost always better than > > > Synopsys. > > > > FPGA Express is pretty dismal. People who bitch about how buggy Microsoft's > > operating systems are should try FPGA Express for awhile... > > > > > Only one design forced me to switch back to Synopsys. It has 12 > > > 125MHz/16bit Serdes inputs (12 Rx clocks routing locally) across to a > > > global 133MHz clock domain. Synplicity failed. > > > > [Cough] > > > > We've got an HP, I mean Agilent, HDMP-1536 running at fiber channel speeds. > > The '1536 needs byte-wide data feed to it at 106.25MHz, and spits out 2 > > bytes of data with two clocks 180 degrees out of phase. We had to build the > > ROM32x1's ourselves to make timing. Synplify would have met the timing, but > > the ROM it inferes exposes a bug in Xilinx PAR that causes PAR to error out. > > Specifically, the 6B->5B decoder needs a 64 entry ROM, and the mux Synplify > > builds to route the outputs of two ROM32x1's together causes the problem. > > > > ---Joel Kolstad > > -- > ============================== > William Lenihan > lenihan3weNOSPAM@earthlink.net > ============================== > > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26009
We are setting up a design center in new delhi, india. Pre-IPO company. Stock options in US parent company. www.forasic.com regards, KashArticle: 26010
Theron Hicks wrote: > > Daniel Nilsson wrote: > > > I mean a schematic that tells you how to build the design using ordinary 74 > > logic. I am a student, and fpga's cost me very much, so if I only do a small > > design it makes more sense for me to put it in discrete logic. I also wonder > > if anyone has knowledge of putting part of the logic outside the fpga to > > reduce fpga size? (counters, shift-registers) > > Daniel, > A small FPGA (5000 equivalent gates) circuit can be done for about $15 (US) > in parts in single piece quantities. This assumes a Xilinx XCS05XL and a serial > configuration prom. You do however need a prom programmer. I happen to like > the Atmel reprogrammable proms. Atmel even has a simple prom programmer circuit > on thier web site. You would be wasting money even in small quantities to pull > gates out from the FPGA unless there is some other reason than to cut gate > count. Xilinx provides a similar very simple circuit for their JTAG parts (such as the XC18V serial PROMs), to program them via a parallel port with only a couple of very inexpensive components. It looks like a very easy way to go. http://www.xilinx.com/support/programr/jtag_cable.pdf I doubt Xilinx will give away the software, but this should not be too difficult to write. I plan to put a similar interface and a parallel port connector onto a board I am working on, and will write the software (under Linux - at least at first). It may be a couple of months before I get to it, but I plan to give away the software when I am finished. -- My real email is akamail.com@dclark (or something like that).Article: 26011
On Wed, 20 Sep 2000 09:32:29, eml@riverside-machines.com.NOSPAM wrote: > It occurs to me that it would be useful to pool the information that > we do have, and to find a structured way of getting the information > that we don't have, so that this information gets into the public > domain. This would involve, as a starting point, writing or collecting > various code templates, passing them around to anyone who has the > appropriate tools and is willing to help (possibly anonymously), and > collecting the results on a website. I'm certainly interested. I have Synplify (non-pro) for all vendors (just use Xilinx) and will likely get an Amplify license shortly. I don't think I could contribute designs, but maybe there is something to contribute. This certainly seems like a worthwile project. > There's a potential issue with vendors, who may believe that > publishing this information contravenes an individual licence > agreement. However, these tend to explicitly prohibit "benchmarking" > operations, rather than anything else. Benchmarking, as such, wouldn't > necessarily be covered. Most of the issues covered above are simply > functionality issues. Oh. I had better read the license again. I hadn't thought of that. That could get stickey indeed. ---- KeithArticle: 26012
Bill Lenihan wrote: > You should never have to instantiate Xilinx-specific I/O registers in the > code to make this happen. As long as there is no combinatorial logic between > pin & register and as long as the type (D-type w/ proper kind of > reset/preset) of register is do-able in the IOB. What you must do though is > push the registers into the IOB in the synthesis tool (see your synth tool > documentation for the switch to do this) AND set the appropriate constraints > and options in the Xilinx Alliance tool. Trying to do it with Alliance alone > won't work -- the IOB-type-registers have to be there in the EDIF netlist > first, and that's the job of your synthesis tool. > That works o.k. for single in's & out's. Where you run into trouble is on a bi-dir registered IO. To get both of them into the IOB for Virtex you have to observe 2 rules: (1) They must share the same clock. (2) They must share the same initialisation input. Each one can be configured separately as syn/async set/reset but the signal input has to be the same. Generally, unless you're not using the global clock, (1) is not a problem. Its (2) that causes hassle. Firstly it means that if one of the FF's has some sort of init or reset condition then the other one has to as well - even if you don't want it. Secondly my synth tool - Synplify - feels free to use the sync reset of a Xilinx FF as a free and gate so sometimes I end up violating (2) even though the source code says I'm not. Another circumstance where (2) can be broken goes like this [recent example]. A 72 bit bi-dir data bus had all the FFs with a sync set coming from a single register. Synplify did its usual register replication and then allocated them randomly to the data bus FFs. Fortunately at least Virtex has independent clock enable inputs to the IOB FFs which the XC4K series didn't.Article: 26013
The Achilles heel of the Atmel architecture, IMHO is that it does not have a fast carry chain. As a result, Altera and Xilinx implementations will run circles around anything done in Atmel for arithmetically heavy applications (that includes binary counters, folks!). If you can manage without carry chains, the parts are closer to equal, although Atmel does have the best partial reconfiguration out there right now. Ulf Samuelsson wrote: > > <graham_moss@my-deja.com> wrote in message > news:8qub1g$3me$1@nnrp1.deja.com... > > Hello, > > My current project requires the use of a fpga to achieve all the > > associated logic functionality. Simply put the peripherals will > > communicate via a bus internal to the fpga, therefore the fpga will > > contains busses and muxes, registers (may use fpga ram), and contain > > some complex random logic and sequencers. > > > > I have investigated both the Atmel AT40 and the Altera Flex 10K family. > > > > This has left me confused as their architectures seem quite different, > > yet both could ultimately do the job. > > > > Have I missed the point? My question is how to determine which family > > will be better suited to my particular application. > > You need to specify your needs. > Key to efficient use of the AT40K is to use the SRAM. > SRAM can be used to implement logic in many different ways. > > If you have a design, which has some volume, Atmel can certainly > Place and Route it for you. Send a mail to fpga@atmel.com and ask the > question. > > Otherwise you can get the toolset for free at the Atmel website, do a P&R. > The toolset supports timing analysis so you can find out if you > will meet timing spec. > > If you need a controller in the design, then the new FPSLIC may > be of interest to you. AVR RISC+ memory + 40K gates FPGA. > > -- > Best regards, > ulf at atmel dot com > The contents of this message is intended to be my private opinion and > may or may not be shared by my employer Atmel Sweden -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26014
best I could tell, synplify pro just has a bunch of bells and whistles I wasn't going to use anyway. I'm sticking to 6.0 plus the RTL analyst. It looked like pro gives you the analyst as part of the package, plus a different GUI, the ability to sprinkle pipeline registers inside multipliers (Big Fat Hairy Deal if you construct the logic you need anyway), ability to have two designs open at once and a few other little things. Nothin I could see there justified the big price difference. Andy Peters wrote: > > "S. Ramirez" wrote: > > > > Andy, > > Great and candid response! I just wish you had talked to me about FPGA > > Express a couple of years ago!! > > I wish I'd known the bugs a couple of years ago. As for being candid, > telling the vendors the truth, even if they can't handle it, is the > thing to do. > > > To make Synplicity less expensive, order the Xilinx-only license. > > What's sorta funny is that the Synplicity rep just called to follow up > on a request I'd made awhile ago. So I downloaded the newest version, > and my demo license JUST arrived via e-mail. > > Now, to figure out the diff betwixt Synplify and Synplify Pro... any > takers? > > -- a > ---------------------------- > Andy Peters > Sr. Electrical Engineer > National Optical Astronomy Observatory > 950 N Cherry Ave > Tucson, AZ 85719 > apeters (at) n o a o [dot] e d u -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26015
I was looking at an Atmel FPSLIC ad today and it made me think about how it might let me put one chip on my board instead of four. I use four FPGAs for two reasons. One is that I need a total of about 350 IOs for the whole board. But the real reason is that at least two sections of the FPGA design are used as interface to add on daughter cards (AIO modules). When the AIO module is detected at boot up, the appropriate FPGA design is loaded to drive the module. This saves hardware on the modules and (theoretically) saves me money. The problem is that I have to use two separate chips for the AIO interfaces in addition to the main FPGA for the central board control. I am expecting to split the main FPGA in two because there is also some other board IO that I would like to make reconfigurable. If I could get one large FPGA with in circuit, partial reconfigurability, I could replace four parts with one or two. But looking at web pricing for the Atmel parts, it seems that it would still cost me more for one or two AT40K parts than it does for four Lucent or Xilinx parts. That still leaves the issue of how well Atmel supports partial reconfiguration, both in the design stage and in the reconfiguration stage. Anyone using these parts in a partial reconfiguration application? Ray Andraka wrote: > > The Achilles heel of the Atmel architecture, IMHO is that it does not have a > fast carry chain. As a result, Altera and Xilinx implementations will run > circles around anything done in Atmel for arithmetically heavy applications > (that includes binary counters, folks!). If you can manage without carry > chains, the parts are closer to equal, although Atmel does have the best partial > reconfiguration out there right now. > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com or http://www.fpga-guru.com -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 26016
Are you looking for people to move to New Delhi?
I like your name -- Kash!
-Simon Ramirez, Consultant
Synchronous Design, Inc.
"kashjohal" <kash@ix.netcom.com> wrote in message
news:8r53np$k1v$1@slb6.atl.mindspring.net...
> We are setting up a design center in new delhi, india.
>
> Pre-IPO company.
>
> Stock options in US parent company.
>
> www.forasic.com
>
> regards,
>
>
> Kash
>
>
>
Article: 26017The only useful difference I can see is the portification option. You can set an attribute on any net at any point in hierarchy and the tools makes an output pin for it. This is really nice during debugging where you have to pull signals to the top level. It is done automagically. The problem is it doesn't work very nicely. First you can't control the name (you get a hierarchical name which you have to put into the ucf file) and if the signal is in a module which has multiple instantiations, you get one pin per instantiation. I'd rather they implemented support for hierachical references in Verilog. On Sat, 30 Sep 2000 20:55:39 GMT, Ray Andraka <ray@andraka.com> wrote: >best I could tell, synplify pro just has a bunch of bells and whistles I wasn't >going to use anyway. I'm sticking to 6.0 plus the RTL analyst. It looked like >pro gives you the analyst as part of the package, plus a different GUI, the >ability to sprinkle pipeline registers inside multipliers (Big Fat Hairy Deal if >you construct the logic you need anyway), ability to have two designs open at >once and a few other little things. Nothin I could see there justified the big >price difference. > >Andy Peters wrote: >> >> "S. Ramirez" wrote: >> > >> > Andy, >> > Great and candid response! I just wish you had talked to me about FPGA >> > Express a couple of years ago!! >> >> I wish I'd known the bugs a couple of years ago. As for being candid, >> telling the vendors the truth, even if they can't handle it, is the >> thing to do. >> >> > To make Synplicity less expensive, order the Xilinx-only license. >> >> What's sorta funny is that the Synplicity rep just called to follow up >> on a request I'd made awhile ago. So I downloaded the newest version, >> and my demo license JUST arrived via e-mail. >> >> Now, to figure out the diff betwixt Synplify and Synplify Pro... any >> takers? >> >> -- a >> ---------------------------- >> Andy Peters >> Sr. Electrical Engineer >> National Optical Astronomy Observatory >> 950 N Cherry Ave >> Tucson, AZ 85719 >> apeters (at) n o a o [dot] e d uArticle: 26018
hi everyone, what is the best way to implement multi-input adders in virtex ? I need to add around 20 18-bit numbers (which are outputs of multipliers) and I am wondering whether a wallace tree or 4-2 compressor tree makes sense. thanks for any suggestions, MuzafferArticle: 26019
Like I said, lots of bells and whistles, but nothing that I can see to justify the extra $$$. Muzaffer Kal wrote: > > The only useful difference I can see is the portification option. You > can set an attribute on any net at any point in hierarchy and the > tools makes an output pin for it. This is really nice during debugging > where you have to pull signals to the top level. It is done > automagically. The problem is it doesn't work very nicely. First you > can't control the name (you get a hierarchical name which you have to > put into the ucf file) and if the signal is in a module which has > multiple instantiations, you get one pin per instantiation. I'd rather > they implemented support for hierachical references in Verilog. > > -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26020
A wallace tree virtually never makes sense in an FPGA like Virtex that has a fast ripple carry chain, and for that matter, the 4-2 comprressor isn't much help either. In an ASIC, you can get adders that are considerably faster than a ripple carry adder by using any one of a number of fast carry/ carry-look-ahead schemes. All of these trade gates for speed. The Wallace Tree is attractive in an ASIC because it puts off the carry propagation to the last sum, thereby avoiding the use of expensive fast adders in the earlier sum stages. The ripple carry adder constructed in the FPGA using the fast carry chains is extremely hard to beat in terms of both performance and area because the dedicated logic is nearly an order of magnitude faster than the general routing, and (at least in xilinx) it uses dedicated logic so you don't have to use a second lut for the carry function at each bit. Now, the 'best' way to implement a multi-input adder depends on what metric you use to define 'best'. Are you looking for maximum pipelined speed or is it to be strictly combinatorial? Is latency an issue? how about routing congestion? The answer changes depending on these. Nevertheless, the use of the fast ripple carry is common among most of the best solutions, and they tend to be based on row ripple structures rather than column ripple structures such as the 3-2, 4-2 or wallace tree. THere is some discussion on my multiplier page on my website regarding this issue. Muzaffer Kal wrote: > > hi everyone, > what is the best way to implement multi-input adders in virtex ? I > need to add around 20 18-bit numbers (which are outputs of > multipliers) and I am wondering whether a wallace tree or 4-2 > compressor tree makes sense. > > thanks for any suggestions, > > Muzaffer -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26021
Atmel's device handles partial reconfig really nicely. A reconfiguration can be specified for any rectangular area down to a 1x1 cell area, which means you can reconfigure just what you want, not a whole column like virtex. Atmel has some tools for using reconfiguration for changing constants, and they may have added more since I last played with it. The toolset and silicon (as of over 2 years ago) is more friendly to partial configuration than any of the xilinx tools/silicon up to v3.1. That said, the device weaknesses in arithmetic applications may make it a non-contender for your application anyway. Nobody really has suitable tools yet for handling all the intricacies of partial reconfiguration correctly (especially if it is to be done while the application clock is running). rickman wrote: > > I was looking at an Atmel FPSLIC ad today and it made me think about how > it might let me put one chip on my board instead of four. I use four > FPGAs for two reasons. One is that I need a total of about 350 IOs for > the whole board. But the real reason is that at least two sections of > the FPGA design are used as interface to add on daughter cards (AIO > modules). When the AIO module is detected at boot up, the appropriate > FPGA design is loaded to drive the module. This saves hardware on the > modules and (theoretically) saves me money. > > The problem is that I have to use two separate chips for the AIO > interfaces in addition to the main FPGA for the central board control. I > am expecting to split the main FPGA in two because there is also some > other board IO that I would like to make reconfigurable. > > If I could get one large FPGA with in circuit, partial > reconfigurability, I could replace four parts with one or two. But > looking at web pricing for the Atmel parts, it seems that it would still > cost me more for one or two AT40K parts than it does for four Lucent or > Xilinx parts. > > That still leaves the issue of how well Atmel supports partial > reconfiguration, both in the design stage and in the reconfiguration > stage. Anyone using these parts in a partial reconfiguration > application? > > Ray Andraka wrote: > > > > The Achilles heel of the Atmel architecture, IMHO is that it does not have a > > fast carry chain. As a result, Altera and Xilinx implementations will run > > circles around anything done in Atmel for arithmetically heavy applications > > (that includes binary counters, folks!). If you can manage without carry > > chains, the parts are closer to equal, although Atmel does have the best partial > > reconfiguration out there right now. > > -- > > -Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email ray@andraka.com > > http://www.andraka.com or http://www.fpga-guru.com > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26022
I am implementing a programmable FIR and latency is a very big problem. So my definition of best is the fastest design with at most one pipeline in the adder tree. Size of no importance. On Sun, 01 Oct 2000 01:06:22 GMT, Ray Andraka <ray@andraka.com> wrote: >A wallace tree virtually never makes sense in an FPGA like Virtex that has a >fast ripple carry chain, and for that matter, the 4-2 comprressor isn't much >help either. In an ASIC, you can get adders that are considerably faster than >a ripple carry adder by using any one of a number of fast carry/ >carry-look-ahead schemes. All of these trade gates for speed. The Wallace Tree >is attractive in an ASIC because it puts off the carry propagation to the last >sum, thereby avoiding the use of expensive fast adders in the earlier sum >stages. > >The ripple carry adder constructed in the FPGA using the fast carry chains is >extremely hard to beat in terms of both performance and area because the >dedicated logic is nearly an order of magnitude faster than the general routing, >and (at least in xilinx) it uses dedicated logic so you don't have to use a >second lut for the carry function at each bit. > >Now, the 'best' way to implement a multi-input adder depends on what metric you >use to define 'best'. Are you looking for maximum pipelined speed or is it to >be strictly combinatorial? Is latency an issue? how about routing congestion? >The answer changes depending on these. Nevertheless, the use of the fast ripple >carry is common among most of the best solutions, and they tend to be based on >row ripple structures rather than column ripple structures such as the 3-2, 4-2 >or wallace tree. THere is some discussion on my multiplier page on my website >regarding this issue. > >Muzaffer Kal wrote: >> >> hi everyone, >> what is the best way to implement multi-input adders in virtex ? I >> need to add around 20 18-bit numbers (which are outputs of >> multipliers) and I am wondering whether a wallace tree or 4-2 >> compressor tree makes sense. >> >> thanks for any suggestions, >> >> MuzafferArticle: 26023
Actually, I guess I was wrong about needing to partial configure the part while running. With my current multichip design, I have to have the main FPGA running to talk to the rest of the board. But with an all in one chip approach, I can configure in sections in a complete reload of the FPGA. I do still need partial configuration so that I can separately develop and select the four sections of the chip. But I don't see where there is much support for the design side of things. But I have not looked at their tools. As you say, the chips are not the best architecture for many applications. And the cost is a significant issue as well. Do you have any idea how fast a 16 bit counter might run in a -1 part? I have not seen any info on this even in marketing material. In fact, the AT40K40AL does not even have a data sheet on the Atmel web site. But it is listed for sale at the Marshall web site. Ray Andraka wrote: > > Atmel's device handles partial reconfig really nicely. A reconfiguration can be > specified for any rectangular area down to a 1x1 cell area, which means you can > reconfigure just what you want, not a whole column like virtex. Atmel has some > tools for using reconfiguration for changing constants, and they may have added > more since I last played with it. The toolset and silicon (as of over 2 years > ago) is more friendly to partial configuration than any of the xilinx > tools/silicon up to v3.1. That said, the device weaknesses in arithmetic > applications may make it a non-contender for your application anyway. Nobody > really has suitable tools yet for handling all the intricacies of partial > reconfiguration correctly (especially if it is to be done while the application > clock is running). > > rickman wrote: > > > > I was looking at an Atmel FPSLIC ad today and it made me think about how > > it might let me put one chip on my board instead of four. I use four > > FPGAs for two reasons. One is that I need a total of about 350 IOs for > > the whole board. But the real reason is that at least two sections of > > the FPGA design are used as interface to add on daughter cards (AIO > > modules). When the AIO module is detected at boot up, the appropriate > > FPGA design is loaded to drive the module. This saves hardware on the > > modules and (theoretically) saves me money. > > > > The problem is that I have to use two separate chips for the AIO > > interfaces in addition to the main FPGA for the central board control. I > > am expecting to split the main FPGA in two because there is also some > > other board IO that I would like to make reconfigurable. > > > > If I could get one large FPGA with in circuit, partial > > reconfigurability, I could replace four parts with one or two. But > > looking at web pricing for the Atmel parts, it seems that it would still > > cost me more for one or two AT40K parts than it does for four Lucent or > > Xilinx parts. > > > > That still leaves the issue of how well Atmel supports partial > > reconfiguration, both in the design stage and in the reconfiguration > > stage. Anyone using these parts in a partial reconfiguration > > application? > > > > Ray Andraka wrote: > > > > > > The Achilles heel of the Atmel architecture, IMHO is that it does not have a > > > fast carry chain. As a result, Altera and Xilinx implementations will run > > > circles around anything done in Atmel for arithmetically heavy applications > > > (that includes binary counters, folks!). If you can manage without carry > > > chains, the parts are closer to equal, although Atmel does have the best partial > > > reconfiguration out there right now. > > > -- > > > -Ray Andraka, P.E. > > > President, the Andraka Consulting Group, Inc. > > > 401/884-7930 Fax 401/884-7950 > > > email ray@andraka.com > > > http://www.andraka.com or http://www.fpga-guru.com > > > > -- > > > > Rick "rickman" Collins > > > > rick.collins@XYarius.com > > > > Ignore the reply address. To email me use the above address with the XY > > removed. > > > > Arius - A Signal Processing Solutions Company > > Specializing in DSP and FPGA design > > > > Arius > > 4 King Ave > > Frederick, MD 21701-3110 > > 301-682-7772 Voice > > 301-682-7666 FAX > > > > Internet URL http://www.arius.com > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com or http://www.fpga-guru.com -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 26024
I'm a rather "advanced" hobbyist, looking to get into some FPGA design (for starters, as some glue logic for an ISA PC Card). I recently stripped an old videoconferencing system and it had about 50 XC2018-P84C chips on it (also some XC3042's and a pair of XC3090's). It also has a lot of GALs, 57C291's, 57C45's, and some various Altera stuff. In short, it is a reprogrammable logic goldmine. But, many of the parts are out of production and finding development support for them is difficult. I have Protel 99 SE and have a simple design input into it (schematic). But, when I compile it, I get a message about missing PLA2XNF.EXE. I'm assuming this is part of the Xilinx XACT tools? The problem I have is that nothing currently available from Xilinx seems to support my XC2018 chips. I prefer to use the Xilinx stuff at this point, because I can store the programming in an EPROM (I have a burner) rather than having to program the actual chip (I don't have a burner capable of doing any programmable logic burning). Does anyone have some pointers as to where I can find support for these devices? (It appears that the student [and even professional] editions of Xilinx' stuff are geared toward their newer parts). Thanx in advance! Robert Garito rgarito@gate.net
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