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Rick, Floored? To start up a chip with 210 million transistors? Spartan2 transistors are smaller than Virtex transistors, and there are fewer of them, and the engineers (just went a'visiting) improved the design. The increase in current at -40 C is gone in Spartan2 (different design). The characterization is proceeding as we speak, so I would need which parts you want to use (size, package) and I could get you this information ahead of the regular release. Please email me at austin@xilinx.com. For now, the commercial specification for the Virtex parts, would apply to Spartan2 (< 500 mA), even for Spartan2 I grade parts. As for rise time, you can't turn anything on any faster than about 1 ms (it would require many amps to charge the power supply capacitors that fast -- to charge 1000uF to 2.5 V in 1 ms takes 2.5 amps, or I=Cdv/dt), and Spartan2 has an objective of being perfectly OK with 100 ms ramp up time. Again, this is something we have to verify (at the same time as the current). Austin rickman wrote: > I must say that I am floored by this information. All the time I have > been using Xilinx parts, I have never been aware of the high current > required for startup. I guess I was lucky that the systems I worked on > had plenty of power for startup. > > But now I am designing boards that will have very little extra power > supply capacity since the low voltages for powering the FPGAs are > generated on board. I was planning on using 4 of the smaller Spartan II > FPGAs on my board with a 1 Amp 2.5 Volt power converter. Now I realize > that I may need as much as 8 Amps to bring these parts up if I can't > control the output rampup of the power converter. > > I am pretty sure that this will be impossible to acheive on the board I > am designing. If there is no better way to do this, I will be forced to > stick with the Lucent Orca parts I am currently using. > > Any idea of how the Spartan II parts will work? I am assuming that they > are the same as the current Virtex parts and that the industrial parts > will need 2 Amps each worse case. Is this correct? > > Is there any way to prevent this current surge to the part? Will holding > the PRGM- pin low prevent this high power draw? Can the parts be > sequenced to limit the total power draw? Or will I have to add switches > to the Vdd feeds to turn them on one at a time? > > Austin Lesea wrote: > > > > Alain, > > > > We recently (> 1 year ago) implemented a Power On Ramp Up current > > specification for all parts. We have not gone all the way back to the > > original 4K family, but the data sheet now specifies the current > > capacity of the power supply required for clean out and startup prior > > to configuration. > > > > I would recommend that 1 amp be allowed for each older part (4K, 4KE). > > > > I know the 4KXL, and all subsequent parts are characterized AND > > TESTED. > > > > There are also things you can do which make this start up current > > worse. A generally rising voltage, that rises no faster than 2 > > milliseconds, and no slower than 50 milliseconds, and starts from near > > 0 Vdc (< 300 mV) is always the best way to go. Starting from a > > voltage around 450 mV to 700 mV from a previously configured part, or > > holding INIT to prevent configuration, or passing through the POR trip > > point and then going below the POR trip point, are common causes of > > higher currents. > > > > In all cases, check the latest website data sheet. An example is > > here: > > > > http://www.support.xilinx.com/partinfo/ds005.pdf > > > > page 2 of 16 > > > > For parts that have virtually no current requirement at starup, use > > the 4KXLA, 4KXV, SpartanXL, or contact your sales office and FAE for > > assitance in selection. > > > > Austin Lesea > > IC Design, Xilinx > > > > Alain Cloet wrote: > > > > > "Andy Peters n o a o [.] e d u>" <"apeters <"@> wrote in message > > > news:8p6288$5k7$2@noao.edu... > > > > Alexandr V Shuvalov wrote: > > > > > > > > > Which voltage regulators ICs are commonly used to power supply > > > Xilinx XL > > > > > and other low voltage (3.3-2.5v) devices? > > > > > > > > I used a National LM3940IS-3.3 to drop a VME 5V supply down to > > > 3.3V @ 1 > > > > A. > > > > > > > Can you power-up several Xilinx-FPGA's with this element ; or is > > > there a > > > work-around ? > > > > > > We had this problem recently (not completelly solved), and the most > > > recent > > > idea is to supply 3 Xilinx FPGA's with one National LM3940 (other > > > version : > > > WG ?). > > > > > > The element we used before had a fast power-up time which caused the > > > FPGA > > > (4013) to take up to 1 A, and the regulator couldn't give 3A (it > > > went ok a > > > normal temperature, but in a cold phase at -40C it didn't go). > > > > > > Can the LM3940 do the job ? > > > > > > TIA, > > > Alain > > -- > > Rick Collins > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.comArticle: 25376
Look at http://www.micronetworks.com/ for programmable master clocks (M115 series). I heard that that part was being dropped so it may not be available but it sounds like just what you wanted. Note that the output levels were PECLl (Positive ECL) but there are level translators available quite cheaply. The M115 was a full blown oscillator and the last time I used one it went for about $175. Frequency range was 100MHz to 1000MHz depending on model number. Nestor wrote: > Hi. > > Does anyone know any manufacturer who fabricates > numerically-controlled crystal oscillators (NCXO), also known as > digitally-controlled crystal oscillators (DCXO) which are suitable for > digital phase-locked loop designs in VHDL and FPGAs? > > Although these blocks resemble a numerically-controlled oscillator > (NCO), they differ in that the NCXO is not oversampled to generate the > required output signal (an NCO needs to be oversampled by at least > 8-times in order to have an acceptable low jitter output). Rather, a > digital input word is fed to the NCXO and it synthesizes the required > output frequency using a standard, low-cost crystal oscillator. The > output is also a square wave, just like the standard crystal. In > general, the NCXO has a narrow tuning range similar to a > voltage-controlled crystal oscillator (VCXO), e.g. +/-150ppm relative > to a frequency in the MHz range. > > The NCXO technology is fairly recent from what I understand, but > allows one to replace a circuit composed of a digital-to-analog > converter (DAC) and a VCXO by one chip that performs the exact same > task will less design hassles. The DCXO is ideal for custom-made > phase-locked loop (PLL) circuits using digital sections that can be > implemented in VHDL and FPGAs. > > Since I haven't been able to find any NCXO manufacturers over the web, > I am now looking to the knowledgeable engineers, designers and friends > that frequent these newsgroups for some potential referrals and/or > links. > > Thanks in advance for your help. > > NestorArticle: 25377
Andy,
Earlier, I posted a message to the newsgroup that explained how the
disties work and what their motivations are. A large amount of their time
is spent "registering" parts.
You are correct in saying that they will jump all over you asking those
silly questions, because they are trying to build a case for registering the
design socket with, of all people, the Xilinx manufacturer's rep (Xilinx
rep)!
What you should do is get in touch with the Xilinx rep yourself. This
is the person that the disty will go to to get availability and price
information, so why not go there yourself? With Virtex-E parts,
availability and other information are scarce, and the disties are forced to
go to the Xilinx rep for the answers. Tell the rep that you do not want any
disties in on your design. Explain to him/her that you are not interested
in a bunch of people bothering you "on this one." They will keep the
information to themselves and not involve the disties.
The exception to the above is if you need parts that are well
established. In this case, the disties may have parts on their shelves. If
they do, great, but if they don't, they will have to go to the rep again.
In either case, you will have the salesperson or the FAE knocking on your
door or calling you up for the same reason -- to gather information in order
to register the part.
So my advice is, if you don't want the disties to come give you a 2 hour
PowerPoint presentation on why they are the chosen ones, to call the Xilinx
rep yourself regardless of the part. Let the rep find the parts for you at
the disty warehouse or factory. That way you will minimize disty PowerPoint
presentations and obnoxious questions.
By the way, this is true of most semiconductor companies, not just
Xilinx.
-Simon Ramirez, Consultant
Synchronous Design, Inc.
"Andy Peters n o a o [.] e d u>" <"apeters <"@> wrote in message
news:8pbfj5$16qm$1@noao.edu...
> I really hate to ask silly questions like this, but I hate calling the
> distros because once you tell them you're thinking about considering
> thinking about using a part in a design, they jump all over you because
> they think you're gonna be writing a req for 10,000 parts tomorrow ...
>
> I'm looking at doing a VirtexE design. XCV50E should be big enough.
> Mainly, I want the LVDS I/O. Are they available now, or will they be
> available in the next couple of months?
>
> Of course, I could probably do the design with external LVDS parts, but
> this seems like a "neat" solution.
>
> -- andy
> ----------------------------
> Andy Peters
> Sr. Electrical Engineer
> National Optical Astronomy Observatory
> 950 N Cherry Ave
> Tucson, AZ 85719
> apeters (at) n o a o [dot] e d u
>
Article: 25378What frequency range are you interested in and what resolution do you require? On Fri, 08 Sep 2000 20:27:24 GMT, nestor@stansync.com (Nestor) wrote: >Hi. > >Does anyone know any manufacturer who fabricates >numerically-controlled crystal oscillators (NCXO), also known as >digitally-controlled crystal oscillators (DCXO) which are suitable for >digital phase-locked loop designs in VHDL and FPGAs? > >Although these blocks resemble a numerically-controlled oscillator >(NCO), they differ in that the NCXO is not oversampled to generate the >required output signal (an NCO needs to be oversampled by at least >8-times in order to have an acceptable low jitter output). Rather, a >digital input word is fed to the NCXO and it synthesizes the required >output frequency using a standard, low-cost crystal oscillator. The >output is also a square wave, just like the standard crystal. In >general, the NCXO has a narrow tuning range similar to a >voltage-controlled crystal oscillator (VCXO), e.g. +/-150ppm relative >to a frequency in the MHz range. > >The NCXO technology is fairly recent from what I understand, but >allows one to replace a circuit composed of a digital-to-analog >converter (DAC) and a VCXO by one chip that performs the exact same >task will less design hassles. The DCXO is ideal for custom-made >phase-locked loop (PLL) circuits using digital sections that can be >implemented in VHDL and FPGAs. > >Since I haven't been able to find any NCXO manufacturers over the web, >I am now looking to the knowledgeable engineers, designers and friends >that frequent these newsgroups for some potential referrals and/or >links. > >Thanks in advance for your help. > >Nestor > > > --Rolie Baldock. email: <berd_kalamunda@'nospam'techemail.com>Article: 25379
I'm in a senior project class at the University of Colorado. My group has opted to design a general purpose CPU, and we have easy access to 4005s (and some 4010s) and the associated Xilinx tools. My professor told us that our CPU should be 8-bit, with ~20 instructions, and that such a design would take 3 or 4 FPGAs. With that in mind, I just visited this web page, and was shocked: http://www.io.com/~guccione/HW_list.html One guy says he fit a 32-bit RISC design (among other things) on a single 4010. Another guy says he made a 16-bit RISC design that only takes up 75% of a 4005. I'm worried about doing a 16-bit design because my professor thinks the project would be doomed to fail. But now I'm not so sure anymore. Does anyone have any comments or suggestions about this stuff? Please let me know (via e-mail) if you post a reply. Sometimes my news server is flakey. Thanks, Tom KerriganArticle: 25380
Now I am really floored to think that it takes 210 million transistors to make a chip with only 57,906 system gates! The startup current of the XCV50 industrial grade is rated at 2 Amps just like the XCV1000. And yes, I am amazed that the startup current of any of these devices is so large. When the quiesent current is between 50 and 100 mA, I find it amazing that the device is not designed to come up in a well defined state that is not creating a near short between power and ground. I have never seen this type of warning on any of the other dozens and hundreds of other chips I have designed with, so I can only assume that this is unique to the Xilinx configuration process. Austin Lesea wrote: > > Rick, > > Floored? To start up a chip with 210 million transistors? > > Spartan2 transistors are smaller than Virtex transistors, and there are > fewer of them, and the engineers (just went a'visiting) improved the design. > > The increase in current at -40 C is gone in Spartan2 (different design). > > The characterization is proceeding as we speak, so I would need which parts > you want to use (size, package) and I could get you this information ahead > of the regular release. Please email me at austin@xilinx.com. > > For now, the commercial specification for the Virtex parts, would apply to > Spartan2 (< 500 mA), even for Spartan2 I grade parts. > > As for rise time, you can't turn anything on any faster than about 1 ms (it > would require many amps to charge the power supply capacitors that fast -- > to charge 1000uF to 2.5 V in 1 ms takes 2.5 amps, or I=Cdv/dt), and Spartan2 > has an objective of being perfectly OK with 100 ms ramp up time. Again, > this is something we have to verify (at the same time as the current). I don't know where you got your information on my power supply, I don't think I gave any details. We have a 100 uF capacitor (low ESR) on the output of the 1 Amp switcher we are using in our current design. But even so, I don't think it ramps up in 1 mS. I will check my notes on it when I have a chance. Since I am now aware that this is a critical spec for our boards, I will pay more attention to it. The FPGAs we are currently using do require a stated amount of current on powerup (10 mA), but this is only during the time the voltage is crossing the 1 to 1.5 volt region. I assume that this is the time during which the circuitry is first coming alive as the Vdd exceeds the gate thresholds. Otherwise I have seen no spec on high startup currents on these chips, all four of them. I am looking at using the XC2S15, 30 in the TQ100 package and the 50 and 100 in the 256 or 456 pin FPBGA. If this information is still preliminary, can you tell me when it is expected to be released as standard data? I am not looking to rush into production with these parts. I will be waiting for them to be fully characterized. BTW, you have mentioned the term "clean out" several times in this thread. Is this the same as clearing the configuration memory? Is this a reset that is done all at once or are the configuration bits cleared sequentially? > rickman wrote: > > > I must say that I am floored by this information. All the time I have > > been using Xilinx parts, I have never been aware of the high current > > required for startup. I guess I was lucky that the systems I worked on > > had plenty of power for startup. > > > > But now I am designing boards that will have very little extra power > > supply capacity since the low voltages for powering the FPGAs are > > generated on board. I was planning on using 4 of the smaller Spartan II > > FPGAs on my board with a 1 Amp 2.5 Volt power converter. Now I realize > > that I may need as much as 8 Amps to bring these parts up if I can't > > control the output rampup of the power converter. > > > > I am pretty sure that this will be impossible to acheive on the board I > > am designing. If there is no better way to do this, I will be forced to > > stick with the Lucent Orca parts I am currently using. > > > > Any idea of how the Spartan II parts will work? I am assuming that they > > are the same as the current Virtex parts and that the industrial parts > > will need 2 Amps each worse case. Is this correct? > > > > Is there any way to prevent this current surge to the part? Will holding > > the PRGM- pin low prevent this high power draw? Can the parts be > > sequenced to limit the total power draw? Or will I have to add switches > > to the Vdd feeds to turn them on one at a time? > > > > Austin Lesea wrote: > > > > > > Alain, > > > > > > We recently (> 1 year ago) implemented a Power On Ramp Up current > > > specification for all parts. We have not gone all the way back to the > > > original 4K family, but the data sheet now specifies the current > > > capacity of the power supply required for clean out and startup prior > > > to configuration. > > > > > > I would recommend that 1 amp be allowed for each older part (4K, 4KE). > > > > > > I know the 4KXL, and all subsequent parts are characterized AND > > > TESTED. > > > > > > There are also things you can do which make this start up current > > > worse. A generally rising voltage, that rises no faster than 2 > > > milliseconds, and no slower than 50 milliseconds, and starts from near > > > 0 Vdc (< 300 mV) is always the best way to go. Starting from a > > > voltage around 450 mV to 700 mV from a previously configured part, or > > > holding INIT to prevent configuration, or passing through the POR trip > > > point and then going below the POR trip point, are common causes of > > > higher currents. > > > > > > In all cases, check the latest website data sheet. An example is > > > here: > > > > > > http://www.support.xilinx.com/partinfo/ds005.pdf > > > > > > page 2 of 16 > > > > > > For parts that have virtually no current requirement at starup, use > > > the 4KXLA, 4KXV, SpartanXL, or contact your sales office and FAE for > > > assitance in selection. > > > > > > Austin Lesea > > > IC Design, Xilinx > > > > > > Alain Cloet wrote: > > > > > > > "Andy Peters n o a o [.] e d u>" <"apeters <"@> wrote in message > > > > news:8p6288$5k7$2@noao.edu... > > > > > Alexandr V Shuvalov wrote: > > > > > > > > > > > Which voltage regulators ICs are commonly used to power supply > > > > Xilinx XL > > > > > > and other low voltage (3.3-2.5v) devices? > > > > > > > > > > I used a National LM3940IS-3.3 to drop a VME 5V supply down to > > > > 3.3V @ 1 > > > > > A. > > > > > > > > > Can you power-up several Xilinx-FPGA's with this element ; or is > > > > there a > > > > work-around ? > > > > > > > > We had this problem recently (not completelly solved), and the most > > > > recent > > > > idea is to supply 3 Xilinx FPGA's with one National LM3940 (other > > > > version : > > > > WG ?). > > > > > > > > The element we used before had a fast power-up time which caused the > > > > FPGA > > > > (4013) to take up to 1 A, and the regulator couldn't give 3A (it > > > > went ok a > > > > normal temperature, but in a cold phase at -40C it didn't go). > > > > > > > > Can the LM3940 do the job ? > > > > > > > > TIA, > > > > Alain > > > > -- > > > > Rick Collins > > > > rick.collins@XYarius.com > > > > Ignore the reply address. To email me use the above address with the XY > > removed. > > > > Arius - A Signal Processing Solutions Company > > Specializing in DSP and FPGA design > > > > Arius > > 4 King Ave > > Frederick, MD 21701-3110 > > 301-682-7772 Voice > > 301-682-7666 FAX > > > > Internet URL http://www.arius.com -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 25381
Austin Lesea wrote: > > Henryk, > > The INIT holdoff warning applies to 4K only. It does not apply to > Virtex, and Virtex architecture derivatives. > > I am sorry for the confusion. > > In 4K, holding INIT and preventing clean out does not make the device > HOT -- it may be that the 4K device is in contention from the Vcc not > going down below a few hundred millivolts, and then the Vcc returns, > and the 4K device is in a partially configured state, and drawing > current. So the device is already HOT and getting hotter, and INIT > prevents the clean out. > > Again, Virtex, Virtex E, Spartan2 do not have this behavior. The > design is such that the means of contention that were caused by memory > contents which occurred in 4K do not exist in Virtex. Can you be a little more specific as to what behaviour you are talking about? The Virtex data sheet claims it needs up to 2 Amps of current for startup. So I assume that you are saying that the Virtex does not continue to draw heavy current when INIT is held low? Is that right? > Henryk Cieslak wrote: > > > So, what is the smart method of delaying Virtex configuration? I > > need to > > keep Virtex non-configured for an arbitrary time. The config mode > > can vary - > > master or slave. > > Previous data sheets have specified that PROGRAM can be held low to > > make a > > delay, but the latest data sheet (2.2) does not mention it - I think > > it > > means this method is not recommended. > > Now you say that keeping INIT low can make the chip consume plenty > > of > > current = make hot. > > What to do? Let it start configuration and wait infinitely for CCLK > > (slave) > > or configure with random data until it stops due to checksum error? > > > > Henryk Cieslak > > Becker Elektronic Polska > > > > Austin Lesea wrote in message <39B7BF1E.B24BE76F@xilinx.com>... > > >Alain, > > > > > >We recently (> 1 year ago) implemented a Power On Ramp Up current > > specification > > >for all parts. We have not gone all the way back to the original > > 4K > > family, but > > >the data sheet now specifies the current capacity of the power > > supply > > required > > >for clean out and startup prior to configuration. > > > > > >I would recommend that 1 amp be allowed for each older part (4K, > > 4KE). > > > > > >I know the 4KXL, and all subsequent parts are characterized AND > > TESTED. > > > > > >There are also things you can do which make this start up current > > worse. A > > >generally rising voltage, that rises no faster than 2 milliseconds, > > and no > > >slower than 50 milliseconds, and starts from near 0 Vdc (< 300 mV) > > is > > always the > > >best way to go. Starting from a voltage around 450 mV to 700 mV > > from a > > >previously configured part, or holding INIT to prevent > > configuration, or > > passing > > >through the POR trip point and then going below the POR trip point, > > are > > common > > >causes of higher currents. > > > > > >In all cases, check the latest website data sheet. An example is > > here: > > > > > >http://www.support.xilinx.com/partinfo/ds005.pdf > > > > > >page 2 of 16 > > > > > >For parts that have virtually no current requirement at starup, use > > the > > 4KXLA, > > >4KXV, SpartanXL, or contact your sales office and FAE for assitance > > in > > >selection. > > > > > >Austin Lesea > > >IC Design, Xilinx > > > > > >Alain Cloet wrote: > > > > > >> "Andy Peters n o a o [.] e d u>" <"apeters <"@> wrote in message > > >> news:8p6288$5k7$2@noao.edu... > > >> > Alexandr V Shuvalov wrote: > > >> > > > >> > > Which voltage regulators ICs are commonly used to power > > supply Xilinx > > XL > > >> > > and other low voltage (3.3-2.5v) devices? > > >> > > > >> > I used a National LM3940IS-3.3 to drop a VME 5V supply down to > > 3.3V @ 1 > > >> > A. > > >> > > > >> Can you power-up several Xilinx-FPGA's with this element ; or is > > there a > > >> work-around ? > > >> > > >> We had this problem recently (not completelly solved), and the > > most > > recent > > >> idea is to supply 3 Xilinx FPGA's with one National LM3940 (other > > version > > : > > >> WG ?). > > >> > > >> The element we used before had a fast power-up time which caused > > the FPGA > > >> (4013) to take up to 1 A, and the regulator couldn't give 3A (it > > went ok > > a > > >> normal temperature, but in a cold phase at -40C it didn't go). > > >> > > >> Can the LM3940 do the job ? > > >> > > >> TIA, > > >> Alain > > > -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 25382
Jan Gray did a series of articles in circuit cellar magazine this past spring on a risc machine in a small FPGA. He was specifically targeting the XESS board. ANyway I know it can be done. I did a machine a while back that was kind of a cross between a PIC and an RCA1802 that occupied 8x10 XC4000 CLBs. Find Jan's article series, it'll give you a good head start. Tom Kerrigan wrote: > > I'm in a senior project class at the University of Colorado. My group has > opted to design a general purpose CPU, and we have easy access to 4005s (and > some 4010s) and the associated Xilinx tools. > > My professor told us that our CPU should be 8-bit, with ~20 instructions, > and that such a design would take 3 or 4 FPGAs. > > With that in mind, I just visited this web page, and was shocked: > http://www.io.com/~guccione/HW_list.html > > One guy says he fit a 32-bit RISC design (among other things) on a single > 4010. Another guy says he made a 16-bit RISC design that only takes up 75% > of a 4005. > > I'm worried about doing a 16-bit design because my professor thinks the > project would be doomed to fail. But now I'm not so sure anymore. Does > anyone have any comments or suggestions about this stuff? > > Please let me know (via e-mail) if you post a reply. Sometimes my news > server is flakey. > > Thanks, > Tom Kerrigan -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 25383
I believe the VCXO circuit you are describing is a standard crystal oscillator with a variactor diode to control the frequency. All crystal circuits can be tuned slightly by varying the capacitance in the circuit. The variactor diode allows you to use a DC voltage to adjust this capacitance. I am not familiar with the NCXO or DCXO, but I would be willing to bet that this is just a DAC combined with a VCXO. No magic here, just a matter of combining mulitple devices in one package. Nestor wrote: > > Hi. > > Does anyone know any manufacturer who fabricates > numerically-controlled crystal oscillators (NCXO), also known as > digitally-controlled crystal oscillators (DCXO) which are suitable for > digital phase-locked loop designs in VHDL and FPGAs? > > Although these blocks resemble a numerically-controlled oscillator > (NCO), they differ in that the NCXO is not oversampled to generate the > required output signal (an NCO needs to be oversampled by at least > 8-times in order to have an acceptable low jitter output). Rather, a > digital input word is fed to the NCXO and it synthesizes the required > output frequency using a standard, low-cost crystal oscillator. The > output is also a square wave, just like the standard crystal. In > general, the NCXO has a narrow tuning range similar to a > voltage-controlled crystal oscillator (VCXO), e.g. +/-150ppm relative > to a frequency in the MHz range. > > The NCXO technology is fairly recent from what I understand, but > allows one to replace a circuit composed of a digital-to-analog > converter (DAC) and a VCXO by one chip that performs the exact same > task will less design hassles. The DCXO is ideal for custom-made > phase-locked loop (PLL) circuits using digital sections that can be > implemented in VHDL and FPGAs. > > Since I haven't been able to find any NCXO manufacturers over the web, > I am now looking to the knowledgeable engineers, designers and friends > that frequent these newsgroups for some potential referrals and/or > links. > > Thanks in advance for your help. > > Nestor -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 25384
Aside from the larger number of gates required and the slower paths for carry propagation, and signal routing, you should not have any more difficulty in designing a 16 bit CPU compared to an 8 bit one. The logic is identical and the circuitry is the same except that the paths have to be 16 bits wide. In what ways do you expect a 16 bit CPU to be harder to build than an 8 bit one? Of course if you make your instructions 16 bits wide and make them more complex, the 16 bit machine will be more difficult to design. But if you still use 8 bit instructions and the same level of complexity in the instruction encoding you will see little difference. Tom Kerrigan wrote: > > I'm in a senior project class at the University of Colorado. My group has > opted to design a general purpose CPU, and we have easy access to 4005s (and > some 4010s) and the associated Xilinx tools. > > My professor told us that our CPU should be 8-bit, with ~20 instructions, > and that such a design would take 3 or 4 FPGAs. > > With that in mind, I just visited this web page, and was shocked: > http://www.io.com/~guccione/HW_list.html > > One guy says he fit a 32-bit RISC design (among other things) on a single > 4010. Another guy says he made a 16-bit RISC design that only takes up 75% > of a 4005. > > I'm worried about doing a 16-bit design because my professor thinks the > project would be doomed to fail. But now I'm not so sure anymore. Does > anyone have any comments or suggestions about this stuff? > > Please let me know (via e-mail) if you post a reply. Sometimes my news > server is flakey. > > Thanks, > Tom Kerrigan -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 25385
I realize that it's not much harder to design a 16-bit CPU than an 8-bit one. The question is whether or not it will still fit on one FPGA, or how many more FPGAs it requires. If the 8-bit CPU fits on a single FPGA and the 16-bit one doesn't, then that's a serious problem, because we will have to wire wrap the FPGAs together, and wire wrapping a 16-bit bus sounds like more work than it needs to be. -Tom rickman <spamgoeshere4@yahoo.com> wrote in message news:39B9CB69.47BD79C2@yahoo.com... > Aside from the larger number of gates required and the slower paths for > carry propagation, and signal routing, you should not have any more > difficulty in designing a 16 bit CPU compared to an 8 bit one. The logic > is identical and the circuitry is the same except that the paths have to > be 16 bits wide. > > In what ways do you expect a 16 bit CPU to be harder to build than an 8 > bit one? Of course if you make your instructions 16 bits wide and make > them more complex, the 16 bit machine will be more difficult to design. > But if you still use 8 bit instructions and the same level of complexity > in the instruction encoding you will see little difference. > > > Tom Kerrigan wrote: > > > > I'm in a senior project class at the University of Colorado. My group has > > opted to design a general purpose CPU, and we have easy access to 4005s (and > > some 4010s) and the associated Xilinx tools. > > > > My professor told us that our CPU should be 8-bit, with ~20 instructions, > > and that such a design would take 3 or 4 FPGAs. > > > > With that in mind, I just visited this web page, and was shocked: > > http://www.io.com/~guccione/HW_list.html > > > > One guy says he fit a 32-bit RISC design (among other things) on a single > > 4010. Another guy says he made a 16-bit RISC design that only takes up 75% > > of a 4005. > > > > I'm worried about doing a 16-bit design because my professor thinks the > > project would be doomed to fail. But now I'm not so sure anymore. Does > > anyone have any comments or suggestions about this stuff? > > > > Please let me know (via e-mail) if you post a reply. Sometimes my news > > server is flakey. > > > > Thanks, > > Tom Kerrigan > > -- > > Rick Collins > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > removed. > > > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.comArticle: 25386
"Tom Kerrigan" <Thomas.Kerrigan@Colorado.EDU> wrote in message news:8pcads$ime$1@peabody.colorado.edu... > I'm in a senior project class at the University of Colorado. My group has > opted to design a general purpose CPU, and we have easy access to 4005s (and > some 4010s) and the associated Xilinx tools. > > My professor told us that our CPU should be 8-bit, with ~20 instructions, > and that such a design would take 3 or 4 FPGAs. > > With that in mind, I just visited this web page, and was shocked: > http://www.io.com/~guccione/HW_list.html > > One guy says he fit a 32-bit RISC design (among other things) on a single > 4010. Another guy says he made a 16-bit RISC design that only takes up 75% > of a 4005. Hi. I'm that guy with the 32-bit RISC -- in a little more than half of an XC4010 (see www3.sympatico.ca/jsgray/homebrew.htm). The 16-bit R16/RISC4005 was the trailblazing work of Philip Freidin. This spring Circuit Cellar magazine ran my three article series demonstrating how to implement a 16-bit pipelined RISC and system-on-a-chip (video) in an XC4005XL. The sources are available, in Foundation schematics and synthesizable Verilog, C compiler too, see www.fpgacpu.org/xsoc/cc.html and www.fpgacpu.org/xsoc/index.html. There's also a mailing list, www.egroups.com/group/fpga-cpu/info.html, where we supposedly discuss FPGA CPU and SoC design, and also links to other FPGA CPUs at www.fpgacpu.org/links.html. A simple non-pipelined 8-bit processor will make a splendid senior project, and you shouldn't have too much trouble fitting one into an XC4005 or XC4010, if you apply Occam's Razor. See for example the 4- and 8-bit processor designs in the last chapter of Dave Vanden Bout's Practical Xilinx Designer Lab Book (part of the Xilinx Student Ed. product). Some thoughts on the application of FPGA CPUs to teaching are at www.fpgapcu.org/teaching.html. I'd love to hear feedback from educators. Jan Gray Gray Research LLCArticle: 25387
In article <8pcads$ime$1@peabody.colorado.edu>, Tom Kerrigan <Thomas.Kerrigan@Colorado.EDU> wrote: >I'm in a senior project class at the University of Colorado. My group has >opted to design a general purpose CPU, and we have easy access to 4005s (and >some 4010s) and the associated Xilinx tools. > >My professor told us that our CPU should be 8-bit, with ~20 instructions, >and that such a design would take 3 or 4 FPGAs. Nah, an 8 bit, 20 instruction CPU should easily fit in a 4005. There really isn't much there, if you are cleaver. Heck, designing a SIMPLE N-bit CPU is pretty trivial, it was the final exam question in our digital design class, and an easy final it was, too. But some hints: Make the design multicycle, don't bother with pipelining. Implement a single wide mux using the tristate lines, to basically handle routing all the data around. It's suprising how much of a CPU design, especially a simple CPU design, is muxes, muxes and more muxes. FPGAs are GOOD at muxes, if you read the data sheet to know which style to use when. A one-hot state machine for your control logic, makes it simple to design and debug, and pretty efficient on a Xilinx to boot, and there should be NO problem at all. However, it may be reasonable to do a 16 bit processor in that space, I'd advise against it. The key to making a class project work well is KISS: Keep it Simple and Stupid. Do the minimum spec required to get a good grade. Only AFTER it is done, should you try playing with the design to get more performance. I'd suggest pipelining, it's the easiest and can easily get you a 3-5x performance increase with only a minor area cost. Oh, just make sure, these are 4000Es right? It is easier with the Es to do the register file, because of the synchronous memories (knowing universitys, it could be very well classic 4000s instead of the Es). -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 25388
"Tom Kerrigan" <Thomas.Kerrigan@Colorado.EDU> wrote in message news:8pcigr$n7m$1@peabody.colorado.edu... > I realize that it's not much harder to design a 16-bit CPU than an 8-bit > one. > > The question is whether or not it will still fit on one FPGA, or how many > more FPGAs it requires. > > If the 8-bit CPU fits on a single FPGA and the 16-bit one doesn't, then > that's a serious problem, because we will have to wire wrap the FPGAs > together, and wire wrapping a 16-bit bus sounds like more work than it needs > to be. It is difficult to generalize. You haven't stated whether you are building a simple multi-cycle CPU, or a one-cycle CPU, or a pipelined CPU, etc. Assuming a simple design, you should not have too much trouble building a 16-bit CPU in a 4010. It may well fit in a 4005 but you may have to put more effort into designing the processor to take advantage of the available device features. For example, R16, j32, xr16, etc. all use TBUFs (on-chip 3-state buffers), instead of logic, to implement a wide, many-input result multiplexer, in order to conserve gates. How can you tell if a design is feasible before implementing it and discovering it doesn't fit? Part of the "art" of FPGA design is to prepare a sketch of a datapath and/or control logic, and then estimate approximately how many LUTs (or CLBs) the sketch will require. This estimate can be used to determine which size of part will be required and/or to determine that the current design won't fit in the specified part, indicating necessary rework of the implementation sketch or of the design requirements. So sketch your proposed 16-bit datapath on paper. Add up resources required: every bit of adder, or logic, or mux, or RAM, is a LUT (lookup table), and every bit of every register is a flip-flop. Now you can quickly derive an estimate of resources required and/or feasibility. In your case, probably-infeasible if max(#LUTs, #flops) > f*14*14*2 (device=XC4005) or > f*20*20*2 (XC4010). Here let f=0.75 or so (you don't want to fill the device past 75% if this is you first project, and leave yourself some margin of error). Jan Gray Gray Research LLCArticle: 25389
The problem may occur even if you don’t have those 0.01 ns delays. For flip-flops sharing the same clock domain the clock must come not only in the same time but also in the same delta tick. For example FFA uses 32MHz and its output drives FFB using 16MHz derived from the 32MHz. If 32MHz is delayed even by delta ticks, the circuit won’t work well on functional only simulation (it will however work in functional + timing). Here is a case where I needed to solve a problem. The designer used clock enable derived from a DLL. The clock enable was in the same delta tick as the clock and flip-flop did not see it on time. The fix was to add a buffer (delta delay in functional). The buffer was named carefully, because it was needed when the design was converted to ASIC (to fix hold problems for the same very reason). As for the UNSIM library. I think it is a little scary to touch the library. I would recommend to have a generic that bypasses all XILINX buffer on the clock during functional simulation.Article: 25390
S. Ramirez <sramirez@deleet.cfl.rr.com> wrote in message news:Judu5.13363$98.1346052@typhoon.tampabay.rr.com... > Andy, > Earlier, I posted a message to the newsgroup that explained how the > disties work and what their motivations are. A large amount of their time > is spent "registering" parts. Because that's the only way that they get lower pricing from Xilinx - it's what Xilinx want them to do. > You are correct in saying that they will jump all over you asking those > silly questions, because they are trying to build a case for registering the > design socket with, of all people, the Xilinx manufacturer's rep (Xilinx > rep)! > What you should do is get in touch with the Xilinx rep yourself. This > is the person that the disty will go to to get availability and price > information, so why not go there yourself? With Virtex-E parts, > availability and other information are scarce, and the disties are forced to > go to the Xilinx rep for the answers. >Tell the rep that you do not want any > disties in on your design. Explain to him/her that you are not interested > in a bunch of people bothering you "on this one." They will keep the > information to themselves and not involve the disties. If the rep in my area did this, the disties run would screaming to Xilinx, no rep should ever do this, after all the rep can't sell the parts, only the disties. > The exception to the above is if you need parts that are well > established. In this case, the disties may have parts on their shelves. If > they do, great, but if they don't, they will have to go to the rep again. Why, he certainly doesn't have any on HIS shelf! > In either case, you will have the salesperson or the FAE knocking on your > door or calling you up for the same reason -- to gather information in order > to register the part. > So my advice is, if you don't want the disties to come give you a 2 hour > PowerPoint presentation on why they are the chosen ones, to call the Xilinx > rep yourself regardless of the part. Let the rep find the parts for you at > the disty warehouse or factory. What's the point of asking the rep to ask the disty? ..and if the rep sells direct from factory, the disty should immediately complain to Xilinx. That way you will minimize disty PowerPoint > presentations and obnoxious questions. Better just to tell the disty to leave his powerpoint slides at home. At the end of the day, all Xilinx devices sold thru the disties must undergo the design registration process, it's better to build a relationship with a disty that you trust, who gives good tech support & service and let him/her register all your designs - that way he/she is guaranteed lower pricing from the rep & has further incentive to keep giving you support. Use the design registration as a carrot on a stick to wave in front of the disty.....no support, no registration. > By the way, this is true of most semiconductor companies, not just > Xilinx. > -Simon Ramirez, Consultant > Synchronous Design, Inc. > > > > "Andy Peters n o a o [.] e d u>" <"apeters <"@> wrote in message > news:8pbfj5$16qm$1@noao.edu... > > I really hate to ask silly questions like this, but I hate calling the > > distros because once you tell them you're thinking about considering > > thinking about using a part in a design, they jump all over you because > > they think you're gonna be writing a req for 10,000 parts tomorrow ... > > > > I'm looking at doing a VirtexE design. XCV50E should be big enough. > > Mainly, I want the LVDS I/O. Are they available now, or will they be > > available in the next couple of months? > > > > Of course, I could probably do the design with external LVDS parts, but > > this seems like a "neat" solution. > > > > -- andy > > ---------------------------- > > Andy Peters > > Sr. Electrical Engineer > > National Optical Astronomy Observatory > > 950 N Cherry Ave > > Tucson, AZ 85719 > > apeters (at) n o a o [dot] e d u > > > >Article: 25391
On Wed, 06 Sep 2000 21:17:25 GMT, uwuh@my-deja.com wrote: > Hi, > Is there such a thing as a BGA to DIP converter? > Thanks > > > Sent via Deja.com http://www.deja.com/ > Before you buy. I sincerely doubt it, but you may find something of use from Emulation Technology, inc. (http://www.emulation.com/) They make a LOT of adapters for almost every type of package to almost every type of package. They do make a BGA emulator adaptor that solders down in place of the BGA, then the BGA is soldered to the top. Out the sides come pins for logic analysis. Good luck! Michael Kohne mhkohne@discordia.orgArticle: 25392
Mark, The relationship between disti and manufacturer is not as well balanced and even handed as you might think. The manufacturer often takes accounts direct and cuts the disti out entirely. It is all based on volume and price pressure. If the volume is high enough and especially if the manufacture feels too much pressure to reduce prices, they will cut the disti out and pocket the difference themselves. It is seldom that the distis get an exclusive sales agreement with the large manufacturers. It is also often a *good* idea to speak directly to the manufacturers rep as they can give you breaks on pricing that the disti can't, even if you are ultimately buying through the disti. Of course this only works if you are buying thousands of units. But even at 1000 pieces I have gotten better pricing than what the disti would quote me. Mark Harvey wrote: > > S. Ramirez <sramirez@deleet.cfl.rr.com> wrote in message > news:Judu5.13363$98.1346052@typhoon.tampabay.rr.com... > > Andy, > > Earlier, I posted a message to the newsgroup that explained how the > > disties work and what their motivations are. A large amount of their time > > is spent "registering" parts. > > Because that's the only way that they get lower pricing from Xilinx - it's > what > Xilinx want them to do. > > > You are correct in saying that they will jump all over you asking > those > > silly questions, because they are trying to build a case for registering > the > > design socket with, of all people, the Xilinx manufacturer's rep (Xilinx > > rep)! > > What you should do is get in touch with the Xilinx rep yourself. > This > > is the person that the disty will go to to get availability and price > > information, so why not go there yourself? With Virtex-E parts, > > availability and other information are scarce, and the disties are forced > to > > go to the Xilinx rep for the answers. > >Tell the rep that you do not want any > > disties in on your design. Explain to him/her that you are not interested > > in a bunch of people bothering you "on this one." They will keep the > > information to themselves and not involve the disties. > > If the rep in my area did this, the disties run would screaming to Xilinx, > no rep should ever do this, after all the rep can't sell the parts, only the > disties. > > > The exception to the above is if you need parts that are well > > established. In this case, the disties may have parts on their shelves. > If > > they do, great, but if they don't, they will have to go to the rep again. > > Why, he certainly doesn't have any on HIS shelf! > > > In either case, you will have the salesperson or the FAE knocking on your > > door or calling you up for the same reason -- to gather information in > order > > to register the part. > > So my advice is, if you don't want the disties to come give you a 2 > hour > > PowerPoint presentation on why they are the chosen ones, to call the > Xilinx > > rep yourself regardless of the part. Let the rep find the parts for you > at > > the disty warehouse or factory. > > What's the point of asking the rep to ask the disty? ..and if the rep sells > direct from factory, the disty should immediately complain to Xilinx. > > That way you will minimize disty PowerPoint > > presentations and obnoxious questions. > > Better just to tell the disty to leave his powerpoint slides at home. > > At the end of the day, all Xilinx devices sold thru the disties must > undergo the design registration process, it's better to build a > relationship with a disty that you trust, who gives good tech support & > service and let > him/her register all your designs - that way he/she is guaranteed lower > pricing from the rep & has further incentive to keep giving you support. > > Use the design registration as a carrot on a stick to wave in front of the > disty.....no support, no registration. > > > By the way, this is true of most semiconductor companies, not just > > Xilinx. > > -Simon Ramirez, Consultant > > Synchronous Design, Inc. > > > > > > > > "Andy Peters n o a o [.] e d u>" <"apeters <"@> wrote in message > > news:8pbfj5$16qm$1@noao.edu... > > > I really hate to ask silly questions like this, but I hate calling the > > > distros because once you tell them you're thinking about considering > > > thinking about using a part in a design, they jump all over you because > > > they think you're gonna be writing a req for 10,000 parts tomorrow ... > > > > > > I'm looking at doing a VirtexE design. XCV50E should be big enough. > > > Mainly, I want the LVDS I/O. Are they available now, or will they be > > > available in the next couple of months? > > > > > > Of course, I could probably do the design with external LVDS parts, but > > > this seems like a "neat" solution. > > > > > > -- andy > > > ---------------------------- > > > Andy Peters > > > Sr. Electrical Engineer > > > National Optical Astronomy Observatory > > > 950 N Cherry Ave > > > Tucson, AZ 85719 > > > apeters (at) n o a o [dot] e d u > > > > > > > -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 25393
"B. Joshua Rosen" wrote: > > Do a DG Nova 16 bit CPU. The Nova was able to fit on a single board in > 1969, surely it can fit in a 4005. The Nova's instruction set requires > almost no decoding, it has a fixed width 16 bit instruction and a tiny > number of instructions. The instruction set is very simple, load, store, > jump, and a single type of execute instruction called and ALC which > combines a simple operation (add,sub, mov, neg, and, or, xor, com), with > a carry in select (0,1,Carry,!Carry), a shift (left 1, right 1, no shift > and byte swap), and a skip (noskip, always skip, skip on zero, skip on > not zero, skip on carry 1, skip on carry 0, skip on neg, skip on pos). > Here is some photos of the Nova Computers ,and more information on the instruction set. http://www.ultranet.com/~crfriend/museum/ Ben. PS.I wonder how many 8008's does it take to replace the 586? -- "We do not inherit our time on this planet from our parents... We borrow it from our children." "Luna family of Octal Computers" http://www.jetnet.ab.ca/users/bfranchukArticle: 25394
On Fri, 08 Sep 2000 13:52:00 -0700, Austin Lesea <austin.lesea@xilinx.com> wrote: >Spartan2 transistors are smaller than Virtex transistors, and there are >fewer of them, and the engineers (just went a'visiting) improved the design. Can you tell us why there are fewer transistors in Spartan2? Is this just a blockRAM size difference? I thought the only significant difference was the geometry. EvanArticle: 25395
On Fri, 08 Sep 2000 19:02:27 +0200, "Jaap H. Mol" <jh_mol@wxs.nl> wrote: > >Hi, > >I'm looking for VHDL (conversions) functions supporting the IEEE 754 >floating point standard. To be more specific, I want to convert >variables >of type "real" to the IEEE 754 floating point format (single precision, >32-bit), and vice versa. VHDL (in common with other languages) doesn't define the bit-representation of a float; all you know is that you have at least 6 decimal digits of precision, and the range is in the bounds -1.0E38 to +1.0E38. The actual representation will the same as the one used by the processor, so it's likely to be 754 anyway. Even if you knew what the representation was, you'd have a problem getting to the bits to do anything with them. >In addition, I would greatly appreciate anyone who could direct me to >the (lastest version of) the (proposed?) VHDL MATH package. The package has been around for a few years now - it's not free, and you have to get it from the IEEE. EvanArticle: 25396
Hi out there! Can anybody tell me where I can find a GOOD Abel-tutorial? Thanks MichaelArticle: 25397
ed.moore@snellwilcox.com wrote: > > Does anyone have any information on the PCILOGIC cells in Xilinx Virtex > devices ?. > > From viewing the layout in FPGA Viewer (I would call it FPGA Editor if > it didn't crash 90% of the time I try to edit anything) they seem to > take in IRDY and TRDY from dedicated PCIIOB cells, plus a couple of > other signals, and generate a clock enable signal for use by local IOBs. > > Anyone know anything more ? The easy way to find out more about the block is just instantiate it in a design. It is named "pcilogic" and has the inputs IRDY, TRDY, I1, I2, and I3, and the output PCI_CE, all of which can be determined from "FPGA Viewer". Run map and par, then ngdanno and ngd2vhdl. The result is a VHDL file that includes a VHDL model of that logic block. It is a very simple combinatorial logic block, where I1 is an enable for IRDY, I3 is an enable for TRDY, and I2 is a direct enable. -- My real email is akamail.com@dclark (or something like that).Article: 25398
HI! I never tried mixing verilog and vhdl modules in synplify. But i can tell you a workaround that will surely work. Synthesize your verilog module (assuming your VHDL module instanciates all the verilog modules) first, create a black box for all the verilog instances, compile the VHDL module and write out the EDIF file, So now you are left with two EDIF files, one generated from Verilog and other from VHDL synthesis. Your place and route tool will take care of the rest. Hope this helps. If you require any further help please mail me at rkadam@asic.qntm.com Rajkumar... In article <39B8F7FA.A8727396@emw.ericsson.se>, Thomas Karlsson <thomas.karlsson@emw.ericsson.se> wrote: > Hi all, > > I trying to synthesize an old design written in verilog (which is not my > cup of tea, I use VHDL). This design instantiate some module, but I want > to use a new version of this module, written in VHDL. How do I do this? > I am using Synplify 6.0, which should support mixed language source > files, but it complains that the referenced module can not be found. > I know that the module name is not declared in any verilog file anymore, > but when the vhdl file with the corresponding entity name is compiled > into the library work, I supposed that Synplify should be able to plug > that compiled entity name into the place where the module name is > referenced, but I can not figure out how to do it. Maybe I trying the > impossible here? > > Thanks for any help. > > Thomas > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 25399
Hi!
I would just like to add my personal comments which i
have gained through designing many state machines.
First of all when designing a real ASIC, mostly you
end up with a mixture of Moore and Mealy, I mean sometimes
your output depends on state only sometimes it depends on
State and the present input.
I have rarely found Pure ( Text book ) state machines
implemented in reality, except for small state machines.
Now whether you should implement the state machine using
one process or multiple processes, I think the best way
is to follow the Hardware description ( Diagram ) of the
State machine, in which we end up with three processes,
Ist process -> P.S <= NS;
IInd process -> Next State assignment
IIIrd process -> Output assignment.
You can actually end up with four processes if you want to
register the output, Other way of implementing is to have
a single process for output and next state assignment.
And use the third process for Registered outputs.
I follow this as it is close to the hardware definition of
the state machine and it is easier to understand.
Rajkumar...
In article <G0H2wq.6sB@world.std.com>,
jhallen@world.std.com (Joseph H Allen) wrote:
> In article <39b607f5.7405564@news.dial.pipex.com>,
> <eml@riverside-machines.com.NOSPAM> wrote:
>
> >Isn't this a classic Verilog race condition? What happens if the 2
> >always blocks are executed in a different order?
>
> Oops, you're right, it is. You can use = for temporary variables,
since
> execution within an always block is sequential, but you had better not
use
> it for generating Mealy state signals unless it's in a seperate
> combinatorial always block.
>
> Verilog just doesn't work the way I want it to :-)
>
> --
> /* jhallen@world.std.com (192.74.137.5) */ /* Joseph H.
Allen */
> int
a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time
(0)
>
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!
a[p+q*2
> ]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n","
#"[!a[q-1]]);}
>
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