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This is a multi-part message in MIME format. --------------2557D730B7296CBD06F29839 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit I wanted to also add that this is a very good thread, with many good points made about both soft and hard copies of data sheets. I think this will always be a matter of personal preference for people. There is another issue that I'm not sure if anyone has directly mentioned yet as to the benefit of the soft-version (though I think it was hinted at, but I wanted to really point it out): Revisions. The way I see it, there aren't just two versions of our data book (book and CD), but rather there are three (book, CD, and Web). Right now, anyone with internet access (and I know that's another can-of-worms...) can go to www.xilinx.com , click on "Products", click on the product family that they're interested in, and they can be sure to be accessing the latest rev. of the data sheet. If you're after timing numbers - and I know there are some of you out there that like to get the timing numbers out of the data sheet for preliminary planning purposes - you will be guaranteed the latest this way. Here's a food-for-thought question: how many times have you seen *any* IC vender get the data sheet perfect the first time for any product? For any given IC vender, that data book is great for marking up with personal notes, but chances are in a few months after release, there could already be some updated timing numbers (or whatever) for the family that you're interested in, and a new rev is out there. This is especially true for new products. Now, keep in mind that any vendor hates this as much as you, and are constantly striving to improve on this (some more than others....), but it is an unavoidable fact in our industry. Do you need to be sure that you're looking at the latest rev? It probably depends on what you're doing. But, for any IC vendor, a particular data sheet may get revised *several* times in between data book printings. Anyhow, it's just another thing to consider. Thanks for the good debate on this subject - lots of good points and great feedback for Xilinx. -Scott Schlachter Xilinx - Systems Engineer > --------------2557D730B7296CBD06F29839 Content-Type: text/x-vcard; charset=us-ascii; name="scott.schlachter.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Scott Schlachter Content-Disposition: attachment; filename="scott.schlachter.vcf" begin:vcard n:Schlachter;Scott tel;work:408-879-6876 x-mozilla-html:TRUE url:www.xilinx.com org:Xilinx;General Products Division adr:;;2100 Logic Drive;San Jose;CA;95124-3400;USA version:2.1 email;internet:scott.schlachter@xilinx.com title:Systems Engineer fn:Scott Schlachter end:vcard --------------2557D730B7296CBD06F29839--Article: 25251
The problem faced here, was that the non global clock net was being split into 4 groups. The synthesis tool must have done this and the resulting routing seemed to have skew between the 4 clock groups. The FAE said that there is a constraint that can be added in 3.1i to use low skewlines, I have to try that yet and prevent the synthesis tool from splitting the net. Thank you for your comments Jamie. HannahArticle: 25252
Hi all; My thanks in advance for reading this post. I'm looking to use the Virtex-E DLL's to double a clock. I'm not able to find a great deal of documentation, so I'm a little unsure of my planned configuration. Perhaps someone could comment. The Virtex-E device receives a 50 MHz clock, which is used to time an external SSRAM interface. My goal is to have the option of putting in a 100 MHz SSRAM in the future, without any other board changes. To accomplish this, I'd like to source the SSRAM clock from the FPGA. That way, if I want to source 100 MHz, instead of 50 MHz, it's only an FPGA change. The thing that's giving me problems are the limitations on how the DLL feedback can be connected. I want to do all of this in a single quadrant, meaning only one BUFG should be used. The other constraint is that I want to source the BUFG from the clock after it has left and re-entered the device. That's because I don't want the external SSRAM to be operating on a clock that's significantly delayed with respect to the FPGA's internal clock net. That means that just sending the 2x output to a pin is not an option. What I had in mind was bringing the 50 MHz clock in on both the IBUFG and its LVDS pair, both of which are comparable of driving DLL inputs. The secondary DLL would be fed by the LVDS input (not actually configured as LVDS), and its CLK0 or CLK2X output would go to a nearby pin. Externally, that signal would be routed to the IBUFG input and the SSRAM. The IBUFG would feed the primary DLL, and the internal logic would run off the BUFG fed by the DLL CLK0. The part I'm not sure about is how to connect the DLL feedback inputs. The primary DLL can obviously take the BUFG output as its feedback signal. However, can the secondary DLL use the same signal? If not, how else could I connect it? Would it be better to connect it to the IBUFG output instead? If someone wants to suggest an entirely different configuration, I'd like to hear that as well. Best regards, Jamie SandersonArticle: 25253
Hi all, I'm playing with Mentor FPGA Advantage and xapp175 (FIFO controller). I downloaded the sample verilog design from the Xilinx web page and read it with Renoir. Two instances are missing: RAMB4_S8_S8 and BUFGP. I believe one would normally generate these instances from the Xilinx CoreGenerator. I have Xilinx Alliance on order, but delivery isn't until late October. In the meantime, could some kind soul post or email verilog code for these two instances so I can play with the software I have on the FIFO reference design? Thanks!!! Paul SmithArticle: 25254
These are primitives in the unisim library, not generated cores. If you have tools at all, there's a good shot you already have this library on your system, but you will have to put the library and use statements in your code so they can be found. You might also neet to put synthesis translate off pragmas around the library declaration to keep the synthesizer form complaining. If you don't have them on your system, I believe the library is available for download on the xilinx website, at least it used to be. With all the password protecting etc they are doing now, it may no longer be acceesible without a valid maintenance account. Paul Smith wrote: > > Hi all, > > I'm playing with Mentor FPGA Advantage and xapp175 (FIFO controller). I > downloaded the sample verilog design from the Xilinx web page and read > it with Renoir. Two instances are missing: RAMB4_S8_S8 and BUFGP. > > I believe one would normally generate these instances from the Xilinx > CoreGenerator. I have Xilinx Alliance on order, but delivery isn't until > late October. In the meantime, could some kind soul post or email > verilog code for these two instances so I can play with the software I > have on the FIFO reference design? > > Thanks!!! > > Paul Smith -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 25255
Has anyone used the Spartan II power down mode ?? It does not seem that useful since all I/O cells are disabled including pullups, pulldowns, and weak keepers. Also, you have to watch the status pin to wait for it to wake up and its not clear how long that takes. (In my application I am connecting two busses so when the Spartan II goes to sleep it will wind-up floating both busses and hence they will be subject random current consumption as the bus voltages float around.) -- StuartArticle: 25256
In Synplicity, if you instantiate an array of the size of the block RAM, won't it use the block RAM? It does it this way for CLB RAM... I've never tried it, but I am curious... Ray Andraka <ray@andraka.com> wrote in article <39B02D42.4C45F75D@andraka.com>... > These are primitives in the unisim library, not generated cores. If you have > tools at all, there's a good shot you already have this library on your system, > but you will have to put the library and use statements in your code so they can > be found. You might also neet to put synthesis translate off pragmas around the > library declaration to keep the synthesizer form complaining. > > If you don't have them on your system, I believe the library is available for > download on the xilinx website, at least it used to be. With all the password > protecting etc they are doing now, it may no longer be acceesible without a > valid maintenance account. > > Paul Smith wrote: > > > > Hi all, > > > > I'm playing with Mentor FPGA Advantage and xapp175 (FIFO controller). I > > downloaded the sample verilog design from the Xilinx web page and read > > it with Renoir. Two instances are missing: RAMB4_S8_S8 and BUFGP. > > > > I believe one would normally generate these instances from the Xilinx > > CoreGenerator. I have Xilinx Alliance on order, but delivery isn't until > > late October. In the meantime, could some kind soul post or email > > verilog code for these two instances so I can play with the software I > > have on the FIFO reference design? > > > > Thanks!!! > > > > Paul Smith > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com or http://www.fpga-guru.com >Article: 25257
There is a synthesis directive to tell Synplify to use a block RAM, I wouldn't count on it figuring it out on it's own. Josh Austin Franklin wrote: > > In Synplicity, if you instantiate an array of the size of the block RAM, > won't it use the block RAM? It does it this way for CLB RAM... I've never > tried it, but I am curious... > > Ray Andraka <ray@andraka.com> wrote in article > <39B02D42.4C45F75D@andraka.com>... > > These are primitives in the unisim library, not generated cores. If you > have > > tools at all, there's a good shot you already have this library on your > system, > > but you will have to put the library and use statements in your code so > they can > > be found. You might also neet to put synthesis translate off pragmas > around the > > library declaration to keep the synthesizer form complaining. > > > > If you don't have them on your system, I believe the library is available > for > > download on the xilinx website, at least it used to be. With all the > password > > protecting etc they are doing now, it may no longer be acceesible without > a > > valid maintenance account. > > > > Paul Smith wrote: > > > > > > Hi all, > > > > > > I'm playing with Mentor FPGA Advantage and xapp175 (FIFO controller). > I > > > downloaded the sample verilog design from the Xilinx web page and read > > > it with Renoir. Two instances are missing: RAMB4_S8_S8 and BUFGP. > > > > > > I believe one would normally generate these instances from the Xilinx > > > CoreGenerator. I have Xilinx Alliance on order, but delivery isn't > until > > > late October. In the meantime, could some kind soul post or email > > > verilog code for these two instances so I can play with the software I > > > have on the FIFO reference design? > > > > > > Thanks!!! > > > > > > Paul Smith > > > > -- > > -Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email ray@andraka.com > > http://www.andraka.com or http://www.fpga-guru.com > >Article: 25258
Paul Smith <ptsmith@indiana.edu> wrote: >Hi all, > >I'm playing with Mentor FPGA Advantage and xapp175 (FIFO controller). I >downloaded the sample verilog design from the Xilinx web page and read >it with Renoir. Two instances are missing: RAMB4_S8_S8 and BUFGP. > >I believe one would normally generate these instances from the Xilinx >CoreGenerator. I have Xilinx Alliance on order, but delivery isn't until >late October. In the meantime, could some kind soul post or email >verilog code for these two instances so I can play with the software I >have on the FIFO reference design? > >Thanks!!! > >Paul Smith You are missing a library file which you need to include in your synthesis project list. You should be able to find this file in your synthesis tool tree. There should be a file for what ever fpga family you are using which defines all the primitives for that fpga. For synplicity it is called (surprise) virtex.v. Do a "grep RAMB4 *.v" hierarchically in fpga advantage tool tree. MuzafferArticle: 25259
"Austin Franklin" <austin@darkr98oom.com> wrote: >In Synplicity, if you instantiate an array of the size of the block RAM, >won't it use the block RAM? It does it this way for CLB RAM... I've never >tried it, but I am curious... No it won't. Synplicity 6.0 defaults to selectram so it uses a lot of ram32x1 and similar stuff. You need to annotate your RTL with a syn_ram attribute for block ram. MuzafferArticle: 25260
Article: 25261
Muzaffer Kal <muzaffer@kal.st> wrote in article <pc62rs0nkfo66vhlnr9puumlic8d2c8nk8@4ax.com>... > > "Austin Franklin" <austin@darkr98oom.com> wrote: > > >In Synplicity, if you instantiate an array of the size of the block RAM, > >won't it use the block RAM? It does it this way for CLB RAM... I've never > >tried it, but I am curious... > > No it won't. Synplicity 6.0 defaults to selectram so it uses a lot of > ram32x1 and similar stuff. You need to annotate your RTL with a > syn_ram attribute for block ram. That's excellent that I can control it, thanks!Article: 25262
"Ben Franchuk" <bfranchuk@jetnet.ab.ca> wrote in message news:39ADA050.56A4E4D9@jetnet.ab.ca... > Myself I would redesign the project to use 6 chips of 50 pins > each. Then they would fit in nice cheap 84 pin PLCC sockets with nice > cheap FPGA's. OK... but you show me your board with six discrete 50 pin ICs, and I'll show you my board that does the same thing but considerably faster, all in one part. :-) There's a reason those gigaHertz Pentiums are still using 100 and 133MHz front side busses... ---Joel KolstadArticle: 25263
Hello, does somebody have experience about using the tool Statecad from VSS ? Is ist suitable for more complex design and why there is no affordable version for students?? Thanx for more Danijel Sebalj, HamburgArticle: 25264
Peter Alfke <palfke@earthlink.net> wrote in message > architecture fpga. > I just don't know anybody who is interested in this subject. > As I said before, an employer who asks for an NDA in a first-level > interview should have his head examined... Yes. Is this asking for NDAs specifically a US-of-A issue ? I've never been required to sign one (or even see one, for that matter). Does seem to be a bit excessively paranoid. Just tell the company to bog off. Richard [in PE12]Article: 25265
Hi all, 3 Free OpenTech cdroms will be sent to the winners of the OpenTech contests. there are 3 contests 1. Logo. 2. CDROM covers 3. OpenHW design For more information visit http://www.opencores.org/OIPC/projects/OpenTech/prizes.shtml Regards Jamil Khatib Sent via Deja.com http://www.deja.com/ Before you buy.Article: 25266
Which Xilinx APP note/pdf shows the details of the Configuration Data for the XC3000A series? I would like to dynamically program that device with a microprocessor. Thanks in advance.Article: 25267
On Thu, 31 Aug 2000 00:01:20 +0000, Ben Franchuk <bfranchuk@jetnet.ab.ca> wrote: >John Larkin wrote: >> >> Well, I want to do a really cool image-processing gadget, and I'll >> need an FPGA with 300 I/O pins or so. Peter Alfke was kind enough to >> send me a couple of sample Xilinx BGA parts. I showed them to my >> manufacturing people and actually escaped with my life. >> >Myself I would redesign the project to use 6 chips of 50 pins >each. Then they would fit in nice cheap 84 pin PLCC sockets with nice >cheap FPGA's. The best bet would be to make a small daughter pcb >with the FPGA and ROM?. The smaller board would permit easier inspection >and manufacturing because of the smaller size. The PCB also would permit >brain transplants when it was time to upgrade the product. >Good Luck with what you have. >Ben. Ben, thanks, but I have a situation where all the data must be available to the core algorithm at once, and, besides, I'd lose pins faster than I'd gain them if I were to partition things into multiple chips. This chip has to be connected to nine 12-bit flash ADCs, two big banks of SRAM, a 68332 uP (to do the slow stuff!) and the PCI bus. The core algorithm must do massively nasty pipelined parallel stuff on the ADC data streams at 60 MHz or so. Wow. The first thing I ever designed for money had four vacuum-tube flipflops in it and it was, at the time, just as scary as this is now. You can't relax in this business! JohnArticle: 25268
In article <QpOyOTTKnsWfbM=MacxXqtYEDVgb@4ax.com>, John Larkin <jjlarkin@highlandSNIPTHIStechnology.com> wrote: >Ben, > >thanks, but I have a situation where all the data must be available to >the core algorithm at once, and, besides, I'd lose pins faster than >I'd gain them if I were to partition things into multiple chips. > >This chip has to be connected to nine 12-bit flash ADCs, two big banks >of SRAM, a 68332 uP (to do the slow stuff!) and the PCI bus. The core >algorithm must do massively nasty pipelined parallel stuff on the ADC >data streams at 60 MHz or so. One suggestion: BGA sockets. Several manufacturers make BGA sockets, semi-custom jobs, around $50 each (minimum quantity 5) which will fit various FPGAs. They have the nice property of they also BGA mount, with an identical profile, so you can use a socket during development and then solder down the parts when the board goes into a higher level of production. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 25269
> Yes. Is this asking for NDAs specifically a US-of-A issue ? I've never I think it is a peculiarily American practise. It may have originated from some legal CYA. Its a bit pointless IHMO because, like all NDAs, unless it specifies exactly what they're trying not to disclose or some specific documentation changes hands (not likely in a job interview!) then its only a matter of opinion about what was disclosed to whom. That interview candidate might be a competitor on a fishing expedition. Its unlikely. However, its the only time I know when I'd get hosted by a company, taken into their inner sanctums, shown exactly what they're doing, how they're doing it and be introduced to the engineering team who's doing it. You're quite likely to figure out their product development plans, their schedules, their team strengths and weaknesses and how well they're doing. Useful information. They probably should avoid trying to hire from direct competitors - I do; it not only avoids problems with accidental disclosure of things I'd rather not be disclosed but it also avoids any potential problems due to unathorized transfer of IP if you did hire that person.Article: 25270
Why would you do this on an SRAM based FPGA? The socket just adds one more thing that can go wrong, and nothing sucks quite as much as socket induced problems. With the SRAM based parts, just make sure you leave a way to laod a program in directly instead of in a PROM or buried in the processor ROM build. "Nicholas C. Weaver" wrote: > > In article <QpOyOTTKnsWfbM=MacxXqtYEDVgb@4ax.com>, > John Larkin <jjlarkin@highlandSNIPTHIStechnology.com> wrote: > >Ben, > > > >thanks, but I have a situation where all the data must be available to > >the core algorithm at once, and, besides, I'd lose pins faster than > >I'd gain them if I were to partition things into multiple chips. > > > >This chip has to be connected to nine 12-bit flash ADCs, two big banks > >of SRAM, a 68332 uP (to do the slow stuff!) and the PCI bus. The core > >algorithm must do massively nasty pipelined parallel stuff on the ADC > >data streams at 60 MHz or so. > > One suggestion: BGA sockets. Several manufacturers make BGA > sockets, semi-custom jobs, around $50 each (minimum quantity 5) which > will fit various FPGAs. They have the nice property of they also BGA > mount, with an identical profile, so you can use a socket during > development and then solder down the parts when the board goes into a > higher level of production. > -- > Nicholas C. Weaver nweaver@cs.berkeley.edu -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 25271
Hi, I have two Xilinx Virtex XCV200-5PQ240C's for sale, 240-pin TQPF. They are individually sealed in a level 3 bag. $80/ea obo. I also have two IDT 71V3558S/133PF 133MHz 256Kx18 SRAMS, 100-pin TQFP, also individually sealed. $20/ea obo. Thanks. -- Jeffrey J. Cook University of Illinois Computer Engineering Student jjcook@ews.uiuc.edu "Sometimes the easiest way to get something done is to be a little naïve about it -- and just ship it." Bill Joy, Sun Microsystems - Jini EngineerArticle: 25272
Hi, I think this appnote might be what you are looking for http://www.xilinx.com/appnotes/bus_conf.pdf Thomas Anthony Tekatch wrote: > > Which Xilinx APP note/pdf shows the details of the Configuration Data for > the XC3000A series? > > I would like to dynamically program that device with a microprocessor. > > Thanks in advance.Article: 25273
The problem of very slow routing of PWR/GND nets is supposed to be fixed in 2.1i Service Pack 6, but I am still suffering from it (running the Unix tools on a Sun Ultra 10 workstation). An XCV600 is taking about 8 hours to build, of which over 7 hours is the PWR/GND routing (all signals are successfully routed in under 40 minutes). Does the problem remain in SP6, or is this a specific issue related to the use of the Unix version ? Richard. http://www.rtrussell.co.uk/Article: 25274
Hello, That file only shows how the preamble data is generated. I would like to know how to construct the entire configuration data block (something that the Foundation software does). In article <39B37AB7.3730F97B@emw.ericsson.se>, Thomas Karlsson <thomas.karlsson@emw.ericsson.se> wrote: > Hi, > > I think this appnote might be what you are looking for > > http://www.xilinx.com/appnotes/bus_conf.pdf > > Thomas > > Anthony Tekatch wrote: >> >> Which Xilinx APP note/pdf shows the details of the Configuration Data >> for the XC3000A series? >> >> I would like to dynamically program that device with a microprocessor. >> >> Thanks in advance.
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