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Does anyone have any information on the PCILOGIC cells in Xilinx Virtex devices ?. From viewing the layout in FPGA Viewer (I would call it FPGA Editor if it didn't crash 90% of the time I try to edit anything) they seem to take in IRDY and TRDY from dedicated PCIIOB cells, plus a couple of other signals, and generate a clock enable signal for use by local IOBs. Anyone know anything more ? Ed Sent via Deja.com http://www.deja.com/ Before you buy.Article: 25326
Alexandr V Shuvalov wrote: > Which voltage regulators ICs are commonly used to power supply Xilinx XL > and other low voltage (3.3-2.5v) devices? I used a National LM3940IS-3.3 to drop a VME 5V supply down to 3.3V @ 1 A. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d uArticle: 25327
Ulf Samuelsson wrote: > > > Correct-it's the two-process style that I'm complaining about. A single > > process can be used for both Mealy and Moore state machines. Many people > > assume that two processes are needed for Mealy, and write all of their > state > > machines that way. (actually the second always block is not really a > > process- just combinatorial logic). > > > > I thought the main reason for dividing up state machines into several > processes is limitations in synthesizers I do all of my state machines as a single process, and FPGA Express 3.4 and 3.4 don't seem to have any problems. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d uArticle: 25328
You should be able to figure out the synthesized name by looking at the edif file in Xemacs or whatever editor you use. Different synthesis tools use different means of handling hierarchy, Synplicity uses a Unix like path with /, Synopsys allowed you to specify the format, I don't know what FPGA Express does. The easiest way is to figure it out is just look at the edif file. Peter Desmet wrote: > > Hi all, > > Does anyone know how to modify constraints when using an EDIF for > design implementation instead of an XNF file? > I've recently switched to a new PC, with brand new software, yippie, but now > it seems that FPGA Express (v3.4) generates edif-files for my XC4036XLA > part. That used to be an xnf-file. > My constraint file contains stuff like > INST name TNM = CPUFFS; > but since edif-files have a totally different structure, Design manager > reports > numerous errors in the translation step and basically says 'bugger off and > give me decent constraints'. > > There doesn't seem to be a menu option that allows switching between edif > and xnf, so... > > I suppose I can always re-install an older version of FPGA Express and get > me > an xnf-file to work with. > > Thnx for any repliesArticle: 25329
Hi - I've been trying to use FPGA_Express v3.1 with Powerview v6.1 on a Solaris machine and am running into an annoying problem. Here's the setup: I have a schematic in Viewdraw that contains some components out of the xc4000x library and a number of symbols, each of which represents some VHDL code. I'd like to take one of those pieces of VHDL, run it through FPGA_Express, and then simulate again using the synthesized circuit instead of the VHDL code. Basically, I want to incrementally replace VHDL code with circuits synthesized by FPGA_Express. Eventually, I'll be generating an EDIF file of the whole circuit (that contains some Xilinx components directly, and some synthesized pieces) and running it through Xilinx place and route. Here's the problem: When I run a design through FPGA_express with Xilinx XC4010XL as a target, the tool ONLY wants to generate an xnf file! What I need is an EDIF file! (actually, what I need is a wir file, but Powerview can read an EDIF file and turn it into a wir file). So, a couple questions: 1 - Is there a way to force FPGA_express v3.1 to produce an EDIF file instead of an XNF file if your target is a Xilinx chip? 2 - Is there something else that I'm just being stupid and overlooking about this process? Thanks! -ErikArticle: 25330
Any hints for making a dram controller for use with a sharc dsp processor? (60 ns dram)Article: 25331
"Andy Peters n o a o [.] e d u>" <"apeters <"@> wrote in message news:8p6288$5k7$2@noao.edu... > Alexandr V Shuvalov wrote: > > > Which voltage regulators ICs are commonly used to power supply Xilinx XL > > and other low voltage (3.3-2.5v) devices? > > I used a National LM3940IS-3.3 to drop a VME 5V supply down to 3.3V @ 1 > A. > Can you power-up several Xilinx-FPGA's with this element ; or is there a work-around ? We had this problem recently (not completelly solved), and the most recent idea is to supply 3 Xilinx FPGA's with one National LM3940 (other version : WG ?). The element we used before had a fast power-up time which caused the FPGA (4013) to take up to 1 A, and the regulator couldn't give 3A (it went ok a normal temperature, but in a cold phase at -40C it didn't go). Can the LM3940 do the job ? TIA, AlainArticle: 25332
Alain Cloet wrote: > "Andy Peters n o a o [.] e d u>" <"apeters <"@> wrote in message > news:8p6288$5k7$2@noao.edu... > > Alexandr V Shuvalov wrote: > > > > > Which voltage regulators ICs are commonly used to power supply Xilinx XL > > > and other low voltage (3.3-2.5v) devices? > > > > I used a National LM3940IS-3.3 to drop a VME 5V supply down to 3.3V @ 1 > > A. > > > Can you power-up several Xilinx-FPGA's with this element ; or is there a > work-around ? > > We had this problem recently (not completelly solved), and the most recent > idea is to supply 3 Xilinx FPGA's with one National LM3940 (other version : > WG ?). > > The element we used before had a fast power-up time which caused the FPGA > (4013) to take up to 1 A, and the regulator couldn't give 3A (it went ok a > normal temperature, but in a cold phase at -40C it didn't go). > > Can the LM3940 do the job ? > > TIA, > Alain I don't know if it can or not but I originally designed with an LT1764EQ-3.3. When that part became unavailable (Extremely long lead times and no support for small users.) I went to the LM3940. It worked OK but I like the shutdown on the 1764 as it is a ground referenced input as opposed to an input referenced shutdown (i.e a couple of volts as opposed to almost the input voltage.) Perhaps the shutdown inputs and the done outputs (or something similar) could be used to daisy-chain sequence the powersupplies on your three chips. If I recall correctly the I finally found the 1764's through Wyle. As I look at the LT web site I also see an LT1963 that looks promising.Article: 25333
kolja@prowokulta.org wrote: > > "Peter Schulz" <p.schulz@signaal.de> wrote: > > > >I certainly hope it's no secret.. I'm sure there must be a market for > > >programming the devices from uP generated data rather than predefined > > >layouts. > > There is some reverse engineered LCA documentation. You can uses that > together with makebits to generate bitstreams on the fly. > > But today you should move to Spartan-II and use Steve Guccione and > Delon Levi's JBits Software instead. > It is a Java API that allows you to modify Virtex Bitstreams on the fly. > > Officiall the bitsream is not disclosed to prevent the distruction > of the device by short circuit connections, which is allegedly > checked by JBits. > But as someone on FPL'99 pointed out, it is easy to damage the chip > anyway by bus contention or by implementing a couple of oscillator to > overheat it. So this function is more or less useless. Actually, JBits doesn't check short circuit connections, though you could write a DRC checker using the JBits API if you were concerned about it. Since JBits gives you full access to all the configurable resources within a device, if you want to blow up a Virtex, go ahead. PhilArticle: 25334
Hi, Is there such a thing as a BGA to DIP converter? Thanks Sent via Deja.com http://www.deja.com/ Before you buy.Article: 25335
A company named Ironwood makes a BGA to sort of a DIP adapter. Its got more than two rows of pins because of the large number of i/o, but they area rranged in rows like dips. I used it for a customer who had a wirewrapped prototype about 2 years ago. SOrry, I don't have a URL. uwuh@my-deja.com wrote: > > Hi, > Is there such a thing as a BGA to DIP converter? > Thanks > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 25336
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Article: 25337Thank to everybody! It helps me great! Alexandr.Article: 25338
<uwuh@my-deja.com> wrote in message news:8p6c8f$gqu$1@nnrp1.deja.com... > Hi, > Is there such a thing as a BGA to DIP converter? > Thanks > Aries might be able to make you a custom converter (if they don't have something suitable in stock). http://www.arieselec.com/ Regards, - OlafArticle: 25339
> I do all of my state machines as a single process, and FPGA Express 3.4 > and 3.4 don't seem to have any problems. > I think synthesizers have improved since I heard this comment 5 years ago from an experienced ASIC designer. Synopsys had problems to synthesize *complex* single process state machines from time to time when timing constraints were applied, so he felt they were better off adopting a style that ALWAYS worked. If I remember correctly they actually were using three processes. The fact that the synthesis *works* for one tool also does not say anything about the speed/power consumption/area. It does not say anything about portability of the design. If you want to sell a synthesizable IP block to someone, then you want something which is as robust as possible. I.E: works with all conceivable tools. I do not thing that the extra process is such a nuisance, since I normally instantiate a programmable width register instead of the always statement. dff #(8) reg(state,next_state,clk,reset_z); Since the "dff" is implemented using behavioural statements it is portable. -- Best regards, ulf at atmel dot com The contents of this message is intended to be my private opinion and may or may not be shared by my employer Atmel SwedenArticle: 25340
In article <39B6B196.A9326D1B@xilinx.com>, Phil James-Roxby <phil.james-roxby@xilinx.com> wrote: > > Officiall the bitsream is not disclosed to prevent the distruction > > of the device by short circuit connections, which is allegedly > > checked by JBits. > > But as someone on FPL'99 pointed out, it is easy to damage the chip > > anyway by bus contention or by implementing a couple of oscillator to > > overheat it. So this function is more or less useless. > > Actually, JBits doesn't check short circuit connections, though you > could write a DRC checker using the JBits API if you were concerned > about it. Since JBits gives you full access to all the configurable > resources within a device, if you want to blow up a Virtex, go ahead. > Phil Booom! So, then I can not the why you should keep the bitstream secret? I would like to do self reconfiguration from the FPGA so I do not have Java around in that environment. JBits will help a lot with reverse engineering but a disclosed bitstream format would be easier. Go ahead and publish it. CU, Kolja Sent via Deja.com http://www.deja.com/ Before you buy.Article: 25341
In article <39B6B196.A9326D1B@xilinx.com>, Phil James-Roxby <phil.james-roxby@xilinx.com> wrote: > > Officiall the bitsream is not disclosed to prevent the distruction > > of the device by short circuit connections, which is allegedly > > checked by JBits. > > But as someone on FPL'99 pointed out, it is easy to damage the chip > > anyway by bus contention or by implementing a couple of oscillator to > > overheat it. So this function is more or less useless. > > Actually, JBits doesn't check short circuit connections, though you > could write a DRC checker using the JBits API if you were concerned > about it. Since JBits gives you full access to all the configurable > resources within a device, if you want to blow up a Virtex, go ahead. > Phil Booom! So, then I can not the why you should keep the bitstream secret? I would like to do self reconfiguration from the FPGA so I do not have Java around in that environment. JBits will help a lot with reverse engineering but a disclosed bitstream format would be easier. Go ahead and publish it. CU, Kolja Sent via Deja.com http://www.deja.com/ Before you buy.Article: 25342
I hadn't changed any instantiation names in vhdl-code, so that wasn't actually the problem. What was apparently wrong was that the constraint when using an xnf file looked something like INST level1_level2_regname_reg TNM=group1; whereas for the edif-file the constraint needs to look like: INST level1/level2/regname_reg TNM = group1; I found this out when running the design (nearly) constraintless, letting the router stop after mapping, and then defining my constraints using the built-in Constraints Editor. Cheers, P. Thomas Karlsson <thomas.karlsson@emw.ericsson.se> wrote in message news:39B64CEB.37546B0A@emw.ericsson.se... > Hello Peter! > > The different structure of XNF and EDIF files does not affect the syntax > of the UCF file in any way, but when you do a new synthesis run > (especially with new software), > the tool may invent totally new names for signals. > So in > INST name TNM = CPUFFS; > name may not exist anymore. > > Could this be the problem in your case? > > /Thomas Karlsson > > Peter Desmet wrote: > > > > Hi all, > > > > Does anyone know how to modify constraints when using an EDIF for > > design implementation instead of an XNF file? > > I've recently switched to a new PC, with brand new software, yippie, but now > > it seems that FPGA Express (v3.4) generates edif-files for my XC4036XLA > > part. That used to be an xnf-file. > > My constraint file contains stuff like > > INST name TNM = CPUFFS; > > but since edif-files have a totally different structure, Design manager > > reports > > numerous errors in the translation step and basically says 'bugger off and > > give me decent constraints'. > > > > There doesn't seem to be a menu option that allows switching between edif > > and xnf, so... > > > > I suppose I can always re-install an older version of FPGA Express and get > > me > > an xnf-file to work with. > > > > Thnx for any repliesArticle: 25343
--------------C9F8785A76E873218CD65EEF Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Alain, We recently (> 1 year ago) implemented a Power On Ramp Up current specification for all parts. We have not gone all the way back to the original 4K family, but the data sheet now specifies the current capacity of the power supply required for clean out and startup prior to configuration. I would recommend that 1 amp be allowed for each older part (4K, 4KE). I know the 4KXL, and all subsequent parts are characterized AND TESTED. There are also things you can do which make this start up current worse. A generally rising voltage, that rises no faster than 2 milliseconds, and no slower than 50 milliseconds, and starts from near 0 Vdc (< 300 mV) is always the best way to go. Starting from a voltage around 450 mV to 700 mV from a previously configured part, or holding INIT to prevent configuration, or passing through the POR trip point and then going below the POR trip point, are common causes of higher currents. In all cases, check the latest website data sheet. An example is here: http://www.support.xilinx.com/partinfo/ds005.pdf page 2 of 16 For parts that have virtually no current requirement at starup, use the 4KXLA, 4KXV, SpartanXL, or contact your sales office and FAE for assitance in selection. Austin Lesea IC Design, Xilinx Alain Cloet wrote: > "Andy Peters n o a o [.] e d u>" <"apeters <"@> wrote in message > news:8p6288$5k7$2@noao.edu... > > Alexandr V Shuvalov wrote: > > > > > Which voltage regulators ICs are commonly used to power supply Xilinx XL > > > and other low voltage (3.3-2.5v) devices? > > > > I used a National LM3940IS-3.3 to drop a VME 5V supply down to 3.3V @ 1 > > A. > > > Can you power-up several Xilinx-FPGA's with this element ; or is there a > work-around ? > > We had this problem recently (not completelly solved), and the most recent > idea is to supply 3 Xilinx FPGA's with one National LM3940 (other version : > WG ?). > > The element we used before had a fast power-up time which caused the FPGA > (4013) to take up to 1 A, and the regulator couldn't give 3A (it went ok a > normal temperature, but in a cold phase at -40C it didn't go). > > Can the LM3940 do the job ? > > TIA, > Alain --------------C9F8785A76E873218CD65EEF Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> Alain, <p>We recently (> 1 year ago) implemented a Power On Ramp Up current specification for all parts. We have not gone all the way back to the original 4K family, but the data sheet now specifies the current capacity of the power supply required for clean out and startup prior to configuration. <p>I would recommend that 1 amp be allowed for each older part (4K, 4KE). <p>I know the 4KXL, and all subsequent parts are characterized AND TESTED. <p>There are also things you can do which make this start up current worse. A generally rising voltage, that rises no faster than 2 milliseconds, and no slower than 50 milliseconds, and starts from near 0 Vdc (< 300 mV) is always the best way to go. Starting from a voltage around 450 mV to 700 mV from a previously configured part, or holding INIT to prevent configuration, or passing through the POR trip point and then going below the POR trip point, are common causes of higher currents. <p>In all cases, check the latest website data sheet. An example is here:<a href="http://www.support.xilinx.com/partinfo/ds005.pdf"></a> <p><a href="http://www.support.xilinx.com/partinfo/ds005.pdf">http://www.support.xilinx.com/partinfo/ds005.pdf</a> <p>page 2 of 16 <p>For parts that have virtually no current requirement at starup, use the 4KXLA, 4KXV, SpartanXL, or contact your sales office and FAE for assitance in selection. <p>Austin Lesea <br>IC Design, Xilinx <p>Alain Cloet wrote: <blockquote TYPE=CITE>"Andy Peters n o a o [.] e d u>" <"apeters <"@> wrote in message <br><a href="news:8p6288$5k7$2@noao.edu">news:8p6288$5k7$2@noao.edu</a>... <br>> Alexandr V Shuvalov wrote: <br>> <br>> > Which voltage regulators ICs are commonly used to power supply Xilinx XL <br>> > and other low voltage (3.3-2.5v) devices? <br>> <br>> I used a National LM3940IS-3.3 to drop a VME 5V supply down to 3.3V @ 1 <br>> A. <br>> <br>Can you power-up several Xilinx-FPGA's with this element ; or is there a <br>work-around ? <p>We had this problem recently (not completelly solved), and the most recent <br>idea is to supply 3 Xilinx FPGA's with one National LM3940 (other version : <br>WG ?). <p>The element we used before had a fast power-up time which caused the FPGA <br>(4013) to take up to 1 A, and the regulator couldn't give 3A (it went ok a <br>normal temperature, but in a cold phase at -40C it didn't go). <p>Can the LM3940 do the job ? <p>TIA, <br>Alain</blockquote> </html> --------------C9F8785A76E873218CD65EEF--Article: 25344
I must say that I am floored by this information. All the time I have been using Xilinx parts, I have never been aware of the high current required for startup. I guess I was lucky that the systems I worked on had plenty of power for startup. But now I am designing boards that will have very little extra power supply capacity since the low voltages for powering the FPGAs are generated on board. I was planning on using 4 of the smaller Spartan II FPGAs on my board with a 1 Amp 2.5 Volt power converter. Now I realize that I may need as much as 8 Amps to bring these parts up if I can't control the output rampup of the power converter. I am pretty sure that this will be impossible to acheive on the board I am designing. If there is no better way to do this, I will be forced to stick with the Lucent Orca parts I am currently using. Any idea of how the Spartan II parts will work? I am assuming that they are the same as the current Virtex parts and that the industrial parts will need 2 Amps each worse case. Is this correct? Is there any way to prevent this current surge to the part? Will holding the PRGM- pin low prevent this high power draw? Can the parts be sequenced to limit the total power draw? Or will I have to add switches to the Vdd feeds to turn them on one at a time? Austin Lesea wrote: > > Alain, > > We recently (> 1 year ago) implemented a Power On Ramp Up current > specification for all parts. We have not gone all the way back to the > original 4K family, but the data sheet now specifies the current > capacity of the power supply required for clean out and startup prior > to configuration. > > I would recommend that 1 amp be allowed for each older part (4K, 4KE). > > I know the 4KXL, and all subsequent parts are characterized AND > TESTED. > > There are also things you can do which make this start up current > worse. A generally rising voltage, that rises no faster than 2 > milliseconds, and no slower than 50 milliseconds, and starts from near > 0 Vdc (< 300 mV) is always the best way to go. Starting from a > voltage around 450 mV to 700 mV from a previously configured part, or > holding INIT to prevent configuration, or passing through the POR trip > point and then going below the POR trip point, are common causes of > higher currents. > > In all cases, check the latest website data sheet. An example is > here: > > http://www.support.xilinx.com/partinfo/ds005.pdf > > page 2 of 16 > > For parts that have virtually no current requirement at starup, use > the 4KXLA, 4KXV, SpartanXL, or contact your sales office and FAE for > assitance in selection. > > Austin Lesea > IC Design, Xilinx > > Alain Cloet wrote: > > > "Andy Peters n o a o [.] e d u>" <"apeters <"@> wrote in message > > news:8p6288$5k7$2@noao.edu... > > > Alexandr V Shuvalov wrote: > > > > > > > Which voltage regulators ICs are commonly used to power supply > > Xilinx XL > > > > and other low voltage (3.3-2.5v) devices? > > > > > > I used a National LM3940IS-3.3 to drop a VME 5V supply down to > > 3.3V @ 1 > > > A. > > > > > Can you power-up several Xilinx-FPGA's with this element ; or is > > there a > > work-around ? > > > > We had this problem recently (not completelly solved), and the most > > recent > > idea is to supply 3 Xilinx FPGA's with one National LM3940 (other > > version : > > WG ?). > > > > The element we used before had a fast power-up time which caused the > > FPGA > > (4013) to take up to 1 A, and the regulator couldn't give 3A (it > > went ok a > > normal temperature, but in a cold phase at -40C it didn't go). > > > > Can the LM3940 do the job ? > > > > TIA, > > Alain -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 25345
This is one of the things I have always found difficult. Determining naming conventions of the different tools in use. Often this is poorly documented or not at all. Even the support people are often not familiar enough to actually be able to tell you the rules for constructing the names. So if you don't have the constraints editor, you would be poking in the dark! Peter Desmet wrote: > > I hadn't changed any instantiation names in vhdl-code, so that wasn't > actually the problem. > What was apparently wrong was that the constraint when using an xnf file > looked something like > INST level1_level2_regname_reg TNM=group1; > whereas for the edif-file the constraint needs to look like: > INST level1/level2/regname_reg TNM = group1; > > I found this out when running the design (nearly) constraintless, letting > the router stop after mapping, and then defining my constraints using the > built-in Constraints Editor. > > Cheers, > > P. > > Thomas Karlsson <thomas.karlsson@emw.ericsson.se> wrote in message > news:39B64CEB.37546B0A@emw.ericsson.se... > > Hello Peter! > > > > The different structure of XNF and EDIF files does not affect the syntax > > of the UCF file in any way, but when you do a new synthesis run > > (especially with new software), > > the tool may invent totally new names for signals. > > So in > > INST name TNM = CPUFFS; > > name may not exist anymore. > > > > Could this be the problem in your case? > > > > /Thomas Karlsson > > > > Peter Desmet wrote: > > > > > > Hi all, > > > > > > Does anyone know how to modify constraints when using an EDIF for > > > design implementation instead of an XNF file? > > > I've recently switched to a new PC, with brand new software, yippie, but > now > > > it seems that FPGA Express (v3.4) generates edif-files for my XC4036XLA > > > part. That used to be an xnf-file. > > > My constraint file contains stuff like > > > INST name TNM = CPUFFS; > > > but since edif-files have a totally different structure, Design manager > > > reports > > > numerous errors in the translation step and basically says 'bugger off > and > > > give me decent constraints'. > > > > > > There doesn't seem to be a menu option that allows switching between > edif > > > and xnf, so... > > > > > > I suppose I can always re-install an older version of FPGA Express and > get > > > me > > > an xnf-file to work with. > > > > > > Thnx for any replies -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 25346
Alain Cloet wrote: > > "Andy Peters n o a o [.] e d u>" <"apeters <"@> wrote in message > news:8p6288$5k7$2@noao.edu... > > Alexandr V Shuvalov wrote: > > > > > Which voltage regulators ICs are commonly used to power supply Xilinx XL > > > and other low voltage (3.3-2.5v) devices? > > > > I used a National LM3940IS-3.3 to drop a VME 5V supply down to 3.3V @ 1 > > A. > > > Can you power-up several Xilinx-FPGA's with this element ; or is there a > work-around ? > > We had this problem recently (not completelly solved), and the most recent > idea is to supply 3 Xilinx FPGA's with one National LM3940 (other version : > WG ?). > > The element we used before had a fast power-up time which caused the FPGA > (4013) to take up to 1 A, and the regulator couldn't give 3A (it went ok a > normal temperature, but in a cold phase at -40C it didn't go). > > Can the LM3940 do the job ? My most-recent board has two XC4013XLAs, an XCS20XL, and eight 128Mb SDRAM devices (as well as a clock tree). I used two 3940s. One powers one 4013, four SDRAMs and the two of the clock buffers. The other powers the other 4013, four SDRAMs and the XCS20. I split my power plane down the middle. Common ground plane to all, of course. Works just fine. The 5V regulator input comes from the VME backplane. I don't have any low-temperature requirements (this board will live in a thermal enclosure with a fairly constant temperature), so I can't tell you how it works at -40C. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d uArticle: 25347
kolja@prowokulta.org wrote: > Booom! > > So, then I can not the why you should keep the bitstream secret? > I would like to do self reconfiguration from the FPGA so I do > not have Java around in that environment. > JBits will help a lot with reverse engineering but a disclosed > bitstream format would be easier. > > Go ahead and publish it. I'm not going to get into the ins and outs of proprietary configuration datastreams. Like Peter Schulz in an earlier reply said, it is a secret, definitively for the protection of customer designs. I've worked with JBits for several years now, and my standpoint on trying to use it as a reverse engineering tool is its just a bad idea. Superficially, it appears attractive, all you need is the bitstream, and lo and behold suddenly you can work out the circuit underneath. Well, in practice, this just isn't the case. At the level of abstraction JBits gives you, all you get is LUT-FFs and about a billion switch settings, which you could trace to give you interconnections. Thats a hell of a way from anything you could usefully call a circuit, and imho gives you nothing over just copying the bitstream and calling that reverse engineering. Far better would be to determine the owner of the IP and go steal their filing cabinet. Its bad enough trying to determine what the tools have done to your own circuit using JBits, let alone trying to figure out what someone elses circuit does. As for self-reconfiguration from the FPGA, I suggest you look at the work-horse of reconfigurable computing,the XC6200 and the work of Adam Donlin published at FPL98. Phil -- --------------------------------------------------------------------- __ / /\/ Dr Phil James-Roxby Direct Dial: 303-544-5545 \ \ Staff Software Engineer Fax: Unreliable use email :-) / / Loki/DARPA Email: phil.james-roxby@xilinx.com \_\/\ Xilinx Boulder ---------------------------------------------------------------------Article: 25348
"rickman" <spamgoeshere4@yahoo.com> wrote in message news:39B7CD44.B9D9F57F@yahoo.com... > I must say that I am floored by this information. All the time I have > been using Xilinx parts, I have never been aware of the high current > required for startup. I guess I was lucky that the systems I worked on > had plenty of power for startup. > I could imagine it either, but when I was told of the startup problems at low temperature it was my first guess. I'm not a designer, so I wasn't aware that after boot the FPGAs consumed so less ofter startup - the whole 3.3 part of the board (which is mainly just the three XL4013XL-parts and some capacitors near the power) consumes after startup approx. 50 mA. The whole boot thing takes from 500µs to 5 ms depending on the temperature, so you can't possible notice this if you don't measure this intentionally... In a test of the startup power with a external power source with a max of 5 A (!) it's still possible to see that the voltage doesn't go up in a regulated way - in other words: the 3 parts & the capacitors (which, of course, have their influence as well with fast power-up) would have taken more than 5 A if it were possible...(at -40C, and more than half an hour unpowered) Under relative normal condition the former regulator could make it (even though the voltage didn't went up in a continuous way) at room temperature, but under the maximum stressed specs of the board - at -40C for more than 30 minutes unpowered (so really cold, even internally) and a supply voltage of 4V5 - it didn't... In the measurements it showed oscillating of the voltage even at -20C (due to the current limiting of the regulator), but the core of FPGA - my guess again - got warm enough to start. Also at -40C a supply voltage of 5V2 made it possible to boot... Thanks for all the reactions, AlainArticle: 25349
For VHDL, I find it's useful to do all of the floorplanning via
a single function of the form: (Please excuse VHDL errors, I'm
writing this without a VHDL reference)
function XPlace( -- Global Placement function
Thing: string; -- Thing to place
P1,P2,P3: integer -- 3 Parameters (e.g. Bit number, Bank number)
) return string is
...
begin
if Thing="InFifo" then
R= ... Function of P1,P2,P3 to determine row
C= ... Column
return "R" & to_string(R) & "C" & to_string(C);
else if Thing="StatusReg" then
....
This allows global control over placement, so you can try
quick changes, like moving entire busses up a few rows,
swapping columns, etc.
When called from an entity, (usually inside a generate loop)
it looks something like:
for B in 0 to 31 generate
constant Loc=XPlace("VReg",B,0,0); -- Must use a cosntant
attribute PLOC of R:label is Loc;
begin
R: V_bit port map (....
erika_uk@my-deja.com wrote:
> my question is mainly to you RAY. you are saying all the time that you
> perform flooplanning.
> could you give us some tips for free ?
> I find it really hard, how one should do a placement, escpecially for
> parrallel arithmetic.
> Let's take an example. a simple FIR , inverted mode, multpliers and
> adders built from the carry logic, could you tell me please how you
> will floorplan such architecture?
> Moreover is the flooplanning soft placement or hard one
>
> with best regards
>
> --Erika
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.
>
Sent via Deja.com http://www.deja.com/
Before you buy.
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