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Here I have Xilinx Demo board for X4003A, so by what kind of software I can use to generate bit file and download to the demo board? Thank you very much! QianArticle: 26101
"Keith R. Williams" wrote: > I've gone through the Amplify PowerPoint-Ware. ...well, mostly. > I have many questions, which I really should talk to their FAEs > about. ...though since you've volunteered! ;-) > - I've looked through the flow and it seems that my Synplify > license is useless, given that I wanted to stay with Virtex (I'm > still fighting with a SpartanXL, so this isn't a biggie). Yes, but you can't lose by asking "If I buy Amplify and turn in my Synplify license will you give me a credit for it?" > - Given the above, and Synplicities wish to move me to -Pro, why? > Sure, I see some use for -Pro for higher speed designs, but > doesn't Amplify trump -Pro here. I don't see the cross. Amplify is "Synplicity Pro with Amplify". I've heard several people express the opinion that -Pro isn't a good choice: if you want a good push-button flow, non-Pro is good enough. If you need more go all the way to Amplify. > - How hard is Amplify to learn. Can I pick it up (they did send > me the manual) or should I take a *valuable* week off to go to > their new training? I think Amplify is fairly easy to pick up. I've used it since the first Beta release, so I would hope your learning would be quicker than mine (little documentation and I sent the first bug report after trying the tool for a less than a hour) On the other hand, I've been building Xilinx parts for a decade, using schematics and hand written placements at first, so it's not like I'm a newbie. As you are still thinking about buying it, you sure could ask for some FAE time to help you get started as part of the deal. A few hours with a good FAE should take days off your learning time. The problem I have with training courses is that I often just dive in, learn the tool by doing, and have it fairly well mastered by the time the training course is scheduled. Didn't work for my first Xilinx design, however. > There are many more questions, but I'm about to go dream in VHDL, > again. Today was not good. Been there, done that. Good luck. -- Phil HaysArticle: 26102
Please help me. I'm doing make the simple b'd using xilinx xc4010e device. If you have schematic and any infomation, help me. thank you very much. bill.Article: 26103
It's a testArticle: 26104
I'm currently using a virtex e device with bank 2 VCCO= 3.3V and all other banks connected to 2.5V. I've got LVDS receivers powered off 3.3V connected to banks 4 and 5. 3.3V levels are thus supplied on these banks. After configuration I see that the 3.3V rail is supplying a portion of the power to the 2.5V rail throuht some unknown path.Currently I'm powering the 3.3V rail and 2.5V rail off a current limited bench supply. Eventually the current drawn from the 2.5v bench supply reaches 0mA and can be removed from the equation- 2.5V being maintained by the 3.3V supply through some unknown path. With my LVDS bank disabled and all outputs <0.8V then the 2.5V rail is ok. However enabling the 32 outputs of the LVDS sets them to 3.3V and this gets passed on to the LVCMOS2 i/ps on the FPGA. In this scenario the 2.5V rail rises to 2.8V. The FPGA's are still functioning and performing as designed- but I need to know what is going on here- are my devices damaged? Are there clamp diodes on LVCMOS2 i/ps that allow 3.3V to migrate onto the 2.5V rail!! Has anyone else haqd a similar experience. rgds PauricArticle: 26105
Can anybody explain in detail the problem of propagation delays and prospective dangers of hazards in FPGA modules???Article: 26106
Hi, I have a question concerning Xilink Virtex E FPGAs . I'm going to use a XCV1000E-fg680 Xilink FPGA with somes IOs configured as LVDS differential Signals. This means that an Input or an Output will take 2 pins. The question is for Boundary Scan Test. Each pin of an LVDS Signal is connected to an independant BS cell. So It seems like it will be a problem to read or drive an LVDS Signals in Boundary Scan mode since the datasheet says that "Boundary-scan operation is independent of individual IOB configurations". Note that we aim at develloping extended test and that the FPGA will be connected to a LVDS to LVTTL buffer which is not JTAG compliant. So Is it possible to perform a Boundary Scan Test with LVDS Signals ? And if yes how ? Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26107
You said: "And now, Virtex is going to release all of this for free with the WebPack? (Up to the XCV-300, anyways.) Am I missing something, or did they not inform my distributor?" But who says that the WabPack supports FPGAs?? I thought it only supports CPLDs. Can You tell me where You got Your information? Marc korthner@inf.furukawa.co.jp schrieb: > Okay, now I'm really confused with Xilinx's Licensing. > > A few weeks ago, we had the distributor over, pushing the new ISE. > > If we pay for the time based license for 3.1i Base, we get the old > GUI, support for up to Virtex '50. Or we can pay more, get the 'ISE' > version (Which is explained to me as a new GUI, same tools.) > Alternatively, We can get the 'Express', which is full device support, > 3.1i synthesis tools, old GUI. Pay an *additional fee* for the ISE, > and still get full device support, new GUI. > > We're using Spartan II / Virtex '150, so we can't use the Base, since > it only supports up to Virtex '50. > > All this was last week. > > And now, Virtex is going to release all of this for free with the > WebPack? (Up to the XCV-300, anyways.) Am I missing something, or > did they not inform my distributor? > > Anything that can sort this mess ou is appreciated. > > -KentArticle: 26108
any more explanation,ray, i don't see really what do you mean In article <39DA4D27.D380F6E8@andraka.com>, Ray Andraka <ray@andraka.com> wrote: > SO you are using up a pin to get your fixed logic '1' or '0' ???? Perhaps from > an unbonded pin... > > erika_uk@my-deja.com wrote: > > > > hey, > > > > Sourcing a GND and VCC was an issue weeks ago in this news group. > > > > Xilinx claims that the Virtex is rich in terms of routing ressources, > > so why not source the Pwr and Gnd wires from the IOB? > > > > I know a friend who does so in the xc4k, is it not possible in virtex ? > > > > --Erika > > > > Sent via Deja.com http://www.deja.com/ > > Before you buy. > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com or http://www.fpga-guru.com > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26109
Hey, I know those spikes on signals simply routed 1to 1 through XC9572. They're coming from (that's what I think) crosstalk on the chip from other signals. This is fact since Xilinx changed from ASJ9745 to AEM9917 (new Mask+Manuf). Seems like having many bad sideeffects also.Article: 26110
Do you now of any that you can use for free in commercial applications? Perhaps one that served as a master thesis or something, which needs some work, but not the rewriting of the whole proc. Richard Jan Gray wrote: > "Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message > news:XLkC5.64438$zJ5.3129190@news.chello.at... > > Hi, > > > > I'm thinking about implementing a JVM ( Java Virtual Machine ) processor > in > > a FPGA. > > But I don't want to invent the wheel once more. > > Does enyone know if this is done allready? > > Here are a couple of Java processor core implementations that I have read > have been run in an FPGA: > > Austin Kim (Lucent), Morris Chang (IIT) paper: Designing a Java > Microprocessor Core Using FPGA Technology > http://csl.cs.iit.edu/~java/publication/asic98.html > > Advancel Logic Corp. TinyJ > http://www.advancel.com/home.htm > > Jedi Technologies JStar > http://www.jeditech.com/jstarwp.html > > Derivation Systems LavaCore > http://www.derivation.com/news/pressrelease_06-21-1999.html > > Vulcan Moon > http://www.vulcanasic.com/eda.htm > > I suspect at least one of the Sun picoJava cores has been synthesized to an > FPGA. Certainly it had been discussed. > > See also www.fpgacpu.org/usenet/java.html. > > And someday we'll have an FPGA CPU+SoC implementing (or hosting) a JVM, > hosting an EDA application, with jbits, that emits version n+1 of itself. > > Jan Gray > Gray Research LLC > www.fpgacpu.org -- Quest Innovations tel: +31 (0) 227 604046 http://www.quest-innovations.comArticle: 26111
http://www.xilinx.com/prs_rls/webfpga.html Go to the above link for the words from the horses' mouth. The first part of the press release below. SAN JOSE, Calif., October 2, 2000—Xilinx, Inc. (NASDAQ: XLNX) today announced full support of the entire Spartan®-II FPGA family as well as the 300,000 system gate Virtex™ XCV300E FPGA in the WebPACK ISE™ tool suite. The free downloadable software, previously available only for Xilinx CPLDs, now offers a zero-cost-of-entry point for designing with Xilinx FPGAs. Happy gate slinging Jerry English Marc Reinert wrote: > You said: > > "And now, Virtex is going to release all of this for free with the > WebPack? (Up to the XCV-300, anyways.) Am I missing something, or > did they not inform my distributor?" > > But who says that the WabPack supports FPGAs?? I thought it only supports > CPLDs. > > Can You tell me where You got Your information? > > Marc > > korthner@inf.furukawa.co.jp schrieb: > > > Okay, now I'm really confused with Xilinx's Licensing. > > > > A few weeks ago, we had the distributor over, pushing the new ISE. > > > > If we pay for the time based license for 3.1i Base, we get the old > > GUI, support for up to Virtex '50. Or we can pay more, get the 'ISE' > > version (Which is explained to me as a new GUI, same tools.) > > Alternatively, We can get the 'Express', which is full device support, > > 3.1i synthesis tools, old GUI. Pay an *additional fee* for the ISE, > > and still get full device support, new GUI. > > > > We're using Spartan II / Virtex '150, so we can't use the Base, since > > it only supports up to Virtex '50. > > > > All this was last week. > > > > And now, Virtex is going to release all of this for free with the > > WebPack? (Up to the XCV-300, anyways.) Am I missing something, or > > did they not inform my distributor? > > > > Anything that can sort this mess ou is appreciated. > > > > -KentArticle: 26112
Hi. I wonder what it would take to make a sharc dsp to pci controller (I only need very basic pci functionality, enough to control a pci ethernet card, with dma).Article: 26113
"Richard Meester" <rme@quest-innovations.com> wrote > Do you now of any that you can use for free in commercial applications? Perhaps > one that served as a master thesis or something, which needs some work, but not > the rewriting of the whole proc. With the exception of picoJava, I don't know if any of the listed cores are free for commercial use. Sun's PicoJava Technology is licensed under the Sun Community Source License (http://www.sun.com/microelectronics/communitysource/picojava/license.html) and "Commercial Use" as defined apparently incurs royalties. See also my mini-essay on FPGA cores business models, the second item at www.fpgacpu.org/index.html#001002. Jan Gray Gray Research LLCArticle: 26114
Phil Hays wrote: > > Ray Andraka wrote: > > > Personally, I'm not going to spend the $$$ for it. I've already built a fairly > > sizable library of completely placed thingies (technical term for macros), that > > will run rings around what amplify will do, plus, it'll work with a customer's > > tool suite, and has a better than even shot of being portable across synthesis > > tools. > > I'm aware of your design style and am not surprised that you don't want to use > Amplify. It is more that I can hardly justify the cost for doing something I've already figured out how to do reasonably fast, and that is more portable across tools and doesn't require my customer to have the extras to support the design. > > > If you are > > not reusing the pieces (one time designs), then it is fast to just place them in > > the floorplanner (xilinx) and be done with it. > > Amplify is easier and faster to use than the Xilinx floorplanner and gets better > results. It is faster to use as you have fewer things to place. The placement > is stable even if the source changes. Amplify does a better job of mapping to > logic by using the hints from the block level floorplan. > > -- > Phil Hays -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26115
Perhaps I don't understand your point. The discussion a few weeks ago, IIRC was regarding instantiation of logic 0's and logic 1's to get around a bug in the xilinx mapper that mapped all the SRL16 address inputs to a single generator (usually a carry chain element). The result was the net could become overloaded, which may or may not cause problems in routing or in the DRC if you use a lot of SRL16's in the design. If I understand you right, you are suggesting you use an IOB to generate the logic 0 or logic 1 signal? If that is the case, then I am assuming you are doing so by either externally tying the pin, or internally using the pad pull-up and leaving the pin floating. In either case, you tie up the pin so it can't be used for something else. Where many designs are already pin limited, I don't think it makes sense to use an IOB for a function that can be accomplished better by a core cell. I then mentioned an exception might be if you used an unbonded pin as the generator, since those IOBs are otherwise unusable anyway. erika_uk@my-deja.com wrote: > > any more explanation,ray, i don't see really what do you mean > > In article <39DA4D27.D380F6E8@andraka.com>, > Ray Andraka <ray@andraka.com> wrote: > > SO you are using up a pin to get your fixed logic '1' or '0' ???? > Perhaps from > > an unbonded pin... > > > > erika_uk@my-deja.com wrote: > > > > > > hey, > > > > > > Sourcing a GND and VCC was an issue weeks ago in this news group. > > > > > > Xilinx claims that the Virtex is rich in terms of routing > ressources, > > > so why not source the Pwr and Gnd wires from the IOB? > > > > > > I know a friend who does so in the xc4k, is it not possible in > virtex ? > > > > > > --Erika > > > > > > Sent via Deja.com http://www.deja.com/ > > > Before you buy. > > > > -- > > -Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email ray@andraka.com > > http://www.andraka.com or http://www.fpga-guru.com > > > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26116
Oops -- I wrote: > With the exception of picoJava, I don't know if any of the listed cores are > free for commercial use. Whereas I meant to express: "I don't know if any of the listed cores are free for commercial use -- and I understand that picoJava in particular is NOT FREE for commercial use." Sorry for any misunderstanding. Jan Gray Gray Research LLCArticle: 26117
In article <39D8B9DC.269C249C@andraka.com>, Ray Andraka <ray@andraka.com> wrote: > ... Don't let anyone convince you the tools can > do as good a job with placement as the human brain. I agree, but there must be a lot of people (myself included) who havn't got the time for relative placement, and rely on P&R software to do a good job on their inferred designs. Problem is, current software is not good enough. For example, I really really want to infer adders, but current Xilinx MAP software nobbles my virtex designs down from an easily achievable 135 MHz to about 120 MHz, all because Xilinx MAP can't keep carry logic and flip-flops together. (Some time ago, Xilinx were talking about timing-driven MAP. This sounded good, but it hasn't happened. Common-sense driven MAP would be a start). I think the FPGA manufacturers should aim to get the maximum performance out of non-rloc'd designs. If their software departments can't do it, make the P&R algorithmns open-source and let other people have a go. -- Ed. Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26118
Jerry English wrote: > > http://www.xilinx.com/prs_rls/webfpga.html > Go to the above link for the words from the horses' mouth. > > The first part of the press release below. > SAN JOSE, Calif., October 2, 2000—Xilinx, Inc. (NASDAQ: XLNX) today announced > full > support of the entire Spartan®-II FPGA family as well as the 300,000 system > gate Virtex™ > XCV300E FPGA in the WebPACK ISE™ tool suite. The free downloadable > software, > previously available only for Xilinx CPLDs, now offers a zero-cost-of-entry > point for designing > with Xilinx FPGAs. Does this mean that it WON'T support the XC4K and Spartan/XL parts? -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d uArticle: 26119
Sounds like we need a "scorecard" matrix for what product/license does what to whom and for how much ! Anyone from X company care to clear the fog away ? We is a confused lot! (actually, I wasn't all that confused until I read this thread. *NOW* I'm confused!) -- Bob Elkind Andy Peters wrote: > > Jerry English wrote: > > > > http://www.xilinx.com/prs_rls/webfpga.html > > Go to the above link for the words from the horses' mouth. > > > > The first part of the press release below. > > SAN JOSE, Calif., October 2, 2000—Xilinx, Inc. (NASDAQ: XLNX) today announced > > full > > support of the entire Spartan®-II FPGA family as well as the 300,000 system > > gate Virtex™ > > XCV300E FPGA in the WebPACK ISE™ tool suite. The free downloadable > > software, > > previously available only for Xilinx CPLDs, now offers a zero-cost-of-entry > > point for designing > > with Xilinx FPGAs. > > Does this mean that it WON'T support the XC4K and Spartan/XL parts? > > -- a > ---------------------------- > Andy Peters > Sr. Electrical Engineer > National Optical Astronomy Observatory > 950 N Cherry Ave > Tucson, AZ 85719 > apeters (at) n o a o [dot] e d uArticle: 26120
Hi, I have a problem with a Virtex-e part that has symptoms very similar to those described in the recent thread "Virtex 'shutdown' phenomenon" initiated by Richard Russell. In my case however, a DLL stops producing a clock after a few seconds to a few minutes. The "locked" output of that DLL remains high, even though the input clock is still present. Other DLLs (running at lower rates) on the same chip continue to produce clocks. This problem doesn't happen if the clock is less than 130MHz, and happens regularly above 150MHz. It seems to happen more often if data signals on the fpga are toggling. Once the DLL stops, the part has to be reloaded to get it to work again. The connections are basically identical to XAPP 132 Figure 9 "Standard DLL Implementation" (except that a DLLHF has been used, and that the reset input of the DLL is connected to gnd). The clock input is HSTL_I, and is clean. The reference voltage is correct and is also clean. Has anyone else seen this phenomenon, or have some idea as to the cause? I can understand that the DLL might lose lock due to noise, but why wouldn't the locked output be deasserted? Thanks, Allan.Article: 26121
Pauric Hennessy wrote: > I'm currently using a virtex e device with bank 2 VCCO= 3.3V and all other banks connected to 2.5V. > I've got LVDS receivers powered off 3.3V connected to banks 4 and 5. 3.3V levels are thus supplied on these banks. > After configuration I see that the 3.3V rail is supplying a portion of the power to the 2.5V rail throuht some unknown path.Currently I'm powering the 3.3V rail and 2.5V rail off a current limited bench supply. Eventually the current drawn from the 2.5v bench supply reaches 0mA and can be removed from the equation- 2.5V being maintained by the 3.3V supply through some unknown path. > With my LVDS bank disabled and all outputs <0.8V then the 2.5V rail is ok. However enabling the 32 outputs of the LVDS sets them to 3.3V and this gets passed on to the LVCMOS2 i/ps on the FPGA. In this scenario the 2.5V rail rises to 2.8V. > The FPGA's are still functioning and performing as designed- but I need to know what is going on here- are my devices damaged? Are there clamp diodes on LVCMOS2 i/ps that allow 3.3V to migrate onto the 2.5V rail!! > Has anyone else haqd a similar experience. > rgds > Pauric I'm not sure if its your problem but there are some VCCO voltage restrictions on banks 2,3. They carry the JTAG & config pins and are, I think, supposed to be connected to 3.3V. Its very difficult to find this info in the data sheet but, if you use non-3.3V standards on these bank, I have seen warning messages in the bank summary section of the .par report file from the router [PAR].Article: 26122
Actually, a scorecard would be a great idea. It should indicate what features and chips are supported with which packages. Just like they release a chart showing the package/die combinations with the IO counts and temp ranges. Unfortunately, the software options are much more confusing than the chips they sell. It would also be nice for them to indicate when they plan to obsolete software well in advance of it happening. They always give you lots of notice of chips being dropped from production. But when was the last time they gave you a "last buy" warning for a line of software? At this point, I count no less than three families of software to support the Xilinx chips. Is that right? Foundation, Foundation ISE, WebPack ISE. Are these three all distinct, or is WebPack just another way to distribute the Foundation ISE tools? Of course the Alliance tool set is really the same as the Foundation with different interfaces for the third party front end tools, right? Either way, I expect that the old line Foundation tool days are numbered. Anyone else have an opinion on that? bob elkind wrote: > > Sounds like we need a "scorecard" matrix for what product/license does what to whom and for how much ! > > Anyone from X company care to clear the fog away ? We is a confused lot! > > (actually, I wasn't all that confused until I read this thread. *NOW* I'm confused!) > > -- Bob Elkind > > Andy Peters wrote: > > > > Jerry English wrote: > > > > > > http://www.xilinx.com/prs_rls/webfpga.html > > > Go to the above link for the words from the horses' mouth. > > > > > > The first part of the press release below. > > > SAN JOSE, Calif., October 2, 2000—Xilinx, Inc. (NASDAQ: XLNX) today announced > > > full > > > support of the entire Spartan®-II FPGA family as well as the 300,000 system > > > gate Virtex™ > > > XCV300E FPGA in the WebPACK ISE™ tool suite. The free downloadable > > > software, > > > previously available only for Xilinx CPLDs, now offers a zero-cost-of-entry > > > point for designing > > > with Xilinx FPGAs. > > > > Does this mean that it WON'T support the XC4K and Spartan/XL parts? > > > > -- a > > ---------------------------- > > Andy Peters > > Sr. Electrical Engineer > > National Optical Astronomy Observatory > > 950 N Cherry Ave > > Tucson, AZ 85719 > > apeters (at) n o a o [dot] e d u -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 26123
Allan, Based on what you've described, I'd be inclined to start with freeze spray on the device to uncover any simple AC performance issue. If cooling the device makes it work, and reheating with a heat gun causes it to fail, then you've got an old-fashioned silicon-too-slow type performance problem. Your comments about the problem becoming more frequent when lots of data signals are toggling (read: when node toggling increases on chip power consumption and heat buildup) suggests that you're close to the speed-power limit of the device. In any case, this is a real quick check which gives unambiguous results. Regardless of which way the test ends up, you've learned something about the problem. -- Bob Elkind Allan Herriman wrote: > > Hi, > > I have a problem with a Virtex-e part that has symptoms very similar to > those described in the recent thread "Virtex 'shutdown' phenomenon" > initiated by Richard Russell. > > In my case however, a DLL stops producing a clock after a few seconds to > a few minutes. The "locked" output of that DLL remains high, even > though the input clock is still present. > Other DLLs (running at lower rates) on the same chip continue to produce > clocks. > > This problem doesn't happen if the clock is less than 130MHz, and > happens regularly above 150MHz. > It seems to happen more often if data signals on the fpga are toggling. > > Once the DLL stops, the part has to be reloaded to get it to work again. > > The connections are basically identical to XAPP 132 Figure 9 "Standard > DLL Implementation" (except that a DLLHF has been used, and that the > reset input of the DLL is connected to gnd). > > The clock input is HSTL_I, and is clean. The reference voltage is > correct and is also clean. > > Has anyone else seen this phenomenon, or have some idea as to the cause? > I can understand that the DLL might lose lock due to noise, but why > wouldn't the locked output be deasserted? > > Thanks, > Allan.Article: 26124
The sales apps probably *do* have a scorecard, but its probably a sales sheet listing which products support which products, running on which platforms, etc. etc. If the sales sheet gets too complicated, the sales/apps guys have a hard time using it (much less explaining it). In this regard, buying the SW might very well be way more complicated and problematic than picking the right device and package and speed grade for your design. sigh... Usually, if your customers are telling you that your product selection is too complicated, then your product selection is too complicated. This sort of thing tends to swing back and forth cyclically. Would anyone in X-land care to alpha-test a software product selection matrix chart to this newsgroup ? Guaranteed we are a friendly and technologically sophisticated test group! (does the smiley face go here?) -- Bob Elkind rickman wrote: > > Actually, a scorecard would be a great idea. It should indicate what > features and chips are supported with which packages. Just like they > release a chart showing the package/die combinations with the IO counts > and temp ranges. Unfortunately, the software options are much more > confusing than the chips they sell. > > It would also be nice for them to indicate when they plan to obsolete > software well in advance of it happening. They always give you lots of > notice of chips being dropped from production. But when was the last > time they gave you a "last buy" warning for a line of software? At this > point, I count no less than three families of software to support the > Xilinx chips. Is that right? Foundation, Foundation ISE, WebPack ISE. > Are these three all distinct, or is WebPack just another way to > distribute the Foundation ISE tools? Of course the Alliance tool set is > really the same as the Foundation with different interfaces for the > third party front end tools, right? > > Either way, I expect that the old line Foundation tool days are > numbered. Anyone else have an opinion on that? >
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