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Threads Starting Nov 1998
12839: 98/11/01: Alexander Sherstuk: Q: 3.3 V regulators suitable for XILINX - ?
12848: 98/11/02: Jan Coombs: Re: Q: 3.3 V regulators suitable for XILINX - ?
12852: 98/11/02: <msimon@tefbbs.com>: Re: Q: 3.3 V regulators suitable for XILINX - ?
12858: 98/11/02: Philip Freidin: Re: Q: 3.3 V regulators suitable for XILINX - ?
12859: 98/11/02: Arrigo Benedetti: Re: Q: 3.3 V regulators suitable for XILINX - ?
12863: 98/11/03: <msimon@tefbbs.com>: Re: Q: 3.3 V regulators suitable for XILINX - ?
12907: 98/11/04: Peter: Re: Q: 3.3 V regulators suitable for XILINX - ?
12913: 98/11/04: Mike Randelzhofer: Re: Q: 3.3 V regulators suitable for XILINX - ?
12941: 98/11/06: Peter: Re: Q: 3.3 V regulators suitable for XILINX - ?
12978: 98/11/09: Peter: Re: Q: 3.3 V regulators suitable for XILINX - ?
12861: 98/11/02: Stefan Ludwig: Re: Q: 3.3 V regulators suitable for XILINX - ?
12985: 98/11/09: Brian Boorman: Re: Q: 3.3 V regulators suitable for XILINX - ?
12844: 98/11/01: Garynlang: ASIC/FPGA designers for US/Canada+work visa
12846: 98/11/01: Michael T. Horne: New Online Seminar in the Qualis Library: "A Strategic Process for System-Level Verification"
12849: 98/11/02: Tetsuo HIRONAKA: [CFP] The Seventh Japanese FPGA/PLD Conf. & Exhibit (July 7-9, 1999)
12853: 98/11/02: <info@lykjxowq.edu>: bestore.com º¸Çè»óÇ°¾È³»
12855: 98/11/02: M: Q: fifo flags
12869: 98/11/03: Paul Walker: Re: Q: fifo flags
12899: 98/11/04: Bill Warner: Re: Q: fifo flags
12905: 98/11/04: <ems@riverside-machines.com.NOSPAM>: Re: Q: fifo flags
12930: 98/11/05: Jonas Thor: Re: Q: fifo flags
12942: 98/11/06: Paul Walker: Re: Q: fifo flags
13164: 98/11/18: M: Re: Q: fifo flags
12856: 98/11/02: <oxpbsxby@hotmail.com>: Music stations live from internet
12860: 98/11/02: Cindy Harris: Concept or Viewlogic viewer?
12918: 98/11/04: CHa5253105: Re: Concept or Viewlogic viewer?
12864: 98/11/03: <leslie.yip@asmpt.com>: Re: USB Joypad vhdl source code
12865: 98/11/02: <jamesantone@if.rmci.net>: Altera bitstream file format
12866: 98/11/03: Jamie Lokier: Re: Altera bitstream file format
12925: 98/11/04: <jamesantone@if.rmci.net>: Re: Altera bitstream file format
12870: 98/11/03: Juergen Baumgartner: Altera MAX+plus II fitting problem
12873: 98/11/03: Michael T. Horne: New additions to the Qualis Library: SoC Verification, RMM review, point tools
12879: 98/11/03: Dan Kuechle: Xilinx bit file format question
12884: 98/11/03: Philip Freidin: Re: Xilinx bit file format question
12893: 98/11/03: Matthew Robinson: Re: Xilinx bit file format question
12880: 98/11/03: Dunstan Power: Xchecker cable NT problem
12901: 98/11/04: Rickman: Re: XILINX NODELAY Attribute
12908: 98/11/04: Peter: Re: XILINX NODELAY Attribute
12904: 98/11/04: Richard Schwarz: XILINX NODELAY Attribute
12906: 98/11/04: Richard Schwarz: Need FPGA/VHDL designers in Balt/Washington area
12909: 98/11/04: Gabriel Rusaneanu: Re: Need FPGA/VHDL designers in Balt/Washington area
12929: 98/11/05: G Henry Yogendran: Free I2C model
12988: 98/11/09: Brian Boorman: Re: Free I2C model
12937: 98/11/05: Blake Nelson: FPGA Developers Available
12938: 98/11/05: <yygcdyla@mailcity.com>: Midi archive
12943: 98/11/06: Le mer Michel: clock doubler
12944: 98/11/06: Yves Tchapda: Re: Clock Doubler
12947: 98/11/06: Le mer Michel: Re: Clock Doubler
12962: 98/11/08: <ems@riverside-machines.com.NOSPAM>: Re: Clock Doubler
12946: 98/11/06: Pacem: Intelligent VHDL editor for Windows
12952: 98/11/06: jerry english: FPGA HDL tool benchmarks
12966: 98/11/08: Stuart Clubb: Re: FPGA HDL tool benchmarks
12953: 98/11/06: Greg Watson: aLTERA 10KA Series PCI question
12955: 98/11/07: JOHN KENNEDY: How to determine macro size in Xilinx Foundation?
13007: 98/11/10: Edward Moore: Re: How to determine macro size in Xilinx Foundation?
12960: 98/11/07: alpha: FPGA VGA interface
12967: 98/11/08: Farhad Abdolian: Re: FPGA VGA interface
12969: 98/11/08: alpha: Re: FPGA VGA interface
12975: 98/11/09: Roman Pollak: Re: FPGA VGA interface
13016: 98/11/11: Ray Andraka: Re: FPGA VGA interface
12981: 98/11/09: Herbert Kleebauer: Re: FPGA VGA interface
12996: 98/11/10: Jonathan Bromley: Re: FPGA VGA interface
12998: 98/11/10: Matthias Sauer: Re: FPGA VGA interface
12970: 98/11/09: <mcintosh@vima.austin.tx.us>: TE16 ENV1
12983: 98/11/09: <mcintosh@vima.austin.tx.us>: TE16 ENV1
12971: 98/11/08: ejob: employment @ lucent <nj>
12972: 98/11/08: Joel Kolstad: Why doesn't Xilinx's simulator work?
12989: 98/11/09: Ray Andraka: Re: Why doesn't Xilinx's simulator work?
12995: 98/11/10: <jdehaven@my-dejanews.com>: Re: Why doesn't Xilinx's simulator work?
13226: 98/11/20: Bruce Reid: Re: Why doesn't Xilinx's simulator work?
13502: 98/12/06: <khartman@conwin.com>: Re: Why doesn't Xilinx's simulator work?
13574: 98/12/10: Grzegorz Apczynski: Re: Why doesn't Xilinx's simulator work?
13709: 98/12/19: NHartl: Re: Why doesn't Xilinx's simulator work?
12973: 98/11/09: John Kennedy: help xc3000 series
12980: 98/11/09: <timolmst@cyberramp.net>: Re: help xc3000 series
12974: 98/11/09: Utku Ozcan: placement&routing problems
12990: 98/11/09: Ray Andraka: Re: placement&routing problems
13006: 98/11/10: Edward Moore: Re: placement&routing problems
13026: 98/11/12: <randraka@my-dejanews.com>: Re: placement&routing problems
13042: 98/11/12: Philip Freidin: Re: placement&routing problems
13047: 98/11/12: Phil Hays: Re: placement&routing problems
13054: 98/11/13: Ray Andraka: Re: placement&routing problems
13050: 98/11/13: Jonas Thor: Re: placement&routing problems
13076: 98/11/14: <ems@riverside-machines.com.NOSPAM>: Re: placement&routing problems
13154: 98/11/17: <ems@riverside-machines.com.NOSPAM>: Re: placement&routing problems
13108: 98/11/16: Utku Ozcan: Re: placement&routing problems
13068: 98/11/14: Edward Moore: Re: placement&routing problems
13079: 98/11/15: Simon Bacon: Re: placement&routing problems
13083: 98/11/15: <ems@riverside-machines.com.NOSPAM>: Re: placement&routing problems
13071: 98/11/14: Edward Moore: Re: placement&routing problems
13072: 98/11/14: Edward Moore: Re: placement&routing problems
12976: 98/11/09: paval: HELP MAX PLUS v9.01
12977: 98/11/09: wpauwels: design multipier?
12991: 98/11/09: Ray Andraka: Re: design multipier?
12979: 98/11/09: <pshimizu@fa2.so-net.ne.jp>: Synthsizable processor code
12982: 98/11/09: John L. Smith: Xilinx Floorplanner Support for Virtex?
12997: 98/11/10: Jonas Thor: Reporting asynchronous loops in Foundation?
13001: 98/11/10: Steven K. Knapp: Re: free Xilinx developer tools
13002: 98/11/10: Andreas Doering: hard macros design flow for XILINX Foundation Express
13019: 98/11/11: Todd Kline: Re: hard macros design flow for XILINX Foundation Express
13060: 98/11/13: Fredj Rouatbi: Re: hard macros design flow for XILINX Foundation Express
13003: 98/11/10: Edward Wallington: Affordable boundary scan (JTAG) interconnect testing software any
13049: 98/11/13: Andreas Doering: Re: Affordable boundary scan (JTAG) interconnect testing software anybody?
13052: 98/11/13: Jonathan Bromley: Re: Affordable boundary scan (JTAG) interconnect testing software any
13057: 98/11/13: Ray Andraka: Re: Affordable boundary scan (JTAG) interconnect testing software any
13004: 98/11/10: Jaroslaw Cichorski Jr.: Problem with the ABEL to Macro convertion in XILINX FB1.3
13028: 98/11/12: MZurlo4054: Re: Problem with the ABEL to Macro convertion in XILINX FB1.3
13032: 98/11/12: Jaroslaw Cichorski Jr.: Re: Problem with the ABEL to Macro convertion in XILINX FB1.3
13067: 98/11/14: Manfred Kraus: Re: Problem with the ABEL to Macro convertion in XILINX FB1.3
13005: 98/11/10: F. Arnold: free Xilinx developer tools
13008: 98/11/10: Stephen Swearingen: Power Consumption
13009: 98/11/10: Stephen Swearingen: CCLK on Spartan
13011: 98/11/11: Philip Freidin: Re: CCLK on Spartan
13013: 98/11/11: Allan Herriman: Re: CCLK on Spartan
13014: 98/11/11: Mike Randelzhofer: Re: CCLK on Spartan
13010: 98/11/11: David Ward: Make your own Printed Circuit Boards. Press-n-Peel in Europe
13012: 98/11/11: Leprechaun: connecting 2 FPGA together
13023: 98/11/11: Todd Kline: Re: connecting 2 FPGA together
13097: 98/11/16: Le mer Michel: Re: connecting 2 FPGA together
13284: 98/11/24: Leprechaun: Re: connecting 2 FPGA together
13015: 98/11/11: ovilup: Example of clock circuit needed !
13098: 98/11/16: Le mer Michel: Re: Example of clock circuit needed !
13103: 98/11/16: <msimon@tefbbs.com>: Re: Example of clock circuit needed !
13104: 98/11/16: Brian Boorman: Re: Example of clock circuit needed !
13129: 98/11/17: Thomas A. Coonan: Re: Example of clock circuit needed !
13128: 98/11/16: Ray Andraka: Re: Example of clock circuit needed !
13149: 98/11/17: Rickman: Re: Example of clock circuit needed !
13209: 98/11/20: <leslie.yip@asmpt.com>: Re: Example of clock circuit needed !
13351: 98/11/30: craig domeny: Re: Example of clock circuit needed !
13017: 98/11/11: ovilup: Looking for a good documentation on FPGA
13070: 98/11/14: Steven K. Knapp: Re: Looking for a good documentation on FPGA
13109: 98/11/16: Utku Ozcan: Re: Looking for a good documentation on FPGA
13112: 98/11/16: Jer-Sheng Chen: Re: Looking for a good documentation on FPGA
13148: 98/11/17: Steven K. Knapp: Re: Looking for a good documentation on FPGA
13186: 98/11/19: <leslie.yip@asmpt.com>: Re: Looking for a good documentation on FPGA
13348: 98/11/29: John Harrop: Re: Looking for a good documentation on FPGA
13349: 98/11/29: John Harrop: Re: Looking for a good documentation on FPGA
13018: 98/11/11: johnd: Test - please ignore!
13020: 98/11/11: johnd: Test - please ignore!
13021: 98/11/11: John Davis: Test - Ignore2
13022: 98/11/11: <johnd1489@my-dejanews.com>: Test - Ignore
13036: 98/11/12: John Davis: Re: Test - Ignore
13037: 98/11/12: John Davis: Re: Test - Ignore
13024: 98/11/11: <michael@webuyparts.com>: FS: XC3142A5PC84C
13025: 98/11/11: johnd: Test - please ignore!
13027: 98/11/12: Chris Eilbeck: DES in VHDL?
13029: 98/11/11: Rickman: Re: DES in VHDL?
13043: 98/11/12: Chris Eilbeck: Re: DES in VHDL?
13044: 98/11/13: Vincenzo Liguori: Re: DES in VHDL?
13034: 98/11/12: Brian Gladman: Re: DES in VHDL?
13039: 98/11/12: <ssimpson@hertreg.ac.uk>: Re: DES in VHDL?
13035: 98/11/12: Nicko van Someren: Re: DES in VHDL?
13038: 98/11/12: Peter Gutmann: Re: DES in VHDL?
13064: 98/11/14: Christof Paar: Re: DES in VHDL?
13087: 98/11/15: Christof Paar: Re: DES in VHDL?
13143: 98/11/17: Andrew Haley: Re: DES in VHDL?
13202: 98/11/19: Mathias Schmalisch: Re: DES in VHDL?
13030: 98/11/12: GSB: Help with identifying possible programmable logic chip
13092: 98/11/15: GSB: Re: Help with identifying possible programmable logic chip
13094: 98/11/16: Philip Freidin: Re: Help with identifying possible programmable logic chip
13031: 98/11/12: John Huang: WorkView office Library files need
13040: 98/11/12: Alex Protasiewicz: Re: WorkView office Library files need
13048: 98/11/13: John Huang: Re: WorkView office Library files need
13081: 98/11/15: Austin Franklin: Re: WorkView office Library files need
13082: 98/11/15: Austin Franklin: Re: WorkView office Library files need
13055: 98/11/13: Chris Rottner: Re: WorkView office Library files need
13033: 98/11/12: Loic Lagadec: FPGAs evolution
13099: 98/11/16: Le mer Michel: Re: FPGAs evolution
13041: 98/11/12: Zahir Parpia: ZEN News, Nov. 10, 1998
13045: 98/11/13: iccra: Help] Altera FloorPlan Editor
13376: 98/12/01: Calvin Lee: Re: Help] Altera FloorPlan Editor
13046: 98/11/13: <leslie.yip@asmpt.com>: Re: VHDL project
13053: 98/11/13: Ray Andraka: Re: VHDL project
13095: 98/11/16: <smeiyapp@my-dejanews.com>: Re: VHDL project
13274: 98/11/23: Mohsin Riaz: Re: VHDL project
13279: 98/11/23: Ray Andraka: Re: VHDL project
13051: 98/11/13: Dominic Camus: SIS under Linux
13056: 98/11/13: Arnold Beland: Alternative to EPM5128 OTP
13058: 98/11/13: Steve: Re: Alternative to EPM5128 OTP
13061: 98/11/13: Arnold Beland: Re: Alternative to EPM5128 OTP
13059: 98/11/13: Fredj Rouatbi: Xilinx Core generator
13063: 98/11/13: Fredj Rouatbi: Re: Xilinx Core generator
13062: 98/11/13: <p52mofej@uco.es>: Board for FPGA ?
13069: 98/11/14: Steven K. Knapp: Re: Board for FPGA ?
13075: 98/11/14: APS: Re: Board for FPGA ?
13088: 98/11/15: <msimon@tefbbs.com>: Re: Board for FPGA ?
13089: 98/11/15: Steven J. Ackerman: Re: Board for FPGA ?
13126: 98/11/16: Jeff Vallier: Re: Board for FPGA ?
13065: 98/11/14: Jacob W Janovetz: Xilinx COREgen and Leonardo troubles...
13100: 98/11/16: Le mer Michel: Re: Xilinx COREgen and Leonardo troubles...
13101: 98/11/16: Mark Snook: Re: Xilinx COREgen and Leonardo troubles...
13105: 98/11/16: Brian Boorman: Re: Xilinx COREgen and Leonardo troubles...
13107: 98/11/16: Jacob W Janovetz: Re: Xilinx COREgen and Leonardo troubles...
13106: 98/11/16: Graeme Durant: Re: Xilinx COREgen and Leonardo troubles...
13167: 98/11/18: David Bishop: Re: Xilinx COREgen and Leonardo troubles...
13066: 98/11/14: John Huang: Help! ViewSynther Error
13073: 98/11/14: <Hlebasko@t-online.de>: Low Cost FPGA Development Tools
13124: 98/11/16: Jeff Vallier: Re: Low Cost FPGA Development Tools
13147: 98/11/17: Steven K. Knapp: Re: Low Cost FPGA Development Tools
13232: 98/11/20: <russv44@my-dejanews.com>: Re: Low Cost FPGA Development Tools
13077: 98/11/14: glenn kubota: Xilinx Foundation vs. Altera Max Plus II
13660: 98/12/16: Ken Coffman: Re: Xilinx Foundation vs. Altera Max Plus II
13686: 98/12/18: David Hawke: Re: Xilinx Foundation vs. Altera Max Plus II
13688: 98/12/18: Ray Andraka: Re: Xilinx Foundation vs. Altera Max Plus II
13690: 98/12/18: Seftie: Re: Xilinx Foundation vs. Altera Max Plus II
13700: 98/12/18: bob elkind: Re: Xilinx Foundation vs. Altera Max Plus II
13744: 98/12/21: Ken Coffman: Re: Xilinx Foundation vs. Altera Max Plus II
13745: 98/12/21: bob elkind: Re: Xilinx Foundation vs. Altera Max Plus II
13078: 98/11/14: glenn kubota: Xilinx Foundation vs. Altera Max Plus
13111: 98/11/16: Steve: Re: Xilinx Foundation vs. Altera Max Plus
13080: 98/11/15: noam: This is the Subject line !
13084: 98/11/15: Elron Osafat: Modifying Disk serial number in boot sector....anyone have any problems with it?
13086: 98/11/15: Rickman: Re: Modifying Disk serial number in boot sector....anyone have any problems with it?
13119: 98/11/16: Austin Franklin: Re: Modifying Disk serial number in boot sector....anyone have any problems with it?
13135: 98/11/17: Hans: Re: Modifying Disk serial number in boot sector....anyone have any problems with it?
13138: 98/11/17: Peter: Re: Modifying Disk serial number in boot sector....anyone have any problems with it?
13198: 98/11/19: Don Husby: Re: Modifying Disk serial number in boot sector....anyone have any problems with it?
13085: 98/11/16: John Huang: Help, Workview error!
13090: 98/11/16: noam: Sorry
13091: 98/11/15: Michael T. Horne: New in the Qualis Library: SoC Verification Online Seminar, Behavioral Synthesis hints, more
13093: 98/11/16: Leprechaun: programming EPROM
13096: 98/11/16: <shailbains007@my-dejanews.com>: CPUs: Big Endianness vs Small Endianness
13161: 98/11/18: Bryan Hackney: Re: CPUs: Big Endianness vs Small Endianness
13251: 98/11/21: Tim Shoppa: Re: CPUs: Big Endianness vs Small Endianness
13252: 98/11/21: Lasse Langwadt Christensen: Re: CPUs: Big Endianness vs Small Endianness
13166: 98/11/18: Wade D. Peterson: Re: CPUs: Big Endianness vs Small Endianness
13102: 98/11/16: Yves Tchapda: Re: Big-Endian vs Little-Endian
13114: 98/11/16: <shailbains007@my-dejanews.com>: Re: Big-Endian vs Little-Endian
13116: 98/11/16: muzo: Re: Big-Endian vs Little-Endian
13117: 98/11/16: Russell May: Re: Big-Endian vs Little-Endian
13118: 98/11/16: Russell May: Re: Big-Endian vs Little-Endian
13152: 98/11/17: <tronsmith@my-dejanews.com>: Re: Big-Endian vs Little-Endian
13127: 98/11/17: Zoltan Kocsi: Re: Big-Endian vs Little-Endian
13220: 98/11/20: <d.cary@ieee.org>: Re: Big-Endian vs Little-Endian
13458: 98/12/03: Brad Taylor: Re: Big-Endian vs Little-Endian
13131: 98/11/16: Kalyan Gokhale: Re: Big-Endian vs Little-Endian
13184: 98/11/19: glen herrmannsfeldt: Re: Big-Endian vs Little-Endian
13142: 98/11/17: Brian Drummond: Re: Big-Endian vs Little-Endian
13271: 98/11/23: David Wragg: Re: Big-Endian vs Little-Endian
13278: 98/11/23: Lasse Langwadt Christensen: Re: Big-Endian vs Little-Endian
13301: 98/11/24: glen herrmannsfeldt: Re: Big-Endian vs Little-Endian
13242: 98/11/21: Alex Leyn: Re: Big-Endian vs Little-Endian
13250: 98/11/21: muzo: Re: Big-Endian vs Little-Endian
13110: 98/11/16: Sebastien Erard: Xilinx 4k programming
13115: 98/11/16: Philip Freidin: Re: Xilinx 4k programming
13162: 98/11/18: Sebastien Erard: Re: Xilinx 4k programming, the solution
13137: 98/11/17: Peter: Re: Xilinx 4k programming
13113: 98/11/16: Arnold Beland: Is there an alternative to Altera EPM5128 OTP?
13136: 98/11/17: "Håkan Pettersson": Is there an alternative to Altera EPM5128 OTP?
13141: 98/11/17: Arnold Beland: Re: Is there an alternative to Altera EPM5128 OTP?
13146: 98/11/17: Steve: Re: Is there an alternative to Altera EPM5128 OTP?
13156: 98/11/17: Arnold Beland: Re: Is there an alternative to Altera EPM5128 OTP?
13159: 98/11/17: Ray Andraka: Re: Is there an alternative to Altera EPM5128 OTP?
13170: 98/11/18: Arnold Beland: Re: Is there an alternative to Altera EPM5128 OTP?
13120: 98/11/16: jai: newbie question about timing
13123: 98/11/16: Ken Coffman: Re: newbie question about timing
13130: 98/11/16: Ray Andraka: Re: newbie question about timing
13140: 98/11/17: Peter: Re: newbie question about timing
13122: 98/11/16: DouglasUT: CE Student Seeks Research Pointers
13125: 98/11/17: James LaLone: Synthesizeablel fifo
13145: 98/11/17: Rene Becker: Re: Synthesizeablel fifo
13151: 98/11/17: <smeiyapp@my-dejanews.com>: Re: Synthesizeablel fifo
13150: 98/11/17: Jamie Lokier: Re: Synthesizeablel fifo
13160: 98/11/18: Johnny Smooth: Re: Synthesizeablel fifo
13165: 98/11/18: Ray Andraka: Re: Synthesizeablel fifo
13188: 98/11/18: Johnny Smooth: Re: Synthesizeablel fifo
13190: 98/11/18: Ray Andraka: Re: Synthesizeablel fifo
13204: 98/11/19: Rickman: Re: Synthesizeablel fifo
13212: 98/11/20: Ray Andraka: Re: Synthesizeablel fifo
13234: 98/11/20: Rickman: Re: Synthesizeablel fifo
13241: 98/11/21: Ray Andraka: Re: Synthesizeablel fifo
13261: 98/11/22: Johnny Smooth: Re: Synthesizeablel fifo
13267: 98/11/22: Ray Andraka: Re: Synthesizeablel fifo
13223: 98/11/20: Jamie Lokier: Re: Synthesizeablel fifo
13235: 98/11/20: Rickman: Re: Synthesizeablel fifo
13260: 98/11/22: Jamie Lokier: Re: Synthesizeablel fifo
13270: 98/11/22: Rickman: Re: Synthesizeablel fifo
13282: 98/11/23: Ray Andraka: Re: Synthesizeablel fifo
13217: 98/11/20: <Goran.Bilski@enator.se>: Re: Synthesizeablel fifo
13168: 98/11/18: David Bishop: Re: Synthesizeablel fifo
13187: 98/11/19: James LaLone: Re: Synthesizeablel fifo
13210: 98/11/20: <leslie.yip@asmpt.com>: Re: Synthesizeablel fifo
13132: 98/11/16: The Bearded Dave: Re: DES in VHDL
13139: 98/11/17: Peter: Re: DES in VHDL
13153: 98/11/17: Chris Eilbeck: Re: DES in VHDL
13133: 98/11/17: msj: Motorola MPA Latchup?
13134: 98/11/16: Arrigo Benedetti: Xilinx Virtex and ZBT SRAM
13144: 98/11/17: Farhad Abdolian: Atmel AT17C010?
13174: 98/11/18: Andrew Cannon: Re: Atmel AT17C010?
13175: 98/11/18: Farhad Abdolian: Re: Atmel AT17C010?
13176: 98/11/18: Andy Peters: Re: Atmel AT17C010?
13183: 98/11/18: David Tang: Re: Atmel AT17C010?
13157: 98/11/18: John Huang: Help for WorkView Office
13185: 98/11/19: <bthiruma@my-dejanews.com>: Re: Help for WorkView Office
13158: 98/11/18: John Huang: Help for WorkView office
13163: 98/11/18: Darren Koh: which programing
13171: 98/11/18: Rickman: Re: which programing
13173: 98/11/18: Joe Gallegos: Re: which programing
13169: 98/11/18: Rolavine: Abel limitations in xilinx foundation base?
13197: 98/11/19: <timolmst@cyberramp.net>: Re: Abel limitations in xilinx foundation base?
13172: 98/11/18: <eugene_huh@yahoo.com>: Configuring using Parallel port
13208: 98/11/19: "Karl Yung": Configuring using Parallel port
13177: 98/11/18: Utku Ozcan: XNF issue
13178: 98/11/19: Erik de Castro Lopo: Re: XNF issue
13254: 98/11/22: Fredj Rouatbi: Re: XNF issue
13181: 98/11/18: Ray Andraka: Re: XNF issue
13203: 98/11/19: Le mer Michel: Re: XNF issue
13230: 98/11/20: Utku Ozcan: Re: XNF issue
13179: 98/11/18: ds12: VHDL testbench supporting reconfiguration?
13201: 98/11/19: mj: Re: VHDL testbench supporting reconfiguration?
13180: 98/11/18: Chris Eilbeck: Serial EPROMs
13182: 98/11/18: Ray Andraka: Re: Serial EPROMs
13215: 98/11/20: <jdehaven@my-dejanews.com>: Re: Serial EPROMs
13189: 98/11/19: Anthony Ellis - LogicWorks: VHDL Block Capture
13193: 98/11/19: Steve Bird: Re: VHDL Block Capture
13191: 98/11/19: <sandcl@my-dejanews.com>: Need VLSI usenet group
13192: 98/11/19: Alistair McEwan: Content Addressable Memorys
13194: 98/11/19: "Håkan Pettersson": Content Addressable Memorys
13196: 98/11/19: Brian Drummond: Re: Content Addressable Memorys
13200: 98/11/19: Marc Delvaux: Re: Content Addressable Memorys
13195: 98/11/19: Stefan Derhaschnig: Combination of Xilinx FPGA and TMS320c40 or c60
13205: 98/11/19: Austin Franklin: Xilinx 5.2/6 tools v M1.5 tools for an XC4013E part.....
13211: 98/11/20: David Decker: Re: Xilinx 5.2/6 tools v M1.5 tools for an XC4013E part.....
13213: 98/11/20: Ray Andraka: Re: Xilinx 5.2/6 tools v M1.5 tools for an XC4013E part.....
13221: 98/11/20: peterc: Re: Xilinx 5.2/6 tools v M1.5 tools for an XC4013E part.....
13225: 98/11/20: Ray Andraka: Re: Xilinx 5.2/6 tools v M1.5 tools for an XC4013E part.....
13332: 98/11/25: Jan Gray: Re: Xilinx 5.2/6 tools v M1.5 tools for an XC4013E part.....
13360: 98/11/30: Austin Franklin: Re: Xilinx 5.2/6 tools v M1.5 tools for an XC4013E part.....
13368: 98/11/30: Ray Andraka: Re: Xilinx 5.2/6 tools v M1.5 tools for an XC4013E part.....
13206: 98/11/19: John J. Hovey: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
13207: 98/11/19: Austin Franklin: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
13245: 98/11/21: john hovey: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
13248: 98/11/21: Brian Drummond: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
13263: 98/11/22: Ray Andraka: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
13214: 98/11/20: Ray Andraka: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
13216: 98/11/20: rjs: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
13227: 98/11/20: Fredj Rouatbi: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
13229: 98/11/20: Austin Franklin: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
13233: 98/11/20: rjs: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
13236: 98/11/20: Austin Franklin: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
13238: 98/11/21: rjs: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
13239: 98/11/21: Austin Franklin: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
13243: 98/11/21: rjs: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
13240: 98/11/21: Ray Andraka: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
13246: 98/11/21: john hovey: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
13253: 98/11/22: Fredj Rouatbi: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
13255: 98/11/22: Rickman: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
13258: 98/11/22: Fredj Rouatbi: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
13269: 98/11/22: john hovey: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
13219: 98/11/20: gs: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
13222: 98/11/20: peterc: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
13224: 98/11/20: Steve: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
13247: 98/11/21: john hovey: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
13231: 98/11/20: Ken Coffman: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
13244: 98/11/21: john hovey: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
13228: 98/11/20: Chris Stephens: UK Microprocessor H/W & S/W Developers - read on
13237: 98/11/20: <kzietlow@my-dejanews.com>: functional simulation w/ Alliance???
13249: 98/11/21: Austin Franklin: Digital Millennium Copyright Act of 1998 (S.2037)
13256: 98/11/22: <msimon@tefbbs.com>: Combining busses Xilinx
13257: 98/11/22: Fredj Rouatbi: Re: Combining busses Xilinx
13264: 98/11/22: <msimon@tefbbs.com>: Re: Combining busses Xilinx
13275: 98/11/23: Dave Decker: Re: Combining busses Xilinx
13280: 98/11/23: Ray Andraka: Re: Combining busses Xilinx
13327: 98/11/25: Jan Gray: Re: Combining busses Xilinx
13262: 98/11/22: Brian Boorman: Re: Combining busses Xilinx
13265: 98/11/22: <msimon@tefbbs.com>: Re: Combining busses Xilinx
13266: 98/11/22: Ray Andraka: Re: Combining busses Xilinx
13288: 98/11/24: Jonas Thor: Re: Combining busses Xilinx
13345: 98/11/27: Eric Pearson: Re: Combining busses Xilinx
13259: 98/11/22: Scott Paul Johnston: NEW ENGINEERING PAGE: Please Visit
13268: 98/11/22: The Bearded Dave: RE: DES in VHDL
13272: 98/11/23: Romanovsky Sergey: Microelectronic firm would like to set prolonged contacts
13273: 98/11/23: Austin Franklin: Anyone use XChecker cable with 3.3V Xilinx parts?
13281: 98/11/23: Ray Andraka: Re: Anyone use XChecker cable with 3.3V Xilinx parts?
13283: 98/11/24: Austin Franklin: Re: Anyone use XChecker cable with 3.3V Xilinx parts?
13276: 98/11/23: Jacob W Janovetz: Xilinx XL vs XLA.
13277: 98/11/23: Guest: FPGA vs. CPLD
13292: 98/11/24: Steven K. Knapp: Re: FPGA vs. CPLD
13285: 98/11/24: jamie morken: Foundation 1.4 error message
13286: 98/11/24: R A Felton: Report problems
13291: 98/11/24: Steven K. Knapp: Re: Report problems
13287: 98/11/24: Andreas Jungmaier: Actel FPGA libraries for Synopsys
13295: 98/11/24: rich katz: Re: Actel FPGA libraries for Synopsys
13290: 98/11/24: Info: Wafer mapping software
13293: 98/11/24: Kamal Patel: daisy chain help!!!!
13304: 98/11/25: Bob Sefton: Re: daisy chain help!!!!
13325: 98/11/25: gs: Re: daisy chain help!!!!
13294: 98/11/24: Paul S Secinaro: Integer divide algorithms
13296: 98/11/24: Lorenzo Di Gregorio: Re: Integer divide algorithms
13299: 98/11/24: Mike Albaugh: Re: Integer divide algorithms
13300: 98/11/24: Ray Andraka: Re: Integer divide algorithms
13316: 98/11/25: Lorenzo Di Gregorio: Re: Integer divide algorithms
13298: 98/11/24: Lasse Langwadt Christensen: Re: Integer divide algorithms
13297: 98/11/24: Vito P. Errico: Add-in board with FPGA Secondary Processor
13312: 98/11/25: Richard Schwarz: Re: Add-in board with FPGA Secondary Processor
13315: 98/11/25: Ray Andraka: Re: Add-in board with FPGA Secondary Processor
13568: 98/12/09: Steve Casselman: Re: Add-in board with FPGA Secondary Processor
13337: 98/11/26: Craig Slorach: Re: Add-in board with FPGA Secondary Processor
13302: 98/11/24: Steve: Which parts are fastest for 3-state enables?
13303: 98/11/25: Bob Sefton: Re: Which parts are fastest for 3-state enables?
13305: 98/11/25: Mikeandmax: Re: Which parts are fastest for 3-state enables?
13318: 98/11/25: Steve: Re: Which parts are fastest for 3-state enables?
13308: 98/11/25: Francisco José Blasco Abril: Re: Which parts are fastest for 3-state enables?
13317: 98/11/25: Steve: Re: Which parts are fastest for 3-state enables?
13335: 98/11/26: Francisco José Blasco Abril: Re: Which parts are fastest for 3-state enables?
13343: 98/11/27: D.H. Chung: Re: Which parts are fastest for 3-state enables?
13309: 98/11/25: Francisco José Blasco Abril: Re: Which parts are fastest for 3-state enables?
13326: 98/11/25: gs: Re: Which parts are fastest for 3-state enables?
13331: 98/11/26: Louis Zhang: Re: Which parts are fastest for 3-state enables?
13329: 98/11/25: Rickman: Re: Which parts are fastest for 3-state enables?
13339: 98/11/26: Steve: Re: Which parts are fastest for 3-state enables?
13340: 98/11/26: Bob Sefton: Re: Which parts are fastest for 3-state enables?
13341: 98/11/26: Steve: Re: Which parts are fastest for 3-state enables?
13395: 98/11/30: Daniel K. Elftmann: Re: Which parts are fastest for 3-state enables?
13396: 98/11/30: rk: Re: Which parts are fastest for 3-state enables?
13407: 98/12/01: bob elkind: Re: Which parts are fastest for 3-state enables?
13462: 98/12/03: gs: Re: Which parts are fastest for 3-state enables?
13464: 98/12/03: Peter Alfke: Re: Which parts are fastest for 3-state enables?
13467: 98/12/03: rk: Re: Which parts are fastest for 3-state enables?
13485: 98/12/05: Peter: Re: Which parts are fastest for 3-state enables?
13508: 98/12/07: Hal Murray: Re: Which parts are fastest for 3-state enables?
13504: 98/12/06: Daniel K. Elftmann: Re: Which parts are fastest for 3-state enables?
13401: 98/12/01: <cartoffice@mail3.clio.it>: Re: Which parts are fastest for 3-state enables?
13306: 98/11/25: Yann Guidon: VHDL->boolean equation
13324: 98/11/25: gs: Re: VHDL->boolean equation
13307: 98/11/25: Jo Depreitere: Foundation Schematic Entry
13310: 98/11/25: <bjong@my-dejanews.com>: PCI for Xilinx Virtex
13319: 98/11/25: Francisco José Blasco Abril: Re: PCI for Xilinx Virtex
13311: 98/11/25: Axel Dietrich: Xilinx6216 cal->edn conversion?
13313: 98/11/25: Richard Schwarz: Free VHDL/FPGA Newsletter released q498
13314: 98/11/25: Raanan: Synchronous SRAM design wanted
13323: 98/11/25: gs: Re: Synchronous SRAM design wanted
13333: 98/11/26: Le mer Michel: Re: Synchronous SRAM design wanted
13320: 98/11/25: Gang Li: AD: Reading Secured Devices
13321: 98/11/25: <pshimizu@fa2.so-net.ne.jp>: Open source Java processor
13322: 98/11/25: Martin Duffy: DynaChip
13328: 98/11/26: Peter Graeme Cobb: DynaChi -> Have you used there devices?
13330: 98/11/26: jamie morken: parallel cable III -> Spartan
13475: 98/12/04: Bruce Reid: Re: parallel cable III -> Spartan
13334: 98/11/26: Richard Cant: Detailed Configuration Format
13336: 98/11/26: Craig Slorach: Re: Detailed Configuration Format
13338: 98/11/26: Carla Sewell: Exciting Job Opportunities
13342: 98/11/27: Graeme Robertson: Actel PCI Cores
13344: 98/11/27: wdmun: Bus Conflict
13346: 98/11/28: <rswolf@my-dejanews.com>: DynaText **!?!?, One Solution
13347: 98/11/29: Anonymous: Will XILINX survive?
13350: 98/11/30: Gavin Melville: Re: Will XILINX survive?
13352: 98/11/29: alpha: Re: Will XILINX survive?
13354: 98/11/30: Rickman: Re: Will XILINX survive?
13361: 98/11/30: Bob Sefton: Re: Will XILINX survive?
13371: 98/11/30: Austin Franklin: Re: Will XILINX survive?
13374: 98/11/30: Bob Sefton: Re: Will XILINX survive?
13379: 98/11/30: Austin Franklin: Re: Will XILINX survive?
13381: 98/11/30: Bob Sefton: Re: Will XILINX survive?
13385: 98/11/30: Don Husby: Re: Will XILINX survive?
13366: 98/11/30: Peter: Re: Will XILINX survive?
13372: 98/11/30: Austin Franklin: Re: Will XILINX survive?
13384: 98/11/30: Don Husby: Re: Will XILINX survive?
13388: 98/11/30: Austin Franklin: Re: Will XILINX survive?
13411: 98/12/01: Stuart Clubb: Re: Will XILINX survive?
13489: 98/12/05: Rickman: A short digression...
13492: 98/12/05: Ray Andraka: Re: A short digression...
13496: 98/12/06: Austin Franklin: Re: A short digression...
13499: 98/12/06: Ray Andraka: Re: A short digression...
13500: 98/12/06: Rickman: Re: A short digression...
13510: 98/12/07: Ray Andraka: Re: A short digression...
13513: 98/12/07: Austin Franklin: Re: A short digression...
13529: 98/12/08: Philip Freidin: Re: A short digression...
13555: 98/12/09: Rickman: Re: A short digression...
13571: 98/12/10: Austin Franklin: Re: A short digression...
13575: 98/12/10: rk: Re: A short digression...
13578: 98/12/10: Todd Kline: Re: A short digression...
13585: 98/12/10: Andy Peters: Re: A short digression...
13577: 98/12/10: Peter: Re: A short digression...
13582: 98/12/10: Austin Franklin: Re: A short digression...
13583: 98/12/10: Ray Andraka: Re: A short digression...
13584: 98/12/10: rich katz: Re: A short digression...
13424: 98/12/02: Brian Boorman: Re: Will XILINX survive?
13430: 98/12/02: Austin Franklin: Re: Will XILINX survive?
13377: 98/11/30: Wade D. Peterson: Re: Will XILINX survive?
13380: 98/11/30: Austin Franklin: Re: Will XILINX survive?
13382: 98/11/30: Wade D. Peterson: Re: Will XILINX survive?
13397: 98/11/30: Mike & Jen: Re: Will XILINX survive?
13410: 98/12/01: Wade D. Peterson: Re: Will XILINX survive?
13413: 98/12/01: Peter Alfke: Re: Will XILINX survive?
13453: 98/12/03: Richard Schwarz: Re: Will XILINX survive?
13454: 98/12/03: Peter: Re: Will XILINX survive?
13457: 98/12/03: Peter Alfke: Re: Will XILINX survive?
13459: 98/12/03: Austin Franklin: Re: Will XILINX survive?
13461: 98/12/03: Peter Alfke: Re: Will XILINX survive?
13512: 98/12/07: Austin Franklin: Re: Will XILINX survive?
13486: 98/12/05: Peter: Re: Will XILINX survive?
13490: 98/12/05: Rickman: Re: Will XILINX survive?
13523: 98/12/07: Richard Dungan: Re: Will XILINX survive?
13408: 98/12/01: Wade D. Peterson: Re: Will XILINX survive?
13451: 98/12/03: Richard Schwarz: Re: Will XILINX survive?
13390: 98/11/30: Tim Tyler: Re: Will XILINX survive?
13393: 98/11/30: Froilan P Montenegro: Re: Will XILINX survive?
13353: 98/11/30: Bob Sefton: Re: Will XILINX survive?
13387: 98/11/30: Tim Tyler: Re: Will XILINX survive?
13399: 98/12/01: Victor the Cleaner: Re: Will XILINX survive?
13402: 98/12/01: Tim Tyler: Re: Will XILINX survive?
13363: 98/11/30: tom curran: Re: Will XILINX survive?
13364: 98/11/30: Don Husby: Re: Will XILINX survive?
13365: 98/11/30: Peter: Re: Will XILINX survive?
13386: 98/11/30: Simon: Re: Will XILINX survive?
13392: 98/11/30: Ken Coffman: Re: Will XILINX survive?
13398: 98/11/30: Tim Davis: Re: Will XILINX survive?
13452: 98/12/03: Richard Schwarz: Re: Will XILINX survive?
13477: 98/12/04: Eric Hammervold: Re: Will XILINX survive?
13482: 98/12/04: Eric Hammervold: Re: Will XILINX survive?
13511: 98/12/07: Austin Franklin: Re: Will XILINX survive?
13525: 98/12/08: Wade D. Peterson: Re: Will XILINX survive?
13487: 98/12/05: Richard Cant: Re: Will XILINX survive?
13355: 98/11/30: Tim Forcer: PCB rules for Xilinx ICs
13367: 98/11/30: Ray Andraka: Re: PCB rules for Xilinx ICs
13370: 98/11/30: Bertram Geiger: Re: PCB rules for Xilinx ICs
13509: 98/12/07: Tim Forcer: Re: PCB rules for Xilinx ICs
13356: 98/11/30: Hul Tytus: serial arbitration
13358: 98/11/30: Jonathan Bromley: Re: serial arbitration
13362: 98/11/30: Rickman: Re: serial arbitration
13375: 98/11/30: Jonathan Bromley: Re: serial arbitration
13359: 98/11/30: Ellis Easley: Logical Devices ALLPRO diagnostics
13404: 98/12/01: Paul T. Shultz: Re: Logical Devices ALLPRO diagnostics
13369: 98/11/30: Jonas Thor: VHDL simulation of exported schematics..?
13412: 98/12/01: Stuart Clubb: Re: VHDL simulation of exported schematics..?
13419: 98/12/02: Jonas Thor: Re: VHDL simulation of exported schematics..?
13373: 98/11/30: Dirk Stroobandt: SLIP'99 CFP (Workshop on System-Level Interconnect Prediction)
13378: 98/11/30: Steve: Is it normal to have to edit the xnf file???
13391: 98/12/01: Alexander Sherstuk: Editing XNF file
13405: 98/12/01: Todd Kline: Re: Is it normal to have to edit the xnf file???
13409: 98/12/01: Steve: Re: Is it normal to have to edit the xnf file???
13415: 98/12/01: Austin Franklin: Re: Is it normal to have to edit the xnf file???
13420: 98/12/02: ez: Re: Is it normal to have to edit the xnf file???
13423: 98/12/02: Steve: Re: Is it normal to have to edit the xnf file???
13426: 98/12/02: Brian Boorman: Re: Is it normal to have to edit the xnf file???
13480: 98/12/04: Todd Kline: Re: Is it normal to have to edit the xnf file???
13495: 98/12/05: John: Re: Is it normal to have to edit the xnf file???
13383: 98/11/30: Elder V Costa: Archiving Xilinx Foundation Projects
13389: 98/12/01: Alexander Sherstuk: Re: Archiving Xilinx Foundation Projects
13394: 98/11/30: Michelle Tran: ASIC to FPGA conversion, low NRE
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