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Hi everybody
I am working with Xilinx Foundation Express v1.4. I usually work with
schematics top level design, converting vhdl code to macro. The problem
is the follow:
In my original design I define a case statement with five cases..
library IEEE;
use IEEE.std_logic_1164.all;
entity rgbcore is
port (
data: in STD_LOGIC_VECTOR (5 downto 0);
reset: in STD_LOGIC;
clock: in STD_LOGIC;
rgb: out STD_LOGIC_VECTOR (5 downto 0)
);
end rgbcore;
architecture arch1_rgbcore of rgbcore is
begin
process(clock,reset)
begin
if reset='1' then
rgb <= "000000";
elsif (clock'event and clock='1') then
case data(3 downto 0) is
when "0000" => rgb <= "000000";-- negro
when "0100" => rgb <= "010101";-- gris1
when "1000" => rgb <= "101010";-- gris2
when "1100" => rgb <= "111111";-- blanco
when others => rgb <= "110000"; -- rojo
end case;
end if;
end process;
end arch1_rgbcore;
There is no problem and implementation is OK. But I want add more
options to the case, then I use the | character...
architecture arch2_rgbcore of rgbcore is
begin
process(clock,reset)
begin
if reset='1' then
rgb <= "000000";
elsif (clock'event and clock='1') then
case data(3 downto 0) is
when "0000"|"0001"|"0010"|"0011" => rgb <= "000000";-- negro
when "0100"|"0101"|"0110"|"0111" => rgb <= "010101";-- gris1
when "1000"|"1001"|"1010"|"1011" => rgb <= "101010";-- gris2
when "1100"|"1101"|"1110"|"1111" => rgb <= "111111";-- blanco
when others => rgb <= "110000"; -- rojo
end case;
end if;
end process;
end arch2_rgbcore;
Now the synthesis is OK but one error occurred in the Traslation phase
of the implementation
Traslation report
ERROR:basnb:79 - Pin mismatch between block "U1", TYPE="RGBCORE", and
file
"C:\MyDesign\FProj\BORRAR\xproj\ver2\RGBCORE.ngo" at pin "DATA<1>".
Please
make sure that all pins on the instantiated component match pins in
the
lower-level design block. (Pin-name matching is case-insensitive.)
I rewrite the architecture avoiding | and describing all the cases
architecture arch3_rgbcore of rgbcore is
begin
process(clock,reset)
begin
if reset='1' then
rgb <= "000000";
elsif (clock'event and clock='1') then
case data(3 downto 0) is
when "0000" => rgb <= "000000";-- negro
when "0001" => rgb <= "000000";-- negro
when "0010" => rgb <= "000000";-- negro
when "0011" => rgb <= "000000";-- negro
when "0100" => rgb <= "010101";-- gris1
when "0101" => rgb <= "010101";-- gris1
..................and so on...
The same error occurred again !!!!!
ERROR:basnb:79 - Pin mismatch ......
Could somebody help me?
Thank in advanced
===================================================================
Sergio A. Cuenca Asensi
Dept. Tecnologia Informatica y Computacion (TIC)
Escuela Politecnica Superior, Campus de San Vicente
Universidad de Alicante
Ap. Correos 99, E-03080 ALICANTE
email : sergio@dtic.ua.es
Phone : +34 96 590 39 34
Fax : +34 96 590 39 02
===================================================================
Article: 13726
z80@ds2.com (Peter) writes:
> I wish there was a 22V10, zero-power (like Philips P3Z22V10) which was
> ISP, programmable in-circuit via 3 pins. Then one could use a TSOP-28
> version, or some other tiny package.
Lattice? Not zero-power, but anyway. Both their SSOP-28 and their
TQFP48 is smaller than a 28-pin PLCC. Especially if you are using a
socket... ;-)
Homann
--
Magnus Homann Email: d0asta@dtek.chalmers.se
URL : http://www.dtek.chalmers.se/DCIG/d0asta.html
The Climbing Archive!: http://www.dtek.chalmers.se/Climbing/index.html
Article: 13727Magnus Homann <d0asta@mis.dtek.chalmers.se> wrote in article <ltww3lzo0u.fsf@mis.dtek.chalmers.se>... > z80@ds2.com (Peter) writes: > > I wish there was a 22V10, zero-power (like Philips P3Z22V10) which was > > ISP, programmable in-circuit via 3 pins. Then one could use a TSOP-28 > > version, or some other tiny package. > > Lattice? Not zero-power, but anyway. Both their SSOP-28 and their > TQFP48 is smaller than a 28-pin PLCC. Especially if you are using a > socket... ;-) Is there a socket for the SSOP28 or the TQFP48? The 28 pin socket is only used for initial prototyping....then it is removed for production. There are very good sockets out there that take up almost no more room than the chip it self does, and you need room around the chip anyway...it's not like you can just 'butt' the chips up against each other... My point on the socket was it really sucks to have to de-solder an SMT chip just to make a PAL change when doing first debug...and a socket is certainly easier. AustinArticle: 13728
"Austin Franklin" <dark8room@altavista.net> writes:
> Magnus Homann <d0asta@mis.dtek.chalmers.se> wrote in article
> <ltww3lzo0u.fsf@mis.dtek.chalmers.se>...
> > z80@ds2.com (Peter) writes:
> > > I wish there was a 22V10, zero-power (like Philips P3Z22V10) which was
> > > ISP, programmable in-circuit via 3 pins. Then one could use a TSOP-28
> > > version, or some other tiny package.
> >
> > Lattice? Not zero-power, but anyway. Both their SSOP-28 and their
> > TQFP48 is smaller than a 28-pin PLCC. Especially if you are using a
> > socket... ;-)
>
> Is there a socket for the SSOP28 or the TQFP48? The 28 pin socket is only
> used for initial prototyping....then it is removed for production.
None needed. They have ISP.
> There
> are very good sockets out there that take up almost no more room than the
> chip it self does, and you need room around the chip anyway...it's not like
> you can just 'butt' the chips up against each other...
Yes, but you need even more room when using a socket. And the parts
themselves are bigger.
> My point on the socket was it really sucks to have to de-solder an SMT chip
> just to make a PAL change when doing first debug...and a socket is
> certainly easier.
I don't agree. Those parts have ISP, which I think is easier than
sockets. In fact, I try to avoid sockets.
Homann
--
Magnus Homann Email: d0asta@dtek.chalmers.se
URL : http://www.dtek.chalmers.se/DCIG/d0asta.html
The Climbing Archive!: http://www.dtek.chalmers.se/Climbing/index.html
Article: 13729Bo Bjerre wrote in message <367A6328.44A7E60B@Bjerre-Technology.dk>... >You may instead look at the atmel serial PROM for configuring FPGA's. >They are ISP, and they have some application notes on this, >http://www.atmel.com > Thanks for the reference. Looking over Atmel's web site tells me that what I want to do (load Xilinx config file into 3rd party serial eeprom) is possible. Unfortunately I couldn't find what I'm hoping for, that is, a serial eeprom that uses JTAG for ISP. I saw the AT17Cxxx devices, but they use the traditional ISP. I did run across an ATF1502AS CPLD which is more than just the serial eeprom I'm looking for. CarlArticle: 13730
Steve Dewey wrote in message <913916218snz@s-deweynospam.demon.co.uk>... > >Carl > >Have you any availability info from Altera about the EPC2 ? >Samples or production ? They were supposed to be available in October, but >I've not seen any yet. I heard there were some production problems... I'll be double-checking it now, but I'm told that one group has actually received samples ... Thanks for the heads-up. CarlArticle: 13731
Brian Boorman wrote in message <36791872.F4A6D68D@harris.com>... >The Altera device is just a serial eeprom. Since I don't have a data sheet for >this device, I am going to make the assumption that its interface is the same >as the EPC1 device. > >Connect FPGA /INIT Pin to EPC OE Pin >Connect FPGA /LDC Pin to EPC nCS Pin >Connect FPGA DIN Pin to EPC DATA Pin >Connect FPGA CCLK Pin to EPC CLK Pin. > >The only other concern is that the Altera Prom is large enough to hold all the >Data. > >BTW - Are you in Rochester? I've actually gotten that far. It's the "software" side that I'm interested in. Can I get a Xilinx configuration file into the EPC2 to begin with? It seems to me that Atmel provides this kind of assistance (getting Xilinx/Altera config files into eeproms) so I know the theory seems sound, I just can't find someone who has done it for this particular pair (Altera eeprom => Xilinx FPGA) ... maybe you can help me out on this one? Sounds like you may have accomplished this before with the EPC1 configuring some Xilinx device? And yes, I'm in Rochester. Elmgrove Plant. Thanks, CarlArticle: 13732
I like the point and click of the flow engine and the grouping of all the report files, but I'm continuously frustrated with the lack of control. How can I remove a something from the flow? In particular (this time), I am using the floorplanner, and somehow the flow engine now knows I want to add that to my map command. But I don't like how the 1.5i mapper is handling my floorplan so I want to take it out. How??? I tried a grep on my project directory to try and find where the info was stored, but all I found was binaries and reports. Is my own batch file the only/best option? SteveArticle: 13733
Peter wrote: > I am speaking in ignorance of Xilinx pricing structure for commercial > v. industrial, I looked up some prices, and I think we do not take advantage of the industrial customers. Here are some numbers, and bear in mind that the industrial part is inherently almost a speed grade "faster" than the commercial one, since identical parameter values are being guaranteed over a wider temperature and voltage range. Here are the $ numbers, taken at random, commercial first, industrial second: 17.35 - 19.75 13.70 - 14.40 17.80 - 20.20 106.00 - 122.00 Usually, the industrial pricing is below the "one-speed-grade-faster" commercial pricing. We just try to be reasonable. Early availability of industrial devices is often delayed because the extra characterization has not yet been completed. Peter Alfke, Xilinx ApplicationsArticle: 13734
Edward Moore wrote: > >The design approach will be heavily influendced by the required > speed. > >If both clocks are fully asynchronous and run at 80 MHz, it may be > >beyond the reach of VHDL, > >but the silicon can still do it. > >At low clock rates, the design can be quite simple. > > > >Peter Alfke, Xilinx Applications > > > > Why is this beyond the reach of VHDL ? > > And if it is, isn't a pity that Xilinx are going to abandon schematic > entry ? > > Or do you mean the fifo should be designed in EPIC ? > > Please explain. Maybe I explained it poorly. At the outer limits of the possible silicon performance, there is very limited or no freedom in partitioning, placement, and routing. My perhaps poor understanding of VHDL tells me that such mapping and placing is not possible in VHDL. But that may just show my ignorance. There are certeinly more experienced people in this newsgroup who can correct me. Assume that at 100 MHz in XC4000XL ( and at 170 MHz in Virtex ) a FIFO with completely asynchronous read and write clocks needs to be partitioned and floorplanned carefully, in order to generate reliable FULL and EMPTY flags. That is all I meant to say. Peter Alfke, Xilinx ApplicationsArticle: 13735
"sam" <cong_sp@willnet.co.jp> wrote:
>Does anyone have trouble when use Atmel's PLD ?
>I will never use Atmel's PLD . It's too bad .
IMHO generally they're very good. The V750s and V2500s have that nice ability to
route clocks, although it does encourage nasty asynchronous designs.
The only problem I had was with a 2500L which had an 8 bit bus interface and a
synchronous counter with an independent (of the bus) clock. This could (AFAIR)
occasionally gain an extra count or two in several thousand in the presence of
bus activity.
The problem was much reduced by putting a 22K (* 8) pullup to Vcc on the bus
lines. The 2500L did not like bus lines that floated during processor
(in)activity even though the bus had nothing to do with the counter. 2500Hs were
fine BTW.
I spoke with Atmel about it at the time and they said they were aware of the
problem and suggested a fix (apart from using a 2500H). They were also planning
a die revision which would eliminate it.
Richard
------------Richard Dungan-------------
Radix Electronic Designs, Orpington, UK
Spamtrapped: Remove the XY
---------------------------------------
Article: 13736I use the unix make to run everything from synthesis to trce. I can send you a sample of my Makefile if you are running your design on an unix machine. BTW, you can run the floor planning tool by itself. In a unix machine, the command is "floorplanner". Good luck, Hing-FaiArticle: 13737
Richard Dungan wrote: > > "sam" <cong_sp@willnet.co.jp> wrote: > > >Does anyone have trouble when use Atmel's PLD ? > >I will never use Atmel's PLD . It's too bad . Which PLD / What Application / Define 'bad'. Not all SPLDs are created equal. We had one app where one brand had a pull-up, and another did not. ( once the 'difference' was identified, there were no problems. ) PLDS generally, also do not like slow edges. -jgArticle: 13738
Austin Franklin wrote: > > > Tim is correct, I believe there is a need for smaller pincount devices, > > the 150 mil SO16/DIP16 would seem a logical part, and resource to > > replace > > a large chunk of all TTL grade MSI. > > Also the 20 / 24 pin device with 22i/o lines is a candidate. > > I agree, except the package can be a problem. If you want to socket it, > the SMT SO devices don't have very friendly (if at all) sockets. True, tho for new devices, this would be ISP. This just needs a dual-function pin, for High Voltage (12V) PGM enable, and then some form of simple Serial PGM. ( SPI / i2c ) VppEn on a low end part means - you do not loose any pins - you save chargepump die area - you cannot have any 'accidental' pgm mode state trigger We have developed an ISP product, for the 20 Pin SOL uC (89C2051), that clips over the SOL20 package and does pin-overdrive ISP. ( Vpp on pin 1 on this part ) This works very well, and means you can buy the devices on tape/reel, and pgm after assembly. - jgArticle: 13739
I ran across a reference in a 1994 paper to the Altera 881152GC192 FPGA. I am looking for an approximate gate count so that I can compare it to current FPGAs. Altera could not identify it. Unfortunately, the authors of the paper don't have their literature accessible either. Anyone know what this is? Thanks, ScottArticle: 13740
Not zero power, more like 30mA. This is 10x more than the entire draw of some of my products :) >Lattice? Not zero-power, but anyway. Both their SSOP-28 and their >TQFP48 is smaller than a 28-pin PLCC. Especially if you are using a >socket... ;-) -- Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 13741
I have never seen a socket for those packages which takes up the same footprint as the package. Only for DIP and PLCC (and some odd J-lead packages) is this possible, AFAIK. >Is there a socket for the SSOP28 or the TQFP48? The 28 pin socket is only >used for initial prototyping....then it is removed for production. There >are very good sockets out there that take up almost no more room than the >chip it self does, and you need room around the chip anyway...it's not like >you can just 'butt' the chips up against each other... > >My point on the socket was it really sucks to have to de-solder an SMT chip >just to make a PAL change when doing first debug...and a socket is >certainly easier. -- Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 13742
Hello, I developed an embedded application and would like to move it to an
FPGA. Basically, I need some pointers to refrence material on how to do this.
Some of the topics I need to learn about:
* Converting a flowchart to a state diagram.
(I can write the code up in VHDL once i have done the state diagram.)
* moving the code to an FPGA implementation.
Please let me know of any book concerning these cocepts and procedures.
Thank you in advance.
Eldho kuriakose
-----------== Posted via Deja News, The Discussion Network ==----------
http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own
Article: 13743i've got some information on creating VHDL RPMs, and some example code, at: http://www.riverside-machines.com/pub2/xilinx/vhdl_rpm/top.htm evanArticle: 13744
Well, that will teach me to try to be nice to Altera. I did a design where video entered on one side of the 8K device and exited on the other side (after convolution) and the design worked just fine. I didn't spend a lot of time analyzing routing, but I assume it worked fast because there was a directional flow and not a lot of feedback. This is what I'd call a datapath application, with data flowing through the device.The design didn't have any counters, just hard-wired pipelined multipliers. This last year I've converted to brand X and I don't see myself going back. My hat is off to whoever said they love Xilinx's silicon and Altera's Software. bob elkind wrote in message <367ABB62.E7A2C0BC@aracnet.com>... >Ray's post was excellent. Let me add my 2 cents... > >1. I've used Xilinx 4K, Lucent Orca2C, and Altera 6K/10K extensively. > To a **First approximation**, the Xilinx and Orca technologies are > very similar. The Altera devices are very different. > >2. Xilinx and Orca devices are large sandboxes. Reconfiguring output > pins (or locking them down) is pretty easy to do, within limits, and > that eases the worries about post-board-layout design additions. > >3. Altera FPGAs are constructed as an array of smaller sandboxes. > If your design doesn't partition well amongst the subsections, you > run the risk of > a) not enough interconnect to route the design or > b) a quantum decrease in operating frequency, due to interconnect delays. > >I agree with Ray's assessment, datapath intensive design (esp DSPs) will >tend to be happier with Xilinx and Orca devices. Random logic and smaller >datapaths will be happy in any of the devices. The inefficiencies in any of >these products can, in general (but not always), be overcome with bigger >or faster grade parts. > >4. It's the tools, stupid! You can become proficient in Max+II (Altera) > **very** quickly. That is a very compelling attribute! If you are > designing a part that someone else will have to maintain (i.e. a client), > this is a very powerful weapon in the consultant's arsenal. Also, if > you don't use the tool often enough to become proficient and stay > proficient, consider a less demanding toolset, like Max+2. > >5. Compile time. You *can* configure a Xilinx or Orca design to > eventually compile quickly, but this takes time, and major design > changes generally mean several hours of compile time. (do 28 > compiles and keep the best 4 :=) ). On the other hand, Max+2 > compiles (generally) in 5-10 minutes. Instant gratification, > fewer coffee breaks (and bathroom runs). > >Summary: For video processing, I stay with Orca or Xilinx. > For interface logic design, and designs where I know the customer > will want to maintain it, I tend to use Altera, where I know I can > get useable results more quickly. > >**************************************************************** >Bob Elkind mailto:eteam@aracnet.com >7118 SW Lee Road part-time fax number:503.357.9001 >Gaston, OR 97119 cell:503.709.1985 home:503.359.4903 >****** Video processing, R&D, ASIC, FPGA design consulting ***** > >Article: 13745
This wouldn't be the first case of several intelligent and informed (not to mention handsome and charming) engineers had differing opinions on a matter of subjective preferences. Once again, it can be demonstrated that there are still some areas of engineering that defy being simplified into *absolutes* ! Merry Christmas, may all your logic gates fly with the wind, and remember: Christmas season isn't just a time to cram a bunch of work in to meet a year-end deadline. Peace be with you! Ken Coffman wrote: > Well, that will teach me to try to be nice to Altera. I did a design where > video entered on one side of the 8K device and exited on the other side > (after convolution) and the design worked just fine. I didn't spend a lot of > time analyzing routing, but I assume it worked fast because there was a > directional flow and not a lot of feedback. This is what I'd call a datapath > application, with data flowing through the device.The design didn't have any > counters, just hard-wired pipelined multipliers. > This last year I've converted to brand X and I don't see myself going back. > My hat is off to whoever said they love Xilinx's silicon and Altera's > Software. **************************************************************** Bob Elkind mailto:eteam@aracnet.com 7118 SW Lee Road part-time fax number:503.357.9001 Gaston, OR 97119 cell:503.709.1985 home:503.359.4903 ****** Video processing, R&D, ASIC, FPGA design consulting *****Article: 13746
This is a multi-part message in MIME format. --------------0AF91C5ADC4B463F320D8F8C Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Steve, I wrestled with this one a while back when I started using the M1.5 stuff. It seems that someone at Xilinx decided to make it 'easy' for an inexperienced user to do floorplanning by forcing the Flow Engine to launch map with -fp not only after you've selected that option, but even after you've de-selected it (Design->Set Floorplan Files -> None), as long as a floorplan file exists, seemingly anywhere among your design versions/revs. The only way I've found to get back to no floorplanning is to delete/move/rename any and all floorplan files (fnf). Once the FE can't find them, it will go back to launching map w/o -fp. It is very frustrating when these "conveniences" get in the way of the design flow. Steve wrote: > I like the point and click of the flow engine and the grouping of all > the report files, but I'm continuously frustrated with the lack of > control. How can I remove a something from the flow? > > In particular (this time), I am using the floorplanner, and somehow > the flow engine now knows I want to add that to my map command. > But I don't like how the 1.5i mapper is handling my floorplan so I want > to take it out. How??? I tried a grep on my project directory to try > and find where the info was stored, but all I found was binaries and > reports. Is my own batch file the only/best option? > > Steve --------------0AF91C5ADC4B463F320D8F8C Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for John L. Smith Content-Disposition: attachment; filename="vcard.vcf" begin: vcard fn: John L. Smith n: Smith;John L. org: Visicom Imaging Products adr: 1 Burlington Woods;;;Burlington;MA;01803;USA email;internet: jsmith@visicom.com title: Principal Engineer tel;work: 781-221-6700 tel;fax: 781-221-6777 note: http://www.visicom.com/products/Vigra/index.html x-mozilla-cpt: ;0 x-mozilla-html: TRUE version: 2.1 end: vcard --------------0AF91C5ADC4B463F320D8F8C--Article: 13747
"Sergio A. Cuenca Asensi" wrote: > > Hi everybody > > I am working with Xilinx Foundation Express v1.4. I usually work with > schematics top level design, converting vhdl code to macro. The problem > is the follow: > In my original design I define a case statement with five cases.. > > library IEEE; > use IEEE.std_logic_1164.all; > > entity rgbcore is > port ( > data: in STD_LOGIC_VECTOR (5 downto 0); > reset: in STD_LOGIC; > clock: in STD_LOGIC; > rgb: out STD_LOGIC_VECTOR (5 downto 0) > ); > end rgbcore; > architecture arch1_rgbcore of rgbcore is > begin > process(clock,reset) > begin > if reset='1' then > rgb <= "000000"; > elsif (clock'event and clock='1') then > case data(3 downto 0) is > when "0000" => rgb <= "000000";-- negro > when "0100" => rgb <= "010101";-- gris1 > when "1000" => rgb <= "101010";-- gris2 > when "1100" => rgb <= "111111";-- blanco > when others => rgb <= "110000"; -- rojo > end case; > end if; > end process; > end arch1_rgbcore; > > There is no problem and implementation is OK. But I want add more > options to the case, then I use the | character... > > architecture arch2_rgbcore of rgbcore is > begin > process(clock,reset) > begin > if reset='1' then > rgb <= "000000"; > elsif (clock'event and clock='1') then > case data(3 downto 0) is > when "0000"|"0001"|"0010"|"0011" => rgb <= "000000";-- negro > when "0100"|"0101"|"0110"|"0111" => rgb <= "010101";-- gris1 > when "1000"|"1001"|"1010"|"1011" => rgb <= "101010";-- gris2 > when "1100"|"1101"|"1110"|"1111" => rgb <= "111111";-- blanco > when others => rgb <= "110000"; -- rojo > end case; > end if; > end process; > end arch2_rgbcore; > > Now the synthesis is OK but one error occurred in the Traslation phase > of the implementation > > Traslation report > ERROR:basnb:79 - Pin mismatch between block "U1", TYPE="RGBCORE", and > file > "C:\MyDesign\FProj\BORRAR\xproj\ver2\RGBCORE.ngo" at pin "DATA<1>". > Please > make sure that all pins on the instantiated component match pins in > the > lower-level design block. (Pin-name matching is case-insensitive.) > > I rewrite the architecture avoiding | and describing all the cases > > architecture arch3_rgbcore of rgbcore is > begin > process(clock,reset) > begin > if reset='1' then > rgb <= "000000"; > elsif (clock'event and clock='1') then > case data(3 downto 0) is > when "0000" => rgb <= "000000";-- negro > when "0001" => rgb <= "000000";-- negro > when "0010" => rgb <= "000000";-- negro > when "0011" => rgb <= "000000";-- negro > when "0100" => rgb <= "010101";-- gris1 > when "0101" => rgb <= "010101";-- gris1 > ..................and so on... > > The same error occurred again !!!!! > ERROR:basnb:79 - Pin mismatch ...... > > Could somebody help me? I am no guru, but I don't think your problem is in the architecture of your code. I have been using Foundation for a while and the only time I get this error is when I have made a change to either the schematic symbol or the VHDL code and the symbol pin list does not match the port list in the VHDL. It does not look like you changed this intentionally, but have you made an accidental typo, or did you accidentally change a pin on the symbol? Perhaps you changed the number of bits in a bus on one and not the other? If you don't see a problem, you might want to delete the symbol and add it back again. I have seen "invisible" problems where I had to do this to fix it. Of course, there are many bug fixes in V1.5 so an obvious suggestion is to upgrade. I haven't myself because I am in the middle of a design. But then I am still fighting bugs that I am told are fixed in V1.5i. Sometimes it seems that the only hard part of doing FPGA design is learning how to work around the tools! -- Rick Collins redsp@XYusa.net remove the XY to email me. "A man who carries a cat by the tail learns something he can learn in no other way." -- Mark TwainArticle: 13748
Does anyone but CAST supply a 16550 core? They've just quoted $15K for the VHDL source or $7500 for a Xilinx netlist. In either case, that's too much for this application. Can it be found elsewhere? thx. JonathanArticle: 13749
Hi:
I need a method that can make random number(integer) in VHDL,
and any one know how to use the STYX function within WorkView
,I've written a function by C, and use styxcomp.exe to compule it.
but I don't know the argument -LIB mean?
Please help me, thanks
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